Texas Instruments TM4C1290NCZAD 2024.06.02 ARM Cortex-M4 Tiva TM4C Device CM4 r1p2 little true 3 false 8 32 ADC0 Register map for ADC0 peripheral ADC 0x0 0x0 0x1000 registers n ADC0SS0 14 ADC0SS1 15 ADC0SS2 16 ADC0SS3 17 ACTSS ADC Active Sample Sequencer 0x0 -1 read-write n 0x0 0x0 ADC_ACTSS_ADEN0 ADC SS1 DMA Enable 8 9 ADC_ACTSS_ADEN1 ADC SS1 DMA Enable 9 10 ADC_ACTSS_ADEN2 ADC SS2 DMA Enable 10 11 ADC_ACTSS_ADEN3 ADC SS3 DMA Enable 11 12 ADC_ACTSS_ASEN0 ADC SS0 Enable 0 1 ADC_ACTSS_ASEN1 ADC SS1 Enable 1 2 ADC_ACTSS_ASEN2 ADC SS2 Enable 2 3 ADC_ACTSS_ASEN3 ADC SS3 Enable 3 4 ADC_ACTSS_BUSY ADC Busy 16 17 ADC0ACTSS ADC Active Sample Sequencer 0x0 read-write n 0x0 0x0 ADC_ACTSS_ADEN0 ADC SS1 DMA Enable 8 9 ADC_ACTSS_ADEN1 ADC SS1 DMA Enable 9 10 ADC_ACTSS_ADEN2 ADC SS2 DMA Enable 10 11 ADC_ACTSS_ADEN3 ADC SS3 DMA Enable 11 12 ADC_ACTSS_ASEN0 ADC SS0 Enable 0 1 ADC_ACTSS_ASEN1 ADC SS1 Enable 1 2 ADC_ACTSS_ASEN2 ADC SS2 Enable 2 3 ADC_ACTSS_ASEN3 ADC SS3 Enable 3 4 ADC_ACTSS_BUSY ADC Busy 16 17 ADC0CC ADC Clock Configuration 0xFC8 read-write n 0x0 0x0 ADC_CC_CLKDIV PLL VCO Clock Divisor 4 10 ADC_CC_CS ADC Clock Source 0 4 ADC_CC_CS_SYSPLL PLL VCO divided by CLKDIV 0x0 ADC_CC_CS_PIOSC PIOSC 0x1 ADC_CC_CS_MOSC MOSC 0x2 ADC0CTL ADC Control 0x38 read-write n 0x0 0x0 ADC_CTL_DITHER Dither Mode Enable 6 7 ADC_CTL_VREF Voltage Reference Select 0 1 ADC_CTL_VREF_INTERNAL VDDA and GNDA are the voltage references 0x0 ADC_CTL_VREF_EXT_3V The external VREFA+ and VREFA- inputs are the voltage references 0x1 ADC0DCCMP0 ADC Digital Comparator Range 0 0xE40 read-write n 0x0 0x0 ADC_DCCMP0_COMP0 Compare 0 0 12 ADC_DCCMP0_COMP1 Compare 1 16 28 ADC0DCCMP1 ADC Digital Comparator Range 1 0xE44 read-write n 0x0 0x0 ADC_DCCMP1_COMP0 Compare 0 0 12 ADC_DCCMP1_COMP1 Compare 1 16 28 ADC0DCCMP2 ADC Digital Comparator Range 2 0xE48 read-write n 0x0 0x0 ADC_DCCMP2_COMP0 Compare 0 0 12 ADC_DCCMP2_COMP1 Compare 1 16 28 ADC0DCCMP3 ADC Digital Comparator Range 3 0xE4C read-write n 0x0 0x0 ADC_DCCMP3_COMP0 Compare 0 0 12 ADC_DCCMP3_COMP1 Compare 1 16 28 ADC0DCCMP4 ADC Digital Comparator Range 4 0xE50 read-write n 0x0 0x0 ADC_DCCMP4_COMP0 Compare 0 0 12 ADC_DCCMP4_COMP1 Compare 1 16 28 ADC0DCCMP5 ADC Digital Comparator Range 5 0xE54 read-write n 0x0 0x0 ADC_DCCMP5_COMP0 Compare 0 0 12 ADC_DCCMP5_COMP1 Compare 1 16 28 ADC0DCCMP6 ADC Digital Comparator Range 6 0xE58 read-write n 0x0 0x0 ADC_DCCMP6_COMP0 Compare 0 0 12 ADC_DCCMP6_COMP1 Compare 1 16 28 ADC0DCCMP7 ADC Digital Comparator Range 7 0xE5C read-write n 0x0 0x0 ADC_DCCMP7_COMP0 Compare 0 0 12 ADC_DCCMP7_COMP1 Compare 1 16 28 ADC0DCCTL0 ADC Digital Comparator Control 0 0xE00 read-write n 0x0 0x0 ADC_DCCTL0_CIC Comparison Interrupt Condition 2 4 ADC_DCCTL0_CIC_LOW Low Band 0x0 ADC_DCCTL0_CIC_MID Mid Band 0x1 ADC_DCCTL0_CIC_HIGH High Band 0x3 ADC_DCCTL0_CIE Comparison Interrupt Enable 4 5 ADC_DCCTL0_CIM Comparison Interrupt Mode 0 2 ADC_DCCTL0_CIM_ALWAYS Always 0x0 ADC_DCCTL0_CIM_ONCE Once 0x1 ADC_DCCTL0_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL0_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL0_CTC Comparison Trigger Condition 10 12 ADC_DCCTL0_CTC_LOW Low Band 0x0 ADC_DCCTL0_CTC_MID Mid Band 0x1 ADC_DCCTL0_CTC_HIGH High Band 0x3 ADC_DCCTL0_CTE Comparison Trigger Enable 12 13 ADC_DCCTL0_CTM Comparison Trigger Mode 8 10 ADC_DCCTL0_CTM_ALWAYS Always 0x0 ADC_DCCTL0_CTM_ONCE Once 0x1 ADC_DCCTL0_CTM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL0_CTM_HONCE Hysteresis Once 0x3 ADC0DCCTL1 ADC Digital Comparator Control 1 0xE04 read-write n 0x0 0x0 ADC_DCCTL1_CIC Comparison Interrupt Condition 2 4 ADC_DCCTL1_CIC_LOW Low Band 0x0 ADC_DCCTL1_CIC_MID Mid Band 0x1 ADC_DCCTL1_CIC_HIGH High Band 0x3 ADC_DCCTL1_CIE Comparison Interrupt Enable 4 5 ADC_DCCTL1_CIM Comparison Interrupt Mode 0 2 ADC_DCCTL1_CIM_ALWAYS Always 0x0 ADC_DCCTL1_CIM_ONCE Once 0x1 ADC_DCCTL1_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL1_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL1_CTC Comparison Trigger Condition 10 12 ADC_DCCTL1_CTC_LOW Low Band 0x0 ADC_DCCTL1_CTC_MID Mid Band 0x1 ADC_DCCTL1_CTC_HIGH High Band 0x3 ADC_DCCTL1_CTE Comparison Trigger Enable 12 13 ADC_DCCTL1_CTM Comparison Trigger Mode 8 10 ADC_DCCTL1_CTM_ALWAYS Always 0x0 ADC_DCCTL1_CTM_ONCE Once 0x1 ADC_DCCTL1_CTM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL1_CTM_HONCE Hysteresis Once 0x3 ADC0DCCTL2 ADC Digital Comparator Control 2 0xE08 read-write n 0x0 0x0 ADC_DCCTL2_CIC Comparison Interrupt Condition 2 4 ADC_DCCTL2_CIC_LOW Low Band 0x0 ADC_DCCTL2_CIC_MID Mid Band 0x1 ADC_DCCTL2_CIC_HIGH High Band 0x3 ADC_DCCTL2_CIE Comparison Interrupt Enable 4 5 ADC_DCCTL2_CIM Comparison Interrupt Mode 0 2 ADC_DCCTL2_CIM_ALWAYS Always 0x0 ADC_DCCTL2_CIM_ONCE Once 0x1 ADC_DCCTL2_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL2_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL2_CTC Comparison Trigger Condition 10 12 ADC_DCCTL2_CTC_LOW Low Band 0x0 ADC_DCCTL2_CTC_MID Mid Band 0x1 ADC_DCCTL2_CTC_HIGH High Band 0x3 ADC_DCCTL2_CTE Comparison Trigger Enable 12 13 ADC_DCCTL2_CTM Comparison Trigger Mode 8 10 ADC_DCCTL2_CTM_ALWAYS Always 0x0 ADC_DCCTL2_CTM_ONCE Once 0x1 ADC_DCCTL2_CTM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL2_CTM_HONCE Hysteresis Once 0x3 ADC0DCCTL3 ADC Digital Comparator Control 3 0xE0C read-write n 0x0 0x0 ADC_DCCTL3_CIC Comparison Interrupt Condition 2 4 ADC_DCCTL3_CIC_LOW Low Band 0x0 ADC_DCCTL3_CIC_MID Mid Band 0x1 ADC_DCCTL3_CIC_HIGH High Band 0x3 ADC_DCCTL3_CIE Comparison Interrupt Enable 4 5 ADC_DCCTL3_CIM Comparison Interrupt Mode 0 2 ADC_DCCTL3_CIM_ALWAYS Always 0x0 ADC_DCCTL3_CIM_ONCE Once 0x1 ADC_DCCTL3_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL3_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL3_CTC Comparison Trigger Condition 10 12 ADC_DCCTL3_CTC_LOW Low Band 0x0 ADC_DCCTL3_CTC_MID Mid Band 0x1 ADC_DCCTL3_CTC_HIGH High Band 0x3 ADC_DCCTL3_CTE Comparison Trigger Enable 12 13 ADC_DCCTL3_CTM Comparison Trigger Mode 8 10 ADC_DCCTL3_CTM_ALWAYS Always 0x0 ADC_DCCTL3_CTM_ONCE Once 0x1 ADC_DCCTL3_CTM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL3_CTM_HONCE Hysteresis Once 0x3 ADC0DCCTL4 ADC Digital Comparator Control 4 0xE10 read-write n 0x0 0x0 ADC_DCCTL4_CIC Comparison Interrupt Condition 2 4 ADC_DCCTL4_CIC_LOW Low Band 0x0 ADC_DCCTL4_CIC_MID Mid Band 0x1 ADC_DCCTL4_CIC_HIGH High Band 0x3 ADC_DCCTL4_CIE Comparison Interrupt Enable 4 5 ADC_DCCTL4_CIM Comparison Interrupt Mode 0 2 ADC_DCCTL4_CIM_ALWAYS Always 0x0 ADC_DCCTL4_CIM_ONCE Once 0x1 ADC_DCCTL4_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL4_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL4_CTC Comparison Trigger Condition 10 12 ADC_DCCTL4_CTC_LOW Low Band 0x0 ADC_DCCTL4_CTC_MID Mid Band 0x1 ADC_DCCTL4_CTC_HIGH High Band 0x3 ADC_DCCTL4_CTE Comparison Trigger Enable 12 13 ADC_DCCTL4_CTM Comparison Trigger Mode 8 10 ADC_DCCTL4_CTM_ALWAYS Always 0x0 ADC_DCCTL4_CTM_ONCE Once 0x1 ADC_DCCTL4_CTM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL4_CTM_HONCE Hysteresis Once 0x3 ADC0DCCTL5 ADC Digital Comparator Control 5 0xE14 read-write n 0x0 0x0 ADC_DCCTL5_CIC Comparison Interrupt Condition 2 4 ADC_DCCTL5_CIC_LOW Low Band 0x0 ADC_DCCTL5_CIC_MID Mid Band 0x1 ADC_DCCTL5_CIC_HIGH High Band 0x3 ADC_DCCTL5_CIE Comparison Interrupt Enable 4 5 ADC_DCCTL5_CIM Comparison Interrupt Mode 0 2 ADC_DCCTL5_CIM_ALWAYS Always 0x0 ADC_DCCTL5_CIM_ONCE Once 0x1 ADC_DCCTL5_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL5_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL5_CTC Comparison Trigger Condition 10 12 ADC_DCCTL5_CTC_LOW Low Band 0x0 ADC_DCCTL5_CTC_MID Mid Band 0x1 ADC_DCCTL5_CTC_HIGH High Band 0x3 ADC_DCCTL5_CTE Comparison Trigger Enable 12 13 ADC_DCCTL5_CTM Comparison Trigger Mode 8 10 ADC_DCCTL5_CTM_ALWAYS Always 0x0 ADC_DCCTL5_CTM_ONCE Once 0x1 ADC_DCCTL5_CTM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL5_CTM_HONCE Hysteresis Once 0x3 ADC0DCCTL6 ADC Digital Comparator Control 6 0xE18 read-write n 0x0 0x0 ADC_DCCTL6_CIC Comparison Interrupt Condition 2 4 ADC_DCCTL6_CIC_LOW Low Band 0x0 ADC_DCCTL6_CIC_MID Mid Band 0x1 ADC_DCCTL6_CIC_HIGH High Band 0x3 ADC_DCCTL6_CIE Comparison Interrupt Enable 4 5 ADC_DCCTL6_CIM Comparison Interrupt Mode 0 2 ADC_DCCTL6_CIM_ALWAYS Always 0x0 ADC_DCCTL6_CIM_ONCE Once 0x1 ADC_DCCTL6_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL6_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL6_CTC Comparison Trigger Condition 10 12 ADC_DCCTL6_CTC_LOW Low Band 0x0 ADC_DCCTL6_CTC_MID Mid Band 0x1 ADC_DCCTL6_CTC_HIGH High Band 0x3 ADC_DCCTL6_CTE Comparison Trigger Enable 12 13 ADC_DCCTL6_CTM Comparison Trigger Mode 8 10 ADC_DCCTL6_CTM_ALWAYS Always 0x0 ADC_DCCTL6_CTM_ONCE Once 0x1 ADC_DCCTL6_CTM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL6_CTM_HONCE Hysteresis Once 0x3 ADC0DCCTL7 ADC Digital Comparator Control 7 0xE1C read-write n 0x0 0x0 ADC_DCCTL7_CIC Comparison Interrupt Condition 2 4 ADC_DCCTL7_CIC_LOW Low Band 0x0 ADC_DCCTL7_CIC_MID Mid Band 0x1 ADC_DCCTL7_CIC_HIGH High Band 0x3 ADC_DCCTL7_CIE Comparison Interrupt Enable 4 5 ADC_DCCTL7_CIM Comparison Interrupt Mode 0 2 ADC_DCCTL7_CIM_ALWAYS Always 0x0 ADC_DCCTL7_CIM_ONCE Once 0x1 ADC_DCCTL7_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL7_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL7_CTC Comparison Trigger Condition 10 12 ADC_DCCTL7_CTC_LOW Low Band 0x0 ADC_DCCTL7_CTC_MID Mid Band 0x1 ADC_DCCTL7_CTC_HIGH High Band 0x3 ADC_DCCTL7_CTE Comparison Trigger Enable 12 13 ADC_DCCTL7_CTM Comparison Trigger Mode 8 10 ADC_DCCTL7_CTM_ALWAYS Always 0x0 ADC_DCCTL7_CTM_ONCE Once 0x1 ADC_DCCTL7_CTM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL7_CTM_HONCE Hysteresis Once 0x3 ADC0DCISC ADC Digital Comparator Interrupt Status and Clear 0x34 read-write n 0x0 0x0 ADC_DCISC_DCINT0 Digital Comparator 0 Interrupt Status and Clear 0 1 ADC_DCISC_DCINT1 Digital Comparator 1 Interrupt Status and Clear 1 2 ADC_DCISC_DCINT2 Digital Comparator 2 Interrupt Status and Clear 2 3 ADC_DCISC_DCINT3 Digital Comparator 3 Interrupt Status and Clear 3 4 ADC_DCISC_DCINT4 Digital Comparator 4 Interrupt Status and Clear 4 5 ADC_DCISC_DCINT5 Digital Comparator 5 Interrupt Status and Clear 5 6 ADC_DCISC_DCINT6 Digital Comparator 6 Interrupt Status and Clear 6 7 ADC_DCISC_DCINT7 Digital Comparator 7 Interrupt Status and Clear 7 8 ADC0DCRIC ADC Digital Comparator Reset Initial Conditions 0xD00 write-only n 0x0 0x0 ADC_DCRIC_DCINT0 Digital Comparator Interrupt 0 0 1 write-only ADC_DCRIC_DCINT1 Digital Comparator Interrupt 1 1 2 write-only ADC_DCRIC_DCINT2 Digital Comparator Interrupt 2 2 3 write-only ADC_DCRIC_DCINT3 Digital Comparator Interrupt 3 3 4 write-only ADC_DCRIC_DCINT4 Digital Comparator Interrupt 4 4 5 write-only ADC_DCRIC_DCINT5 Digital Comparator Interrupt 5 5 6 write-only ADC_DCRIC_DCINT6 Digital Comparator Interrupt 6 6 7 write-only ADC_DCRIC_DCINT7 Digital Comparator Interrupt 7 7 8 write-only ADC_DCRIC_DCTRIG0 Digital Comparator Trigger 0 16 17 write-only ADC_DCRIC_DCTRIG1 Digital Comparator Trigger 1 17 18 write-only ADC_DCRIC_DCTRIG2 Digital Comparator Trigger 2 18 19 write-only ADC_DCRIC_DCTRIG3 Digital Comparator Trigger 3 19 20 write-only ADC_DCRIC_DCTRIG4 Digital Comparator Trigger 4 20 21 write-only ADC_DCRIC_DCTRIG5 Digital Comparator Trigger 5 21 22 write-only ADC_DCRIC_DCTRIG6 Digital Comparator Trigger 6 22 23 write-only ADC_DCRIC_DCTRIG7 Digital Comparator Trigger 7 23 24 write-only ADC0EMUX ADC Event Multiplexer Select 0x14 read-write n 0x0 0x0 ADC_EMUX_EM0 SS0 Trigger Select 0 4 ADC_EMUX_EM0_PROCESSOR Processor (default) 0x0 ADC_EMUX_EM0_COMP0 Analog Comparator 0 0x1 ADC_EMUX_EM0_COMP1 Analog Comparator 1 0x2 ADC_EMUX_EM0_COMP2 Analog Comparator 2 0x3 ADC_EMUX_EM0_EXTERNAL External (GPIO Pins) 0x4 ADC_EMUX_EM0_TIMER Timer 0x5 ADC_EMUX_EM0_PWM0 PWM generator 0 0x6 ADC_EMUX_EM0_PWM1 PWM generator 1 0x7 ADC_EMUX_EM0_PWM2 PWM generator 2 0x8 ADC_EMUX_EM0_PWM3 PWM generator 3 0x9 ADC_EMUX_EM0_NEVER Never Trigger 0xe ADC_EMUX_EM0_ALWAYS Always (continuously sample) 0xf ADC_EMUX_EM1 SS1 Trigger Select 4 8 ADC_EMUX_EM1_PROCESSOR Processor (default) 0x0 ADC_EMUX_EM1_COMP0 Analog Comparator 0 0x1 ADC_EMUX_EM1_COMP1 Analog Comparator 1 0x2 ADC_EMUX_EM1_COMP2 Analog Comparator 2 0x3 ADC_EMUX_EM1_EXTERNAL External (GPIO Pins) 0x4 ADC_EMUX_EM1_TIMER Timer 0x5 ADC_EMUX_EM1_PWM0 PWM generator 0 0x6 ADC_EMUX_EM1_PWM1 PWM generator 1 0x7 ADC_EMUX_EM1_PWM2 PWM generator 2 0x8 ADC_EMUX_EM1_PWM3 PWM generator 3 0x9 ADC_EMUX_EM1_NEVER Never Trigger 0xe ADC_EMUX_EM1_ALWAYS Always (continuously sample) 0xf ADC_EMUX_EM2 SS2 Trigger Select 8 12 ADC_EMUX_EM2_PROCESSOR Processor (default) 0x0 ADC_EMUX_EM2_COMP0 Analog Comparator 0 0x1 ADC_EMUX_EM2_COMP1 Analog Comparator 1 0x2 ADC_EMUX_EM2_COMP2 Analog Comparator 2 0x3 ADC_EMUX_EM2_EXTERNAL External (GPIO Pins) 0x4 ADC_EMUX_EM2_TIMER Timer 0x5 ADC_EMUX_EM2_PWM0 PWM generator 0 0x6 ADC_EMUX_EM2_PWM1 PWM generator 1 0x7 ADC_EMUX_EM2_PWM2 PWM generator 2 0x8 ADC_EMUX_EM2_PWM3 PWM generator 3 0x9 ADC_EMUX_EM2_NEVER Never Trigger 0xe ADC_EMUX_EM2_ALWAYS Always (continuously sample) 0xf ADC_EMUX_EM3 SS3 Trigger Select 12 16 ADC_EMUX_EM3_PROCESSOR Processor (default) 0x0 ADC_EMUX_EM3_COMP0 Analog Comparator 0 0x1 ADC_EMUX_EM3_COMP1 Analog Comparator 1 0x2 ADC_EMUX_EM3_COMP2 Analog Comparator 2 0x3 ADC_EMUX_EM3_EXTERNAL External (GPIO Pins) 0x4 ADC_EMUX_EM3_TIMER Timer 0x5 ADC_EMUX_EM3_PWM0 PWM generator 0 0x6 ADC_EMUX_EM3_PWM1 PWM generator 1 0x7 ADC_EMUX_EM3_PWM2 PWM generator 2 0x8 ADC_EMUX_EM3_PWM3 PWM generator 3 0x9 ADC_EMUX_EM3_NEVER Never Trigger 0xe ADC_EMUX_EM3_ALWAYS Always (continuously sample) 0xf ADC0IM ADC Interrupt Mask 0x8 read-write n 0x0 0x0 ADC_IM_DCONSS0 Digital Comparator Interrupt on SS0 16 17 ADC_IM_DCONSS1 Digital Comparator Interrupt on SS1 17 18 ADC_IM_DCONSS2 Digital Comparator Interrupt on SS2 18 19 ADC_IM_DCONSS3 Digital Comparator Interrupt on SS3 19 20 ADC_IM_DMAMASK0 SS0 DMA Interrupt Mask 8 9 ADC_IM_DMAMASK1 SS1 DMA Interrupt Mask 9 10 ADC_IM_DMAMASK2 SS2 DMA Interrupt Mask 10 11 ADC_IM_DMAMASK3 SS3 DMA Interrupt Mask 11 12 ADC_IM_MASK0 SS0 Interrupt Mask 0 1 ADC_IM_MASK1 SS1 Interrupt Mask 1 2 ADC_IM_MASK2 SS2 Interrupt Mask 2 3 ADC_IM_MASK3 SS3 Interrupt Mask 3 4 ADC0ISC ADC Interrupt Status and Clear 0xC read-write n 0x0 0x0 ADC_ISC_DCINSS0 Digital Comparator Interrupt Status on SS0 16 17 ADC_ISC_DCINSS1 Digital Comparator Interrupt Status on SS1 17 18 ADC_ISC_DCINSS2 Digital Comparator Interrupt Status on SS2 18 19 ADC_ISC_DCINSS3 Digital Comparator Interrupt Status on SS3 19 20 ADC_ISC_DMAIN0 SS0 DMA Interrupt Status and Clear 8 9 ADC_ISC_DMAIN1 SS1 DMA Interrupt Status and Clear 9 10 ADC_ISC_DMAIN2 SS2 DMA Interrupt Status and Clear 10 11 ADC_ISC_DMAIN3 SS3 DMA Interrupt Status and Clear 11 12 ADC_ISC_IN0 SS0 Interrupt Status and Clear 0 1 ADC_ISC_IN1 SS1 Interrupt Status and Clear 1 2 ADC_ISC_IN2 SS2 Interrupt Status and Clear 2 3 ADC_ISC_IN3 SS3 Interrupt Status and Clear 3 4 ADC0OSTAT ADC Overflow Status 0x10 read-write n 0x0 0x0 ADC_OSTAT_OV0 SS0 FIFO Overflow 0 1 ADC_OSTAT_OV1 SS1 FIFO Overflow 1 2 ADC_OSTAT_OV2 SS2 FIFO Overflow 2 3 ADC_OSTAT_OV3 SS3 FIFO Overflow 3 4 ADC0PC ADC Peripheral Configuration 0xFC4 read-write n 0x0 0x0 ADC_PC_MCR Conversion Rate 0 4 ADC_PC_MCR_1_8 Eighth conversion rate. After a conversion completes, the logic pauses for 112 TADC periods before starting the next conversion 0x1 ADC_PC_MCR_1_4 Quarter conversion rate. After a conversion completes, the logic pauses for 48 TADC periods before starting the next conversion 0x3 ADC_PC_MCR_1_2 Half conversion rate. After a conversion completes, the logic pauses for 16 TADC periods before starting the next conversion 0x5 ADC_PC_MCR_FULL Full conversion rate (FCONV) as defined by TADC and NSH 0x7 ADC0PP ADC Peripheral Properties 0xFC0 read-write n 0x0 0x0 ADC_PP_APSHT Application-Programmable Sample-and-Hold Time 24 25 ADC_PP_CH ADC Channel Count 4 10 ADC_PP_DC Digital Comparator Count 10 16 ADC_PP_MCR Maximum Conversion Rate 0 4 ADC_PP_MCR_FULL Full conversion rate (FCONV) as defined by TADC and NSH 0x7 ADC_PP_RSL Resolution 18 23 ADC_PP_TS Temperature Sensor 23 24 ADC_PP_TYPE ADC Architecture 16 18 ADC_PP_TYPE_SAR SAR 0x0 ADC0PSSI ADC Processor Sample Sequence Initiate 0x28 read-write n 0x0 0x0 ADC_PSSI_GSYNC Global Synchronize 31 32 ADC_PSSI_SS0 SS0 Initiate 0 1 ADC_PSSI_SS1 SS1 Initiate 1 2 ADC_PSSI_SS2 SS2 Initiate 2 3 ADC_PSSI_SS3 SS3 Initiate 3 4 ADC_PSSI_SYNCWAIT Synchronize Wait 27 28 ADC0RIS ADC Raw Interrupt Status 0x4 read-write n 0x0 0x0 ADC_RIS_DMAINR0 SS0 DMA Raw Interrupt Status 8 9 ADC_RIS_DMAINR1 SS1 DMA Raw Interrupt Status 9 10 ADC_RIS_DMAINR2 SS2 DMA Raw Interrupt Status 10 11 ADC_RIS_DMAINR3 SS3 DMA Raw Interrupt Status 11 12 ADC_RIS_INR0 SS0 Raw Interrupt Status 0 1 ADC_RIS_INR1 SS1 Raw Interrupt Status 1 2 ADC_RIS_INR2 SS2 Raw Interrupt Status 2 3 ADC_RIS_INR3 SS3 Raw Interrupt Status 3 4 ADC_RIS_INRDC Digital Comparator Raw Interrupt Status 16 17 ADC0SAC ADC Sample Averaging Control 0x30 read-write n 0x0 0x0 ADC_SAC_AVG Hardware Averaging Control 0 3 ADC_SAC_AVG_OFF No hardware oversampling 0x0 ADC_SAC_AVG_2X 2x hardware oversampling 0x1 ADC_SAC_AVG_4X 4x hardware oversampling 0x2 ADC_SAC_AVG_8X 8x hardware oversampling 0x3 ADC_SAC_AVG_16X 16x hardware oversampling 0x4 ADC_SAC_AVG_32X 32x hardware oversampling 0x5 ADC_SAC_AVG_64X 64x hardware oversampling 0x6 ADC0SPC ADC Sample Phase Control 0x24 read-write n 0x0 0x0 ADC_SPC_PHASE Phase Difference 0 4 ADC_SPC_PHASE_0 ADC sample lags by 0.0 0x0 ADC_SPC_PHASE_22_5 ADC sample lags by 22.5 0x1 ADC_SPC_PHASE_45 ADC sample lags by 45.0 0x2 ADC_SPC_PHASE_67_5 ADC sample lags by 67.5 0x3 ADC_SPC_PHASE_90 ADC sample lags by 90.0 0x4 ADC_SPC_PHASE_112_5 ADC sample lags by 112.5 0x5 ADC_SPC_PHASE_135 ADC sample lags by 135.0 0x6 ADC_SPC_PHASE_157_5 ADC sample lags by 157.5 0x7 ADC_SPC_PHASE_180 ADC sample lags by 180.0 0x8 ADC_SPC_PHASE_202_5 ADC sample lags by 202.5 0x9 ADC_SPC_PHASE_225 ADC sample lags by 225.0 0xa ADC_SPC_PHASE_247_5 ADC sample lags by 247.5 0xb ADC_SPC_PHASE_270 ADC sample lags by 270.0 0xc ADC_SPC_PHASE_292_5 ADC sample lags by 292.5 0xd ADC_SPC_PHASE_315 ADC sample lags by 315.0 0xe ADC_SPC_PHASE_337_5 ADC sample lags by 337.5 0xf ADC0SSCTL0 ADC Sample Sequence Control 0 0x44 read-write n 0x0 0x0 ADC_SSCTL0_D0 1st Sample Differential Input Select 0 1 ADC_SSCTL0_D1 2nd Sample Differential Input Select 4 5 ADC_SSCTL0_D2 3rd Sample Differential Input Select 8 9 ADC_SSCTL0_D3 4th Sample Differential Input Select 12 13 ADC_SSCTL0_D4 5th Sample Differential Input Select 16 17 ADC_SSCTL0_D5 6th Sample Differential Input Select 20 21 ADC_SSCTL0_D6 7th Sample Differential Input Select 24 25 ADC_SSCTL0_D7 8th Sample Differential Input Select 28 29 ADC_SSCTL0_END0 1st Sample is End of Sequence 1 2 ADC_SSCTL0_END1 2nd Sample is End of Sequence 5 6 ADC_SSCTL0_END2 3rd Sample is End of Sequence 9 10 ADC_SSCTL0_END3 4th Sample is End of Sequence 13 14 ADC_SSCTL0_END4 5th Sample is End of Sequence 17 18 ADC_SSCTL0_END5 6th Sample is End of Sequence 21 22 ADC_SSCTL0_END6 7th Sample is End of Sequence 25 26 ADC_SSCTL0_END7 8th Sample is End of Sequence 29 30 ADC_SSCTL0_IE0 1st Sample Interrupt Enable 2 3 ADC_SSCTL0_IE1 2nd Sample Interrupt Enable 6 7 ADC_SSCTL0_IE2 3rd Sample Interrupt Enable 10 11 ADC_SSCTL0_IE3 4th Sample Interrupt Enable 14 15 ADC_SSCTL0_IE4 5th Sample Interrupt Enable 18 19 ADC_SSCTL0_IE5 6th Sample Interrupt Enable 22 23 ADC_SSCTL0_IE6 7th Sample Interrupt Enable 26 27 ADC_SSCTL0_IE7 8th Sample Interrupt Enable 30 31 ADC_SSCTL0_TS0 1st Sample Temp Sensor Select 3 4 ADC_SSCTL0_TS1 2nd Sample Temp Sensor Select 7 8 ADC_SSCTL0_TS2 3rd Sample Temp Sensor Select 11 12 ADC_SSCTL0_TS3 4th Sample Temp Sensor Select 15 16 ADC_SSCTL0_TS4 5th Sample Temp Sensor Select 19 20 ADC_SSCTL0_TS5 6th Sample Temp Sensor Select 23 24 ADC_SSCTL0_TS6 7th Sample Temp Sensor Select 27 28 ADC_SSCTL0_TS7 8th Sample Temp Sensor Select 31 32 ADC0SSCTL1 ADC Sample Sequence Control 1 0x64 read-write n 0x0 0x0 ADC_SSCTL1_D0 1st Sample Differential Input Select 0 1 ADC_SSCTL1_D1 2nd Sample Differential Input Select 4 5 ADC_SSCTL1_D2 3rd Sample Differential Input Select 8 9 ADC_SSCTL1_D3 4th Sample Differential Input Select 12 13 ADC_SSCTL1_END0 1st Sample is End of Sequence 1 2 ADC_SSCTL1_END1 2nd Sample is End of Sequence 5 6 ADC_SSCTL1_END2 3rd Sample is End of Sequence 9 10 ADC_SSCTL1_END3 4th Sample is End of Sequence 13 14 ADC_SSCTL1_IE0 1st Sample Interrupt Enable 2 3 ADC_SSCTL1_IE1 2nd Sample Interrupt Enable 6 7 ADC_SSCTL1_IE2 3rd Sample Interrupt Enable 10 11 ADC_SSCTL1_IE3 4th Sample Interrupt Enable 14 15 ADC_SSCTL1_TS0 1st Sample Temp Sensor Select 3 4 ADC_SSCTL1_TS1 2nd Sample Temp Sensor Select 7 8 ADC_SSCTL1_TS2 3rd Sample Temp Sensor Select 11 12 ADC_SSCTL1_TS3 4th Sample Temp Sensor Select 15 16 ADC0SSCTL2 ADC Sample Sequence Control 2 0x84 read-write n 0x0 0x0 ADC_SSCTL2_D0 1st Sample Differential Input Select 0 1 ADC_SSCTL2_D1 2nd Sample Differential Input Select 4 5 ADC_SSCTL2_D2 3rd Sample Differential Input Select 8 9 ADC_SSCTL2_D3 4th Sample Differential Input Select 12 13 ADC_SSCTL2_END0 1st Sample is End of Sequence 1 2 ADC_SSCTL2_END1 2nd Sample is End of Sequence 5 6 ADC_SSCTL2_END2 3rd Sample is End of Sequence 9 10 ADC_SSCTL2_END3 4th Sample is End of Sequence 13 14 ADC_SSCTL2_IE0 1st Sample Interrupt Enable 2 3 ADC_SSCTL2_IE1 2nd Sample Interrupt Enable 6 7 ADC_SSCTL2_IE2 3rd Sample Interrupt Enable 10 11 ADC_SSCTL2_IE3 4th Sample Interrupt Enable 14 15 ADC_SSCTL2_TS0 1st Sample Temp Sensor Select 3 4 ADC_SSCTL2_TS1 2nd Sample Temp Sensor Select 7 8 ADC_SSCTL2_TS2 3rd Sample Temp Sensor Select 11 12 ADC_SSCTL2_TS3 4th Sample Temp Sensor Select 15 16 ADC0SSCTL3 ADC Sample Sequence Control 3 0xA4 read-write n 0x0 0x0 ADC_SSCTL3_D0 Sample Differential Input Select 0 1 ADC_SSCTL3_END0 End of Sequence 1 2 ADC_SSCTL3_IE0 Sample Interrupt Enable 2 3 ADC_SSCTL3_TS0 1st Sample Temp Sensor Select 3 4 ADC0SSDC0 ADC Sample Sequence 0 Digital Comparator Select 0x54 read-write n 0x0 0x0 ADC_SSDC0_S0DCSEL Sample 0 Digital Comparator Select 0 4 ADC_SSDC0_S1DCSEL Sample 1 Digital Comparator Select 4 8 ADC_SSDC0_S2DCSEL Sample 2 Digital Comparator Select 8 12 ADC_SSDC0_S3DCSEL Sample 3 Digital Comparator Select 12 16 ADC_SSDC0_S4DCSEL Sample 4 Digital Comparator Select 16 20 ADC_SSDC0_S5DCSEL Sample 5 Digital Comparator Select 20 24 ADC_SSDC0_S6DCSEL Sample 6 Digital Comparator Select 24 28 ADC_SSDC0_S7DCSEL Sample 7 Digital Comparator Select 28 32 ADC0SSDC1 ADC Sample Sequence 1 Digital Comparator Select 0x74 read-write n 0x0 0x0 ADC_SSDC1_S0DCSEL Sample 0 Digital Comparator Select 0 4 ADC_SSDC1_S1DCSEL Sample 1 Digital Comparator Select 4 8 ADC_SSDC1_S2DCSEL Sample 2 Digital Comparator Select 8 12 ADC_SSDC1_S3DCSEL Sample 3 Digital Comparator Select 12 16 ADC0SSDC2 ADC Sample Sequence 2 Digital Comparator Select 0x94 read-write n 0x0 0x0 ADC_SSDC2_S0DCSEL Sample 0 Digital Comparator Select 0 4 ADC_SSDC2_S1DCSEL Sample 1 Digital Comparator Select 4 8 ADC_SSDC2_S2DCSEL Sample 2 Digital Comparator Select 8 12 ADC_SSDC2_S3DCSEL Sample 3 Digital Comparator Select 12 16 ADC0SSDC3 ADC Sample Sequence 3 Digital Comparator Select 0xB4 read-write n 0x0 0x0 ADC_SSDC3_S0DCSEL Sample 0 Digital Comparator Select 0 4 ADC0SSEMUX0 ADC Sample Sequence Extended Input Multiplexer Select 0 0x58 read-write n 0x0 0x0 ADC_SSEMUX0_EMUX0 1st Sample Input Select (Upper Bit) 0 1 ADC_SSEMUX0_EMUX1 2th Sample Input Select (Upper Bit) 4 5 ADC_SSEMUX0_EMUX2 3rd Sample Input Select (Upper Bit) 8 9 ADC_SSEMUX0_EMUX3 4th Sample Input Select (Upper Bit) 12 13 ADC_SSEMUX0_EMUX4 5th Sample Input Select (Upper Bit) 16 17 ADC_SSEMUX0_EMUX5 6th Sample Input Select (Upper Bit) 20 21 ADC_SSEMUX0_EMUX6 7th Sample Input Select (Upper Bit) 24 25 ADC_SSEMUX0_EMUX7 8th Sample Input Select (Upper Bit) 28 29 ADC0SSEMUX1 ADC Sample Sequence Extended Input Multiplexer Select 1 0x78 read-write n 0x0 0x0 ADC_SSEMUX1_EMUX0 1st Sample Input Select (Upper Bit) 0 1 ADC_SSEMUX1_EMUX1 2th Sample Input Select (Upper Bit) 4 5 ADC_SSEMUX1_EMUX2 3rd Sample Input Select (Upper Bit) 8 9 ADC_SSEMUX1_EMUX3 4th Sample Input Select (Upper Bit) 12 13 ADC0SSEMUX2 ADC Sample Sequence Extended Input Multiplexer Select 2 0x98 read-write n 0x0 0x0 ADC_SSEMUX2_EMUX0 1st Sample Input Select (Upper Bit) 0 1 ADC_SSEMUX2_EMUX1 2th Sample Input Select (Upper Bit) 4 5 ADC_SSEMUX2_EMUX2 3rd Sample Input Select (Upper Bit) 8 9 ADC_SSEMUX2_EMUX3 4th Sample Input Select (Upper Bit) 12 13 ADC0SSEMUX3 ADC Sample Sequence Extended Input Multiplexer Select 3 0xB8 read-write n 0x0 0x0 ADC_SSEMUX3_EMUX0 1st Sample Input Select (Upper Bit) 0 1 ADC0SSFIFO0 ADC Sample Sequence Result FIFO 0 0x48 read-write n 0x0 0x0 ADC_SSFIFO0_DATA Conversion Result Data 0 12 ADC0SSFIFO1 ADC Sample Sequence Result FIFO 1 0x68 read-write n 0x0 0x0 ADC_SSFIFO1_DATA Conversion Result Data 0 12 ADC0SSFIFO2 ADC Sample Sequence Result FIFO 2 0x88 read-write n 0x0 0x0 ADC_SSFIFO2_DATA Conversion Result Data 0 12 ADC0SSFIFO3 ADC Sample Sequence Result FIFO 3 0xA8 read-write n 0x0 0x0 ADC_SSFIFO3_DATA Conversion Result Data 0 12 ADC0SSFSTAT0 ADC Sample Sequence FIFO 0 Status 0x4C read-write n 0x0 0x0 ADC_SSFSTAT0_EMPTY FIFO Empty 8 9 ADC_SSFSTAT0_FULL FIFO Full 12 13 ADC_SSFSTAT0_HPTR FIFO Head Pointer 4 8 ADC_SSFSTAT0_TPTR FIFO Tail Pointer 0 4 ADC0SSFSTAT1 ADC Sample Sequence FIFO 1 Status 0x6C read-write n 0x0 0x0 ADC_SSFSTAT1_EMPTY FIFO Empty 8 9 ADC_SSFSTAT1_FULL FIFO Full 12 13 ADC_SSFSTAT1_HPTR FIFO Head Pointer 4 8 ADC_SSFSTAT1_TPTR FIFO Tail Pointer 0 4 ADC0SSFSTAT2 ADC Sample Sequence FIFO 2 Status 0x8C read-write n 0x0 0x0 ADC_SSFSTAT2_EMPTY FIFO Empty 8 9 ADC_SSFSTAT2_FULL FIFO Full 12 13 ADC_SSFSTAT2_HPTR FIFO Head Pointer 4 8 ADC_SSFSTAT2_TPTR FIFO Tail Pointer 0 4 ADC0SSFSTAT3 ADC Sample Sequence FIFO 3 Status 0xAC read-write n 0x0 0x0 ADC_SSFSTAT3_EMPTY FIFO Empty 8 9 ADC_SSFSTAT3_FULL FIFO Full 12 13 ADC_SSFSTAT3_HPTR FIFO Head Pointer 4 8 ADC_SSFSTAT3_TPTR FIFO Tail Pointer 0 4 ADC0SSMUX0 ADC Sample Sequence Input Multiplexer Select 0 0x40 read-write n 0x0 0x0 ADC_SSMUX0_MUX0 1st Sample Input Select 0 4 ADC_SSMUX0_MUX1 2nd Sample Input Select 4 8 ADC_SSMUX0_MUX2 3rd Sample Input Select 8 12 ADC_SSMUX0_MUX3 4th Sample Input Select 12 16 ADC_SSMUX0_MUX4 5th Sample Input Select 16 20 ADC_SSMUX0_MUX5 6th Sample Input Select 20 24 ADC_SSMUX0_MUX6 7th Sample Input Select 24 28 ADC_SSMUX0_MUX7 8th Sample Input Select 28 32 ADC0SSMUX1 ADC Sample Sequence Input Multiplexer Select 1 0x60 read-write n 0x0 0x0 ADC_SSMUX1_MUX0 1st Sample Input Select 0 4 ADC_SSMUX1_MUX1 2nd Sample Input Select 4 8 ADC_SSMUX1_MUX2 3rd Sample Input Select 8 12 ADC_SSMUX1_MUX3 4th Sample Input Select 12 16 ADC0SSMUX2 ADC Sample Sequence Input Multiplexer Select 2 0x80 read-write n 0x0 0x0 ADC_SSMUX2_MUX0 1st Sample Input Select 0 4 ADC_SSMUX2_MUX1 2nd Sample Input Select 4 8 ADC_SSMUX2_MUX2 3rd Sample Input Select 8 12 ADC_SSMUX2_MUX3 4th Sample Input Select 12 16 ADC0SSMUX3 ADC Sample Sequence Input Multiplexer Select 3 0xA0 read-write n 0x0 0x0 ADC_SSMUX3_MUX0 1st Sample Input Select 0 4 ADC0SSOP0 ADC Sample Sequence 0 Operation 0x50 read-write n 0x0 0x0 ADC_SSOP0_S0DCOP Sample 0 Digital Comparator Operation 0 1 ADC_SSOP0_S1DCOP Sample 1 Digital Comparator Operation 4 5 ADC_SSOP0_S2DCOP Sample 2 Digital Comparator Operation 8 9 ADC_SSOP0_S3DCOP Sample 3 Digital Comparator Operation 12 13 ADC_SSOP0_S4DCOP Sample 4 Digital Comparator Operation 16 17 ADC_SSOP0_S5DCOP Sample 5 Digital Comparator Operation 20 21 ADC_SSOP0_S6DCOP Sample 6 Digital Comparator Operation 24 25 ADC_SSOP0_S7DCOP Sample 7 Digital Comparator Operation 28 29 ADC0SSOP1 ADC Sample Sequence 1 Operation 0x70 read-write n 0x0 0x0 ADC_SSOP1_S0DCOP Sample 0 Digital Comparator Operation 0 1 ADC_SSOP1_S1DCOP Sample 1 Digital Comparator Operation 4 5 ADC_SSOP1_S2DCOP Sample 2 Digital Comparator Operation 8 9 ADC_SSOP1_S3DCOP Sample 3 Digital Comparator Operation 12 13 ADC0SSOP2 ADC Sample Sequence 2 Operation 0x90 read-write n 0x0 0x0 ADC_SSOP2_S0DCOP Sample 0 Digital Comparator Operation 0 1 ADC_SSOP2_S1DCOP Sample 1 Digital Comparator Operation 4 5 ADC_SSOP2_S2DCOP Sample 2 Digital Comparator Operation 8 9 ADC_SSOP2_S3DCOP Sample 3 Digital Comparator Operation 12 13 ADC0SSOP3 ADC Sample Sequence 3 Operation 0xB0 read-write n 0x0 0x0 ADC_SSOP3_S0DCOP Sample 0 Digital Comparator Operation 0 1 ADC0SSPRI ADC Sample Sequencer Priority 0x20 read-write n 0x0 0x0 ADC_SSPRI_SS0 SS0 Priority 0 2 ADC_SSPRI_SS1 SS1 Priority 4 6 ADC_SSPRI_SS2 SS2 Priority 8 10 ADC_SSPRI_SS3 SS3 Priority 12 14 ADC0SSTSH0 ADC Sample Sequence 0 Sample and Hold Time 0x5C read-write n 0x0 0x0 ADC_SSTSH0_TSH0 1st Sample and Hold Period Select 0 4 ADC_SSTSH0_TSH1 2nd Sample and Hold Period Select 4 8 ADC_SSTSH0_TSH2 3rd Sample and Hold Period Select 8 12 ADC_SSTSH0_TSH3 4th Sample and Hold Period Select 12 16 ADC_SSTSH0_TSH4 5th Sample and Hold Period Select 16 20 ADC_SSTSH0_TSH5 6th Sample and Hold Period Select 20 24 ADC_SSTSH0_TSH6 7th Sample and Hold Period Select 24 28 ADC_SSTSH0_TSH7 8th Sample and Hold Period Select 28 32 ADC0SSTSH1 ADC Sample Sequence 1 Sample and Hold Time 0x7C read-write n 0x0 0x0 ADC_SSTSH1_TSH0 1st Sample and Hold Period Select 0 4 ADC_SSTSH1_TSH1 2nd Sample and Hold Period Select 4 8 ADC_SSTSH1_TSH2 3rd Sample and Hold Period Select 8 12 ADC_SSTSH1_TSH3 4th Sample and Hold Period Select 12 16 ADC0SSTSH2 ADC Sample Sequence 2 Sample and Hold Time 0x9C read-write n 0x0 0x0 ADC_SSTSH2_TSH0 1st Sample and Hold Period Select 0 4 ADC_SSTSH2_TSH1 2nd Sample and Hold Period Select 4 8 ADC_SSTSH2_TSH2 3rd Sample and Hold Period Select 8 12 ADC_SSTSH2_TSH3 4th Sample and Hold Period Select 12 16 ADC0SSTSH3 ADC Sample Sequence 3 Sample and Hold Time 0xBC read-write n 0x0 0x0 ADC_SSTSH3_TSH0 1st Sample and Hold Period Select 0 4 ADC0TSSEL ADC Trigger Source Select 0x1C read-write n 0x0 0x0 ADC_TSSEL_PS0 Generator 0 PWM Module Trigger Select 4 6 ADC_TSSEL_PS0_0 Use Generator 0 (and its trigger) in PWM module 0 0x0 ADC_TSSEL_PS1 Generator 1 PWM Module Trigger Select 12 14 ADC_TSSEL_PS1_0 Use Generator 1 (and its trigger) in PWM module 0 0x0 ADC_TSSEL_PS2 Generator 2 PWM Module Trigger Select 20 22 ADC_TSSEL_PS2_0 Use Generator 2 (and its trigger) in PWM module 0 0x0 ADC_TSSEL_PS3 Generator 3 PWM Module Trigger Select 28 30 ADC_TSSEL_PS3_0 Use Generator 3 (and its trigger) in PWM module 0 0x0 ADC0USTAT ADC Underflow Status 0x18 read-write n 0x0 0x0 ADC_USTAT_UV0 SS0 FIFO Underflow 0 1 ADC_USTAT_UV1 SS1 FIFO Underflow 1 2 ADC_USTAT_UV2 SS2 FIFO Underflow 2 3 ADC_USTAT_UV3 SS3 FIFO Underflow 3 4 CC ADC Clock Configuration 0xFC8 -1 read-write n 0x0 0x0 ADC_CC_CLKDIV PLL VCO Clock Divisor 4 10 ADC_CC_CS ADC Clock Source 0 4 ADC_CC_CS_SYSPLL PLL VCO divided by CLKDIV 0x0 ADC_CC_CS_PIOSC PIOSC 0x1 ADC_CC_CS_MOSC MOSC 0x2 CTL ADC Control 0x38 -1 read-write n 0x0 0x0 ADC_CTL_DITHER Dither Mode Enable 6 7 ADC_CTL_VREF Voltage Reference Select 0 1 ADC_CTL_VREF_INTERNAL VDDA and GNDA are the voltage references 0x0 ADC_CTL_VREF_EXT_3V The external VREFA+ and VREFA- inputs are the voltage references 0x1 DCCMP0 ADC Digital Comparator Range 0 0xE40 -1 read-write n 0x0 0x0 ADC_DCCMP0_COMP0 Compare 0 0 12 ADC_DCCMP0_COMP1 Compare 1 16 28 DCCMP1 ADC Digital Comparator Range 1 0xE44 -1 read-write n 0x0 0x0 ADC_DCCMP1_COMP0 Compare 0 0 12 ADC_DCCMP1_COMP1 Compare 1 16 28 DCCMP2 ADC Digital Comparator Range 2 0xE48 -1 read-write n 0x0 0x0 ADC_DCCMP2_COMP0 Compare 0 0 12 ADC_DCCMP2_COMP1 Compare 1 16 28 DCCMP3 ADC Digital Comparator Range 3 0xE4C -1 read-write n 0x0 0x0 ADC_DCCMP3_COMP0 Compare 0 0 12 ADC_DCCMP3_COMP1 Compare 1 16 28 DCCMP4 ADC Digital Comparator Range 4 0xE50 -1 read-write n 0x0 0x0 ADC_DCCMP4_COMP0 Compare 0 0 12 ADC_DCCMP4_COMP1 Compare 1 16 28 DCCMP5 ADC Digital Comparator Range 5 0xE54 -1 read-write n 0x0 0x0 ADC_DCCMP5_COMP0 Compare 0 0 12 ADC_DCCMP5_COMP1 Compare 1 16 28 DCCMP6 ADC Digital Comparator Range 6 0xE58 -1 read-write n 0x0 0x0 ADC_DCCMP6_COMP0 Compare 0 0 12 ADC_DCCMP6_COMP1 Compare 1 16 28 DCCMP7 ADC Digital Comparator Range 7 0xE5C -1 read-write n 0x0 0x0 ADC_DCCMP7_COMP0 Compare 0 0 12 ADC_DCCMP7_COMP1 Compare 1 16 28 DCCTL0 ADC Digital Comparator Control 0 0xE00 -1 read-write n 0x0 0x0 ADC_DCCTL0_CIC Comparison Interrupt Condition 2 4 ADC_DCCTL0_CIC_LOW Low Band 0x0 ADC_DCCTL0_CIC_MID Mid Band 0x1 ADC_DCCTL0_CIC_HIGH High Band 0x3 ADC_DCCTL0_CIE Comparison Interrupt Enable 4 5 ADC_DCCTL0_CIM Comparison Interrupt Mode 0 2 ADC_DCCTL0_CIM_ALWAYS Always 0x0 ADC_DCCTL0_CIM_ONCE Once 0x1 ADC_DCCTL0_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL0_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL0_CTC Comparison Trigger Condition 10 12 ADC_DCCTL0_CTC_LOW Low Band 0x0 ADC_DCCTL0_CTC_MID Mid Band 0x1 ADC_DCCTL0_CTC_HIGH High Band 0x3 ADC_DCCTL0_CTE Comparison Trigger Enable 12 13 ADC_DCCTL0_CTM Comparison Trigger Mode 8 10 ADC_DCCTL0_CTM_ALWAYS Always 0x0 ADC_DCCTL0_CTM_ONCE Once 0x1 ADC_DCCTL0_CTM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL0_CTM_HONCE Hysteresis Once 0x3 DCCTL1 ADC Digital Comparator Control 1 0xE04 -1 read-write n 0x0 0x0 ADC_DCCTL1_CIC Comparison Interrupt Condition 2 4 ADC_DCCTL1_CIC_LOW Low Band 0x0 ADC_DCCTL1_CIC_MID Mid Band 0x1 ADC_DCCTL1_CIC_HIGH High Band 0x3 ADC_DCCTL1_CIE Comparison Interrupt Enable 4 5 ADC_DCCTL1_CIM Comparison Interrupt Mode 0 2 ADC_DCCTL1_CIM_ALWAYS Always 0x0 ADC_DCCTL1_CIM_ONCE Once 0x1 ADC_DCCTL1_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL1_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL1_CTC Comparison Trigger Condition 10 12 ADC_DCCTL1_CTC_LOW Low Band 0x0 ADC_DCCTL1_CTC_MID Mid Band 0x1 ADC_DCCTL1_CTC_HIGH High Band 0x3 ADC_DCCTL1_CTE Comparison Trigger Enable 12 13 ADC_DCCTL1_CTM Comparison Trigger Mode 8 10 ADC_DCCTL1_CTM_ALWAYS Always 0x0 ADC_DCCTL1_CTM_ONCE Once 0x1 ADC_DCCTL1_CTM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL1_CTM_HONCE Hysteresis Once 0x3 DCCTL2 ADC Digital Comparator Control 2 0xE08 -1 read-write n 0x0 0x0 ADC_DCCTL2_CIC Comparison Interrupt Condition 2 4 ADC_DCCTL2_CIC_LOW Low Band 0x0 ADC_DCCTL2_CIC_MID Mid Band 0x1 ADC_DCCTL2_CIC_HIGH High Band 0x3 ADC_DCCTL2_CIE Comparison Interrupt Enable 4 5 ADC_DCCTL2_CIM Comparison Interrupt Mode 0 2 ADC_DCCTL2_CIM_ALWAYS Always 0x0 ADC_DCCTL2_CIM_ONCE Once 0x1 ADC_DCCTL2_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL2_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL2_CTC Comparison Trigger Condition 10 12 ADC_DCCTL2_CTC_LOW Low Band 0x0 ADC_DCCTL2_CTC_MID Mid Band 0x1 ADC_DCCTL2_CTC_HIGH High Band 0x3 ADC_DCCTL2_CTE Comparison Trigger Enable 12 13 ADC_DCCTL2_CTM Comparison Trigger Mode 8 10 ADC_DCCTL2_CTM_ALWAYS Always 0x0 ADC_DCCTL2_CTM_ONCE Once 0x1 ADC_DCCTL2_CTM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL2_CTM_HONCE Hysteresis Once 0x3 DCCTL3 ADC Digital Comparator Control 3 0xE0C -1 read-write n 0x0 0x0 ADC_DCCTL3_CIC Comparison Interrupt Condition 2 4 ADC_DCCTL3_CIC_LOW Low Band 0x0 ADC_DCCTL3_CIC_MID Mid Band 0x1 ADC_DCCTL3_CIC_HIGH High Band 0x3 ADC_DCCTL3_CIE Comparison Interrupt Enable 4 5 ADC_DCCTL3_CIM Comparison Interrupt Mode 0 2 ADC_DCCTL3_CIM_ALWAYS Always 0x0 ADC_DCCTL3_CIM_ONCE Once 0x1 ADC_DCCTL3_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL3_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL3_CTC Comparison Trigger Condition 10 12 ADC_DCCTL3_CTC_LOW Low Band 0x0 ADC_DCCTL3_CTC_MID Mid Band 0x1 ADC_DCCTL3_CTC_HIGH High Band 0x3 ADC_DCCTL3_CTE Comparison Trigger Enable 12 13 ADC_DCCTL3_CTM Comparison Trigger Mode 8 10 ADC_DCCTL3_CTM_ALWAYS Always 0x0 ADC_DCCTL3_CTM_ONCE Once 0x1 ADC_DCCTL3_CTM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL3_CTM_HONCE Hysteresis Once 0x3 DCCTL4 ADC Digital Comparator Control 4 0xE10 -1 read-write n 0x0 0x0 ADC_DCCTL4_CIC Comparison Interrupt Condition 2 4 ADC_DCCTL4_CIC_LOW Low Band 0x0 ADC_DCCTL4_CIC_MID Mid Band 0x1 ADC_DCCTL4_CIC_HIGH High Band 0x3 ADC_DCCTL4_CIE Comparison Interrupt Enable 4 5 ADC_DCCTL4_CIM Comparison Interrupt Mode 0 2 ADC_DCCTL4_CIM_ALWAYS Always 0x0 ADC_DCCTL4_CIM_ONCE Once 0x1 ADC_DCCTL4_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL4_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL4_CTC Comparison Trigger Condition 10 12 ADC_DCCTL4_CTC_LOW Low Band 0x0 ADC_DCCTL4_CTC_MID Mid Band 0x1 ADC_DCCTL4_CTC_HIGH High Band 0x3 ADC_DCCTL4_CTE Comparison Trigger Enable 12 13 ADC_DCCTL4_CTM Comparison Trigger Mode 8 10 ADC_DCCTL4_CTM_ALWAYS Always 0x0 ADC_DCCTL4_CTM_ONCE Once 0x1 ADC_DCCTL4_CTM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL4_CTM_HONCE Hysteresis Once 0x3 DCCTL5 ADC Digital Comparator Control 5 0xE14 -1 read-write n 0x0 0x0 ADC_DCCTL5_CIC Comparison Interrupt Condition 2 4 ADC_DCCTL5_CIC_LOW Low Band 0x0 ADC_DCCTL5_CIC_MID Mid Band 0x1 ADC_DCCTL5_CIC_HIGH High Band 0x3 ADC_DCCTL5_CIE Comparison Interrupt Enable 4 5 ADC_DCCTL5_CIM Comparison Interrupt Mode 0 2 ADC_DCCTL5_CIM_ALWAYS Always 0x0 ADC_DCCTL5_CIM_ONCE Once 0x1 ADC_DCCTL5_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL5_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL5_CTC Comparison Trigger Condition 10 12 ADC_DCCTL5_CTC_LOW Low Band 0x0 ADC_DCCTL5_CTC_MID Mid Band 0x1 ADC_DCCTL5_CTC_HIGH High Band 0x3 ADC_DCCTL5_CTE Comparison Trigger Enable 12 13 ADC_DCCTL5_CTM Comparison Trigger Mode 8 10 ADC_DCCTL5_CTM_ALWAYS Always 0x0 ADC_DCCTL5_CTM_ONCE Once 0x1 ADC_DCCTL5_CTM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL5_CTM_HONCE Hysteresis Once 0x3 DCCTL6 ADC Digital Comparator Control 6 0xE18 -1 read-write n 0x0 0x0 ADC_DCCTL6_CIC Comparison Interrupt Condition 2 4 ADC_DCCTL6_CIC_LOW Low Band 0x0 ADC_DCCTL6_CIC_MID Mid Band 0x1 ADC_DCCTL6_CIC_HIGH High Band 0x3 ADC_DCCTL6_CIE Comparison Interrupt Enable 4 5 ADC_DCCTL6_CIM Comparison Interrupt Mode 0 2 ADC_DCCTL6_CIM_ALWAYS Always 0x0 ADC_DCCTL6_CIM_ONCE Once 0x1 ADC_DCCTL6_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL6_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL6_CTC Comparison Trigger Condition 10 12 ADC_DCCTL6_CTC_LOW Low Band 0x0 ADC_DCCTL6_CTC_MID Mid Band 0x1 ADC_DCCTL6_CTC_HIGH High Band 0x3 ADC_DCCTL6_CTE Comparison Trigger Enable 12 13 ADC_DCCTL6_CTM Comparison Trigger Mode 8 10 ADC_DCCTL6_CTM_ALWAYS Always 0x0 ADC_DCCTL6_CTM_ONCE Once 0x1 ADC_DCCTL6_CTM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL6_CTM_HONCE Hysteresis Once 0x3 DCCTL7 ADC Digital Comparator Control 7 0xE1C -1 read-write n 0x0 0x0 ADC_DCCTL7_CIC Comparison Interrupt Condition 2 4 ADC_DCCTL7_CIC_LOW Low Band 0x0 ADC_DCCTL7_CIC_MID Mid Band 0x1 ADC_DCCTL7_CIC_HIGH High Band 0x3 ADC_DCCTL7_CIE Comparison Interrupt Enable 4 5 ADC_DCCTL7_CIM Comparison Interrupt Mode 0 2 ADC_DCCTL7_CIM_ALWAYS Always 0x0 ADC_DCCTL7_CIM_ONCE Once 0x1 ADC_DCCTL7_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL7_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL7_CTC Comparison Trigger Condition 10 12 ADC_DCCTL7_CTC_LOW Low Band 0x0 ADC_DCCTL7_CTC_MID Mid Band 0x1 ADC_DCCTL7_CTC_HIGH High Band 0x3 ADC_DCCTL7_CTE Comparison Trigger Enable 12 13 ADC_DCCTL7_CTM Comparison Trigger Mode 8 10 ADC_DCCTL7_CTM_ALWAYS Always 0x0 ADC_DCCTL7_CTM_ONCE Once 0x1 ADC_DCCTL7_CTM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL7_CTM_HONCE Hysteresis Once 0x3 DCISC ADC Digital Comparator Interrupt Status and Clear 0x34 -1 read-write n 0x0 0x0 ADC_DCISC_DCINT0 Digital Comparator 0 Interrupt Status and Clear 0 1 ADC_DCISC_DCINT1 Digital Comparator 1 Interrupt Status and Clear 1 2 ADC_DCISC_DCINT2 Digital Comparator 2 Interrupt Status and Clear 2 3 ADC_DCISC_DCINT3 Digital Comparator 3 Interrupt Status and Clear 3 4 ADC_DCISC_DCINT4 Digital Comparator 4 Interrupt Status and Clear 4 5 ADC_DCISC_DCINT5 Digital Comparator 5 Interrupt Status and Clear 5 6 ADC_DCISC_DCINT6 Digital Comparator 6 Interrupt Status and Clear 6 7 ADC_DCISC_DCINT7 Digital Comparator 7 Interrupt Status and Clear 7 8 DCRIC ADC Digital Comparator Reset Initial Conditions 0xD00 -1 write-only n 0x0 0x0 ADC_DCRIC_DCINT0 Digital Comparator Interrupt 0 0 1 write-only ADC_DCRIC_DCINT1 Digital Comparator Interrupt 1 1 2 write-only ADC_DCRIC_DCINT2 Digital Comparator Interrupt 2 2 3 write-only ADC_DCRIC_DCINT3 Digital Comparator Interrupt 3 3 4 write-only ADC_DCRIC_DCINT4 Digital Comparator Interrupt 4 4 5 write-only ADC_DCRIC_DCINT5 Digital Comparator Interrupt 5 5 6 write-only ADC_DCRIC_DCINT6 Digital Comparator Interrupt 6 6 7 write-only ADC_DCRIC_DCINT7 Digital Comparator Interrupt 7 7 8 write-only ADC_DCRIC_DCTRIG0 Digital Comparator Trigger 0 16 17 write-only ADC_DCRIC_DCTRIG1 Digital Comparator Trigger 1 17 18 write-only ADC_DCRIC_DCTRIG2 Digital Comparator Trigger 2 18 19 write-only ADC_DCRIC_DCTRIG3 Digital Comparator Trigger 3 19 20 write-only ADC_DCRIC_DCTRIG4 Digital Comparator Trigger 4 20 21 write-only ADC_DCRIC_DCTRIG5 Digital Comparator Trigger 5 21 22 write-only ADC_DCRIC_DCTRIG6 Digital Comparator Trigger 6 22 23 write-only ADC_DCRIC_DCTRIG7 Digital Comparator Trigger 7 23 24 write-only EMUX ADC Event Multiplexer Select 0x14 -1 read-write n 0x0 0x0 ADC_EMUX_EM0 SS0 Trigger Select 0 4 ADC_EMUX_EM0_PROCESSOR Processor (default) 0x0 ADC_EMUX_EM0_COMP0 Analog Comparator 0 0x1 ADC_EMUX_EM0_COMP1 Analog Comparator 1 0x2 ADC_EMUX_EM0_COMP2 Analog Comparator 2 0x3 ADC_EMUX_EM0_EXTERNAL External (GPIO Pins) 0x4 ADC_EMUX_EM0_TIMER Timer 0x5 ADC_EMUX_EM0_PWM0 PWM generator 0 0x6 ADC_EMUX_EM0_PWM1 PWM generator 1 0x7 ADC_EMUX_EM0_PWM2 PWM generator 2 0x8 ADC_EMUX_EM0_PWM3 PWM generator 3 0x9 ADC_EMUX_EM0_NEVER Never Trigger 0xe ADC_EMUX_EM0_ALWAYS Always (continuously sample) 0xf ADC_EMUX_EM1 SS1 Trigger Select 4 8 ADC_EMUX_EM1_PROCESSOR Processor (default) 0x0 ADC_EMUX_EM1_COMP0 Analog Comparator 0 0x1 ADC_EMUX_EM1_COMP1 Analog Comparator 1 0x2 ADC_EMUX_EM1_COMP2 Analog Comparator 2 0x3 ADC_EMUX_EM1_EXTERNAL External (GPIO Pins) 0x4 ADC_EMUX_EM1_TIMER Timer 0x5 ADC_EMUX_EM1_PWM0 PWM generator 0 0x6 ADC_EMUX_EM1_PWM1 PWM generator 1 0x7 ADC_EMUX_EM1_PWM2 PWM generator 2 0x8 ADC_EMUX_EM1_PWM3 PWM generator 3 0x9 ADC_EMUX_EM1_NEVER Never Trigger 0xe ADC_EMUX_EM1_ALWAYS Always (continuously sample) 0xf ADC_EMUX_EM2 SS2 Trigger Select 8 12 ADC_EMUX_EM2_PROCESSOR Processor (default) 0x0 ADC_EMUX_EM2_COMP0 Analog Comparator 0 0x1 ADC_EMUX_EM2_COMP1 Analog Comparator 1 0x2 ADC_EMUX_EM2_COMP2 Analog Comparator 2 0x3 ADC_EMUX_EM2_EXTERNAL External (GPIO Pins) 0x4 ADC_EMUX_EM2_TIMER Timer 0x5 ADC_EMUX_EM2_PWM0 PWM generator 0 0x6 ADC_EMUX_EM2_PWM1 PWM generator 1 0x7 ADC_EMUX_EM2_PWM2 PWM generator 2 0x8 ADC_EMUX_EM2_PWM3 PWM generator 3 0x9 ADC_EMUX_EM2_NEVER Never Trigger 0xe ADC_EMUX_EM2_ALWAYS Always (continuously sample) 0xf ADC_EMUX_EM3 SS3 Trigger Select 12 16 ADC_EMUX_EM3_PROCESSOR Processor (default) 0x0 ADC_EMUX_EM3_COMP0 Analog Comparator 0 0x1 ADC_EMUX_EM3_COMP1 Analog Comparator 1 0x2 ADC_EMUX_EM3_COMP2 Analog Comparator 2 0x3 ADC_EMUX_EM3_EXTERNAL External (GPIO Pins) 0x4 ADC_EMUX_EM3_TIMER Timer 0x5 ADC_EMUX_EM3_PWM0 PWM generator 0 0x6 ADC_EMUX_EM3_PWM1 PWM generator 1 0x7 ADC_EMUX_EM3_PWM2 PWM generator 2 0x8 ADC_EMUX_EM3_PWM3 PWM generator 3 0x9 ADC_EMUX_EM3_NEVER Never Trigger 0xe ADC_EMUX_EM3_ALWAYS Always (continuously sample) 0xf IM ADC Interrupt Mask 0x8 -1 read-write n 0x0 0x0 ADC_IM_DCONSS0 Digital Comparator Interrupt on SS0 16 17 ADC_IM_DCONSS1 Digital Comparator Interrupt on SS1 17 18 ADC_IM_DCONSS2 Digital Comparator Interrupt on SS2 18 19 ADC_IM_DCONSS3 Digital Comparator Interrupt on SS3 19 20 ADC_IM_DMAMASK0 SS0 DMA Interrupt Mask 8 9 ADC_IM_DMAMASK1 SS1 DMA Interrupt Mask 9 10 ADC_IM_DMAMASK2 SS2 DMA Interrupt Mask 10 11 ADC_IM_DMAMASK3 SS3 DMA Interrupt Mask 11 12 ADC_IM_MASK0 SS0 Interrupt Mask 0 1 ADC_IM_MASK1 SS1 Interrupt Mask 1 2 ADC_IM_MASK2 SS2 Interrupt Mask 2 3 ADC_IM_MASK3 SS3 Interrupt Mask 3 4 ISC ADC Interrupt Status and Clear 0xC -1 read-write n 0x0 0x0 ADC_ISC_DCINSS0 Digital Comparator Interrupt Status on SS0 16 17 ADC_ISC_DCINSS1 Digital Comparator Interrupt Status on SS1 17 18 ADC_ISC_DCINSS2 Digital Comparator Interrupt Status on SS2 18 19 ADC_ISC_DCINSS3 Digital Comparator Interrupt Status on SS3 19 20 ADC_ISC_DMAIN0 SS0 DMA Interrupt Status and Clear 8 9 ADC_ISC_DMAIN1 SS1 DMA Interrupt Status and Clear 9 10 ADC_ISC_DMAIN2 SS2 DMA Interrupt Status and Clear 10 11 ADC_ISC_DMAIN3 SS3 DMA Interrupt Status and Clear 11 12 ADC_ISC_IN0 SS0 Interrupt Status and Clear 0 1 ADC_ISC_IN1 SS1 Interrupt Status and Clear 1 2 ADC_ISC_IN2 SS2 Interrupt Status and Clear 2 3 ADC_ISC_IN3 SS3 Interrupt Status and Clear 3 4 OSTAT ADC Overflow Status 0x10 -1 read-write n 0x0 0x0 ADC_OSTAT_OV0 SS0 FIFO Overflow 0 1 ADC_OSTAT_OV1 SS1 FIFO Overflow 1 2 ADC_OSTAT_OV2 SS2 FIFO Overflow 2 3 ADC_OSTAT_OV3 SS3 FIFO Overflow 3 4 PC ADC Peripheral Configuration 0xFC4 -1 read-write n 0x0 0x0 ADC_PC_MCR Conversion Rate 0 4 ADC_PC_MCR_1_8 Eighth conversion rate. After a conversion completes, the logic pauses for 112 TADC periods before starting the next conversion 0x1 ADC_PC_MCR_1_4 Quarter conversion rate. After a conversion completes, the logic pauses for 48 TADC periods before starting the next conversion 0x3 ADC_PC_MCR_1_2 Half conversion rate. After a conversion completes, the logic pauses for 16 TADC periods before starting the next conversion 0x5 ADC_PC_MCR_FULL Full conversion rate (FCONV) as defined by TADC and NSH 0x7 PP ADC Peripheral Properties 0xFC0 -1 read-write n 0x0 0x0 ADC_PP_APSHT Application-Programmable Sample-and-Hold Time 24 25 ADC_PP_CH ADC Channel Count 4 10 ADC_PP_DC Digital Comparator Count 10 16 ADC_PP_MCR Maximum Conversion Rate 0 4 ADC_PP_MCR_FULL Full conversion rate (FCONV) as defined by TADC and NSH 0x7 ADC_PP_RSL Resolution 18 23 ADC_PP_TS Temperature Sensor 23 24 ADC_PP_TYPE ADC Architecture 16 18 ADC_PP_TYPE_SAR SAR 0x0 PSSI ADC Processor Sample Sequence Initiate 0x28 -1 read-write n 0x0 0x0 ADC_PSSI_GSYNC Global Synchronize 31 32 ADC_PSSI_SS0 SS0 Initiate 0 1 ADC_PSSI_SS1 SS1 Initiate 1 2 ADC_PSSI_SS2 SS2 Initiate 2 3 ADC_PSSI_SS3 SS3 Initiate 3 4 ADC_PSSI_SYNCWAIT Synchronize Wait 27 28 RIS ADC Raw Interrupt Status 0x4 -1 read-write n 0x0 0x0 ADC_RIS_DMAINR0 SS0 DMA Raw Interrupt Status 8 9 ADC_RIS_DMAINR1 SS1 DMA Raw Interrupt Status 9 10 ADC_RIS_DMAINR2 SS2 DMA Raw Interrupt Status 10 11 ADC_RIS_DMAINR3 SS3 DMA Raw Interrupt Status 11 12 ADC_RIS_INR0 SS0 Raw Interrupt Status 0 1 ADC_RIS_INR1 SS1 Raw Interrupt Status 1 2 ADC_RIS_INR2 SS2 Raw Interrupt Status 2 3 ADC_RIS_INR3 SS3 Raw Interrupt Status 3 4 ADC_RIS_INRDC Digital Comparator Raw Interrupt Status 16 17 SAC ADC Sample Averaging Control 0x30 -1 read-write n 0x0 0x0 ADC_SAC_AVG Hardware Averaging Control 0 3 ADC_SAC_AVG_OFF No hardware oversampling 0x0 ADC_SAC_AVG_2X 2x hardware oversampling 0x1 ADC_SAC_AVG_4X 4x hardware oversampling 0x2 ADC_SAC_AVG_8X 8x hardware oversampling 0x3 ADC_SAC_AVG_16X 16x hardware oversampling 0x4 ADC_SAC_AVG_32X 32x hardware oversampling 0x5 ADC_SAC_AVG_64X 64x hardware oversampling 0x6 SPC ADC Sample Phase Control 0x24 -1 read-write n 0x0 0x0 ADC_SPC_PHASE Phase Difference 0 4 ADC_SPC_PHASE_0 ADC sample lags by 0.0 0x0 ADC_SPC_PHASE_22_5 ADC sample lags by 22.5 0x1 ADC_SPC_PHASE_45 ADC sample lags by 45.0 0x2 ADC_SPC_PHASE_67_5 ADC sample lags by 67.5 0x3 ADC_SPC_PHASE_90 ADC sample lags by 90.0 0x4 ADC_SPC_PHASE_112_5 ADC sample lags by 112.5 0x5 ADC_SPC_PHASE_135 ADC sample lags by 135.0 0x6 ADC_SPC_PHASE_157_5 ADC sample lags by 157.5 0x7 ADC_SPC_PHASE_180 ADC sample lags by 180.0 0x8 ADC_SPC_PHASE_202_5 ADC sample lags by 202.5 0x9 ADC_SPC_PHASE_225 ADC sample lags by 225.0 0xa ADC_SPC_PHASE_247_5 ADC sample lags by 247.5 0xb ADC_SPC_PHASE_270 ADC sample lags by 270.0 0xc ADC_SPC_PHASE_292_5 ADC sample lags by 292.5 0xd ADC_SPC_PHASE_315 ADC sample lags by 315.0 0xe ADC_SPC_PHASE_337_5 ADC sample lags by 337.5 0xf SSCTL0 ADC Sample Sequence Control 0 0x44 -1 read-write n 0x0 0x0 ADC_SSCTL0_D0 1st Sample Differential Input Select 0 1 ADC_SSCTL0_D1 2nd Sample Differential Input Select 4 5 ADC_SSCTL0_D2 3rd Sample Differential Input Select 8 9 ADC_SSCTL0_D3 4th Sample Differential Input Select 12 13 ADC_SSCTL0_D4 5th Sample Differential Input Select 16 17 ADC_SSCTL0_D5 6th Sample Differential Input Select 20 21 ADC_SSCTL0_D6 7th Sample Differential Input Select 24 25 ADC_SSCTL0_D7 8th Sample Differential Input Select 28 29 ADC_SSCTL0_END0 1st Sample is End of Sequence 1 2 ADC_SSCTL0_END1 2nd Sample is End of Sequence 5 6 ADC_SSCTL0_END2 3rd Sample is End of Sequence 9 10 ADC_SSCTL0_END3 4th Sample is End of Sequence 13 14 ADC_SSCTL0_END4 5th Sample is End of Sequence 17 18 ADC_SSCTL0_END5 6th Sample is End of Sequence 21 22 ADC_SSCTL0_END6 7th Sample is End of Sequence 25 26 ADC_SSCTL0_END7 8th Sample is End of Sequence 29 30 ADC_SSCTL0_IE0 1st Sample Interrupt Enable 2 3 ADC_SSCTL0_IE1 2nd Sample Interrupt Enable 6 7 ADC_SSCTL0_IE2 3rd Sample Interrupt Enable 10 11 ADC_SSCTL0_IE3 4th Sample Interrupt Enable 14 15 ADC_SSCTL0_IE4 5th Sample Interrupt Enable 18 19 ADC_SSCTL0_IE5 6th Sample Interrupt Enable 22 23 ADC_SSCTL0_IE6 7th Sample Interrupt Enable 26 27 ADC_SSCTL0_IE7 8th Sample Interrupt Enable 30 31 ADC_SSCTL0_TS0 1st Sample Temp Sensor Select 3 4 ADC_SSCTL0_TS1 2nd Sample Temp Sensor Select 7 8 ADC_SSCTL0_TS2 3rd Sample Temp Sensor Select 11 12 ADC_SSCTL0_TS3 4th Sample Temp Sensor Select 15 16 ADC_SSCTL0_TS4 5th Sample Temp Sensor Select 19 20 ADC_SSCTL0_TS5 6th Sample Temp Sensor Select 23 24 ADC_SSCTL0_TS6 7th Sample Temp Sensor Select 27 28 ADC_SSCTL0_TS7 8th Sample Temp Sensor Select 31 32 SSCTL1 ADC Sample Sequence Control 1 0x64 -1 read-write n 0x0 0x0 ADC_SSCTL1_D0 1st Sample Differential Input Select 0 1 ADC_SSCTL1_D1 2nd Sample Differential Input Select 4 5 ADC_SSCTL1_D2 3rd Sample Differential Input Select 8 9 ADC_SSCTL1_D3 4th Sample Differential Input Select 12 13 ADC_SSCTL1_END0 1st Sample is End of Sequence 1 2 ADC_SSCTL1_END1 2nd Sample is End of Sequence 5 6 ADC_SSCTL1_END2 3rd Sample is End of Sequence 9 10 ADC_SSCTL1_END3 4th Sample is End of Sequence 13 14 ADC_SSCTL1_IE0 1st Sample Interrupt Enable 2 3 ADC_SSCTL1_IE1 2nd Sample Interrupt Enable 6 7 ADC_SSCTL1_IE2 3rd Sample Interrupt Enable 10 11 ADC_SSCTL1_IE3 4th Sample Interrupt Enable 14 15 ADC_SSCTL1_TS0 1st Sample Temp Sensor Select 3 4 ADC_SSCTL1_TS1 2nd Sample Temp Sensor Select 7 8 ADC_SSCTL1_TS2 3rd Sample Temp Sensor Select 11 12 ADC_SSCTL1_TS3 4th Sample Temp Sensor Select 15 16 SSCTL2 ADC Sample Sequence Control 2 0x84 -1 read-write n 0x0 0x0 ADC_SSCTL2_D0 1st Sample Differential Input Select 0 1 ADC_SSCTL2_D1 2nd Sample Differential Input Select 4 5 ADC_SSCTL2_D2 3rd Sample Differential Input Select 8 9 ADC_SSCTL2_D3 4th Sample Differential Input Select 12 13 ADC_SSCTL2_END0 1st Sample is End of Sequence 1 2 ADC_SSCTL2_END1 2nd Sample is End of Sequence 5 6 ADC_SSCTL2_END2 3rd Sample is End of Sequence 9 10 ADC_SSCTL2_END3 4th Sample is End of Sequence 13 14 ADC_SSCTL2_IE0 1st Sample Interrupt Enable 2 3 ADC_SSCTL2_IE1 2nd Sample Interrupt Enable 6 7 ADC_SSCTL2_IE2 3rd Sample Interrupt Enable 10 11 ADC_SSCTL2_IE3 4th Sample Interrupt Enable 14 15 ADC_SSCTL2_TS0 1st Sample Temp Sensor Select 3 4 ADC_SSCTL2_TS1 2nd Sample Temp Sensor Select 7 8 ADC_SSCTL2_TS2 3rd Sample Temp Sensor Select 11 12 ADC_SSCTL2_TS3 4th Sample Temp Sensor Select 15 16 SSCTL3 ADC Sample Sequence Control 3 0xA4 -1 read-write n 0x0 0x0 ADC_SSCTL3_D0 Sample Differential Input Select 0 1 ADC_SSCTL3_END0 End of Sequence 1 2 ADC_SSCTL3_IE0 Sample Interrupt Enable 2 3 ADC_SSCTL3_TS0 1st Sample Temp Sensor Select 3 4 SSDC0 ADC Sample Sequence 0 Digital Comparator Select 0x54 -1 read-write n 0x0 0x0 ADC_SSDC0_S0DCSEL Sample 0 Digital Comparator Select 0 4 ADC_SSDC0_S1DCSEL Sample 1 Digital Comparator Select 4 8 ADC_SSDC0_S2DCSEL Sample 2 Digital Comparator Select 8 12 ADC_SSDC0_S3DCSEL Sample 3 Digital Comparator Select 12 16 ADC_SSDC0_S4DCSEL Sample 4 Digital Comparator Select 16 20 ADC_SSDC0_S5DCSEL Sample 5 Digital Comparator Select 20 24 ADC_SSDC0_S6DCSEL Sample 6 Digital Comparator Select 24 28 ADC_SSDC0_S7DCSEL Sample 7 Digital Comparator Select 28 32 SSDC1 ADC Sample Sequence 1 Digital Comparator Select 0x74 -1 read-write n 0x0 0x0 ADC_SSDC1_S0DCSEL Sample 0 Digital Comparator Select 0 4 ADC_SSDC1_S1DCSEL Sample 1 Digital Comparator Select 4 8 ADC_SSDC1_S2DCSEL Sample 2 Digital Comparator Select 8 12 ADC_SSDC1_S3DCSEL Sample 3 Digital Comparator Select 12 16 SSDC2 ADC Sample Sequence 2 Digital Comparator Select 0x94 -1 read-write n 0x0 0x0 ADC_SSDC2_S0DCSEL Sample 0 Digital Comparator Select 0 4 ADC_SSDC2_S1DCSEL Sample 1 Digital Comparator Select 4 8 ADC_SSDC2_S2DCSEL Sample 2 Digital Comparator Select 8 12 ADC_SSDC2_S3DCSEL Sample 3 Digital Comparator Select 12 16 SSDC3 ADC Sample Sequence 3 Digital Comparator Select 0xB4 -1 read-write n 0x0 0x0 ADC_SSDC3_S0DCSEL Sample 0 Digital Comparator Select 0 4 SSEMUX0 ADC Sample Sequence Extended Input Multiplexer Select 0 0x58 -1 read-write n 0x0 0x0 ADC_SSEMUX0_EMUX0 1st Sample Input Select (Upper Bit) 0 1 ADC_SSEMUX0_EMUX1 2th Sample Input Select (Upper Bit) 4 5 ADC_SSEMUX0_EMUX2 3rd Sample Input Select (Upper Bit) 8 9 ADC_SSEMUX0_EMUX3 4th Sample Input Select (Upper Bit) 12 13 ADC_SSEMUX0_EMUX4 5th Sample Input Select (Upper Bit) 16 17 ADC_SSEMUX0_EMUX5 6th Sample Input Select (Upper Bit) 20 21 ADC_SSEMUX0_EMUX6 7th Sample Input Select (Upper Bit) 24 25 ADC_SSEMUX0_EMUX7 8th Sample Input Select (Upper Bit) 28 29 SSEMUX1 ADC Sample Sequence Extended Input Multiplexer Select 1 0x78 -1 read-write n 0x0 0x0 ADC_SSEMUX1_EMUX0 1st Sample Input Select (Upper Bit) 0 1 ADC_SSEMUX1_EMUX1 2th Sample Input Select (Upper Bit) 4 5 ADC_SSEMUX1_EMUX2 3rd Sample Input Select (Upper Bit) 8 9 ADC_SSEMUX1_EMUX3 4th Sample Input Select (Upper Bit) 12 13 SSEMUX2 ADC Sample Sequence Extended Input Multiplexer Select 2 0x98 -1 read-write n 0x0 0x0 ADC_SSEMUX2_EMUX0 1st Sample Input Select (Upper Bit) 0 1 ADC_SSEMUX2_EMUX1 2th Sample Input Select (Upper Bit) 4 5 ADC_SSEMUX2_EMUX2 3rd Sample Input Select (Upper Bit) 8 9 ADC_SSEMUX2_EMUX3 4th Sample Input Select (Upper Bit) 12 13 SSEMUX3 ADC Sample Sequence Extended Input Multiplexer Select 3 0xB8 -1 read-write n 0x0 0x0 ADC_SSEMUX3_EMUX0 1st Sample Input Select (Upper Bit) 0 1 SSFIFO0 ADC Sample Sequence Result FIFO 0 0x48 -1 read-write n 0x0 0x0 ADC_SSFIFO0_DATA Conversion Result Data 0 12 SSFIFO1 ADC Sample Sequence Result FIFO 1 0x68 -1 read-write n 0x0 0x0 ADC_SSFIFO1_DATA Conversion Result Data 0 12 SSFIFO2 ADC Sample Sequence Result FIFO 2 0x88 -1 read-write n 0x0 0x0 ADC_SSFIFO2_DATA Conversion Result Data 0 12 SSFIFO3 ADC Sample Sequence Result FIFO 3 0xA8 -1 read-write n 0x0 0x0 ADC_SSFIFO3_DATA Conversion Result Data 0 12 SSFSTAT0 ADC Sample Sequence FIFO 0 Status 0x4C -1 read-write n 0x0 0x0 ADC_SSFSTAT0_EMPTY FIFO Empty 8 9 ADC_SSFSTAT0_FULL FIFO Full 12 13 ADC_SSFSTAT0_HPTR FIFO Head Pointer 4 8 ADC_SSFSTAT0_TPTR FIFO Tail Pointer 0 4 SSFSTAT1 ADC Sample Sequence FIFO 1 Status 0x6C -1 read-write n 0x0 0x0 ADC_SSFSTAT1_EMPTY FIFO Empty 8 9 ADC_SSFSTAT1_FULL FIFO Full 12 13 ADC_SSFSTAT1_HPTR FIFO Head Pointer 4 8 ADC_SSFSTAT1_TPTR FIFO Tail Pointer 0 4 SSFSTAT2 ADC Sample Sequence FIFO 2 Status 0x8C -1 read-write n 0x0 0x0 ADC_SSFSTAT2_EMPTY FIFO Empty 8 9 ADC_SSFSTAT2_FULL FIFO Full 12 13 ADC_SSFSTAT2_HPTR FIFO Head Pointer 4 8 ADC_SSFSTAT2_TPTR FIFO Tail Pointer 0 4 SSFSTAT3 ADC Sample Sequence FIFO 3 Status 0xAC -1 read-write n 0x0 0x0 ADC_SSFSTAT3_EMPTY FIFO Empty 8 9 ADC_SSFSTAT3_FULL FIFO Full 12 13 ADC_SSFSTAT3_HPTR FIFO Head Pointer 4 8 ADC_SSFSTAT3_TPTR FIFO Tail Pointer 0 4 SSMUX0 ADC Sample Sequence Input Multiplexer Select 0 0x40 -1 read-write n 0x0 0x0 ADC_SSMUX0_MUX0 1st Sample Input Select 0 4 ADC_SSMUX0_MUX1 2nd Sample Input Select 4 8 ADC_SSMUX0_MUX2 3rd Sample Input Select 8 12 ADC_SSMUX0_MUX3 4th Sample Input Select 12 16 ADC_SSMUX0_MUX4 5th Sample Input Select 16 20 ADC_SSMUX0_MUX5 6th Sample Input Select 20 24 ADC_SSMUX0_MUX6 7th Sample Input Select 24 28 ADC_SSMUX0_MUX7 8th Sample Input Select 28 32 SSMUX1 ADC Sample Sequence Input Multiplexer Select 1 0x60 -1 read-write n 0x0 0x0 ADC_SSMUX1_MUX0 1st Sample Input Select 0 4 ADC_SSMUX1_MUX1 2nd Sample Input Select 4 8 ADC_SSMUX1_MUX2 3rd Sample Input Select 8 12 ADC_SSMUX1_MUX3 4th Sample Input Select 12 16 SSMUX2 ADC Sample Sequence Input Multiplexer Select 2 0x80 -1 read-write n 0x0 0x0 ADC_SSMUX2_MUX0 1st Sample Input Select 0 4 ADC_SSMUX2_MUX1 2nd Sample Input Select 4 8 ADC_SSMUX2_MUX2 3rd Sample Input Select 8 12 ADC_SSMUX2_MUX3 4th Sample Input Select 12 16 SSMUX3 ADC Sample Sequence Input Multiplexer Select 3 0xA0 -1 read-write n 0x0 0x0 ADC_SSMUX3_MUX0 1st Sample Input Select 0 4 SSOP0 ADC Sample Sequence 0 Operation 0x50 -1 read-write n 0x0 0x0 ADC_SSOP0_S0DCOP Sample 0 Digital Comparator Operation 0 1 ADC_SSOP0_S1DCOP Sample 1 Digital Comparator Operation 4 5 ADC_SSOP0_S2DCOP Sample 2 Digital Comparator Operation 8 9 ADC_SSOP0_S3DCOP Sample 3 Digital Comparator Operation 12 13 ADC_SSOP0_S4DCOP Sample 4 Digital Comparator Operation 16 17 ADC_SSOP0_S5DCOP Sample 5 Digital Comparator Operation 20 21 ADC_SSOP0_S6DCOP Sample 6 Digital Comparator Operation 24 25 ADC_SSOP0_S7DCOP Sample 7 Digital Comparator Operation 28 29 SSOP1 ADC Sample Sequence 1 Operation 0x70 -1 read-write n 0x0 0x0 ADC_SSOP1_S0DCOP Sample 0 Digital Comparator Operation 0 1 ADC_SSOP1_S1DCOP Sample 1 Digital Comparator Operation 4 5 ADC_SSOP1_S2DCOP Sample 2 Digital Comparator Operation 8 9 ADC_SSOP1_S3DCOP Sample 3 Digital Comparator Operation 12 13 SSOP2 ADC Sample Sequence 2 Operation 0x90 -1 read-write n 0x0 0x0 ADC_SSOP2_S0DCOP Sample 0 Digital Comparator Operation 0 1 ADC_SSOP2_S1DCOP Sample 1 Digital Comparator Operation 4 5 ADC_SSOP2_S2DCOP Sample 2 Digital Comparator Operation 8 9 ADC_SSOP2_S3DCOP Sample 3 Digital Comparator Operation 12 13 SSOP3 ADC Sample Sequence 3 Operation 0xB0 -1 read-write n 0x0 0x0 ADC_SSOP3_S0DCOP Sample 0 Digital Comparator Operation 0 1 SSPRI ADC Sample Sequencer Priority 0x20 -1 read-write n 0x0 0x0 ADC_SSPRI_SS0 SS0 Priority 0 2 ADC_SSPRI_SS1 SS1 Priority 4 6 ADC_SSPRI_SS2 SS2 Priority 8 10 ADC_SSPRI_SS3 SS3 Priority 12 14 SSTSH0 ADC Sample Sequence 0 Sample and Hold Time 0x5C -1 read-write n 0x0 0x0 ADC_SSTSH0_TSH0 1st Sample and Hold Period Select 0 4 ADC_SSTSH0_TSH1 2nd Sample and Hold Period Select 4 8 ADC_SSTSH0_TSH2 3rd Sample and Hold Period Select 8 12 ADC_SSTSH0_TSH3 4th Sample and Hold Period Select 12 16 ADC_SSTSH0_TSH4 5th Sample and Hold Period Select 16 20 ADC_SSTSH0_TSH5 6th Sample and Hold Period Select 20 24 ADC_SSTSH0_TSH6 7th Sample and Hold Period Select 24 28 ADC_SSTSH0_TSH7 8th Sample and Hold Period Select 28 32 SSTSH1 ADC Sample Sequence 1 Sample and Hold Time 0x7C -1 read-write n 0x0 0x0 ADC_SSTSH1_TSH0 1st Sample and Hold Period Select 0 4 ADC_SSTSH1_TSH1 2nd Sample and Hold Period Select 4 8 ADC_SSTSH1_TSH2 3rd Sample and Hold Period Select 8 12 ADC_SSTSH1_TSH3 4th Sample and Hold Period Select 12 16 SSTSH2 ADC Sample Sequence 2 Sample and Hold Time 0x9C -1 read-write n 0x0 0x0 ADC_SSTSH2_TSH0 1st Sample and Hold Period Select 0 4 ADC_SSTSH2_TSH1 2nd Sample and Hold Period Select 4 8 ADC_SSTSH2_TSH2 3rd Sample and Hold Period Select 8 12 ADC_SSTSH2_TSH3 4th Sample and Hold Period Select 12 16 SSTSH3 ADC Sample Sequence 3 Sample and Hold Time 0xBC -1 read-write n 0x0 0x0 ADC_SSTSH3_TSH0 1st Sample and Hold Period Select 0 4 TSSEL ADC Trigger Source Select 0x1C -1 read-write n 0x0 0x0 ADC_TSSEL_PS0 Generator 0 PWM Module Trigger Select 4 6 ADC_TSSEL_PS0_0 Use Generator 0 (and its trigger) in PWM module 0 0x0 ADC_TSSEL_PS1 Generator 1 PWM Module Trigger Select 12 14 ADC_TSSEL_PS1_0 Use Generator 1 (and its trigger) in PWM module 0 0x0 ADC_TSSEL_PS2 Generator 2 PWM Module Trigger Select 20 22 ADC_TSSEL_PS2_0 Use Generator 2 (and its trigger) in PWM module 0 0x0 ADC_TSSEL_PS3 Generator 3 PWM Module Trigger Select 28 30 ADC_TSSEL_PS3_0 Use Generator 3 (and its trigger) in PWM module 0 0x0 USTAT ADC Underflow Status 0x18 -1 read-write n 0x0 0x0 ADC_USTAT_UV0 SS0 FIFO Underflow 0 1 ADC_USTAT_UV1 SS1 FIFO Underflow 1 2 ADC_USTAT_UV2 SS2 FIFO Underflow 2 3 ADC_USTAT_UV3 SS3 FIFO Underflow 3 4 ADC1 Register map for ADC0 peripheral ADC 0x0 0x0 0x1000 registers n ADC1SS0 46 ADC1SS1 47 ADC1SS2 48 ADC1SS3 49 ACTSS ADC Active Sample Sequencer 0x0 -1 read-write n 0x0 0x0 ADC_ACTSS_ADEN0 ADC SS1 DMA Enable 8 9 ADC_ACTSS_ADEN1 ADC SS1 DMA Enable 9 10 ADC_ACTSS_ADEN2 ADC SS2 DMA Enable 10 11 ADC_ACTSS_ADEN3 ADC SS3 DMA Enable 11 12 ADC_ACTSS_ASEN0 ADC SS0 Enable 0 1 ADC_ACTSS_ASEN1 ADC SS1 Enable 1 2 ADC_ACTSS_ASEN2 ADC SS2 Enable 2 3 ADC_ACTSS_ASEN3 ADC SS3 Enable 3 4 ADC_ACTSS_BUSY ADC Busy 16 17 ADC0ACTSS ADC Active Sample Sequencer 0x0 read-write n 0x0 0x0 ADC_ACTSS_ADEN0 ADC SS1 DMA Enable 8 9 ADC_ACTSS_ADEN1 ADC SS1 DMA Enable 9 10 ADC_ACTSS_ADEN2 ADC SS2 DMA Enable 10 11 ADC_ACTSS_ADEN3 ADC SS3 DMA Enable 11 12 ADC_ACTSS_ASEN0 ADC SS0 Enable 0 1 ADC_ACTSS_ASEN1 ADC SS1 Enable 1 2 ADC_ACTSS_ASEN2 ADC SS2 Enable 2 3 ADC_ACTSS_ASEN3 ADC SS3 Enable 3 4 ADC_ACTSS_BUSY ADC Busy 16 17 ADC0CC ADC Clock Configuration 0xFC8 read-write n 0x0 0x0 ADC_CC_CLKDIV PLL VCO Clock Divisor 4 10 ADC_CC_CS ADC Clock Source 0 4 ADC_CC_CS_SYSPLL PLL VCO divided by CLKDIV 0x0 ADC_CC_CS_PIOSC PIOSC 0x1 ADC_CC_CS_MOSC MOSC 0x2 ADC0CTL ADC Control 0x38 read-write n 0x0 0x0 ADC_CTL_DITHER Dither Mode Enable 6 7 ADC_CTL_VREF Voltage Reference Select 0 1 ADC_CTL_VREF_INTERNAL VDDA and GNDA are the voltage references 0x0 ADC_CTL_VREF_EXT_3V The external VREFA+ and VREFA- inputs are the voltage references 0x1 ADC0DCCMP0 ADC Digital Comparator Range 0 0xE40 read-write n 0x0 0x0 ADC_DCCMP0_COMP0 Compare 0 0 12 ADC_DCCMP0_COMP1 Compare 1 16 28 ADC0DCCMP1 ADC Digital Comparator Range 1 0xE44 read-write n 0x0 0x0 ADC_DCCMP1_COMP0 Compare 0 0 12 ADC_DCCMP1_COMP1 Compare 1 16 28 ADC0DCCMP2 ADC Digital Comparator Range 2 0xE48 read-write n 0x0 0x0 ADC_DCCMP2_COMP0 Compare 0 0 12 ADC_DCCMP2_COMP1 Compare 1 16 28 ADC0DCCMP3 ADC Digital Comparator Range 3 0xE4C read-write n 0x0 0x0 ADC_DCCMP3_COMP0 Compare 0 0 12 ADC_DCCMP3_COMP1 Compare 1 16 28 ADC0DCCMP4 ADC Digital Comparator Range 4 0xE50 read-write n 0x0 0x0 ADC_DCCMP4_COMP0 Compare 0 0 12 ADC_DCCMP4_COMP1 Compare 1 16 28 ADC0DCCMP5 ADC Digital Comparator Range 5 0xE54 read-write n 0x0 0x0 ADC_DCCMP5_COMP0 Compare 0 0 12 ADC_DCCMP5_COMP1 Compare 1 16 28 ADC0DCCMP6 ADC Digital Comparator Range 6 0xE58 read-write n 0x0 0x0 ADC_DCCMP6_COMP0 Compare 0 0 12 ADC_DCCMP6_COMP1 Compare 1 16 28 ADC0DCCMP7 ADC Digital Comparator Range 7 0xE5C read-write n 0x0 0x0 ADC_DCCMP7_COMP0 Compare 0 0 12 ADC_DCCMP7_COMP1 Compare 1 16 28 ADC0DCCTL0 ADC Digital Comparator Control 0 0xE00 read-write n 0x0 0x0 ADC_DCCTL0_CIC Comparison Interrupt Condition 2 4 ADC_DCCTL0_CIC_LOW Low Band 0x0 ADC_DCCTL0_CIC_MID Mid Band 0x1 ADC_DCCTL0_CIC_HIGH High Band 0x3 ADC_DCCTL0_CIE Comparison Interrupt Enable 4 5 ADC_DCCTL0_CIM Comparison Interrupt Mode 0 2 ADC_DCCTL0_CIM_ALWAYS Always 0x0 ADC_DCCTL0_CIM_ONCE Once 0x1 ADC_DCCTL0_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL0_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL0_CTC Comparison Trigger Condition 10 12 ADC_DCCTL0_CTC_LOW Low Band 0x0 ADC_DCCTL0_CTC_MID Mid Band 0x1 ADC_DCCTL0_CTC_HIGH High Band 0x3 ADC_DCCTL0_CTE Comparison Trigger Enable 12 13 ADC_DCCTL0_CTM Comparison Trigger Mode 8 10 ADC_DCCTL0_CTM_ALWAYS Always 0x0 ADC_DCCTL0_CTM_ONCE Once 0x1 ADC_DCCTL0_CTM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL0_CTM_HONCE Hysteresis Once 0x3 ADC0DCCTL1 ADC Digital Comparator Control 1 0xE04 read-write n 0x0 0x0 ADC_DCCTL1_CIC Comparison Interrupt Condition 2 4 ADC_DCCTL1_CIC_LOW Low Band 0x0 ADC_DCCTL1_CIC_MID Mid Band 0x1 ADC_DCCTL1_CIC_HIGH High Band 0x3 ADC_DCCTL1_CIE Comparison Interrupt Enable 4 5 ADC_DCCTL1_CIM Comparison Interrupt Mode 0 2 ADC_DCCTL1_CIM_ALWAYS Always 0x0 ADC_DCCTL1_CIM_ONCE Once 0x1 ADC_DCCTL1_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL1_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL1_CTC Comparison Trigger Condition 10 12 ADC_DCCTL1_CTC_LOW Low Band 0x0 ADC_DCCTL1_CTC_MID Mid Band 0x1 ADC_DCCTL1_CTC_HIGH High Band 0x3 ADC_DCCTL1_CTE Comparison Trigger Enable 12 13 ADC_DCCTL1_CTM Comparison Trigger Mode 8 10 ADC_DCCTL1_CTM_ALWAYS Always 0x0 ADC_DCCTL1_CTM_ONCE Once 0x1 ADC_DCCTL1_CTM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL1_CTM_HONCE Hysteresis Once 0x3 ADC0DCCTL2 ADC Digital Comparator Control 2 0xE08 read-write n 0x0 0x0 ADC_DCCTL2_CIC Comparison Interrupt Condition 2 4 ADC_DCCTL2_CIC_LOW Low Band 0x0 ADC_DCCTL2_CIC_MID Mid Band 0x1 ADC_DCCTL2_CIC_HIGH High Band 0x3 ADC_DCCTL2_CIE Comparison Interrupt Enable 4 5 ADC_DCCTL2_CIM Comparison Interrupt Mode 0 2 ADC_DCCTL2_CIM_ALWAYS Always 0x0 ADC_DCCTL2_CIM_ONCE Once 0x1 ADC_DCCTL2_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL2_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL2_CTC Comparison Trigger Condition 10 12 ADC_DCCTL2_CTC_LOW Low Band 0x0 ADC_DCCTL2_CTC_MID Mid Band 0x1 ADC_DCCTL2_CTC_HIGH High Band 0x3 ADC_DCCTL2_CTE Comparison Trigger Enable 12 13 ADC_DCCTL2_CTM Comparison Trigger Mode 8 10 ADC_DCCTL2_CTM_ALWAYS Always 0x0 ADC_DCCTL2_CTM_ONCE Once 0x1 ADC_DCCTL2_CTM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL2_CTM_HONCE Hysteresis Once 0x3 ADC0DCCTL3 ADC Digital Comparator Control 3 0xE0C read-write n 0x0 0x0 ADC_DCCTL3_CIC Comparison Interrupt Condition 2 4 ADC_DCCTL3_CIC_LOW Low Band 0x0 ADC_DCCTL3_CIC_MID Mid Band 0x1 ADC_DCCTL3_CIC_HIGH High Band 0x3 ADC_DCCTL3_CIE Comparison Interrupt Enable 4 5 ADC_DCCTL3_CIM Comparison Interrupt Mode 0 2 ADC_DCCTL3_CIM_ALWAYS Always 0x0 ADC_DCCTL3_CIM_ONCE Once 0x1 ADC_DCCTL3_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL3_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL3_CTC Comparison Trigger Condition 10 12 ADC_DCCTL3_CTC_LOW Low Band 0x0 ADC_DCCTL3_CTC_MID Mid Band 0x1 ADC_DCCTL3_CTC_HIGH High Band 0x3 ADC_DCCTL3_CTE Comparison Trigger Enable 12 13 ADC_DCCTL3_CTM Comparison Trigger Mode 8 10 ADC_DCCTL3_CTM_ALWAYS Always 0x0 ADC_DCCTL3_CTM_ONCE Once 0x1 ADC_DCCTL3_CTM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL3_CTM_HONCE Hysteresis Once 0x3 ADC0DCCTL4 ADC Digital Comparator Control 4 0xE10 read-write n 0x0 0x0 ADC_DCCTL4_CIC Comparison Interrupt Condition 2 4 ADC_DCCTL4_CIC_LOW Low Band 0x0 ADC_DCCTL4_CIC_MID Mid Band 0x1 ADC_DCCTL4_CIC_HIGH High Band 0x3 ADC_DCCTL4_CIE Comparison Interrupt Enable 4 5 ADC_DCCTL4_CIM Comparison Interrupt Mode 0 2 ADC_DCCTL4_CIM_ALWAYS Always 0x0 ADC_DCCTL4_CIM_ONCE Once 0x1 ADC_DCCTL4_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL4_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL4_CTC Comparison Trigger Condition 10 12 ADC_DCCTL4_CTC_LOW Low Band 0x0 ADC_DCCTL4_CTC_MID Mid Band 0x1 ADC_DCCTL4_CTC_HIGH High Band 0x3 ADC_DCCTL4_CTE Comparison Trigger Enable 12 13 ADC_DCCTL4_CTM Comparison Trigger Mode 8 10 ADC_DCCTL4_CTM_ALWAYS Always 0x0 ADC_DCCTL4_CTM_ONCE Once 0x1 ADC_DCCTL4_CTM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL4_CTM_HONCE Hysteresis Once 0x3 ADC0DCCTL5 ADC Digital Comparator Control 5 0xE14 read-write n 0x0 0x0 ADC_DCCTL5_CIC Comparison Interrupt Condition 2 4 ADC_DCCTL5_CIC_LOW Low Band 0x0 ADC_DCCTL5_CIC_MID Mid Band 0x1 ADC_DCCTL5_CIC_HIGH High Band 0x3 ADC_DCCTL5_CIE Comparison Interrupt Enable 4 5 ADC_DCCTL5_CIM Comparison Interrupt Mode 0 2 ADC_DCCTL5_CIM_ALWAYS Always 0x0 ADC_DCCTL5_CIM_ONCE Once 0x1 ADC_DCCTL5_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL5_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL5_CTC Comparison Trigger Condition 10 12 ADC_DCCTL5_CTC_LOW Low Band 0x0 ADC_DCCTL5_CTC_MID Mid Band 0x1 ADC_DCCTL5_CTC_HIGH High Band 0x3 ADC_DCCTL5_CTE Comparison Trigger Enable 12 13 ADC_DCCTL5_CTM Comparison Trigger Mode 8 10 ADC_DCCTL5_CTM_ALWAYS Always 0x0 ADC_DCCTL5_CTM_ONCE Once 0x1 ADC_DCCTL5_CTM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL5_CTM_HONCE Hysteresis Once 0x3 ADC0DCCTL6 ADC Digital Comparator Control 6 0xE18 read-write n 0x0 0x0 ADC_DCCTL6_CIC Comparison Interrupt Condition 2 4 ADC_DCCTL6_CIC_LOW Low Band 0x0 ADC_DCCTL6_CIC_MID Mid Band 0x1 ADC_DCCTL6_CIC_HIGH High Band 0x3 ADC_DCCTL6_CIE Comparison Interrupt Enable 4 5 ADC_DCCTL6_CIM Comparison Interrupt Mode 0 2 ADC_DCCTL6_CIM_ALWAYS Always 0x0 ADC_DCCTL6_CIM_ONCE Once 0x1 ADC_DCCTL6_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL6_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL6_CTC Comparison Trigger Condition 10 12 ADC_DCCTL6_CTC_LOW Low Band 0x0 ADC_DCCTL6_CTC_MID Mid Band 0x1 ADC_DCCTL6_CTC_HIGH High Band 0x3 ADC_DCCTL6_CTE Comparison Trigger Enable 12 13 ADC_DCCTL6_CTM Comparison Trigger Mode 8 10 ADC_DCCTL6_CTM_ALWAYS Always 0x0 ADC_DCCTL6_CTM_ONCE Once 0x1 ADC_DCCTL6_CTM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL6_CTM_HONCE Hysteresis Once 0x3 ADC0DCCTL7 ADC Digital Comparator Control 7 0xE1C read-write n 0x0 0x0 ADC_DCCTL7_CIC Comparison Interrupt Condition 2 4 ADC_DCCTL7_CIC_LOW Low Band 0x0 ADC_DCCTL7_CIC_MID Mid Band 0x1 ADC_DCCTL7_CIC_HIGH High Band 0x3 ADC_DCCTL7_CIE Comparison Interrupt Enable 4 5 ADC_DCCTL7_CIM Comparison Interrupt Mode 0 2 ADC_DCCTL7_CIM_ALWAYS Always 0x0 ADC_DCCTL7_CIM_ONCE Once 0x1 ADC_DCCTL7_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL7_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL7_CTC Comparison Trigger Condition 10 12 ADC_DCCTL7_CTC_LOW Low Band 0x0 ADC_DCCTL7_CTC_MID Mid Band 0x1 ADC_DCCTL7_CTC_HIGH High Band 0x3 ADC_DCCTL7_CTE Comparison Trigger Enable 12 13 ADC_DCCTL7_CTM Comparison Trigger Mode 8 10 ADC_DCCTL7_CTM_ALWAYS Always 0x0 ADC_DCCTL7_CTM_ONCE Once 0x1 ADC_DCCTL7_CTM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL7_CTM_HONCE Hysteresis Once 0x3 ADC0DCISC ADC Digital Comparator Interrupt Status and Clear 0x34 read-write n 0x0 0x0 ADC_DCISC_DCINT0 Digital Comparator 0 Interrupt Status and Clear 0 1 ADC_DCISC_DCINT1 Digital Comparator 1 Interrupt Status and Clear 1 2 ADC_DCISC_DCINT2 Digital Comparator 2 Interrupt Status and Clear 2 3 ADC_DCISC_DCINT3 Digital Comparator 3 Interrupt Status and Clear 3 4 ADC_DCISC_DCINT4 Digital Comparator 4 Interrupt Status and Clear 4 5 ADC_DCISC_DCINT5 Digital Comparator 5 Interrupt Status and Clear 5 6 ADC_DCISC_DCINT6 Digital Comparator 6 Interrupt Status and Clear 6 7 ADC_DCISC_DCINT7 Digital Comparator 7 Interrupt Status and Clear 7 8 ADC0DCRIC ADC Digital Comparator Reset Initial Conditions 0xD00 write-only n 0x0 0x0 ADC_DCRIC_DCINT0 Digital Comparator Interrupt 0 0 1 write-only ADC_DCRIC_DCINT1 Digital Comparator Interrupt 1 1 2 write-only ADC_DCRIC_DCINT2 Digital Comparator Interrupt 2 2 3 write-only ADC_DCRIC_DCINT3 Digital Comparator Interrupt 3 3 4 write-only ADC_DCRIC_DCINT4 Digital Comparator Interrupt 4 4 5 write-only ADC_DCRIC_DCINT5 Digital Comparator Interrupt 5 5 6 write-only ADC_DCRIC_DCINT6 Digital Comparator Interrupt 6 6 7 write-only ADC_DCRIC_DCINT7 Digital Comparator Interrupt 7 7 8 write-only ADC_DCRIC_DCTRIG0 Digital Comparator Trigger 0 16 17 write-only ADC_DCRIC_DCTRIG1 Digital Comparator Trigger 1 17 18 write-only ADC_DCRIC_DCTRIG2 Digital Comparator Trigger 2 18 19 write-only ADC_DCRIC_DCTRIG3 Digital Comparator Trigger 3 19 20 write-only ADC_DCRIC_DCTRIG4 Digital Comparator Trigger 4 20 21 write-only ADC_DCRIC_DCTRIG5 Digital Comparator Trigger 5 21 22 write-only ADC_DCRIC_DCTRIG6 Digital Comparator Trigger 6 22 23 write-only ADC_DCRIC_DCTRIG7 Digital Comparator Trigger 7 23 24 write-only ADC0EMUX ADC Event Multiplexer Select 0x14 read-write n 0x0 0x0 ADC_EMUX_EM0 SS0 Trigger Select 0 4 ADC_EMUX_EM0_PROCESSOR Processor (default) 0x0 ADC_EMUX_EM0_COMP0 Analog Comparator 0 0x1 ADC_EMUX_EM0_COMP1 Analog Comparator 1 0x2 ADC_EMUX_EM0_COMP2 Analog Comparator 2 0x3 ADC_EMUX_EM0_EXTERNAL External (GPIO Pins) 0x4 ADC_EMUX_EM0_TIMER Timer 0x5 ADC_EMUX_EM0_PWM0 PWM generator 0 0x6 ADC_EMUX_EM0_PWM1 PWM generator 1 0x7 ADC_EMUX_EM0_PWM2 PWM generator 2 0x8 ADC_EMUX_EM0_PWM3 PWM generator 3 0x9 ADC_EMUX_EM0_NEVER Never Trigger 0xe ADC_EMUX_EM0_ALWAYS Always (continuously sample) 0xf ADC_EMUX_EM1 SS1 Trigger Select 4 8 ADC_EMUX_EM1_PROCESSOR Processor (default) 0x0 ADC_EMUX_EM1_COMP0 Analog Comparator 0 0x1 ADC_EMUX_EM1_COMP1 Analog Comparator 1 0x2 ADC_EMUX_EM1_COMP2 Analog Comparator 2 0x3 ADC_EMUX_EM1_EXTERNAL External (GPIO Pins) 0x4 ADC_EMUX_EM1_TIMER Timer 0x5 ADC_EMUX_EM1_PWM0 PWM generator 0 0x6 ADC_EMUX_EM1_PWM1 PWM generator 1 0x7 ADC_EMUX_EM1_PWM2 PWM generator 2 0x8 ADC_EMUX_EM1_PWM3 PWM generator 3 0x9 ADC_EMUX_EM1_NEVER Never Trigger 0xe ADC_EMUX_EM1_ALWAYS Always (continuously sample) 0xf ADC_EMUX_EM2 SS2 Trigger Select 8 12 ADC_EMUX_EM2_PROCESSOR Processor (default) 0x0 ADC_EMUX_EM2_COMP0 Analog Comparator 0 0x1 ADC_EMUX_EM2_COMP1 Analog Comparator 1 0x2 ADC_EMUX_EM2_COMP2 Analog Comparator 2 0x3 ADC_EMUX_EM2_EXTERNAL External (GPIO Pins) 0x4 ADC_EMUX_EM2_TIMER Timer 0x5 ADC_EMUX_EM2_PWM0 PWM generator 0 0x6 ADC_EMUX_EM2_PWM1 PWM generator 1 0x7 ADC_EMUX_EM2_PWM2 PWM generator 2 0x8 ADC_EMUX_EM2_PWM3 PWM generator 3 0x9 ADC_EMUX_EM2_NEVER Never Trigger 0xe ADC_EMUX_EM2_ALWAYS Always (continuously sample) 0xf ADC_EMUX_EM3 SS3 Trigger Select 12 16 ADC_EMUX_EM3_PROCESSOR Processor (default) 0x0 ADC_EMUX_EM3_COMP0 Analog Comparator 0 0x1 ADC_EMUX_EM3_COMP1 Analog Comparator 1 0x2 ADC_EMUX_EM3_COMP2 Analog Comparator 2 0x3 ADC_EMUX_EM3_EXTERNAL External (GPIO Pins) 0x4 ADC_EMUX_EM3_TIMER Timer 0x5 ADC_EMUX_EM3_PWM0 PWM generator 0 0x6 ADC_EMUX_EM3_PWM1 PWM generator 1 0x7 ADC_EMUX_EM3_PWM2 PWM generator 2 0x8 ADC_EMUX_EM3_PWM3 PWM generator 3 0x9 ADC_EMUX_EM3_NEVER Never Trigger 0xe ADC_EMUX_EM3_ALWAYS Always (continuously sample) 0xf ADC0IM ADC Interrupt Mask 0x8 read-write n 0x0 0x0 ADC_IM_DCONSS0 Digital Comparator Interrupt on SS0 16 17 ADC_IM_DCONSS1 Digital Comparator Interrupt on SS1 17 18 ADC_IM_DCONSS2 Digital Comparator Interrupt on SS2 18 19 ADC_IM_DCONSS3 Digital Comparator Interrupt on SS3 19 20 ADC_IM_DMAMASK0 SS0 DMA Interrupt Mask 8 9 ADC_IM_DMAMASK1 SS1 DMA Interrupt Mask 9 10 ADC_IM_DMAMASK2 SS2 DMA Interrupt Mask 10 11 ADC_IM_DMAMASK3 SS3 DMA Interrupt Mask 11 12 ADC_IM_MASK0 SS0 Interrupt Mask 0 1 ADC_IM_MASK1 SS1 Interrupt Mask 1 2 ADC_IM_MASK2 SS2 Interrupt Mask 2 3 ADC_IM_MASK3 SS3 Interrupt Mask 3 4 ADC0ISC ADC Interrupt Status and Clear 0xC read-write n 0x0 0x0 ADC_ISC_DCINSS0 Digital Comparator Interrupt Status on SS0 16 17 ADC_ISC_DCINSS1 Digital Comparator Interrupt Status on SS1 17 18 ADC_ISC_DCINSS2 Digital Comparator Interrupt Status on SS2 18 19 ADC_ISC_DCINSS3 Digital Comparator Interrupt Status on SS3 19 20 ADC_ISC_DMAIN0 SS0 DMA Interrupt Status and Clear 8 9 ADC_ISC_DMAIN1 SS1 DMA Interrupt Status and Clear 9 10 ADC_ISC_DMAIN2 SS2 DMA Interrupt Status and Clear 10 11 ADC_ISC_DMAIN3 SS3 DMA Interrupt Status and Clear 11 12 ADC_ISC_IN0 SS0 Interrupt Status and Clear 0 1 ADC_ISC_IN1 SS1 Interrupt Status and Clear 1 2 ADC_ISC_IN2 SS2 Interrupt Status and Clear 2 3 ADC_ISC_IN3 SS3 Interrupt Status and Clear 3 4 ADC0OSTAT ADC Overflow Status 0x10 read-write n 0x0 0x0 ADC_OSTAT_OV0 SS0 FIFO Overflow 0 1 ADC_OSTAT_OV1 SS1 FIFO Overflow 1 2 ADC_OSTAT_OV2 SS2 FIFO Overflow 2 3 ADC_OSTAT_OV3 SS3 FIFO Overflow 3 4 ADC0PC ADC Peripheral Configuration 0xFC4 read-write n 0x0 0x0 ADC_PC_MCR Conversion Rate 0 4 ADC_PC_MCR_1_8 Eighth conversion rate. After a conversion completes, the logic pauses for 112 TADC periods before starting the next conversion 0x1 ADC_PC_MCR_1_4 Quarter conversion rate. After a conversion completes, the logic pauses for 48 TADC periods before starting the next conversion 0x3 ADC_PC_MCR_1_2 Half conversion rate. After a conversion completes, the logic pauses for 16 TADC periods before starting the next conversion 0x5 ADC_PC_MCR_FULL Full conversion rate (FCONV) as defined by TADC and NSH 0x7 ADC0PP ADC Peripheral Properties 0xFC0 read-write n 0x0 0x0 ADC_PP_APSHT Application-Programmable Sample-and-Hold Time 24 25 ADC_PP_CH ADC Channel Count 4 10 ADC_PP_DC Digital Comparator Count 10 16 ADC_PP_MCR Maximum Conversion Rate 0 4 ADC_PP_MCR_FULL Full conversion rate (FCONV) as defined by TADC and NSH 0x7 ADC_PP_RSL Resolution 18 23 ADC_PP_TS Temperature Sensor 23 24 ADC_PP_TYPE ADC Architecture 16 18 ADC_PP_TYPE_SAR SAR 0x0 ADC0PSSI ADC Processor Sample Sequence Initiate 0x28 read-write n 0x0 0x0 ADC_PSSI_GSYNC Global Synchronize 31 32 ADC_PSSI_SS0 SS0 Initiate 0 1 ADC_PSSI_SS1 SS1 Initiate 1 2 ADC_PSSI_SS2 SS2 Initiate 2 3 ADC_PSSI_SS3 SS3 Initiate 3 4 ADC_PSSI_SYNCWAIT Synchronize Wait 27 28 ADC0RIS ADC Raw Interrupt Status 0x4 read-write n 0x0 0x0 ADC_RIS_DMAINR0 SS0 DMA Raw Interrupt Status 8 9 ADC_RIS_DMAINR1 SS1 DMA Raw Interrupt Status 9 10 ADC_RIS_DMAINR2 SS2 DMA Raw Interrupt Status 10 11 ADC_RIS_DMAINR3 SS3 DMA Raw Interrupt Status 11 12 ADC_RIS_INR0 SS0 Raw Interrupt Status 0 1 ADC_RIS_INR1 SS1 Raw Interrupt Status 1 2 ADC_RIS_INR2 SS2 Raw Interrupt Status 2 3 ADC_RIS_INR3 SS3 Raw Interrupt Status 3 4 ADC_RIS_INRDC Digital Comparator Raw Interrupt Status 16 17 ADC0SAC ADC Sample Averaging Control 0x30 read-write n 0x0 0x0 ADC_SAC_AVG Hardware Averaging Control 0 3 ADC_SAC_AVG_OFF No hardware oversampling 0x0 ADC_SAC_AVG_2X 2x hardware oversampling 0x1 ADC_SAC_AVG_4X 4x hardware oversampling 0x2 ADC_SAC_AVG_8X 8x hardware oversampling 0x3 ADC_SAC_AVG_16X 16x hardware oversampling 0x4 ADC_SAC_AVG_32X 32x hardware oversampling 0x5 ADC_SAC_AVG_64X 64x hardware oversampling 0x6 ADC0SPC ADC Sample Phase Control 0x24 read-write n 0x0 0x0 ADC_SPC_PHASE Phase Difference 0 4 ADC_SPC_PHASE_0 ADC sample lags by 0.0 0x0 ADC_SPC_PHASE_22_5 ADC sample lags by 22.5 0x1 ADC_SPC_PHASE_45 ADC sample lags by 45.0 0x2 ADC_SPC_PHASE_67_5 ADC sample lags by 67.5 0x3 ADC_SPC_PHASE_90 ADC sample lags by 90.0 0x4 ADC_SPC_PHASE_112_5 ADC sample lags by 112.5 0x5 ADC_SPC_PHASE_135 ADC sample lags by 135.0 0x6 ADC_SPC_PHASE_157_5 ADC sample lags by 157.5 0x7 ADC_SPC_PHASE_180 ADC sample lags by 180.0 0x8 ADC_SPC_PHASE_202_5 ADC sample lags by 202.5 0x9 ADC_SPC_PHASE_225 ADC sample lags by 225.0 0xa ADC_SPC_PHASE_247_5 ADC sample lags by 247.5 0xb ADC_SPC_PHASE_270 ADC sample lags by 270.0 0xc ADC_SPC_PHASE_292_5 ADC sample lags by 292.5 0xd ADC_SPC_PHASE_315 ADC sample lags by 315.0 0xe ADC_SPC_PHASE_337_5 ADC sample lags by 337.5 0xf ADC0SSCTL0 ADC Sample Sequence Control 0 0x44 read-write n 0x0 0x0 ADC_SSCTL0_D0 1st Sample Differential Input Select 0 1 ADC_SSCTL0_D1 2nd Sample Differential Input Select 4 5 ADC_SSCTL0_D2 3rd Sample Differential Input Select 8 9 ADC_SSCTL0_D3 4th Sample Differential Input Select 12 13 ADC_SSCTL0_D4 5th Sample Differential Input Select 16 17 ADC_SSCTL0_D5 6th Sample Differential Input Select 20 21 ADC_SSCTL0_D6 7th Sample Differential Input Select 24 25 ADC_SSCTL0_D7 8th Sample Differential Input Select 28 29 ADC_SSCTL0_END0 1st Sample is End of Sequence 1 2 ADC_SSCTL0_END1 2nd Sample is End of Sequence 5 6 ADC_SSCTL0_END2 3rd Sample is End of Sequence 9 10 ADC_SSCTL0_END3 4th Sample is End of Sequence 13 14 ADC_SSCTL0_END4 5th Sample is End of Sequence 17 18 ADC_SSCTL0_END5 6th Sample is End of Sequence 21 22 ADC_SSCTL0_END6 7th Sample is End of Sequence 25 26 ADC_SSCTL0_END7 8th Sample is End of Sequence 29 30 ADC_SSCTL0_IE0 1st Sample Interrupt Enable 2 3 ADC_SSCTL0_IE1 2nd Sample Interrupt Enable 6 7 ADC_SSCTL0_IE2 3rd Sample Interrupt Enable 10 11 ADC_SSCTL0_IE3 4th Sample Interrupt Enable 14 15 ADC_SSCTL0_IE4 5th Sample Interrupt Enable 18 19 ADC_SSCTL0_IE5 6th Sample Interrupt Enable 22 23 ADC_SSCTL0_IE6 7th Sample Interrupt Enable 26 27 ADC_SSCTL0_IE7 8th Sample Interrupt Enable 30 31 ADC_SSCTL0_TS0 1st Sample Temp Sensor Select 3 4 ADC_SSCTL0_TS1 2nd Sample Temp Sensor Select 7 8 ADC_SSCTL0_TS2 3rd Sample Temp Sensor Select 11 12 ADC_SSCTL0_TS3 4th Sample Temp Sensor Select 15 16 ADC_SSCTL0_TS4 5th Sample Temp Sensor Select 19 20 ADC_SSCTL0_TS5 6th Sample Temp Sensor Select 23 24 ADC_SSCTL0_TS6 7th Sample Temp Sensor Select 27 28 ADC_SSCTL0_TS7 8th Sample Temp Sensor Select 31 32 ADC0SSCTL1 ADC Sample Sequence Control 1 0x64 read-write n 0x0 0x0 ADC_SSCTL1_D0 1st Sample Differential Input Select 0 1 ADC_SSCTL1_D1 2nd Sample Differential Input Select 4 5 ADC_SSCTL1_D2 3rd Sample Differential Input Select 8 9 ADC_SSCTL1_D3 4th Sample Differential Input Select 12 13 ADC_SSCTL1_END0 1st Sample is End of Sequence 1 2 ADC_SSCTL1_END1 2nd Sample is End of Sequence 5 6 ADC_SSCTL1_END2 3rd Sample is End of Sequence 9 10 ADC_SSCTL1_END3 4th Sample is End of Sequence 13 14 ADC_SSCTL1_IE0 1st Sample Interrupt Enable 2 3 ADC_SSCTL1_IE1 2nd Sample Interrupt Enable 6 7 ADC_SSCTL1_IE2 3rd Sample Interrupt Enable 10 11 ADC_SSCTL1_IE3 4th Sample Interrupt Enable 14 15 ADC_SSCTL1_TS0 1st Sample Temp Sensor Select 3 4 ADC_SSCTL1_TS1 2nd Sample Temp Sensor Select 7 8 ADC_SSCTL1_TS2 3rd Sample Temp Sensor Select 11 12 ADC_SSCTL1_TS3 4th Sample Temp Sensor Select 15 16 ADC0SSCTL2 ADC Sample Sequence Control 2 0x84 read-write n 0x0 0x0 ADC_SSCTL2_D0 1st Sample Differential Input Select 0 1 ADC_SSCTL2_D1 2nd Sample Differential Input Select 4 5 ADC_SSCTL2_D2 3rd Sample Differential Input Select 8 9 ADC_SSCTL2_D3 4th Sample Differential Input Select 12 13 ADC_SSCTL2_END0 1st Sample is End of Sequence 1 2 ADC_SSCTL2_END1 2nd Sample is End of Sequence 5 6 ADC_SSCTL2_END2 3rd Sample is End of Sequence 9 10 ADC_SSCTL2_END3 4th Sample is End of Sequence 13 14 ADC_SSCTL2_IE0 1st Sample Interrupt Enable 2 3 ADC_SSCTL2_IE1 2nd Sample Interrupt Enable 6 7 ADC_SSCTL2_IE2 3rd Sample Interrupt Enable 10 11 ADC_SSCTL2_IE3 4th Sample Interrupt Enable 14 15 ADC_SSCTL2_TS0 1st Sample Temp Sensor Select 3 4 ADC_SSCTL2_TS1 2nd Sample Temp Sensor Select 7 8 ADC_SSCTL2_TS2 3rd Sample Temp Sensor Select 11 12 ADC_SSCTL2_TS3 4th Sample Temp Sensor Select 15 16 ADC0SSCTL3 ADC Sample Sequence Control 3 0xA4 read-write n 0x0 0x0 ADC_SSCTL3_D0 Sample Differential Input Select 0 1 ADC_SSCTL3_END0 End of Sequence 1 2 ADC_SSCTL3_IE0 Sample Interrupt Enable 2 3 ADC_SSCTL3_TS0 1st Sample Temp Sensor Select 3 4 ADC0SSDC0 ADC Sample Sequence 0 Digital Comparator Select 0x54 read-write n 0x0 0x0 ADC_SSDC0_S0DCSEL Sample 0 Digital Comparator Select 0 4 ADC_SSDC0_S1DCSEL Sample 1 Digital Comparator Select 4 8 ADC_SSDC0_S2DCSEL Sample 2 Digital Comparator Select 8 12 ADC_SSDC0_S3DCSEL Sample 3 Digital Comparator Select 12 16 ADC_SSDC0_S4DCSEL Sample 4 Digital Comparator Select 16 20 ADC_SSDC0_S5DCSEL Sample 5 Digital Comparator Select 20 24 ADC_SSDC0_S6DCSEL Sample 6 Digital Comparator Select 24 28 ADC_SSDC0_S7DCSEL Sample 7 Digital Comparator Select 28 32 ADC0SSDC1 ADC Sample Sequence 1 Digital Comparator Select 0x74 read-write n 0x0 0x0 ADC_SSDC1_S0DCSEL Sample 0 Digital Comparator Select 0 4 ADC_SSDC1_S1DCSEL Sample 1 Digital Comparator Select 4 8 ADC_SSDC1_S2DCSEL Sample 2 Digital Comparator Select 8 12 ADC_SSDC1_S3DCSEL Sample 3 Digital Comparator Select 12 16 ADC0SSDC2 ADC Sample Sequence 2 Digital Comparator Select 0x94 read-write n 0x0 0x0 ADC_SSDC2_S0DCSEL Sample 0 Digital Comparator Select 0 4 ADC_SSDC2_S1DCSEL Sample 1 Digital Comparator Select 4 8 ADC_SSDC2_S2DCSEL Sample 2 Digital Comparator Select 8 12 ADC_SSDC2_S3DCSEL Sample 3 Digital Comparator Select 12 16 ADC0SSDC3 ADC Sample Sequence 3 Digital Comparator Select 0xB4 read-write n 0x0 0x0 ADC_SSDC3_S0DCSEL Sample 0 Digital Comparator Select 0 4 ADC0SSEMUX0 ADC Sample Sequence Extended Input Multiplexer Select 0 0x58 read-write n 0x0 0x0 ADC_SSEMUX0_EMUX0 1st Sample Input Select (Upper Bit) 0 1 ADC_SSEMUX0_EMUX1 2th Sample Input Select (Upper Bit) 4 5 ADC_SSEMUX0_EMUX2 3rd Sample Input Select (Upper Bit) 8 9 ADC_SSEMUX0_EMUX3 4th Sample Input Select (Upper Bit) 12 13 ADC_SSEMUX0_EMUX4 5th Sample Input Select (Upper Bit) 16 17 ADC_SSEMUX0_EMUX5 6th Sample Input Select (Upper Bit) 20 21 ADC_SSEMUX0_EMUX6 7th Sample Input Select (Upper Bit) 24 25 ADC_SSEMUX0_EMUX7 8th Sample Input Select (Upper Bit) 28 29 ADC0SSEMUX1 ADC Sample Sequence Extended Input Multiplexer Select 1 0x78 read-write n 0x0 0x0 ADC_SSEMUX1_EMUX0 1st Sample Input Select (Upper Bit) 0 1 ADC_SSEMUX1_EMUX1 2th Sample Input Select (Upper Bit) 4 5 ADC_SSEMUX1_EMUX2 3rd Sample Input Select (Upper Bit) 8 9 ADC_SSEMUX1_EMUX3 4th Sample Input Select (Upper Bit) 12 13 ADC0SSEMUX2 ADC Sample Sequence Extended Input Multiplexer Select 2 0x98 read-write n 0x0 0x0 ADC_SSEMUX2_EMUX0 1st Sample Input Select (Upper Bit) 0 1 ADC_SSEMUX2_EMUX1 2th Sample Input Select (Upper Bit) 4 5 ADC_SSEMUX2_EMUX2 3rd Sample Input Select (Upper Bit) 8 9 ADC_SSEMUX2_EMUX3 4th Sample Input Select (Upper Bit) 12 13 ADC0SSEMUX3 ADC Sample Sequence Extended Input Multiplexer Select 3 0xB8 read-write n 0x0 0x0 ADC_SSEMUX3_EMUX0 1st Sample Input Select (Upper Bit) 0 1 ADC0SSFIFO0 ADC Sample Sequence Result FIFO 0 0x48 read-write n 0x0 0x0 ADC_SSFIFO0_DATA Conversion Result Data 0 12 ADC0SSFIFO1 ADC Sample Sequence Result FIFO 1 0x68 read-write n 0x0 0x0 ADC_SSFIFO1_DATA Conversion Result Data 0 12 ADC0SSFIFO2 ADC Sample Sequence Result FIFO 2 0x88 read-write n 0x0 0x0 ADC_SSFIFO2_DATA Conversion Result Data 0 12 ADC0SSFIFO3 ADC Sample Sequence Result FIFO 3 0xA8 read-write n 0x0 0x0 ADC_SSFIFO3_DATA Conversion Result Data 0 12 ADC0SSFSTAT0 ADC Sample Sequence FIFO 0 Status 0x4C read-write n 0x0 0x0 ADC_SSFSTAT0_EMPTY FIFO Empty 8 9 ADC_SSFSTAT0_FULL FIFO Full 12 13 ADC_SSFSTAT0_HPTR FIFO Head Pointer 4 8 ADC_SSFSTAT0_TPTR FIFO Tail Pointer 0 4 ADC0SSFSTAT1 ADC Sample Sequence FIFO 1 Status 0x6C read-write n 0x0 0x0 ADC_SSFSTAT1_EMPTY FIFO Empty 8 9 ADC_SSFSTAT1_FULL FIFO Full 12 13 ADC_SSFSTAT1_HPTR FIFO Head Pointer 4 8 ADC_SSFSTAT1_TPTR FIFO Tail Pointer 0 4 ADC0SSFSTAT2 ADC Sample Sequence FIFO 2 Status 0x8C read-write n 0x0 0x0 ADC_SSFSTAT2_EMPTY FIFO Empty 8 9 ADC_SSFSTAT2_FULL FIFO Full 12 13 ADC_SSFSTAT2_HPTR FIFO Head Pointer 4 8 ADC_SSFSTAT2_TPTR FIFO Tail Pointer 0 4 ADC0SSFSTAT3 ADC Sample Sequence FIFO 3 Status 0xAC read-write n 0x0 0x0 ADC_SSFSTAT3_EMPTY FIFO Empty 8 9 ADC_SSFSTAT3_FULL FIFO Full 12 13 ADC_SSFSTAT3_HPTR FIFO Head Pointer 4 8 ADC_SSFSTAT3_TPTR FIFO Tail Pointer 0 4 ADC0SSMUX0 ADC Sample Sequence Input Multiplexer Select 0 0x40 read-write n 0x0 0x0 ADC_SSMUX0_MUX0 1st Sample Input Select 0 4 ADC_SSMUX0_MUX1 2nd Sample Input Select 4 8 ADC_SSMUX0_MUX2 3rd Sample Input Select 8 12 ADC_SSMUX0_MUX3 4th Sample Input Select 12 16 ADC_SSMUX0_MUX4 5th Sample Input Select 16 20 ADC_SSMUX0_MUX5 6th Sample Input Select 20 24 ADC_SSMUX0_MUX6 7th Sample Input Select 24 28 ADC_SSMUX0_MUX7 8th Sample Input Select 28 32 ADC0SSMUX1 ADC Sample Sequence Input Multiplexer Select 1 0x60 read-write n 0x0 0x0 ADC_SSMUX1_MUX0 1st Sample Input Select 0 4 ADC_SSMUX1_MUX1 2nd Sample Input Select 4 8 ADC_SSMUX1_MUX2 3rd Sample Input Select 8 12 ADC_SSMUX1_MUX3 4th Sample Input Select 12 16 ADC0SSMUX2 ADC Sample Sequence Input Multiplexer Select 2 0x80 read-write n 0x0 0x0 ADC_SSMUX2_MUX0 1st Sample Input Select 0 4 ADC_SSMUX2_MUX1 2nd Sample Input Select 4 8 ADC_SSMUX2_MUX2 3rd Sample Input Select 8 12 ADC_SSMUX2_MUX3 4th Sample Input Select 12 16 ADC0SSMUX3 ADC Sample Sequence Input Multiplexer Select 3 0xA0 read-write n 0x0 0x0 ADC_SSMUX3_MUX0 1st Sample Input Select 0 4 ADC0SSOP0 ADC Sample Sequence 0 Operation 0x50 read-write n 0x0 0x0 ADC_SSOP0_S0DCOP Sample 0 Digital Comparator Operation 0 1 ADC_SSOP0_S1DCOP Sample 1 Digital Comparator Operation 4 5 ADC_SSOP0_S2DCOP Sample 2 Digital Comparator Operation 8 9 ADC_SSOP0_S3DCOP Sample 3 Digital Comparator Operation 12 13 ADC_SSOP0_S4DCOP Sample 4 Digital Comparator Operation 16 17 ADC_SSOP0_S5DCOP Sample 5 Digital Comparator Operation 20 21 ADC_SSOP0_S6DCOP Sample 6 Digital Comparator Operation 24 25 ADC_SSOP0_S7DCOP Sample 7 Digital Comparator Operation 28 29 ADC0SSOP1 ADC Sample Sequence 1 Operation 0x70 read-write n 0x0 0x0 ADC_SSOP1_S0DCOP Sample 0 Digital Comparator Operation 0 1 ADC_SSOP1_S1DCOP Sample 1 Digital Comparator Operation 4 5 ADC_SSOP1_S2DCOP Sample 2 Digital Comparator Operation 8 9 ADC_SSOP1_S3DCOP Sample 3 Digital Comparator Operation 12 13 ADC0SSOP2 ADC Sample Sequence 2 Operation 0x90 read-write n 0x0 0x0 ADC_SSOP2_S0DCOP Sample 0 Digital Comparator Operation 0 1 ADC_SSOP2_S1DCOP Sample 1 Digital Comparator Operation 4 5 ADC_SSOP2_S2DCOP Sample 2 Digital Comparator Operation 8 9 ADC_SSOP2_S3DCOP Sample 3 Digital Comparator Operation 12 13 ADC0SSOP3 ADC Sample Sequence 3 Operation 0xB0 read-write n 0x0 0x0 ADC_SSOP3_S0DCOP Sample 0 Digital Comparator Operation 0 1 ADC0SSPRI ADC Sample Sequencer Priority 0x20 read-write n 0x0 0x0 ADC_SSPRI_SS0 SS0 Priority 0 2 ADC_SSPRI_SS1 SS1 Priority 4 6 ADC_SSPRI_SS2 SS2 Priority 8 10 ADC_SSPRI_SS3 SS3 Priority 12 14 ADC0SSTSH0 ADC Sample Sequence 0 Sample and Hold Time 0x5C read-write n 0x0 0x0 ADC_SSTSH0_TSH0 1st Sample and Hold Period Select 0 4 ADC_SSTSH0_TSH1 2nd Sample and Hold Period Select 4 8 ADC_SSTSH0_TSH2 3rd Sample and Hold Period Select 8 12 ADC_SSTSH0_TSH3 4th Sample and Hold Period Select 12 16 ADC_SSTSH0_TSH4 5th Sample and Hold Period Select 16 20 ADC_SSTSH0_TSH5 6th Sample and Hold Period Select 20 24 ADC_SSTSH0_TSH6 7th Sample and Hold Period Select 24 28 ADC_SSTSH0_TSH7 8th Sample and Hold Period Select 28 32 ADC0SSTSH1 ADC Sample Sequence 1 Sample and Hold Time 0x7C read-write n 0x0 0x0 ADC_SSTSH1_TSH0 1st Sample and Hold Period Select 0 4 ADC_SSTSH1_TSH1 2nd Sample and Hold Period Select 4 8 ADC_SSTSH1_TSH2 3rd Sample and Hold Period Select 8 12 ADC_SSTSH1_TSH3 4th Sample and Hold Period Select 12 16 ADC0SSTSH2 ADC Sample Sequence 2 Sample and Hold Time 0x9C read-write n 0x0 0x0 ADC_SSTSH2_TSH0 1st Sample and Hold Period Select 0 4 ADC_SSTSH2_TSH1 2nd Sample and Hold Period Select 4 8 ADC_SSTSH2_TSH2 3rd Sample and Hold Period Select 8 12 ADC_SSTSH2_TSH3 4th Sample and Hold Period Select 12 16 ADC0SSTSH3 ADC Sample Sequence 3 Sample and Hold Time 0xBC read-write n 0x0 0x0 ADC_SSTSH3_TSH0 1st Sample and Hold Period Select 0 4 ADC0TSSEL ADC Trigger Source Select 0x1C read-write n 0x0 0x0 ADC_TSSEL_PS0 Generator 0 PWM Module Trigger Select 4 6 ADC_TSSEL_PS0_0 Use Generator 0 (and its trigger) in PWM module 0 0x0 ADC_TSSEL_PS1 Generator 1 PWM Module Trigger Select 12 14 ADC_TSSEL_PS1_0 Use Generator 1 (and its trigger) in PWM module 0 0x0 ADC_TSSEL_PS2 Generator 2 PWM Module Trigger Select 20 22 ADC_TSSEL_PS2_0 Use Generator 2 (and its trigger) in PWM module 0 0x0 ADC_TSSEL_PS3 Generator 3 PWM Module Trigger Select 28 30 ADC_TSSEL_PS3_0 Use Generator 3 (and its trigger) in PWM module 0 0x0 ADC0USTAT ADC Underflow Status 0x18 read-write n 0x0 0x0 ADC_USTAT_UV0 SS0 FIFO Underflow 0 1 ADC_USTAT_UV1 SS1 FIFO Underflow 1 2 ADC_USTAT_UV2 SS2 FIFO Underflow 2 3 ADC_USTAT_UV3 SS3 FIFO Underflow 3 4 CC ADC Clock Configuration 0xFC8 -1 read-write n 0x0 0x0 ADC_CC_CLKDIV PLL VCO Clock Divisor 4 10 ADC_CC_CS ADC Clock Source 0 4 ADC_CC_CS_SYSPLL PLL VCO divided by CLKDIV 0x0 ADC_CC_CS_PIOSC PIOSC 0x1 ADC_CC_CS_MOSC MOSC 0x2 CTL ADC Control 0x38 -1 read-write n 0x0 0x0 ADC_CTL_DITHER Dither Mode Enable 6 7 ADC_CTL_VREF Voltage Reference Select 0 1 ADC_CTL_VREF_INTERNAL VDDA and GNDA are the voltage references 0x0 ADC_CTL_VREF_EXT_3V The external VREFA+ and VREFA- inputs are the voltage references 0x1 DCCMP0 ADC Digital Comparator Range 0 0xE40 -1 read-write n 0x0 0x0 ADC_DCCMP0_COMP0 Compare 0 0 12 ADC_DCCMP0_COMP1 Compare 1 16 28 DCCMP1 ADC Digital Comparator Range 1 0xE44 -1 read-write n 0x0 0x0 ADC_DCCMP1_COMP0 Compare 0 0 12 ADC_DCCMP1_COMP1 Compare 1 16 28 DCCMP2 ADC Digital Comparator Range 2 0xE48 -1 read-write n 0x0 0x0 ADC_DCCMP2_COMP0 Compare 0 0 12 ADC_DCCMP2_COMP1 Compare 1 16 28 DCCMP3 ADC Digital Comparator Range 3 0xE4C -1 read-write n 0x0 0x0 ADC_DCCMP3_COMP0 Compare 0 0 12 ADC_DCCMP3_COMP1 Compare 1 16 28 DCCMP4 ADC Digital Comparator Range 4 0xE50 -1 read-write n 0x0 0x0 ADC_DCCMP4_COMP0 Compare 0 0 12 ADC_DCCMP4_COMP1 Compare 1 16 28 DCCMP5 ADC Digital Comparator Range 5 0xE54 -1 read-write n 0x0 0x0 ADC_DCCMP5_COMP0 Compare 0 0 12 ADC_DCCMP5_COMP1 Compare 1 16 28 DCCMP6 ADC Digital Comparator Range 6 0xE58 -1 read-write n 0x0 0x0 ADC_DCCMP6_COMP0 Compare 0 0 12 ADC_DCCMP6_COMP1 Compare 1 16 28 DCCMP7 ADC Digital Comparator Range 7 0xE5C -1 read-write n 0x0 0x0 ADC_DCCMP7_COMP0 Compare 0 0 12 ADC_DCCMP7_COMP1 Compare 1 16 28 DCCTL0 ADC Digital Comparator Control 0 0xE00 -1 read-write n 0x0 0x0 ADC_DCCTL0_CIC Comparison Interrupt Condition 2 4 ADC_DCCTL0_CIC_LOW Low Band 0x0 ADC_DCCTL0_CIC_MID Mid Band 0x1 ADC_DCCTL0_CIC_HIGH High Band 0x3 ADC_DCCTL0_CIE Comparison Interrupt Enable 4 5 ADC_DCCTL0_CIM Comparison Interrupt Mode 0 2 ADC_DCCTL0_CIM_ALWAYS Always 0x0 ADC_DCCTL0_CIM_ONCE Once 0x1 ADC_DCCTL0_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL0_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL0_CTC Comparison Trigger Condition 10 12 ADC_DCCTL0_CTC_LOW Low Band 0x0 ADC_DCCTL0_CTC_MID Mid Band 0x1 ADC_DCCTL0_CTC_HIGH High Band 0x3 ADC_DCCTL0_CTE Comparison Trigger Enable 12 13 ADC_DCCTL0_CTM Comparison Trigger Mode 8 10 ADC_DCCTL0_CTM_ALWAYS Always 0x0 ADC_DCCTL0_CTM_ONCE Once 0x1 ADC_DCCTL0_CTM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL0_CTM_HONCE Hysteresis Once 0x3 DCCTL1 ADC Digital Comparator Control 1 0xE04 -1 read-write n 0x0 0x0 ADC_DCCTL1_CIC Comparison Interrupt Condition 2 4 ADC_DCCTL1_CIC_LOW Low Band 0x0 ADC_DCCTL1_CIC_MID Mid Band 0x1 ADC_DCCTL1_CIC_HIGH High Band 0x3 ADC_DCCTL1_CIE Comparison Interrupt Enable 4 5 ADC_DCCTL1_CIM Comparison Interrupt Mode 0 2 ADC_DCCTL1_CIM_ALWAYS Always 0x0 ADC_DCCTL1_CIM_ONCE Once 0x1 ADC_DCCTL1_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL1_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL1_CTC Comparison Trigger Condition 10 12 ADC_DCCTL1_CTC_LOW Low Band 0x0 ADC_DCCTL1_CTC_MID Mid Band 0x1 ADC_DCCTL1_CTC_HIGH High Band 0x3 ADC_DCCTL1_CTE Comparison Trigger Enable 12 13 ADC_DCCTL1_CTM Comparison Trigger Mode 8 10 ADC_DCCTL1_CTM_ALWAYS Always 0x0 ADC_DCCTL1_CTM_ONCE Once 0x1 ADC_DCCTL1_CTM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL1_CTM_HONCE Hysteresis Once 0x3 DCCTL2 ADC Digital Comparator Control 2 0xE08 -1 read-write n 0x0 0x0 ADC_DCCTL2_CIC Comparison Interrupt Condition 2 4 ADC_DCCTL2_CIC_LOW Low Band 0x0 ADC_DCCTL2_CIC_MID Mid Band 0x1 ADC_DCCTL2_CIC_HIGH High Band 0x3 ADC_DCCTL2_CIE Comparison Interrupt Enable 4 5 ADC_DCCTL2_CIM Comparison Interrupt Mode 0 2 ADC_DCCTL2_CIM_ALWAYS Always 0x0 ADC_DCCTL2_CIM_ONCE Once 0x1 ADC_DCCTL2_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL2_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL2_CTC Comparison Trigger Condition 10 12 ADC_DCCTL2_CTC_LOW Low Band 0x0 ADC_DCCTL2_CTC_MID Mid Band 0x1 ADC_DCCTL2_CTC_HIGH High Band 0x3 ADC_DCCTL2_CTE Comparison Trigger Enable 12 13 ADC_DCCTL2_CTM Comparison Trigger Mode 8 10 ADC_DCCTL2_CTM_ALWAYS Always 0x0 ADC_DCCTL2_CTM_ONCE Once 0x1 ADC_DCCTL2_CTM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL2_CTM_HONCE Hysteresis Once 0x3 DCCTL3 ADC Digital Comparator Control 3 0xE0C -1 read-write n 0x0 0x0 ADC_DCCTL3_CIC Comparison Interrupt Condition 2 4 ADC_DCCTL3_CIC_LOW Low Band 0x0 ADC_DCCTL3_CIC_MID Mid Band 0x1 ADC_DCCTL3_CIC_HIGH High Band 0x3 ADC_DCCTL3_CIE Comparison Interrupt Enable 4 5 ADC_DCCTL3_CIM Comparison Interrupt Mode 0 2 ADC_DCCTL3_CIM_ALWAYS Always 0x0 ADC_DCCTL3_CIM_ONCE Once 0x1 ADC_DCCTL3_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL3_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL3_CTC Comparison Trigger Condition 10 12 ADC_DCCTL3_CTC_LOW Low Band 0x0 ADC_DCCTL3_CTC_MID Mid Band 0x1 ADC_DCCTL3_CTC_HIGH High Band 0x3 ADC_DCCTL3_CTE Comparison Trigger Enable 12 13 ADC_DCCTL3_CTM Comparison Trigger Mode 8 10 ADC_DCCTL3_CTM_ALWAYS Always 0x0 ADC_DCCTL3_CTM_ONCE Once 0x1 ADC_DCCTL3_CTM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL3_CTM_HONCE Hysteresis Once 0x3 DCCTL4 ADC Digital Comparator Control 4 0xE10 -1 read-write n 0x0 0x0 ADC_DCCTL4_CIC Comparison Interrupt Condition 2 4 ADC_DCCTL4_CIC_LOW Low Band 0x0 ADC_DCCTL4_CIC_MID Mid Band 0x1 ADC_DCCTL4_CIC_HIGH High Band 0x3 ADC_DCCTL4_CIE Comparison Interrupt Enable 4 5 ADC_DCCTL4_CIM Comparison Interrupt Mode 0 2 ADC_DCCTL4_CIM_ALWAYS Always 0x0 ADC_DCCTL4_CIM_ONCE Once 0x1 ADC_DCCTL4_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL4_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL4_CTC Comparison Trigger Condition 10 12 ADC_DCCTL4_CTC_LOW Low Band 0x0 ADC_DCCTL4_CTC_MID Mid Band 0x1 ADC_DCCTL4_CTC_HIGH High Band 0x3 ADC_DCCTL4_CTE Comparison Trigger Enable 12 13 ADC_DCCTL4_CTM Comparison Trigger Mode 8 10 ADC_DCCTL4_CTM_ALWAYS Always 0x0 ADC_DCCTL4_CTM_ONCE Once 0x1 ADC_DCCTL4_CTM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL4_CTM_HONCE Hysteresis Once 0x3 DCCTL5 ADC Digital Comparator Control 5 0xE14 -1 read-write n 0x0 0x0 ADC_DCCTL5_CIC Comparison Interrupt Condition 2 4 ADC_DCCTL5_CIC_LOW Low Band 0x0 ADC_DCCTL5_CIC_MID Mid Band 0x1 ADC_DCCTL5_CIC_HIGH High Band 0x3 ADC_DCCTL5_CIE Comparison Interrupt Enable 4 5 ADC_DCCTL5_CIM Comparison Interrupt Mode 0 2 ADC_DCCTL5_CIM_ALWAYS Always 0x0 ADC_DCCTL5_CIM_ONCE Once 0x1 ADC_DCCTL5_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL5_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL5_CTC Comparison Trigger Condition 10 12 ADC_DCCTL5_CTC_LOW Low Band 0x0 ADC_DCCTL5_CTC_MID Mid Band 0x1 ADC_DCCTL5_CTC_HIGH High Band 0x3 ADC_DCCTL5_CTE Comparison Trigger Enable 12 13 ADC_DCCTL5_CTM Comparison Trigger Mode 8 10 ADC_DCCTL5_CTM_ALWAYS Always 0x0 ADC_DCCTL5_CTM_ONCE Once 0x1 ADC_DCCTL5_CTM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL5_CTM_HONCE Hysteresis Once 0x3 DCCTL6 ADC Digital Comparator Control 6 0xE18 -1 read-write n 0x0 0x0 ADC_DCCTL6_CIC Comparison Interrupt Condition 2 4 ADC_DCCTL6_CIC_LOW Low Band 0x0 ADC_DCCTL6_CIC_MID Mid Band 0x1 ADC_DCCTL6_CIC_HIGH High Band 0x3 ADC_DCCTL6_CIE Comparison Interrupt Enable 4 5 ADC_DCCTL6_CIM Comparison Interrupt Mode 0 2 ADC_DCCTL6_CIM_ALWAYS Always 0x0 ADC_DCCTL6_CIM_ONCE Once 0x1 ADC_DCCTL6_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL6_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL6_CTC Comparison Trigger Condition 10 12 ADC_DCCTL6_CTC_LOW Low Band 0x0 ADC_DCCTL6_CTC_MID Mid Band 0x1 ADC_DCCTL6_CTC_HIGH High Band 0x3 ADC_DCCTL6_CTE Comparison Trigger Enable 12 13 ADC_DCCTL6_CTM Comparison Trigger Mode 8 10 ADC_DCCTL6_CTM_ALWAYS Always 0x0 ADC_DCCTL6_CTM_ONCE Once 0x1 ADC_DCCTL6_CTM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL6_CTM_HONCE Hysteresis Once 0x3 DCCTL7 ADC Digital Comparator Control 7 0xE1C -1 read-write n 0x0 0x0 ADC_DCCTL7_CIC Comparison Interrupt Condition 2 4 ADC_DCCTL7_CIC_LOW Low Band 0x0 ADC_DCCTL7_CIC_MID Mid Band 0x1 ADC_DCCTL7_CIC_HIGH High Band 0x3 ADC_DCCTL7_CIE Comparison Interrupt Enable 4 5 ADC_DCCTL7_CIM Comparison Interrupt Mode 0 2 ADC_DCCTL7_CIM_ALWAYS Always 0x0 ADC_DCCTL7_CIM_ONCE Once 0x1 ADC_DCCTL7_CIM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL7_CIM_HONCE Hysteresis Once 0x3 ADC_DCCTL7_CTC Comparison Trigger Condition 10 12 ADC_DCCTL7_CTC_LOW Low Band 0x0 ADC_DCCTL7_CTC_MID Mid Band 0x1 ADC_DCCTL7_CTC_HIGH High Band 0x3 ADC_DCCTL7_CTE Comparison Trigger Enable 12 13 ADC_DCCTL7_CTM Comparison Trigger Mode 8 10 ADC_DCCTL7_CTM_ALWAYS Always 0x0 ADC_DCCTL7_CTM_ONCE Once 0x1 ADC_DCCTL7_CTM_HALWAYS Hysteresis Always 0x2 ADC_DCCTL7_CTM_HONCE Hysteresis Once 0x3 DCISC ADC Digital Comparator Interrupt Status and Clear 0x34 -1 read-write n 0x0 0x0 ADC_DCISC_DCINT0 Digital Comparator 0 Interrupt Status and Clear 0 1 ADC_DCISC_DCINT1 Digital Comparator 1 Interrupt Status and Clear 1 2 ADC_DCISC_DCINT2 Digital Comparator 2 Interrupt Status and Clear 2 3 ADC_DCISC_DCINT3 Digital Comparator 3 Interrupt Status and Clear 3 4 ADC_DCISC_DCINT4 Digital Comparator 4 Interrupt Status and Clear 4 5 ADC_DCISC_DCINT5 Digital Comparator 5 Interrupt Status and Clear 5 6 ADC_DCISC_DCINT6 Digital Comparator 6 Interrupt Status and Clear 6 7 ADC_DCISC_DCINT7 Digital Comparator 7 Interrupt Status and Clear 7 8 DCRIC ADC Digital Comparator Reset Initial Conditions 0xD00 -1 write-only n 0x0 0x0 ADC_DCRIC_DCINT0 Digital Comparator Interrupt 0 0 1 write-only ADC_DCRIC_DCINT1 Digital Comparator Interrupt 1 1 2 write-only ADC_DCRIC_DCINT2 Digital Comparator Interrupt 2 2 3 write-only ADC_DCRIC_DCINT3 Digital Comparator Interrupt 3 3 4 write-only ADC_DCRIC_DCINT4 Digital Comparator Interrupt 4 4 5 write-only ADC_DCRIC_DCINT5 Digital Comparator Interrupt 5 5 6 write-only ADC_DCRIC_DCINT6 Digital Comparator Interrupt 6 6 7 write-only ADC_DCRIC_DCINT7 Digital Comparator Interrupt 7 7 8 write-only ADC_DCRIC_DCTRIG0 Digital Comparator Trigger 0 16 17 write-only ADC_DCRIC_DCTRIG1 Digital Comparator Trigger 1 17 18 write-only ADC_DCRIC_DCTRIG2 Digital Comparator Trigger 2 18 19 write-only ADC_DCRIC_DCTRIG3 Digital Comparator Trigger 3 19 20 write-only ADC_DCRIC_DCTRIG4 Digital Comparator Trigger 4 20 21 write-only ADC_DCRIC_DCTRIG5 Digital Comparator Trigger 5 21 22 write-only ADC_DCRIC_DCTRIG6 Digital Comparator Trigger 6 22 23 write-only ADC_DCRIC_DCTRIG7 Digital Comparator Trigger 7 23 24 write-only EMUX ADC Event Multiplexer Select 0x14 -1 read-write n 0x0 0x0 ADC_EMUX_EM0 SS0 Trigger Select 0 4 ADC_EMUX_EM0_PROCESSOR Processor (default) 0x0 ADC_EMUX_EM0_COMP0 Analog Comparator 0 0x1 ADC_EMUX_EM0_COMP1 Analog Comparator 1 0x2 ADC_EMUX_EM0_COMP2 Analog Comparator 2 0x3 ADC_EMUX_EM0_EXTERNAL External (GPIO Pins) 0x4 ADC_EMUX_EM0_TIMER Timer 0x5 ADC_EMUX_EM0_PWM0 PWM generator 0 0x6 ADC_EMUX_EM0_PWM1 PWM generator 1 0x7 ADC_EMUX_EM0_PWM2 PWM generator 2 0x8 ADC_EMUX_EM0_PWM3 PWM generator 3 0x9 ADC_EMUX_EM0_NEVER Never Trigger 0xe ADC_EMUX_EM0_ALWAYS Always (continuously sample) 0xf ADC_EMUX_EM1 SS1 Trigger Select 4 8 ADC_EMUX_EM1_PROCESSOR Processor (default) 0x0 ADC_EMUX_EM1_COMP0 Analog Comparator 0 0x1 ADC_EMUX_EM1_COMP1 Analog Comparator 1 0x2 ADC_EMUX_EM1_COMP2 Analog Comparator 2 0x3 ADC_EMUX_EM1_EXTERNAL External (GPIO Pins) 0x4 ADC_EMUX_EM1_TIMER Timer 0x5 ADC_EMUX_EM1_PWM0 PWM generator 0 0x6 ADC_EMUX_EM1_PWM1 PWM generator 1 0x7 ADC_EMUX_EM1_PWM2 PWM generator 2 0x8 ADC_EMUX_EM1_PWM3 PWM generator 3 0x9 ADC_EMUX_EM1_NEVER Never Trigger 0xe ADC_EMUX_EM1_ALWAYS Always (continuously sample) 0xf ADC_EMUX_EM2 SS2 Trigger Select 8 12 ADC_EMUX_EM2_PROCESSOR Processor (default) 0x0 ADC_EMUX_EM2_COMP0 Analog Comparator 0 0x1 ADC_EMUX_EM2_COMP1 Analog Comparator 1 0x2 ADC_EMUX_EM2_COMP2 Analog Comparator 2 0x3 ADC_EMUX_EM2_EXTERNAL External (GPIO Pins) 0x4 ADC_EMUX_EM2_TIMER Timer 0x5 ADC_EMUX_EM2_PWM0 PWM generator 0 0x6 ADC_EMUX_EM2_PWM1 PWM generator 1 0x7 ADC_EMUX_EM2_PWM2 PWM generator 2 0x8 ADC_EMUX_EM2_PWM3 PWM generator 3 0x9 ADC_EMUX_EM2_NEVER Never Trigger 0xe ADC_EMUX_EM2_ALWAYS Always (continuously sample) 0xf ADC_EMUX_EM3 SS3 Trigger Select 12 16 ADC_EMUX_EM3_PROCESSOR Processor (default) 0x0 ADC_EMUX_EM3_COMP0 Analog Comparator 0 0x1 ADC_EMUX_EM3_COMP1 Analog Comparator 1 0x2 ADC_EMUX_EM3_COMP2 Analog Comparator 2 0x3 ADC_EMUX_EM3_EXTERNAL External (GPIO Pins) 0x4 ADC_EMUX_EM3_TIMER Timer 0x5 ADC_EMUX_EM3_PWM0 PWM generator 0 0x6 ADC_EMUX_EM3_PWM1 PWM generator 1 0x7 ADC_EMUX_EM3_PWM2 PWM generator 2 0x8 ADC_EMUX_EM3_PWM3 PWM generator 3 0x9 ADC_EMUX_EM3_NEVER Never Trigger 0xe ADC_EMUX_EM3_ALWAYS Always (continuously sample) 0xf IM ADC Interrupt Mask 0x8 -1 read-write n 0x0 0x0 ADC_IM_DCONSS0 Digital Comparator Interrupt on SS0 16 17 ADC_IM_DCONSS1 Digital Comparator Interrupt on SS1 17 18 ADC_IM_DCONSS2 Digital Comparator Interrupt on SS2 18 19 ADC_IM_DCONSS3 Digital Comparator Interrupt on SS3 19 20 ADC_IM_DMAMASK0 SS0 DMA Interrupt Mask 8 9 ADC_IM_DMAMASK1 SS1 DMA Interrupt Mask 9 10 ADC_IM_DMAMASK2 SS2 DMA Interrupt Mask 10 11 ADC_IM_DMAMASK3 SS3 DMA Interrupt Mask 11 12 ADC_IM_MASK0 SS0 Interrupt Mask 0 1 ADC_IM_MASK1 SS1 Interrupt Mask 1 2 ADC_IM_MASK2 SS2 Interrupt Mask 2 3 ADC_IM_MASK3 SS3 Interrupt Mask 3 4 ISC ADC Interrupt Status and Clear 0xC -1 read-write n 0x0 0x0 ADC_ISC_DCINSS0 Digital Comparator Interrupt Status on SS0 16 17 ADC_ISC_DCINSS1 Digital Comparator Interrupt Status on SS1 17 18 ADC_ISC_DCINSS2 Digital Comparator Interrupt Status on SS2 18 19 ADC_ISC_DCINSS3 Digital Comparator Interrupt Status on SS3 19 20 ADC_ISC_DMAIN0 SS0 DMA Interrupt Status and Clear 8 9 ADC_ISC_DMAIN1 SS1 DMA Interrupt Status and Clear 9 10 ADC_ISC_DMAIN2 SS2 DMA Interrupt Status and Clear 10 11 ADC_ISC_DMAIN3 SS3 DMA Interrupt Status and Clear 11 12 ADC_ISC_IN0 SS0 Interrupt Status and Clear 0 1 ADC_ISC_IN1 SS1 Interrupt Status and Clear 1 2 ADC_ISC_IN2 SS2 Interrupt Status and Clear 2 3 ADC_ISC_IN3 SS3 Interrupt Status and Clear 3 4 OSTAT ADC Overflow Status 0x10 -1 read-write n 0x0 0x0 ADC_OSTAT_OV0 SS0 FIFO Overflow 0 1 ADC_OSTAT_OV1 SS1 FIFO Overflow 1 2 ADC_OSTAT_OV2 SS2 FIFO Overflow 2 3 ADC_OSTAT_OV3 SS3 FIFO Overflow 3 4 PC ADC Peripheral Configuration 0xFC4 -1 read-write n 0x0 0x0 ADC_PC_MCR Conversion Rate 0 4 ADC_PC_MCR_1_8 Eighth conversion rate. After a conversion completes, the logic pauses for 112 TADC periods before starting the next conversion 0x1 ADC_PC_MCR_1_4 Quarter conversion rate. After a conversion completes, the logic pauses for 48 TADC periods before starting the next conversion 0x3 ADC_PC_MCR_1_2 Half conversion rate. After a conversion completes, the logic pauses for 16 TADC periods before starting the next conversion 0x5 ADC_PC_MCR_FULL Full conversion rate (FCONV) as defined by TADC and NSH 0x7 PP ADC Peripheral Properties 0xFC0 -1 read-write n 0x0 0x0 ADC_PP_APSHT Application-Programmable Sample-and-Hold Time 24 25 ADC_PP_CH ADC Channel Count 4 10 ADC_PP_DC Digital Comparator Count 10 16 ADC_PP_MCR Maximum Conversion Rate 0 4 ADC_PP_MCR_FULL Full conversion rate (FCONV) as defined by TADC and NSH 0x7 ADC_PP_RSL Resolution 18 23 ADC_PP_TS Temperature Sensor 23 24 ADC_PP_TYPE ADC Architecture 16 18 ADC_PP_TYPE_SAR SAR 0x0 PSSI ADC Processor Sample Sequence Initiate 0x28 -1 read-write n 0x0 0x0 ADC_PSSI_GSYNC Global Synchronize 31 32 ADC_PSSI_SS0 SS0 Initiate 0 1 ADC_PSSI_SS1 SS1 Initiate 1 2 ADC_PSSI_SS2 SS2 Initiate 2 3 ADC_PSSI_SS3 SS3 Initiate 3 4 ADC_PSSI_SYNCWAIT Synchronize Wait 27 28 RIS ADC Raw Interrupt Status 0x4 -1 read-write n 0x0 0x0 ADC_RIS_DMAINR0 SS0 DMA Raw Interrupt Status 8 9 ADC_RIS_DMAINR1 SS1 DMA Raw Interrupt Status 9 10 ADC_RIS_DMAINR2 SS2 DMA Raw Interrupt Status 10 11 ADC_RIS_DMAINR3 SS3 DMA Raw Interrupt Status 11 12 ADC_RIS_INR0 SS0 Raw Interrupt Status 0 1 ADC_RIS_INR1 SS1 Raw Interrupt Status 1 2 ADC_RIS_INR2 SS2 Raw Interrupt Status 2 3 ADC_RIS_INR3 SS3 Raw Interrupt Status 3 4 ADC_RIS_INRDC Digital Comparator Raw Interrupt Status 16 17 SAC ADC Sample Averaging Control 0x30 -1 read-write n 0x0 0x0 ADC_SAC_AVG Hardware Averaging Control 0 3 ADC_SAC_AVG_OFF No hardware oversampling 0x0 ADC_SAC_AVG_2X 2x hardware oversampling 0x1 ADC_SAC_AVG_4X 4x hardware oversampling 0x2 ADC_SAC_AVG_8X 8x hardware oversampling 0x3 ADC_SAC_AVG_16X 16x hardware oversampling 0x4 ADC_SAC_AVG_32X 32x hardware oversampling 0x5 ADC_SAC_AVG_64X 64x hardware oversampling 0x6 SPC ADC Sample Phase Control 0x24 -1 read-write n 0x0 0x0 ADC_SPC_PHASE Phase Difference 0 4 ADC_SPC_PHASE_0 ADC sample lags by 0.0 0x0 ADC_SPC_PHASE_22_5 ADC sample lags by 22.5 0x1 ADC_SPC_PHASE_45 ADC sample lags by 45.0 0x2 ADC_SPC_PHASE_67_5 ADC sample lags by 67.5 0x3 ADC_SPC_PHASE_90 ADC sample lags by 90.0 0x4 ADC_SPC_PHASE_112_5 ADC sample lags by 112.5 0x5 ADC_SPC_PHASE_135 ADC sample lags by 135.0 0x6 ADC_SPC_PHASE_157_5 ADC sample lags by 157.5 0x7 ADC_SPC_PHASE_180 ADC sample lags by 180.0 0x8 ADC_SPC_PHASE_202_5 ADC sample lags by 202.5 0x9 ADC_SPC_PHASE_225 ADC sample lags by 225.0 0xa ADC_SPC_PHASE_247_5 ADC sample lags by 247.5 0xb ADC_SPC_PHASE_270 ADC sample lags by 270.0 0xc ADC_SPC_PHASE_292_5 ADC sample lags by 292.5 0xd ADC_SPC_PHASE_315 ADC sample lags by 315.0 0xe ADC_SPC_PHASE_337_5 ADC sample lags by 337.5 0xf SSCTL0 ADC Sample Sequence Control 0 0x44 -1 read-write n 0x0 0x0 ADC_SSCTL0_D0 1st Sample Differential Input Select 0 1 ADC_SSCTL0_D1 2nd Sample Differential Input Select 4 5 ADC_SSCTL0_D2 3rd Sample Differential Input Select 8 9 ADC_SSCTL0_D3 4th Sample Differential Input Select 12 13 ADC_SSCTL0_D4 5th Sample Differential Input Select 16 17 ADC_SSCTL0_D5 6th Sample Differential Input Select 20 21 ADC_SSCTL0_D6 7th Sample Differential Input Select 24 25 ADC_SSCTL0_D7 8th Sample Differential Input Select 28 29 ADC_SSCTL0_END0 1st Sample is End of Sequence 1 2 ADC_SSCTL0_END1 2nd Sample is End of Sequence 5 6 ADC_SSCTL0_END2 3rd Sample is End of Sequence 9 10 ADC_SSCTL0_END3 4th Sample is End of Sequence 13 14 ADC_SSCTL0_END4 5th Sample is End of Sequence 17 18 ADC_SSCTL0_END5 6th Sample is End of Sequence 21 22 ADC_SSCTL0_END6 7th Sample is End of Sequence 25 26 ADC_SSCTL0_END7 8th Sample is End of Sequence 29 30 ADC_SSCTL0_IE0 1st Sample Interrupt Enable 2 3 ADC_SSCTL0_IE1 2nd Sample Interrupt Enable 6 7 ADC_SSCTL0_IE2 3rd Sample Interrupt Enable 10 11 ADC_SSCTL0_IE3 4th Sample Interrupt Enable 14 15 ADC_SSCTL0_IE4 5th Sample Interrupt Enable 18 19 ADC_SSCTL0_IE5 6th Sample Interrupt Enable 22 23 ADC_SSCTL0_IE6 7th Sample Interrupt Enable 26 27 ADC_SSCTL0_IE7 8th Sample Interrupt Enable 30 31 ADC_SSCTL0_TS0 1st Sample Temp Sensor Select 3 4 ADC_SSCTL0_TS1 2nd Sample Temp Sensor Select 7 8 ADC_SSCTL0_TS2 3rd Sample Temp Sensor Select 11 12 ADC_SSCTL0_TS3 4th Sample Temp Sensor Select 15 16 ADC_SSCTL0_TS4 5th Sample Temp Sensor Select 19 20 ADC_SSCTL0_TS5 6th Sample Temp Sensor Select 23 24 ADC_SSCTL0_TS6 7th Sample Temp Sensor Select 27 28 ADC_SSCTL0_TS7 8th Sample Temp Sensor Select 31 32 SSCTL1 ADC Sample Sequence Control 1 0x64 -1 read-write n 0x0 0x0 ADC_SSCTL1_D0 1st Sample Differential Input Select 0 1 ADC_SSCTL1_D1 2nd Sample Differential Input Select 4 5 ADC_SSCTL1_D2 3rd Sample Differential Input Select 8 9 ADC_SSCTL1_D3 4th Sample Differential Input Select 12 13 ADC_SSCTL1_END0 1st Sample is End of Sequence 1 2 ADC_SSCTL1_END1 2nd Sample is End of Sequence 5 6 ADC_SSCTL1_END2 3rd Sample is End of Sequence 9 10 ADC_SSCTL1_END3 4th Sample is End of Sequence 13 14 ADC_SSCTL1_IE0 1st Sample Interrupt Enable 2 3 ADC_SSCTL1_IE1 2nd Sample Interrupt Enable 6 7 ADC_SSCTL1_IE2 3rd Sample Interrupt Enable 10 11 ADC_SSCTL1_IE3 4th Sample Interrupt Enable 14 15 ADC_SSCTL1_TS0 1st Sample Temp Sensor Select 3 4 ADC_SSCTL1_TS1 2nd Sample Temp Sensor Select 7 8 ADC_SSCTL1_TS2 3rd Sample Temp Sensor Select 11 12 ADC_SSCTL1_TS3 4th Sample Temp Sensor Select 15 16 SSCTL2 ADC Sample Sequence Control 2 0x84 -1 read-write n 0x0 0x0 ADC_SSCTL2_D0 1st Sample Differential Input Select 0 1 ADC_SSCTL2_D1 2nd Sample Differential Input Select 4 5 ADC_SSCTL2_D2 3rd Sample Differential Input Select 8 9 ADC_SSCTL2_D3 4th Sample Differential Input Select 12 13 ADC_SSCTL2_END0 1st Sample is End of Sequence 1 2 ADC_SSCTL2_END1 2nd Sample is End of Sequence 5 6 ADC_SSCTL2_END2 3rd Sample is End of Sequence 9 10 ADC_SSCTL2_END3 4th Sample is End of Sequence 13 14 ADC_SSCTL2_IE0 1st Sample Interrupt Enable 2 3 ADC_SSCTL2_IE1 2nd Sample Interrupt Enable 6 7 ADC_SSCTL2_IE2 3rd Sample Interrupt Enable 10 11 ADC_SSCTL2_IE3 4th Sample Interrupt Enable 14 15 ADC_SSCTL2_TS0 1st Sample Temp Sensor Select 3 4 ADC_SSCTL2_TS1 2nd Sample Temp Sensor Select 7 8 ADC_SSCTL2_TS2 3rd Sample Temp Sensor Select 11 12 ADC_SSCTL2_TS3 4th Sample Temp Sensor Select 15 16 SSCTL3 ADC Sample Sequence Control 3 0xA4 -1 read-write n 0x0 0x0 ADC_SSCTL3_D0 Sample Differential Input Select 0 1 ADC_SSCTL3_END0 End of Sequence 1 2 ADC_SSCTL3_IE0 Sample Interrupt Enable 2 3 ADC_SSCTL3_TS0 1st Sample Temp Sensor Select 3 4 SSDC0 ADC Sample Sequence 0 Digital Comparator Select 0x54 -1 read-write n 0x0 0x0 ADC_SSDC0_S0DCSEL Sample 0 Digital Comparator Select 0 4 ADC_SSDC0_S1DCSEL Sample 1 Digital Comparator Select 4 8 ADC_SSDC0_S2DCSEL Sample 2 Digital Comparator Select 8 12 ADC_SSDC0_S3DCSEL Sample 3 Digital Comparator Select 12 16 ADC_SSDC0_S4DCSEL Sample 4 Digital Comparator Select 16 20 ADC_SSDC0_S5DCSEL Sample 5 Digital Comparator Select 20 24 ADC_SSDC0_S6DCSEL Sample 6 Digital Comparator Select 24 28 ADC_SSDC0_S7DCSEL Sample 7 Digital Comparator Select 28 32 SSDC1 ADC Sample Sequence 1 Digital Comparator Select 0x74 -1 read-write n 0x0 0x0 ADC_SSDC1_S0DCSEL Sample 0 Digital Comparator Select 0 4 ADC_SSDC1_S1DCSEL Sample 1 Digital Comparator Select 4 8 ADC_SSDC1_S2DCSEL Sample 2 Digital Comparator Select 8 12 ADC_SSDC1_S3DCSEL Sample 3 Digital Comparator Select 12 16 SSDC2 ADC Sample Sequence 2 Digital Comparator Select 0x94 -1 read-write n 0x0 0x0 ADC_SSDC2_S0DCSEL Sample 0 Digital Comparator Select 0 4 ADC_SSDC2_S1DCSEL Sample 1 Digital Comparator Select 4 8 ADC_SSDC2_S2DCSEL Sample 2 Digital Comparator Select 8 12 ADC_SSDC2_S3DCSEL Sample 3 Digital Comparator Select 12 16 SSDC3 ADC Sample Sequence 3 Digital Comparator Select 0xB4 -1 read-write n 0x0 0x0 ADC_SSDC3_S0DCSEL Sample 0 Digital Comparator Select 0 4 SSEMUX0 ADC Sample Sequence Extended Input Multiplexer Select 0 0x58 -1 read-write n 0x0 0x0 ADC_SSEMUX0_EMUX0 1st Sample Input Select (Upper Bit) 0 1 ADC_SSEMUX0_EMUX1 2th Sample Input Select (Upper Bit) 4 5 ADC_SSEMUX0_EMUX2 3rd Sample Input Select (Upper Bit) 8 9 ADC_SSEMUX0_EMUX3 4th Sample Input Select (Upper Bit) 12 13 ADC_SSEMUX0_EMUX4 5th Sample Input Select (Upper Bit) 16 17 ADC_SSEMUX0_EMUX5 6th Sample Input Select (Upper Bit) 20 21 ADC_SSEMUX0_EMUX6 7th Sample Input Select (Upper Bit) 24 25 ADC_SSEMUX0_EMUX7 8th Sample Input Select (Upper Bit) 28 29 SSEMUX1 ADC Sample Sequence Extended Input Multiplexer Select 1 0x78 -1 read-write n 0x0 0x0 ADC_SSEMUX1_EMUX0 1st Sample Input Select (Upper Bit) 0 1 ADC_SSEMUX1_EMUX1 2th Sample Input Select (Upper Bit) 4 5 ADC_SSEMUX1_EMUX2 3rd Sample Input Select (Upper Bit) 8 9 ADC_SSEMUX1_EMUX3 4th Sample Input Select (Upper Bit) 12 13 SSEMUX2 ADC Sample Sequence Extended Input Multiplexer Select 2 0x98 -1 read-write n 0x0 0x0 ADC_SSEMUX2_EMUX0 1st Sample Input Select (Upper Bit) 0 1 ADC_SSEMUX2_EMUX1 2th Sample Input Select (Upper Bit) 4 5 ADC_SSEMUX2_EMUX2 3rd Sample Input Select (Upper Bit) 8 9 ADC_SSEMUX2_EMUX3 4th Sample Input Select (Upper Bit) 12 13 SSEMUX3 ADC Sample Sequence Extended Input Multiplexer Select 3 0xB8 -1 read-write n 0x0 0x0 ADC_SSEMUX3_EMUX0 1st Sample Input Select (Upper Bit) 0 1 SSFIFO0 ADC Sample Sequence Result FIFO 0 0x48 -1 read-write n 0x0 0x0 ADC_SSFIFO0_DATA Conversion Result Data 0 12 SSFIFO1 ADC Sample Sequence Result FIFO 1 0x68 -1 read-write n 0x0 0x0 ADC_SSFIFO1_DATA Conversion Result Data 0 12 SSFIFO2 ADC Sample Sequence Result FIFO 2 0x88 -1 read-write n 0x0 0x0 ADC_SSFIFO2_DATA Conversion Result Data 0 12 SSFIFO3 ADC Sample Sequence Result FIFO 3 0xA8 -1 read-write n 0x0 0x0 ADC_SSFIFO3_DATA Conversion Result Data 0 12 SSFSTAT0 ADC Sample Sequence FIFO 0 Status 0x4C -1 read-write n 0x0 0x0 ADC_SSFSTAT0_EMPTY FIFO Empty 8 9 ADC_SSFSTAT0_FULL FIFO Full 12 13 ADC_SSFSTAT0_HPTR FIFO Head Pointer 4 8 ADC_SSFSTAT0_TPTR FIFO Tail Pointer 0 4 SSFSTAT1 ADC Sample Sequence FIFO 1 Status 0x6C -1 read-write n 0x0 0x0 ADC_SSFSTAT1_EMPTY FIFO Empty 8 9 ADC_SSFSTAT1_FULL FIFO Full 12 13 ADC_SSFSTAT1_HPTR FIFO Head Pointer 4 8 ADC_SSFSTAT1_TPTR FIFO Tail Pointer 0 4 SSFSTAT2 ADC Sample Sequence FIFO 2 Status 0x8C -1 read-write n 0x0 0x0 ADC_SSFSTAT2_EMPTY FIFO Empty 8 9 ADC_SSFSTAT2_FULL FIFO Full 12 13 ADC_SSFSTAT2_HPTR FIFO Head Pointer 4 8 ADC_SSFSTAT2_TPTR FIFO Tail Pointer 0 4 SSFSTAT3 ADC Sample Sequence FIFO 3 Status 0xAC -1 read-write n 0x0 0x0 ADC_SSFSTAT3_EMPTY FIFO Empty 8 9 ADC_SSFSTAT3_FULL FIFO Full 12 13 ADC_SSFSTAT3_HPTR FIFO Head Pointer 4 8 ADC_SSFSTAT3_TPTR FIFO Tail Pointer 0 4 SSMUX0 ADC Sample Sequence Input Multiplexer Select 0 0x40 -1 read-write n 0x0 0x0 ADC_SSMUX0_MUX0 1st Sample Input Select 0 4 ADC_SSMUX0_MUX1 2nd Sample Input Select 4 8 ADC_SSMUX0_MUX2 3rd Sample Input Select 8 12 ADC_SSMUX0_MUX3 4th Sample Input Select 12 16 ADC_SSMUX0_MUX4 5th Sample Input Select 16 20 ADC_SSMUX0_MUX5 6th Sample Input Select 20 24 ADC_SSMUX0_MUX6 7th Sample Input Select 24 28 ADC_SSMUX0_MUX7 8th Sample Input Select 28 32 SSMUX1 ADC Sample Sequence Input Multiplexer Select 1 0x60 -1 read-write n 0x0 0x0 ADC_SSMUX1_MUX0 1st Sample Input Select 0 4 ADC_SSMUX1_MUX1 2nd Sample Input Select 4 8 ADC_SSMUX1_MUX2 3rd Sample Input Select 8 12 ADC_SSMUX1_MUX3 4th Sample Input Select 12 16 SSMUX2 ADC Sample Sequence Input Multiplexer Select 2 0x80 -1 read-write n 0x0 0x0 ADC_SSMUX2_MUX0 1st Sample Input Select 0 4 ADC_SSMUX2_MUX1 2nd Sample Input Select 4 8 ADC_SSMUX2_MUX2 3rd Sample Input Select 8 12 ADC_SSMUX2_MUX3 4th Sample Input Select 12 16 SSMUX3 ADC Sample Sequence Input Multiplexer Select 3 0xA0 -1 read-write n 0x0 0x0 ADC_SSMUX3_MUX0 1st Sample Input Select 0 4 SSOP0 ADC Sample Sequence 0 Operation 0x50 -1 read-write n 0x0 0x0 ADC_SSOP0_S0DCOP Sample 0 Digital Comparator Operation 0 1 ADC_SSOP0_S1DCOP Sample 1 Digital Comparator Operation 4 5 ADC_SSOP0_S2DCOP Sample 2 Digital Comparator Operation 8 9 ADC_SSOP0_S3DCOP Sample 3 Digital Comparator Operation 12 13 ADC_SSOP0_S4DCOP Sample 4 Digital Comparator Operation 16 17 ADC_SSOP0_S5DCOP Sample 5 Digital Comparator Operation 20 21 ADC_SSOP0_S6DCOP Sample 6 Digital Comparator Operation 24 25 ADC_SSOP0_S7DCOP Sample 7 Digital Comparator Operation 28 29 SSOP1 ADC Sample Sequence 1 Operation 0x70 -1 read-write n 0x0 0x0 ADC_SSOP1_S0DCOP Sample 0 Digital Comparator Operation 0 1 ADC_SSOP1_S1DCOP Sample 1 Digital Comparator Operation 4 5 ADC_SSOP1_S2DCOP Sample 2 Digital Comparator Operation 8 9 ADC_SSOP1_S3DCOP Sample 3 Digital Comparator Operation 12 13 SSOP2 ADC Sample Sequence 2 Operation 0x90 -1 read-write n 0x0 0x0 ADC_SSOP2_S0DCOP Sample 0 Digital Comparator Operation 0 1 ADC_SSOP2_S1DCOP Sample 1 Digital Comparator Operation 4 5 ADC_SSOP2_S2DCOP Sample 2 Digital Comparator Operation 8 9 ADC_SSOP2_S3DCOP Sample 3 Digital Comparator Operation 12 13 SSOP3 ADC Sample Sequence 3 Operation 0xB0 -1 read-write n 0x0 0x0 ADC_SSOP3_S0DCOP Sample 0 Digital Comparator Operation 0 1 SSPRI ADC Sample Sequencer Priority 0x20 -1 read-write n 0x0 0x0 ADC_SSPRI_SS0 SS0 Priority 0 2 ADC_SSPRI_SS1 SS1 Priority 4 6 ADC_SSPRI_SS2 SS2 Priority 8 10 ADC_SSPRI_SS3 SS3 Priority 12 14 SSTSH0 ADC Sample Sequence 0 Sample and Hold Time 0x5C -1 read-write n 0x0 0x0 ADC_SSTSH0_TSH0 1st Sample and Hold Period Select 0 4 ADC_SSTSH0_TSH1 2nd Sample and Hold Period Select 4 8 ADC_SSTSH0_TSH2 3rd Sample and Hold Period Select 8 12 ADC_SSTSH0_TSH3 4th Sample and Hold Period Select 12 16 ADC_SSTSH0_TSH4 5th Sample and Hold Period Select 16 20 ADC_SSTSH0_TSH5 6th Sample and Hold Period Select 20 24 ADC_SSTSH0_TSH6 7th Sample and Hold Period Select 24 28 ADC_SSTSH0_TSH7 8th Sample and Hold Period Select 28 32 SSTSH1 ADC Sample Sequence 1 Sample and Hold Time 0x7C -1 read-write n 0x0 0x0 ADC_SSTSH1_TSH0 1st Sample and Hold Period Select 0 4 ADC_SSTSH1_TSH1 2nd Sample and Hold Period Select 4 8 ADC_SSTSH1_TSH2 3rd Sample and Hold Period Select 8 12 ADC_SSTSH1_TSH3 4th Sample and Hold Period Select 12 16 SSTSH2 ADC Sample Sequence 2 Sample and Hold Time 0x9C -1 read-write n 0x0 0x0 ADC_SSTSH2_TSH0 1st Sample and Hold Period Select 0 4 ADC_SSTSH2_TSH1 2nd Sample and Hold Period Select 4 8 ADC_SSTSH2_TSH2 3rd Sample and Hold Period Select 8 12 ADC_SSTSH2_TSH3 4th Sample and Hold Period Select 12 16 SSTSH3 ADC Sample Sequence 3 Sample and Hold Time 0xBC -1 read-write n 0x0 0x0 ADC_SSTSH3_TSH0 1st Sample and Hold Period Select 0 4 TSSEL ADC Trigger Source Select 0x1C -1 read-write n 0x0 0x0 ADC_TSSEL_PS0 Generator 0 PWM Module Trigger Select 4 6 ADC_TSSEL_PS0_0 Use Generator 0 (and its trigger) in PWM module 0 0x0 ADC_TSSEL_PS1 Generator 1 PWM Module Trigger Select 12 14 ADC_TSSEL_PS1_0 Use Generator 1 (and its trigger) in PWM module 0 0x0 ADC_TSSEL_PS2 Generator 2 PWM Module Trigger Select 20 22 ADC_TSSEL_PS2_0 Use Generator 2 (and its trigger) in PWM module 0 0x0 ADC_TSSEL_PS3 Generator 3 PWM Module Trigger Select 28 30 ADC_TSSEL_PS3_0 Use Generator 3 (and its trigger) in PWM module 0 0x0 USTAT ADC Underflow Status 0x18 -1 read-write n 0x0 0x0 ADC_USTAT_UV0 SS0 FIFO Underflow 0 1 ADC_USTAT_UV1 SS1 FIFO Underflow 1 2 ADC_USTAT_UV2 SS2 FIFO Underflow 2 3 ADC_USTAT_UV3 SS3 FIFO Underflow 3 4 CAN0 Register map for CAN0 peripheral CAN 0x0 0x0 0x1000 registers n CAN0 38 BIT CAN Bit Timing 0xC -1 read-write n 0x0 0x0 CAN_BIT_BRP Baud Rate Prescaler 0 6 CAN_BIT_SJW (Re)Synchronization Jump Width 6 8 CAN_BIT_TSEG1 Time Segment Before Sample Point 8 12 CAN_BIT_TSEG2 Time Segment after Sample Point 12 15 BRPE CAN Baud Rate Prescaler Extension 0x18 -1 read-write n 0x0 0x0 CAN_BRPE_BRPE Baud Rate Prescaler Extension 0 4 CAN0BIT CAN Bit Timing 0xC read-write n 0x0 0x0 CAN_BIT_BRP Baud Rate Prescaler 0 6 CAN_BIT_SJW (Re)Synchronization Jump Width 6 8 CAN_BIT_TSEG1 Time Segment Before Sample Point 8 12 CAN_BIT_TSEG2 Time Segment after Sample Point 12 15 CAN0BRPE CAN Baud Rate Prescaler Extension 0x18 read-write n 0x0 0x0 CAN_BRPE_BRPE Baud Rate Prescaler Extension 0 4 CAN0CTL CAN Control 0x0 read-write n 0x0 0x0 CAN_CTL_CCE Configuration Change Enable 6 7 CAN_CTL_DAR Disable Automatic-Retransmission 5 6 CAN_CTL_EIE Error Interrupt Enable 3 4 CAN_CTL_IE CAN Interrupt Enable 1 2 CAN_CTL_INIT Initialization 0 1 CAN_CTL_SIE Status Interrupt Enable 2 3 CAN_CTL_TEST Test Mode Enable 7 8 CAN0ERR CAN Error Counter 0x8 read-write n 0x0 0x0 CAN_ERR_REC Receive Error Counter 8 15 CAN_ERR_RP Received Error Passive 15 16 CAN_ERR_TEC Transmit Error Counter 0 8 CAN0IF1ARB1 CAN IF1 Arbitration 1 0x30 read-write n 0x0 0x0 CAN_IF1ARB1_ID Message Identifier 0 16 CAN0IF1ARB2 CAN IF1 Arbitration 2 0x34 read-write n 0x0 0x0 CAN_IF1ARB2_DIR Message Direction 13 14 CAN_IF1ARB2_ID Message Identifier 0 13 CAN_IF1ARB2_MSGVAL Message Valid 15 16 CAN_IF1ARB2_XTD Extended Identifier 14 15 CAN0IF1CMSK CAN IF1 Command Mask 0x24 read-write n 0x0 0x0 CAN_IF1CMSK_ARB Access Arbitration Bits 5 6 CAN_IF1CMSK_CLRINTPND Clear Interrupt Pending Bit 3 4 CAN_IF1CMSK_CONTROL Access Control Bits 4 5 CAN_IF1CMSK_DATAA Access Data Byte 0 to 3 1 2 CAN_IF1CMSK_DATAB Access Data Byte 4 to 7 0 1 CAN_IF1CMSK_MASK Access Mask Bits 6 7 CAN_IF1CMSK_NEWDAT Access New Data 2 3 CAN_IF1CMSK_WRNRD Write, Not Read 7 8 CAN0IF1CRQ CAN IF1 Command Request 0x20 read-write n 0x0 0x0 CAN_IF1CRQ_BUSY Busy Flag 15 16 CAN_IF1CRQ_MNUM Message Number 0 6 CAN0IF1DA1 CAN IF1 Data A1 0x3C read-write n 0x0 0x0 CAN_IF1DA1_DATA Data 0 16 CAN0IF1DA2 CAN IF1 Data A2 0x40 read-write n 0x0 0x0 CAN_IF1DA2_DATA Data 0 16 CAN0IF1DB1 CAN IF1 Data B1 0x44 read-write n 0x0 0x0 CAN_IF1DB1_DATA Data 0 16 CAN0IF1DB2 CAN IF1 Data B2 0x48 read-write n 0x0 0x0 CAN_IF1DB2_DATA Data 0 16 CAN0IF1MCTL CAN IF1 Message Control 0x38 read-write n 0x0 0x0 CAN_IF1MCTL_DLC Data Length Code 0 4 CAN_IF1MCTL_EOB End of Buffer 7 8 CAN_IF1MCTL_INTPND Interrupt Pending 13 14 CAN_IF1MCTL_MSGLST Message Lost 14 15 CAN_IF1MCTL_NEWDAT New Data 15 16 CAN_IF1MCTL_RMTEN Remote Enable 9 10 CAN_IF1MCTL_RXIE Receive Interrupt Enable 10 11 CAN_IF1MCTL_TXIE Transmit Interrupt Enable 11 12 CAN_IF1MCTL_TXRQST Transmit Request 8 9 CAN_IF1MCTL_UMASK Use Acceptance Mask 12 13 CAN0IF1MSK1 CAN IF1 Mask 1 0x28 read-write n 0x0 0x0 CAN_IF1MSK1_IDMSK Identifier Mask 0 16 CAN0IF1MSK2 CAN IF1 Mask 2 0x2C read-write n 0x0 0x0 CAN_IF1MSK2_IDMSK Identifier Mask 0 13 CAN_IF1MSK2_MDIR Mask Message Direction 14 15 CAN_IF1MSK2_MXTD Mask Extended Identifier 15 16 CAN0IF2ARB1 CAN IF2 Arbitration 1 0x90 read-write n 0x0 0x0 CAN_IF2ARB1_ID Message Identifier 0 16 CAN0IF2ARB2 CAN IF2 Arbitration 2 0x94 read-write n 0x0 0x0 CAN_IF2ARB2_DIR Message Direction 13 14 CAN_IF2ARB2_ID Message Identifier 0 13 CAN_IF2ARB2_MSGVAL Message Valid 15 16 CAN_IF2ARB2_XTD Extended Identifier 14 15 CAN0IF2CMSK CAN IF2 Command Mask 0x84 read-write n 0x0 0x0 CAN_IF2CMSK_ARB Access Arbitration Bits 5 6 CAN_IF2CMSK_CLRINTPND Clear Interrupt Pending Bit 3 4 CAN_IF2CMSK_CONTROL Access Control Bits 4 5 CAN_IF2CMSK_DATAA Access Data Byte 0 to 3 1 2 CAN_IF2CMSK_DATAB Access Data Byte 4 to 7 0 1 CAN_IF2CMSK_MASK Access Mask Bits 6 7 CAN_IF2CMSK_NEWDAT Access New Data 2 3 CAN_IF2CMSK_WRNRD Write, Not Read 7 8 CAN0IF2CRQ CAN IF2 Command Request 0x80 read-write n 0x0 0x0 CAN_IF2CRQ_BUSY Busy Flag 15 16 CAN_IF2CRQ_MNUM Message Number 0 6 CAN0IF2DA1 CAN IF2 Data A1 0x9C read-write n 0x0 0x0 CAN_IF2DA1_DATA Data 0 16 CAN0IF2DA2 CAN IF2 Data A2 0xA0 read-write n 0x0 0x0 CAN_IF2DA2_DATA Data 0 16 CAN0IF2DB1 CAN IF2 Data B1 0xA4 read-write n 0x0 0x0 CAN_IF2DB1_DATA Data 0 16 CAN0IF2DB2 CAN IF2 Data B2 0xA8 read-write n 0x0 0x0 CAN_IF2DB2_DATA Data 0 16 CAN0IF2MCTL CAN IF2 Message Control 0x98 read-write n 0x0 0x0 CAN_IF2MCTL_DLC Data Length Code 0 4 CAN_IF2MCTL_EOB End of Buffer 7 8 CAN_IF2MCTL_INTPND Interrupt Pending 13 14 CAN_IF2MCTL_MSGLST Message Lost 14 15 CAN_IF2MCTL_NEWDAT New Data 15 16 CAN_IF2MCTL_RMTEN Remote Enable 9 10 CAN_IF2MCTL_RXIE Receive Interrupt Enable 10 11 CAN_IF2MCTL_TXIE Transmit Interrupt Enable 11 12 CAN_IF2MCTL_TXRQST Transmit Request 8 9 CAN_IF2MCTL_UMASK Use Acceptance Mask 12 13 CAN0IF2MSK1 CAN IF2 Mask 1 0x88 read-write n 0x0 0x0 CAN_IF2MSK1_IDMSK Identifier Mask 0 16 CAN0IF2MSK2 CAN IF2 Mask 2 0x8C read-write n 0x0 0x0 CAN_IF2MSK2_IDMSK Identifier Mask 0 13 CAN_IF2MSK2_MDIR Mask Message Direction 14 15 CAN_IF2MSK2_MXTD Mask Extended Identifier 15 16 CAN0INT CAN Interrupt 0x10 read-write n 0x0 0x0 CAN_INT_INTID Interrupt Identifier 0 16 CAN_INT_INTID_NONE No interrupt pending 0x0 CAN_INT_INTID_STATUS Status Interrupt 0x8000 CAN0MSG1INT CAN Message 1 Interrupt Pending 0x140 read-write n 0x0 0x0 CAN_MSG1INT_INTPND Interrupt Pending Bits 0 16 CAN0MSG1VAL CAN Message 1 Valid 0x160 read-write n 0x0 0x0 CAN_MSG1VAL_MSGVAL Message Valid Bits 0 16 CAN0MSG2INT CAN Message 2 Interrupt Pending 0x144 read-write n 0x0 0x0 CAN_MSG2INT_INTPND Interrupt Pending Bits 0 16 CAN0MSG2VAL CAN Message 2 Valid 0x164 read-write n 0x0 0x0 CAN_MSG2VAL_MSGVAL Message Valid Bits 0 16 CAN0NWDA1 CAN New Data 1 0x120 read-write n 0x0 0x0 CAN_NWDA1_NEWDAT New Data Bits 0 16 CAN0NWDA2 CAN New Data 2 0x124 read-write n 0x0 0x0 CAN_NWDA2_NEWDAT New Data Bits 0 16 CAN0STS CAN Status 0x4 read-write n 0x0 0x0 CAN_STS_BOFF Bus-Off Status 7 8 CAN_STS_EPASS Error Passive 5 6 CAN_STS_EWARN Warning Status 6 7 CAN_STS_LEC Last Error Code 0 3 CAN_STS_LEC_NONE No Error 0x0 CAN_STS_LEC_STUFF Stuff Error 0x1 CAN_STS_LEC_FORM Format Error 0x2 CAN_STS_LEC_ACK ACK Error 0x3 CAN_STS_LEC_BIT1 Bit 1 Error 0x4 CAN_STS_LEC_BIT0 Bit 0 Error 0x5 CAN_STS_LEC_CRC CRC Error 0x6 CAN_STS_LEC_NOEVENT No Event 0x7 CAN_STS_RXOK Received a Message Successfully 4 5 CAN_STS_TXOK Transmitted a Message Successfully 3 4 CAN0TST CAN Test 0x14 read-write n 0x0 0x0 CAN_TST_BASIC Basic Mode 2 3 CAN_TST_LBACK Loopback Mode 4 5 CAN_TST_RX Receive Observation 7 8 CAN_TST_SILENT Silent Mode 3 4 CAN_TST_TX Transmit Control 5 7 CAN_TST_TX_CANCTL CAN Module Control 0x0 CAN_TST_TX_SAMPLE Sample Point 0x1 CAN_TST_TX_DOMINANT Driven Low 0x2 CAN_TST_TX_RECESSIVE Driven High 0x3 CAN0TXRQ1 CAN Transmission Request 1 0x100 read-write n 0x0 0x0 CAN_TXRQ1_TXRQST Transmission Request Bits 0 16 CAN0TXRQ2 CAN Transmission Request 2 0x104 read-write n 0x0 0x0 CAN_TXRQ2_TXRQST Transmission Request Bits 0 16 CTL CAN Control 0x0 -1 read-write n 0x0 0x0 CAN_CTL_CCE Configuration Change Enable 6 7 CAN_CTL_DAR Disable Automatic-Retransmission 5 6 CAN_CTL_EIE Error Interrupt Enable 3 4 CAN_CTL_IE CAN Interrupt Enable 1 2 CAN_CTL_INIT Initialization 0 1 CAN_CTL_SIE Status Interrupt Enable 2 3 CAN_CTL_TEST Test Mode Enable 7 8 ERR CAN Error Counter 0x8 -1 read-write n 0x0 0x0 CAN_ERR_REC Receive Error Counter 8 15 CAN_ERR_RP Received Error Passive 15 16 CAN_ERR_TEC Transmit Error Counter 0 8 IF1ARB1 CAN IF1 Arbitration 1 0x30 -1 read-write n 0x0 0x0 CAN_IF1ARB1_ID Message Identifier 0 16 IF1ARB2 CAN IF1 Arbitration 2 0x34 -1 read-write n 0x0 0x0 CAN_IF1ARB2_DIR Message Direction 13 14 CAN_IF1ARB2_ID Message Identifier 0 13 CAN_IF1ARB2_MSGVAL Message Valid 15 16 CAN_IF1ARB2_XTD Extended Identifier 14 15 IF1CMSK CAN IF1 Command Mask 0x24 -1 read-write n 0x0 0x0 CAN_IF1CMSK_ARB Access Arbitration Bits 5 6 CAN_IF1CMSK_CLRINTPND Clear Interrupt Pending Bit 3 4 CAN_IF1CMSK_CONTROL Access Control Bits 4 5 CAN_IF1CMSK_DATAA Access Data Byte 0 to 3 1 2 CAN_IF1CMSK_DATAB Access Data Byte 4 to 7 0 1 CAN_IF1CMSK_MASK Access Mask Bits 6 7 CAN_IF1CMSK_NEWDAT Access New Data 2 3 CAN_IF1CMSK_TXRQST Access Transmission Request 2 3 CAN_IF1CMSK_WRNRD Write, Not Read 7 8 IF1CRQ CAN IF1 Command Request 0x20 -1 read-write n 0x0 0x0 CAN_IF1CRQ_BUSY Busy Flag 15 16 CAN_IF1CRQ_MNUM Message Number 0 6 IF1DA1 CAN IF1 Data A1 0x3C -1 read-write n 0x0 0x0 CAN_IF1DA1_DATA Data 0 16 IF1DA2 CAN IF1 Data A2 0x40 -1 read-write n 0x0 0x0 CAN_IF1DA2_DATA Data 0 16 IF1DB1 CAN IF1 Data B1 0x44 -1 read-write n 0x0 0x0 CAN_IF1DB1_DATA Data 0 16 IF1DB2 CAN IF1 Data B2 0x48 -1 read-write n 0x0 0x0 CAN_IF1DB2_DATA Data 0 16 IF1MCTL CAN IF1 Message Control 0x38 -1 read-write n 0x0 0x0 CAN_IF1MCTL_DLC Data Length Code 0 4 CAN_IF1MCTL_EOB End of Buffer 7 8 CAN_IF1MCTL_INTPND Interrupt Pending 13 14 CAN_IF1MCTL_MSGLST Message Lost 14 15 CAN_IF1MCTL_NEWDAT New Data 15 16 CAN_IF1MCTL_RMTEN Remote Enable 9 10 CAN_IF1MCTL_RXIE Receive Interrupt Enable 10 11 CAN_IF1MCTL_TXIE Transmit Interrupt Enable 11 12 CAN_IF1MCTL_TXRQST Transmit Request 8 9 CAN_IF1MCTL_UMASK Use Acceptance Mask 12 13 IF1MSK1 CAN IF1 Mask 1 0x28 -1 read-write n 0x0 0x0 CAN_IF1MSK1_IDMSK Identifier Mask 0 16 IF1MSK2 CAN IF1 Mask 2 0x2C -1 read-write n 0x0 0x0 CAN_IF1MSK2_IDMSK Identifier Mask 0 13 CAN_IF1MSK2_MDIR Mask Message Direction 14 15 CAN_IF1MSK2_MXTD Mask Extended Identifier 15 16 IF2ARB1 CAN IF2 Arbitration 1 0x90 -1 read-write n 0x0 0x0 CAN_IF2ARB1_ID Message Identifier 0 16 IF2ARB2 CAN IF2 Arbitration 2 0x94 -1 read-write n 0x0 0x0 CAN_IF2ARB2_DIR Message Direction 13 14 CAN_IF2ARB2_ID Message Identifier 0 13 CAN_IF2ARB2_MSGVAL Message Valid 15 16 CAN_IF2ARB2_XTD Extended Identifier 14 15 IF2CMSK CAN IF2 Command Mask 0x84 -1 read-write n 0x0 0x0 CAN_IF2CMSK_ARB Access Arbitration Bits 5 6 CAN_IF2CMSK_CLRINTPND Clear Interrupt Pending Bit 3 4 CAN_IF2CMSK_CONTROL Access Control Bits 4 5 CAN_IF2CMSK_DATAA Access Data Byte 0 to 3 1 2 CAN_IF2CMSK_DATAB Access Data Byte 4 to 7 0 1 CAN_IF2CMSK_MASK Access Mask Bits 6 7 CAN_IF2CMSK_NEWDAT Access New Data 2 3 CAN_IF2CMSK_TXRQST Access Transmission Request 2 3 CAN_IF2CMSK_WRNRD Write, Not Read 7 8 IF2CRQ CAN IF2 Command Request 0x80 -1 read-write n 0x0 0x0 CAN_IF2CRQ_BUSY Busy Flag 15 16 CAN_IF2CRQ_MNUM Message Number 0 6 IF2DA1 CAN IF2 Data A1 0x9C -1 read-write n 0x0 0x0 CAN_IF2DA1_DATA Data 0 16 IF2DA2 CAN IF2 Data A2 0xA0 -1 read-write n 0x0 0x0 CAN_IF2DA2_DATA Data 0 16 IF2DB1 CAN IF2 Data B1 0xA4 -1 read-write n 0x0 0x0 CAN_IF2DB1_DATA Data 0 16 IF2DB2 CAN IF2 Data B2 0xA8 -1 read-write n 0x0 0x0 CAN_IF2DB2_DATA Data 0 16 IF2MCTL CAN IF2 Message Control 0x98 -1 read-write n 0x0 0x0 CAN_IF2MCTL_DLC Data Length Code 0 4 CAN_IF2MCTL_EOB End of Buffer 7 8 CAN_IF2MCTL_INTPND Interrupt Pending 13 14 CAN_IF2MCTL_MSGLST Message Lost 14 15 CAN_IF2MCTL_NEWDAT New Data 15 16 CAN_IF2MCTL_RMTEN Remote Enable 9 10 CAN_IF2MCTL_RXIE Receive Interrupt Enable 10 11 CAN_IF2MCTL_TXIE Transmit Interrupt Enable 11 12 CAN_IF2MCTL_TXRQST Transmit Request 8 9 CAN_IF2MCTL_UMASK Use Acceptance Mask 12 13 IF2MSK1 CAN IF2 Mask 1 0x88 -1 read-write n 0x0 0x0 CAN_IF2MSK1_IDMSK Identifier Mask 0 16 IF2MSK2 CAN IF2 Mask 2 0x8C -1 read-write n 0x0 0x0 CAN_IF2MSK2_IDMSK Identifier Mask 0 13 CAN_IF2MSK2_MDIR Mask Message Direction 14 15 CAN_IF2MSK2_MXTD Mask Extended Identifier 15 16 INT CAN Interrupt 0x10 -1 read-write n 0x0 0x0 CAN_INT_INTID Interrupt Identifier 0 16 CAN_INT_INTID_NONE No interrupt pending 0x0 CAN_INT_INTID_STATUS Status Interrupt 0x8000 MSG1INT CAN Message 1 Interrupt Pending 0x140 -1 read-write n 0x0 0x0 CAN_MSG1INT_INTPND Interrupt Pending Bits 0 16 MSG1VAL CAN Message 1 Valid 0x160 -1 read-write n 0x0 0x0 CAN_MSG1VAL_MSGVAL Message Valid Bits 0 16 MSG2INT CAN Message 2 Interrupt Pending 0x144 -1 read-write n 0x0 0x0 CAN_MSG2INT_INTPND Interrupt Pending Bits 0 16 MSG2VAL CAN Message 2 Valid 0x164 -1 read-write n 0x0 0x0 CAN_MSG2VAL_MSGVAL Message Valid Bits 0 16 NWDA1 CAN New Data 1 0x120 -1 read-write n 0x0 0x0 CAN_NWDA1_NEWDAT New Data Bits 0 16 NWDA2 CAN New Data 2 0x124 -1 read-write n 0x0 0x0 CAN_NWDA2_NEWDAT New Data Bits 0 16 STS CAN Status 0x4 -1 read-write n 0x0 0x0 CAN_STS_BOFF Bus-Off Status 7 8 CAN_STS_EPASS Error Passive 5 6 CAN_STS_EWARN Warning Status 6 7 CAN_STS_LEC Last Error Code 0 3 CAN_STS_LEC_NONE No Error 0x0 CAN_STS_LEC_STUFF Stuff Error 0x1 CAN_STS_LEC_FORM Format Error 0x2 CAN_STS_LEC_ACK ACK Error 0x3 CAN_STS_LEC_BIT1 Bit 1 Error 0x4 CAN_STS_LEC_BIT0 Bit 0 Error 0x5 CAN_STS_LEC_CRC CRC Error 0x6 CAN_STS_LEC_NOEVENT No Event 0x7 CAN_STS_RXOK Received a Message Successfully 4 5 CAN_STS_TXOK Transmitted a Message Successfully 3 4 TST CAN Test 0x14 -1 read-write n 0x0 0x0 CAN_TST_BASIC Basic Mode 2 3 CAN_TST_LBACK Loopback Mode 4 5 CAN_TST_RX Receive Observation 7 8 CAN_TST_SILENT Silent Mode 3 4 CAN_TST_TX Transmit Control 5 7 CAN_TST_TX_CANCTL CAN Module Control 0x0 CAN_TST_TX_SAMPLE Sample Point 0x1 CAN_TST_TX_DOMINANT Driven Low 0x2 CAN_TST_TX_RECESSIVE Driven High 0x3 TXRQ1 CAN Transmission Request 1 0x100 -1 read-write n 0x0 0x0 CAN_TXRQ1_TXRQST Transmission Request Bits 0 16 TXRQ2 CAN Transmission Request 2 0x104 -1 read-write n 0x0 0x0 CAN_TXRQ2_TXRQST Transmission Request Bits 0 16 CAN1 Register map for CAN0 peripheral CAN 0x0 0x0 0x1000 registers n CAN1 39 BIT CAN Bit Timing 0xC -1 read-write n 0x0 0x0 CAN_BIT_BRP Baud Rate Prescaler 0 6 CAN_BIT_SJW (Re)Synchronization Jump Width 6 8 CAN_BIT_TSEG1 Time Segment Before Sample Point 8 12 CAN_BIT_TSEG2 Time Segment after Sample Point 12 15 BRPE CAN Baud Rate Prescaler Extension 0x18 -1 read-write n 0x0 0x0 CAN_BRPE_BRPE Baud Rate Prescaler Extension 0 4 CAN0BIT CAN Bit Timing 0xC read-write n 0x0 0x0 CAN_BIT_BRP Baud Rate Prescaler 0 6 CAN_BIT_SJW (Re)Synchronization Jump Width 6 8 CAN_BIT_TSEG1 Time Segment Before Sample Point 8 12 CAN_BIT_TSEG2 Time Segment after Sample Point 12 15 CAN0BRPE CAN Baud Rate Prescaler Extension 0x18 read-write n 0x0 0x0 CAN_BRPE_BRPE Baud Rate Prescaler Extension 0 4 CAN0CTL CAN Control 0x0 read-write n 0x0 0x0 CAN_CTL_CCE Configuration Change Enable 6 7 CAN_CTL_DAR Disable Automatic-Retransmission 5 6 CAN_CTL_EIE Error Interrupt Enable 3 4 CAN_CTL_IE CAN Interrupt Enable 1 2 CAN_CTL_INIT Initialization 0 1 CAN_CTL_SIE Status Interrupt Enable 2 3 CAN_CTL_TEST Test Mode Enable 7 8 CAN0ERR CAN Error Counter 0x8 read-write n 0x0 0x0 CAN_ERR_REC Receive Error Counter 8 15 CAN_ERR_RP Received Error Passive 15 16 CAN_ERR_TEC Transmit Error Counter 0 8 CAN0IF1ARB1 CAN IF1 Arbitration 1 0x30 read-write n 0x0 0x0 CAN_IF1ARB1_ID Message Identifier 0 16 CAN0IF1ARB2 CAN IF1 Arbitration 2 0x34 read-write n 0x0 0x0 CAN_IF1ARB2_DIR Message Direction 13 14 CAN_IF1ARB2_ID Message Identifier 0 13 CAN_IF1ARB2_MSGVAL Message Valid 15 16 CAN_IF1ARB2_XTD Extended Identifier 14 15 CAN0IF1CMSK CAN IF1 Command Mask 0x24 read-write n 0x0 0x0 CAN_IF1CMSK_ARB Access Arbitration Bits 5 6 CAN_IF1CMSK_CLRINTPND Clear Interrupt Pending Bit 3 4 CAN_IF1CMSK_CONTROL Access Control Bits 4 5 CAN_IF1CMSK_DATAA Access Data Byte 0 to 3 1 2 CAN_IF1CMSK_DATAB Access Data Byte 4 to 7 0 1 CAN_IF1CMSK_MASK Access Mask Bits 6 7 CAN_IF1CMSK_NEWDAT Access New Data 2 3 CAN_IF1CMSK_WRNRD Write, Not Read 7 8 CAN0IF1CRQ CAN IF1 Command Request 0x20 read-write n 0x0 0x0 CAN_IF1CRQ_BUSY Busy Flag 15 16 CAN_IF1CRQ_MNUM Message Number 0 6 CAN0IF1DA1 CAN IF1 Data A1 0x3C read-write n 0x0 0x0 CAN_IF1DA1_DATA Data 0 16 CAN0IF1DA2 CAN IF1 Data A2 0x40 read-write n 0x0 0x0 CAN_IF1DA2_DATA Data 0 16 CAN0IF1DB1 CAN IF1 Data B1 0x44 read-write n 0x0 0x0 CAN_IF1DB1_DATA Data 0 16 CAN0IF1DB2 CAN IF1 Data B2 0x48 read-write n 0x0 0x0 CAN_IF1DB2_DATA Data 0 16 CAN0IF1MCTL CAN IF1 Message Control 0x38 read-write n 0x0 0x0 CAN_IF1MCTL_DLC Data Length Code 0 4 CAN_IF1MCTL_EOB End of Buffer 7 8 CAN_IF1MCTL_INTPND Interrupt Pending 13 14 CAN_IF1MCTL_MSGLST Message Lost 14 15 CAN_IF1MCTL_NEWDAT New Data 15 16 CAN_IF1MCTL_RMTEN Remote Enable 9 10 CAN_IF1MCTL_RXIE Receive Interrupt Enable 10 11 CAN_IF1MCTL_TXIE Transmit Interrupt Enable 11 12 CAN_IF1MCTL_TXRQST Transmit Request 8 9 CAN_IF1MCTL_UMASK Use Acceptance Mask 12 13 CAN0IF1MSK1 CAN IF1 Mask 1 0x28 read-write n 0x0 0x0 CAN_IF1MSK1_IDMSK Identifier Mask 0 16 CAN0IF1MSK2 CAN IF1 Mask 2 0x2C read-write n 0x0 0x0 CAN_IF1MSK2_IDMSK Identifier Mask 0 13 CAN_IF1MSK2_MDIR Mask Message Direction 14 15 CAN_IF1MSK2_MXTD Mask Extended Identifier 15 16 CAN0IF2ARB1 CAN IF2 Arbitration 1 0x90 read-write n 0x0 0x0 CAN_IF2ARB1_ID Message Identifier 0 16 CAN0IF2ARB2 CAN IF2 Arbitration 2 0x94 read-write n 0x0 0x0 CAN_IF2ARB2_DIR Message Direction 13 14 CAN_IF2ARB2_ID Message Identifier 0 13 CAN_IF2ARB2_MSGVAL Message Valid 15 16 CAN_IF2ARB2_XTD Extended Identifier 14 15 CAN0IF2CMSK CAN IF2 Command Mask 0x84 read-write n 0x0 0x0 CAN_IF2CMSK_ARB Access Arbitration Bits 5 6 CAN_IF2CMSK_CLRINTPND Clear Interrupt Pending Bit 3 4 CAN_IF2CMSK_CONTROL Access Control Bits 4 5 CAN_IF2CMSK_DATAA Access Data Byte 0 to 3 1 2 CAN_IF2CMSK_DATAB Access Data Byte 4 to 7 0 1 CAN_IF2CMSK_MASK Access Mask Bits 6 7 CAN_IF2CMSK_NEWDAT Access New Data 2 3 CAN_IF2CMSK_WRNRD Write, Not Read 7 8 CAN0IF2CRQ CAN IF2 Command Request 0x80 read-write n 0x0 0x0 CAN_IF2CRQ_BUSY Busy Flag 15 16 CAN_IF2CRQ_MNUM Message Number 0 6 CAN0IF2DA1 CAN IF2 Data A1 0x9C read-write n 0x0 0x0 CAN_IF2DA1_DATA Data 0 16 CAN0IF2DA2 CAN IF2 Data A2 0xA0 read-write n 0x0 0x0 CAN_IF2DA2_DATA Data 0 16 CAN0IF2DB1 CAN IF2 Data B1 0xA4 read-write n 0x0 0x0 CAN_IF2DB1_DATA Data 0 16 CAN0IF2DB2 CAN IF2 Data B2 0xA8 read-write n 0x0 0x0 CAN_IF2DB2_DATA Data 0 16 CAN0IF2MCTL CAN IF2 Message Control 0x98 read-write n 0x0 0x0 CAN_IF2MCTL_DLC Data Length Code 0 4 CAN_IF2MCTL_EOB End of Buffer 7 8 CAN_IF2MCTL_INTPND Interrupt Pending 13 14 CAN_IF2MCTL_MSGLST Message Lost 14 15 CAN_IF2MCTL_NEWDAT New Data 15 16 CAN_IF2MCTL_RMTEN Remote Enable 9 10 CAN_IF2MCTL_RXIE Receive Interrupt Enable 10 11 CAN_IF2MCTL_TXIE Transmit Interrupt Enable 11 12 CAN_IF2MCTL_TXRQST Transmit Request 8 9 CAN_IF2MCTL_UMASK Use Acceptance Mask 12 13 CAN0IF2MSK1 CAN IF2 Mask 1 0x88 read-write n 0x0 0x0 CAN_IF2MSK1_IDMSK Identifier Mask 0 16 CAN0IF2MSK2 CAN IF2 Mask 2 0x8C read-write n 0x0 0x0 CAN_IF2MSK2_IDMSK Identifier Mask 0 13 CAN_IF2MSK2_MDIR Mask Message Direction 14 15 CAN_IF2MSK2_MXTD Mask Extended Identifier 15 16 CAN0INT CAN Interrupt 0x10 read-write n 0x0 0x0 CAN_INT_INTID Interrupt Identifier 0 16 CAN_INT_INTID_NONE No interrupt pending 0x0 CAN_INT_INTID_STATUS Status Interrupt 0x8000 CAN0MSG1INT CAN Message 1 Interrupt Pending 0x140 read-write n 0x0 0x0 CAN_MSG1INT_INTPND Interrupt Pending Bits 0 16 CAN0MSG1VAL CAN Message 1 Valid 0x160 read-write n 0x0 0x0 CAN_MSG1VAL_MSGVAL Message Valid Bits 0 16 CAN0MSG2INT CAN Message 2 Interrupt Pending 0x144 read-write n 0x0 0x0 CAN_MSG2INT_INTPND Interrupt Pending Bits 0 16 CAN0MSG2VAL CAN Message 2 Valid 0x164 read-write n 0x0 0x0 CAN_MSG2VAL_MSGVAL Message Valid Bits 0 16 CAN0NWDA1 CAN New Data 1 0x120 read-write n 0x0 0x0 CAN_NWDA1_NEWDAT New Data Bits 0 16 CAN0NWDA2 CAN New Data 2 0x124 read-write n 0x0 0x0 CAN_NWDA2_NEWDAT New Data Bits 0 16 CAN0STS CAN Status 0x4 read-write n 0x0 0x0 CAN_STS_BOFF Bus-Off Status 7 8 CAN_STS_EPASS Error Passive 5 6 CAN_STS_EWARN Warning Status 6 7 CAN_STS_LEC Last Error Code 0 3 CAN_STS_LEC_NONE No Error 0x0 CAN_STS_LEC_STUFF Stuff Error 0x1 CAN_STS_LEC_FORM Format Error 0x2 CAN_STS_LEC_ACK ACK Error 0x3 CAN_STS_LEC_BIT1 Bit 1 Error 0x4 CAN_STS_LEC_BIT0 Bit 0 Error 0x5 CAN_STS_LEC_CRC CRC Error 0x6 CAN_STS_LEC_NOEVENT No Event 0x7 CAN_STS_RXOK Received a Message Successfully 4 5 CAN_STS_TXOK Transmitted a Message Successfully 3 4 CAN0TST CAN Test 0x14 read-write n 0x0 0x0 CAN_TST_BASIC Basic Mode 2 3 CAN_TST_LBACK Loopback Mode 4 5 CAN_TST_RX Receive Observation 7 8 CAN_TST_SILENT Silent Mode 3 4 CAN_TST_TX Transmit Control 5 7 CAN_TST_TX_CANCTL CAN Module Control 0x0 CAN_TST_TX_SAMPLE Sample Point 0x1 CAN_TST_TX_DOMINANT Driven Low 0x2 CAN_TST_TX_RECESSIVE Driven High 0x3 CAN0TXRQ1 CAN Transmission Request 1 0x100 read-write n 0x0 0x0 CAN_TXRQ1_TXRQST Transmission Request Bits 0 16 CAN0TXRQ2 CAN Transmission Request 2 0x104 read-write n 0x0 0x0 CAN_TXRQ2_TXRQST Transmission Request Bits 0 16 CTL CAN Control 0x0 -1 read-write n 0x0 0x0 CAN_CTL_CCE Configuration Change Enable 6 7 CAN_CTL_DAR Disable Automatic-Retransmission 5 6 CAN_CTL_EIE Error Interrupt Enable 3 4 CAN_CTL_IE CAN Interrupt Enable 1 2 CAN_CTL_INIT Initialization 0 1 CAN_CTL_SIE Status Interrupt Enable 2 3 CAN_CTL_TEST Test Mode Enable 7 8 ERR CAN Error Counter 0x8 -1 read-write n 0x0 0x0 CAN_ERR_REC Receive Error Counter 8 15 CAN_ERR_RP Received Error Passive 15 16 CAN_ERR_TEC Transmit Error Counter 0 8 IF1ARB1 CAN IF1 Arbitration 1 0x30 -1 read-write n 0x0 0x0 CAN_IF1ARB1_ID Message Identifier 0 16 IF1ARB2 CAN IF1 Arbitration 2 0x34 -1 read-write n 0x0 0x0 CAN_IF1ARB2_DIR Message Direction 13 14 CAN_IF1ARB2_ID Message Identifier 0 13 CAN_IF1ARB2_MSGVAL Message Valid 15 16 CAN_IF1ARB2_XTD Extended Identifier 14 15 IF1CMSK CAN IF1 Command Mask 0x24 -1 read-write n 0x0 0x0 CAN_IF1CMSK_ARB Access Arbitration Bits 5 6 CAN_IF1CMSK_CLRINTPND Clear Interrupt Pending Bit 3 4 CAN_IF1CMSK_CONTROL Access Control Bits 4 5 CAN_IF1CMSK_DATAA Access Data Byte 0 to 3 1 2 CAN_IF1CMSK_DATAB Access Data Byte 4 to 7 0 1 CAN_IF1CMSK_MASK Access Mask Bits 6 7 CAN_IF1CMSK_NEWDAT Access New Data 2 3 CAN_IF1CMSK_TXRQST Access Transmission Request 2 3 CAN_IF1CMSK_WRNRD Write, Not Read 7 8 IF1CRQ CAN IF1 Command Request 0x20 -1 read-write n 0x0 0x0 CAN_IF1CRQ_BUSY Busy Flag 15 16 CAN_IF1CRQ_MNUM Message Number 0 6 IF1DA1 CAN IF1 Data A1 0x3C -1 read-write n 0x0 0x0 CAN_IF1DA1_DATA Data 0 16 IF1DA2 CAN IF1 Data A2 0x40 -1 read-write n 0x0 0x0 CAN_IF1DA2_DATA Data 0 16 IF1DB1 CAN IF1 Data B1 0x44 -1 read-write n 0x0 0x0 CAN_IF1DB1_DATA Data 0 16 IF1DB2 CAN IF1 Data B2 0x48 -1 read-write n 0x0 0x0 CAN_IF1DB2_DATA Data 0 16 IF1MCTL CAN IF1 Message Control 0x38 -1 read-write n 0x0 0x0 CAN_IF1MCTL_DLC Data Length Code 0 4 CAN_IF1MCTL_EOB End of Buffer 7 8 CAN_IF1MCTL_INTPND Interrupt Pending 13 14 CAN_IF1MCTL_MSGLST Message Lost 14 15 CAN_IF1MCTL_NEWDAT New Data 15 16 CAN_IF1MCTL_RMTEN Remote Enable 9 10 CAN_IF1MCTL_RXIE Receive Interrupt Enable 10 11 CAN_IF1MCTL_TXIE Transmit Interrupt Enable 11 12 CAN_IF1MCTL_TXRQST Transmit Request 8 9 CAN_IF1MCTL_UMASK Use Acceptance Mask 12 13 IF1MSK1 CAN IF1 Mask 1 0x28 -1 read-write n 0x0 0x0 CAN_IF1MSK1_IDMSK Identifier Mask 0 16 IF1MSK2 CAN IF1 Mask 2 0x2C -1 read-write n 0x0 0x0 CAN_IF1MSK2_IDMSK Identifier Mask 0 13 CAN_IF1MSK2_MDIR Mask Message Direction 14 15 CAN_IF1MSK2_MXTD Mask Extended Identifier 15 16 IF2ARB1 CAN IF2 Arbitration 1 0x90 -1 read-write n 0x0 0x0 CAN_IF2ARB1_ID Message Identifier 0 16 IF2ARB2 CAN IF2 Arbitration 2 0x94 -1 read-write n 0x0 0x0 CAN_IF2ARB2_DIR Message Direction 13 14 CAN_IF2ARB2_ID Message Identifier 0 13 CAN_IF2ARB2_MSGVAL Message Valid 15 16 CAN_IF2ARB2_XTD Extended Identifier 14 15 IF2CMSK CAN IF2 Command Mask 0x84 -1 read-write n 0x0 0x0 CAN_IF2CMSK_ARB Access Arbitration Bits 5 6 CAN_IF2CMSK_CLRINTPND Clear Interrupt Pending Bit 3 4 CAN_IF2CMSK_CONTROL Access Control Bits 4 5 CAN_IF2CMSK_DATAA Access Data Byte 0 to 3 1 2 CAN_IF2CMSK_DATAB Access Data Byte 4 to 7 0 1 CAN_IF2CMSK_MASK Access Mask Bits 6 7 CAN_IF2CMSK_NEWDAT Access New Data 2 3 CAN_IF2CMSK_TXRQST Access Transmission Request 2 3 CAN_IF2CMSK_WRNRD Write, Not Read 7 8 IF2CRQ CAN IF2 Command Request 0x80 -1 read-write n 0x0 0x0 CAN_IF2CRQ_BUSY Busy Flag 15 16 CAN_IF2CRQ_MNUM Message Number 0 6 IF2DA1 CAN IF2 Data A1 0x9C -1 read-write n 0x0 0x0 CAN_IF2DA1_DATA Data 0 16 IF2DA2 CAN IF2 Data A2 0xA0 -1 read-write n 0x0 0x0 CAN_IF2DA2_DATA Data 0 16 IF2DB1 CAN IF2 Data B1 0xA4 -1 read-write n 0x0 0x0 CAN_IF2DB1_DATA Data 0 16 IF2DB2 CAN IF2 Data B2 0xA8 -1 read-write n 0x0 0x0 CAN_IF2DB2_DATA Data 0 16 IF2MCTL CAN IF2 Message Control 0x98 -1 read-write n 0x0 0x0 CAN_IF2MCTL_DLC Data Length Code 0 4 CAN_IF2MCTL_EOB End of Buffer 7 8 CAN_IF2MCTL_INTPND Interrupt Pending 13 14 CAN_IF2MCTL_MSGLST Message Lost 14 15 CAN_IF2MCTL_NEWDAT New Data 15 16 CAN_IF2MCTL_RMTEN Remote Enable 9 10 CAN_IF2MCTL_RXIE Receive Interrupt Enable 10 11 CAN_IF2MCTL_TXIE Transmit Interrupt Enable 11 12 CAN_IF2MCTL_TXRQST Transmit Request 8 9 CAN_IF2MCTL_UMASK Use Acceptance Mask 12 13 IF2MSK1 CAN IF2 Mask 1 0x88 -1 read-write n 0x0 0x0 CAN_IF2MSK1_IDMSK Identifier Mask 0 16 IF2MSK2 CAN IF2 Mask 2 0x8C -1 read-write n 0x0 0x0 CAN_IF2MSK2_IDMSK Identifier Mask 0 13 CAN_IF2MSK2_MDIR Mask Message Direction 14 15 CAN_IF2MSK2_MXTD Mask Extended Identifier 15 16 INT CAN Interrupt 0x10 -1 read-write n 0x0 0x0 CAN_INT_INTID Interrupt Identifier 0 16 CAN_INT_INTID_NONE No interrupt pending 0x0 CAN_INT_INTID_STATUS Status Interrupt 0x8000 MSG1INT CAN Message 1 Interrupt Pending 0x140 -1 read-write n 0x0 0x0 CAN_MSG1INT_INTPND Interrupt Pending Bits 0 16 MSG1VAL CAN Message 1 Valid 0x160 -1 read-write n 0x0 0x0 CAN_MSG1VAL_MSGVAL Message Valid Bits 0 16 MSG2INT CAN Message 2 Interrupt Pending 0x144 -1 read-write n 0x0 0x0 CAN_MSG2INT_INTPND Interrupt Pending Bits 0 16 MSG2VAL CAN Message 2 Valid 0x164 -1 read-write n 0x0 0x0 CAN_MSG2VAL_MSGVAL Message Valid Bits 0 16 NWDA1 CAN New Data 1 0x120 -1 read-write n 0x0 0x0 CAN_NWDA1_NEWDAT New Data Bits 0 16 NWDA2 CAN New Data 2 0x124 -1 read-write n 0x0 0x0 CAN_NWDA2_NEWDAT New Data Bits 0 16 STS CAN Status 0x4 -1 read-write n 0x0 0x0 CAN_STS_BOFF Bus-Off Status 7 8 CAN_STS_EPASS Error Passive 5 6 CAN_STS_EWARN Warning Status 6 7 CAN_STS_LEC Last Error Code 0 3 CAN_STS_LEC_NONE No Error 0x0 CAN_STS_LEC_STUFF Stuff Error 0x1 CAN_STS_LEC_FORM Format Error 0x2 CAN_STS_LEC_ACK ACK Error 0x3 CAN_STS_LEC_BIT1 Bit 1 Error 0x4 CAN_STS_LEC_BIT0 Bit 0 Error 0x5 CAN_STS_LEC_CRC CRC Error 0x6 CAN_STS_LEC_NOEVENT No Event 0x7 CAN_STS_RXOK Received a Message Successfully 4 5 CAN_STS_TXOK Transmitted a Message Successfully 3 4 TST CAN Test 0x14 -1 read-write n 0x0 0x0 CAN_TST_BASIC Basic Mode 2 3 CAN_TST_LBACK Loopback Mode 4 5 CAN_TST_RX Receive Observation 7 8 CAN_TST_SILENT Silent Mode 3 4 CAN_TST_TX Transmit Control 5 7 CAN_TST_TX_CANCTL CAN Module Control 0x0 CAN_TST_TX_SAMPLE Sample Point 0x1 CAN_TST_TX_DOMINANT Driven Low 0x2 CAN_TST_TX_RECESSIVE Driven High 0x3 TXRQ1 CAN Transmission Request 1 0x100 -1 read-write n 0x0 0x0 CAN_TXRQ1_TXRQST Transmission Request Bits 0 16 TXRQ2 CAN Transmission Request 2 0x104 -1 read-write n 0x0 0x0 CAN_TXRQ2_TXRQST Transmission Request Bits 0 16 CCM0 Register map for CCM0 peripheral CCM 0x0 0x0 0x1000 registers n CCM0CRCCTRL CRC Control 0x400 read-write n 0x0 0x0 CCM_CRCCTRL_BR Bit reverse enable 7 8 CCM_CRCCTRL_ENDIAN Endian Control 4 6 CCM_CRCCTRL_ENDIAN_SBHW Configuration unchanged. (B3, B2, B1, B0) 0x0 CCM_CRCCTRL_ENDIAN_SHW Bytes are swapped in half-words but half-words are not swapped (B2, B3, B0, B1) 0x1 CCM_CRCCTRL_ENDIAN_SHWNB Half-words are swapped but bytes are not swapped in half-word. (B1, B0, B3, B2) 0x2 CCM_CRCCTRL_ENDIAN_SBSW Bytes are swapped in half-words and half-words are swapped. (B0, B1, B2, B3) 0x3 CCM_CRCCTRL_INIT CRC Initialization 13 15 CCM_CRCCTRL_INIT_SEED Use the CRCSEED register context as the starting value 0x0 CCM_CRCCTRL_INIT_0 Initialize to all '0s' 0x2 CCM_CRCCTRL_INIT_1 Initialize to all '1s' 0x3 CCM_CRCCTRL_OBR Output Reverse Enable 8 9 CCM_CRCCTRL_RESINV Result Inverse Enable 9 10 CCM_CRCCTRL_SIZE Input Data Size 12 13 CCM_CRCCTRL_TYPE Operation Type 0 4 CCM_CRCCTRL_TYPE_P8055 Polynomial 0x8005 0x0 CCM_CRCCTRL_TYPE_P1021 Polynomial 0x1021 0x1 CCM_CRCCTRL_TYPE_P4C11DB7 Polynomial 0x4C11DB7 0x2 CCM_CRCCTRL_TYPE_P1EDC6F41 Polynomial 0x1EDC6F41 0x3 CCM_CRCCTRL_TYPE_TCPCHKSUM TCP checksum 0x8 CCM0CRCDIN CRC Data Input 0x414 read-write n 0x0 0x0 CCM_CRCDIN_DATAIN Data Input 0 32 CCM0CRCRSLTPP CRC Post Processing Result 0x418 read-write n 0x0 0x0 CCM_CRCRSLTPP_RSLTPP Post Processing Result 0 32 CCM0CRCSEED CRC SEED/Context 0x410 read-write n 0x0 0x0 CCM_CRCSEED_SEED SEED/Context Value 0 32 CRCCTRL CRC Control 0x400 -1 read-write n 0x0 0x0 CCM_CRCCTRL_BR Bit reverse enable 7 8 CCM_CRCCTRL_ENDIAN Endian Control 4 6 CCM_CRCCTRL_ENDIAN_SBHW Configuration unchanged. (B3, B2, B1, B0) 0x0 CCM_CRCCTRL_ENDIAN_SHW Bytes are swapped in half-words but half-words are not swapped (B2, B3, B0, B1) 0x1 CCM_CRCCTRL_ENDIAN_SHWNB Half-words are swapped but bytes are not swapped in half-word. (B1, B0, B3, B2) 0x2 CCM_CRCCTRL_ENDIAN_SBSW Bytes are swapped in half-words and half-words are swapped. (B0, B1, B2, B3) 0x3 CCM_CRCCTRL_INIT CRC Initialization 13 15 CCM_CRCCTRL_INIT_SEED Use the CRCSEED register context as the starting value 0x0 CCM_CRCCTRL_INIT_0 Initialize to all '0s' 0x2 CCM_CRCCTRL_INIT_1 Initialize to all '1s' 0x3 CCM_CRCCTRL_OBR Output Reverse Enable 8 9 CCM_CRCCTRL_RESINV Result Inverse Enable 9 10 CCM_CRCCTRL_SIZE Input Data Size 12 13 CCM_CRCCTRL_TYPE Operation Type 0 4 CCM_CRCCTRL_TYPE_P8055 Polynomial 0x8005 0x0 CCM_CRCCTRL_TYPE_P1021 Polynomial 0x1021 0x1 CCM_CRCCTRL_TYPE_P4C11DB7 Polynomial 0x4C11DB7 0x2 CCM_CRCCTRL_TYPE_P1EDC6F41 Polynomial 0x1EDC6F41 0x3 CCM_CRCCTRL_TYPE_TCPCHKSUM TCP checksum 0x8 CRCDIN CRC Data Input 0x414 -1 read-write n 0x0 0x0 CCM_CRCDIN_DATAIN Data Input 0 32 CRCRSLTPP CRC Post Processing Result 0x418 -1 read-write n 0x0 0x0 CCM_CRCRSLTPP_RSLTPP Post Processing Result 0 32 CRCSEED CRC SEED/Context 0x410 -1 read-write n 0x0 0x0 CCM_CRCSEED_SEED SEED/Context Value 0 32 COMP Register map for COMP peripheral COMP 0x0 0x0 0x1000 registers n COMP0 25 COMP1 26 COMP2 27 ACCTL0 Analog Comparator Control 0 0x24 -1 read-write n 0x0 0x0 COMP_ACCTL0_ASRCP Analog Source Positive 9 11 COMP_ACCTL0_ASRCP_PIN Pin value of Cn+ 0x0 COMP_ACCTL0_ASRCP_PIN0 Pin value of C0+ 0x1 COMP_ACCTL0_ASRCP_REF Internal voltage reference 0x2 COMP_ACCTL0_CINV Comparator Output Invert 1 2 COMP_ACCTL0_ISEN Interrupt Sense 2 4 COMP_ACCTL0_ISEN_LEVEL Level sense, see ISLVAL 0x0 COMP_ACCTL0_ISEN_FALL Falling edge 0x1 COMP_ACCTL0_ISEN_RISE Rising edge 0x2 COMP_ACCTL0_ISEN_BOTH Either edge 0x3 COMP_ACCTL0_ISLVAL Interrupt Sense Level Value 4 5 COMP_ACCTL0_TOEN Trigger Output Enable 11 12 COMP_ACCTL0_TSEN Trigger Sense 5 7 COMP_ACCTL0_TSEN_LEVEL Level sense, see TSLVAL 0x0 COMP_ACCTL0_TSEN_FALL Falling edge 0x1 COMP_ACCTL0_TSEN_RISE Rising edge 0x2 COMP_ACCTL0_TSEN_BOTH Either edge 0x3 COMP_ACCTL0_TSLVAL Trigger Sense Level Value 7 8 ACCTL1 Analog Comparator Control 1 0x44 -1 read-write n 0x0 0x0 COMP_ACCTL1_ASRCP Analog Source Positive 9 11 COMP_ACCTL1_ASRCP_PIN Pin value of Cn+ 0x0 COMP_ACCTL1_ASRCP_PIN0 Pin value of C0+ 0x1 COMP_ACCTL1_ASRCP_REF Internal voltage reference 0x2 COMP_ACCTL1_CINV Comparator Output Invert 1 2 COMP_ACCTL1_ISEN Interrupt Sense 2 4 COMP_ACCTL1_ISEN_LEVEL Level sense, see ISLVAL 0x0 COMP_ACCTL1_ISEN_FALL Falling edge 0x1 COMP_ACCTL1_ISEN_RISE Rising edge 0x2 COMP_ACCTL1_ISEN_BOTH Either edge 0x3 COMP_ACCTL1_ISLVAL Interrupt Sense Level Value 4 5 COMP_ACCTL1_TOEN Trigger Output Enable 11 12 COMP_ACCTL1_TSEN Trigger Sense 5 7 COMP_ACCTL1_TSEN_LEVEL Level sense, see TSLVAL 0x0 COMP_ACCTL1_TSEN_FALL Falling edge 0x1 COMP_ACCTL1_TSEN_RISE Rising edge 0x2 COMP_ACCTL1_TSEN_BOTH Either edge 0x3 COMP_ACCTL1_TSLVAL Trigger Sense Level Value 7 8 ACCTL2 Analog Comparator Control 2 0x64 -1 read-write n 0x0 0x0 COMP_ACCTL2_ASRCP Analog Source Positive 9 11 COMP_ACCTL2_ASRCP_PIN Pin value of Cn+ 0x0 COMP_ACCTL2_ASRCP_PIN0 Pin value of C0+ 0x1 COMP_ACCTL2_ASRCP_REF Internal voltage reference 0x2 COMP_ACCTL2_CINV Comparator Output Invert 1 2 COMP_ACCTL2_ISEN Interrupt Sense 2 4 COMP_ACCTL2_ISEN_LEVEL Level sense, see ISLVAL 0x0 COMP_ACCTL2_ISEN_FALL Falling edge 0x1 COMP_ACCTL2_ISEN_RISE Rising edge 0x2 COMP_ACCTL2_ISEN_BOTH Either edge 0x3 COMP_ACCTL2_ISLVAL Interrupt Sense Level Value 4 5 COMP_ACCTL2_TOEN Trigger Output Enable 11 12 COMP_ACCTL2_TSEN Trigger Sense 5 7 COMP_ACCTL2_TSEN_LEVEL Level sense, see TSLVAL 0x0 COMP_ACCTL2_TSEN_FALL Falling edge 0x1 COMP_ACCTL2_TSEN_RISE Rising edge 0x2 COMP_ACCTL2_TSEN_BOTH Either edge 0x3 COMP_ACCTL2_TSLVAL Trigger Sense Level Value 7 8 ACINTEN Analog Comparator Interrupt Enable 0x8 -1 read-write n 0x0 0x0 COMP_ACINTEN_IN0 Comparator 0 Interrupt Enable 0 1 COMP_ACINTEN_IN1 Comparator 1 Interrupt Enable 1 2 COMP_ACINTEN_IN2 Comparator 2 Interrupt Enable 2 3 ACMIS Analog Comparator Masked Interrupt Status 0x0 -1 read-write n 0x0 0x0 COMP_ACMIS_IN0 Comparator 0 Masked Interrupt Status 0 1 COMP_ACMIS_IN1 Comparator 1 Masked Interrupt Status 1 2 COMP_ACMIS_IN2 Comparator 2 Masked Interrupt Status 2 3 ACREFCTL Analog Comparator Reference Voltage Control 0x10 -1 read-write n 0x0 0x0 COMP_ACREFCTL_EN Resistor Ladder Enable 9 10 COMP_ACREFCTL_RNG Resistor Ladder Range 8 9 COMP_ACREFCTL_VREF Resistor Ladder Voltage Ref 0 4 ACRIS Analog Comparator Raw Interrupt Status 0x4 -1 read-write n 0x0 0x0 COMP_ACRIS_IN0 Comparator 0 Interrupt Status 0 1 COMP_ACRIS_IN1 Comparator 1 Interrupt Status 1 2 COMP_ACRIS_IN2 Comparator 2 Interrupt Status 2 3 ACSTAT0 Analog Comparator Status 0 0x20 -1 read-write n 0x0 0x0 COMP_ACSTAT0_OVAL Comparator Output Value 1 2 ACSTAT1 Analog Comparator Status 1 0x40 -1 read-write n 0x0 0x0 COMP_ACSTAT1_OVAL Comparator Output Value 1 2 ACSTAT2 Analog Comparator Status 2 0x60 -1 read-write n 0x0 0x0 COMP_ACSTAT2_OVAL Comparator Output Value 1 2 COMPACCTL0 Analog Comparator Control 0 0x24 read-write n 0x0 0x0 COMP_ACCTL0_ASRCP Analog Source Positive 9 11 COMP_ACCTL0_ASRCP_PIN Pin value of Cn+ 0x0 COMP_ACCTL0_ASRCP_PIN0 Pin value of C0+ 0x1 COMP_ACCTL0_ASRCP_REF Internal voltage reference 0x2 COMP_ACCTL0_CINV Comparator Output Invert 1 2 COMP_ACCTL0_ISEN Interrupt Sense 2 4 COMP_ACCTL0_ISEN_LEVEL Level sense, see ISLVAL 0x0 COMP_ACCTL0_ISEN_FALL Falling edge 0x1 COMP_ACCTL0_ISEN_RISE Rising edge 0x2 COMP_ACCTL0_ISEN_BOTH Either edge 0x3 COMP_ACCTL0_ISLVAL Interrupt Sense Level Value 4 5 COMP_ACCTL0_TOEN Trigger Output Enable 11 12 COMP_ACCTL0_TSEN Trigger Sense 5 7 COMP_ACCTL0_TSEN_LEVEL Level sense, see TSLVAL 0x0 COMP_ACCTL0_TSEN_FALL Falling edge 0x1 COMP_ACCTL0_TSEN_RISE Rising edge 0x2 COMP_ACCTL0_TSEN_BOTH Either edge 0x3 COMP_ACCTL0_TSLVAL Trigger Sense Level Value 7 8 COMPACCTL1 Analog Comparator Control 1 0x44 read-write n 0x0 0x0 COMP_ACCTL1_ASRCP Analog Source Positive 9 11 COMP_ACCTL1_ASRCP_PIN Pin value of Cn+ 0x0 COMP_ACCTL1_ASRCP_PIN0 Pin value of C0+ 0x1 COMP_ACCTL1_ASRCP_REF Internal voltage reference 0x2 COMP_ACCTL1_CINV Comparator Output Invert 1 2 COMP_ACCTL1_ISEN Interrupt Sense 2 4 COMP_ACCTL1_ISEN_LEVEL Level sense, see ISLVAL 0x0 COMP_ACCTL1_ISEN_FALL Falling edge 0x1 COMP_ACCTL1_ISEN_RISE Rising edge 0x2 COMP_ACCTL1_ISEN_BOTH Either edge 0x3 COMP_ACCTL1_ISLVAL Interrupt Sense Level Value 4 5 COMP_ACCTL1_TOEN Trigger Output Enable 11 12 COMP_ACCTL1_TSEN Trigger Sense 5 7 COMP_ACCTL1_TSEN_LEVEL Level sense, see TSLVAL 0x0 COMP_ACCTL1_TSEN_FALL Falling edge 0x1 COMP_ACCTL1_TSEN_RISE Rising edge 0x2 COMP_ACCTL1_TSEN_BOTH Either edge 0x3 COMP_ACCTL1_TSLVAL Trigger Sense Level Value 7 8 COMPACCTL2 Analog Comparator Control 2 0x64 read-write n 0x0 0x0 COMP_ACCTL2_ASRCP Analog Source Positive 9 11 COMP_ACCTL2_ASRCP_PIN Pin value of Cn+ 0x0 COMP_ACCTL2_ASRCP_PIN0 Pin value of C0+ 0x1 COMP_ACCTL2_ASRCP_REF Internal voltage reference 0x2 COMP_ACCTL2_CINV Comparator Output Invert 1 2 COMP_ACCTL2_ISEN Interrupt Sense 2 4 COMP_ACCTL2_ISEN_LEVEL Level sense, see ISLVAL 0x0 COMP_ACCTL2_ISEN_FALL Falling edge 0x1 COMP_ACCTL2_ISEN_RISE Rising edge 0x2 COMP_ACCTL2_ISEN_BOTH Either edge 0x3 COMP_ACCTL2_ISLVAL Interrupt Sense Level Value 4 5 COMP_ACCTL2_TOEN Trigger Output Enable 11 12 COMP_ACCTL2_TSEN Trigger Sense 5 7 COMP_ACCTL2_TSEN_LEVEL Level sense, see TSLVAL 0x0 COMP_ACCTL2_TSEN_FALL Falling edge 0x1 COMP_ACCTL2_TSEN_RISE Rising edge 0x2 COMP_ACCTL2_TSEN_BOTH Either edge 0x3 COMP_ACCTL2_TSLVAL Trigger Sense Level Value 7 8 COMPACINTEN Analog Comparator Interrupt Enable 0x8 read-write n 0x0 0x0 COMP_ACINTEN_IN0 Comparator 0 Interrupt Enable 0 1 COMP_ACINTEN_IN1 Comparator 1 Interrupt Enable 1 2 COMP_ACINTEN_IN2 Comparator 2 Interrupt Enable 2 3 COMPACMIS Analog Comparator Masked Interrupt Status 0x0 read-write n 0x0 0x0 COMP_ACMIS_IN0 Comparator 0 Masked Interrupt Status 0 1 COMP_ACMIS_IN1 Comparator 1 Masked Interrupt Status 1 2 COMP_ACMIS_IN2 Comparator 2 Masked Interrupt Status 2 3 COMPACREFCTL Analog Comparator Reference Voltage Control 0x10 read-write n 0x0 0x0 COMP_ACREFCTL_EN Resistor Ladder Enable 9 10 COMP_ACREFCTL_RNG Resistor Ladder Range 8 9 COMP_ACREFCTL_VREF Resistor Ladder Voltage Ref 0 4 COMPACRIS Analog Comparator Raw Interrupt Status 0x4 read-write n 0x0 0x0 COMP_ACRIS_IN0 Comparator 0 Interrupt Status 0 1 COMP_ACRIS_IN1 Comparator 1 Interrupt Status 1 2 COMP_ACRIS_IN2 Comparator 2 Interrupt Status 2 3 COMPACSTAT0 Analog Comparator Status 0 0x20 read-write n 0x0 0x0 COMP_ACSTAT0_OVAL Comparator Output Value 1 2 COMPACSTAT1 Analog Comparator Status 1 0x40 read-write n 0x0 0x0 COMP_ACSTAT1_OVAL Comparator Output Value 1 2 COMPACSTAT2 Analog Comparator Status 2 0x60 read-write n 0x0 0x0 COMP_ACSTAT2_OVAL Comparator Output Value 1 2 COMPPP Analog Comparator Peripheral Properties 0xFC0 read-write n 0x0 0x0 COMP_PP_C0O Comparator Output 0 Present 16 17 COMP_PP_C1O Comparator Output 1 Present 17 18 COMP_PP_C2O Comparator Output 2 Present 18 19 COMP_PP_CMP0 Comparator 0 Present 0 1 COMP_PP_CMP1 Comparator 1 Present 1 2 COMP_PP_CMP2 Comparator 2 Present 2 3 PP Analog Comparator Peripheral Properties 0xFC0 -1 read-write n 0x0 0x0 COMP_PP_C0O Comparator Output 0 Present 16 17 COMP_PP_C1O Comparator Output 1 Present 17 18 COMP_PP_C2O Comparator Output 2 Present 18 19 COMP_PP_CMP0 Comparator 0 Present 0 1 COMP_PP_CMP1 Comparator 1 Present 1 2 COMP_PP_CMP2 Comparator 2 Present 2 3 EEPROM Register map for EEPROM peripheral EEPROM 0x0 0x0 0x1000 registers n EEBLOCK EEPROM Current Block 0x4 -1 read-write n 0x0 0x0 EEPROM_EEBLOCK_BLOCK Current Block 0 16 EEDBGME EEPROM Debug Mass Erase 0x80 -1 read-write n 0x0 0x0 EEPROM_EEDBGME_KEY Erase Key 16 32 EEPROM_EEDBGME_ME Mass Erase 0 1 EEDONE EEPROM Done Status 0x18 -1 read-write n 0x0 0x0 EEPROM_EEDONE_NOPERM Write Without Permission 4 5 EEPROM_EEDONE_WKCOPY Working on a Copy 3 4 EEPROM_EEDONE_WKERASE Working on an Erase 2 3 EEPROM_EEDONE_WORKING EEPROM Working 0 1 EEPROM_EEDONE_WRBUSY Write Busy 5 6 EEHIDE0 EEPROM Block Hide 0 0x50 -1 read-write n 0x0 0x0 EEPROM_EEHIDE0_HN Hide Block 1 32 EEHIDE1 EEPROM Block Hide 1 0x54 -1 read-write n 0x0 0x0 EEPROM_EEHIDE1_HN Hide Block 0 32 EEHIDE2 EEPROM Block Hide 2 0x58 -1 read-write n 0x0 0x0 EEPROM_EEHIDE2_HN Hide Block 0 32 EEINT EEPROM Interrupt 0x40 -1 read-write n 0x0 0x0 EEPROM_EEINT_INT Interrupt Enable 0 1 EEOFFSET EEPROM Current Offset 0x8 -1 read-write n 0x0 0x0 EEPROM_EEOFFSET_OFFSET Current Address Offset 0 4 EEPASS0 EEPROM Password 0x34 -1 read-write n 0x0 0x0 EEPROM_EEPASS0_PASS Password 0 32 EEPASS1 EEPROM Password 0x38 -1 read-write n 0x0 0x0 EEPROM_EEPASS1_PASS Password 0 32 EEPASS2 EEPROM Password 0x3C -1 read-write n 0x0 0x0 EEPROM_EEPASS2_PASS Password 0 32 EEPROMEEBLOCK EEPROM Current Block 0x4 read-write n 0x0 0x0 EEPROM_EEBLOCK_BLOCK Current Block 0 16 EEPROMEEDBGME EEPROM Debug Mass Erase 0x80 read-write n 0x0 0x0 EEPROM_EEDBGME_KEY Erase Key 16 32 EEPROM_EEDBGME_ME Mass Erase 0 1 EEPROMEEDONE EEPROM Done Status 0x18 read-write n 0x0 0x0 EEPROM_EEDONE_NOPERM Write Without Permission 4 5 EEPROM_EEDONE_WKCOPY Working on a Copy 3 4 EEPROM_EEDONE_WKERASE Working on an Erase 2 3 EEPROM_EEDONE_WORKING EEPROM Working 0 1 EEPROM_EEDONE_WRBUSY Write Busy 5 6 EEPROMEEHIDE0 EEPROM Block Hide 0 0x50 read-write n 0x0 0x0 EEPROM_EEHIDE0_HN Hide Block 1 32 EEPROMEEHIDE1 EEPROM Block Hide 1 0x54 read-write n 0x0 0x0 EEPROM_EEHIDE1_HN Hide Block 0 32 EEPROMEEHIDE2 EEPROM Block Hide 2 0x58 read-write n 0x0 0x0 EEPROM_EEHIDE2_HN Hide Block 0 32 EEPROMEEINT EEPROM Interrupt 0x40 read-write n 0x0 0x0 EEPROM_EEINT_INT Interrupt Enable 0 1 EEPROMEEOFFSET EEPROM Current Offset 0x8 read-write n 0x0 0x0 EEPROM_EEOFFSET_OFFSET Current Address Offset 0 4 EEPROMEEPASS0 EEPROM Password 0x34 read-write n 0x0 0x0 EEPROM_EEPASS0_PASS Password 0 32 EEPROMEEPASS1 EEPROM Password 0x38 read-write n 0x0 0x0 EEPROM_EEPASS1_PASS Password 0 32 EEPROMEEPASS2 EEPROM Password 0x3C read-write n 0x0 0x0 EEPROM_EEPASS2_PASS Password 0 32 EEPROMEEPROT EEPROM Protection 0x30 read-write n 0x0 0x0 EEPROM_EEPROT_ACC Access Control 3 4 EEPROM_EEPROT_PROT Protection Control 0 3 EEPROM_EEPROT_PROT_RWNPW This setting is the default. If there is no password, the block is not protected and is readable and writable 0x0 EEPROM_EEPROT_PROT_RWPW If there is a password, the block is readable or writable only when unlocked 0x1 EEPROM_EEPROT_PROT_RONPW If there is no password, the block is readable, not writable 0x2 EEPROMEERDWR EEPROM Read-Write 0x10 read-write n 0x0 0x0 EEPROM_EERDWR_VALUE EEPROM Read or Write Data 0 32 EEPROMEERDWRINC EEPROM Read-Write with Increment 0x14 read-write n 0x0 0x0 EEPROM_EERDWRINC_VALUE EEPROM Read or Write Data with Increment 0 32 EEPROMEESIZE EEPROM Size Information 0x0 read-write n 0x0 0x0 EEPROM_EESIZE_BLKCNT Number of 16-Word Blocks 16 27 EEPROM_EESIZE_WORDCNT Number of 32-Bit Words 0 16 EEPROMEESUPP EEPROM Support Control and Status 0x1C read-write n 0x0 0x0 EEPROM_EESUPP_ERETRY Erase Must Be Retried 2 3 EEPROM_EESUPP_PRETRY Programming Must Be Retried 3 4 EEPROMEEUNLOCK EEPROM Unlock 0x20 read-write n 0x0 0x0 EEPROM_EEUNLOCK_UNLOCK EEPROM Unlock 0 32 EEPROMPP EEPROM Peripheral Properties 0xFC0 read-write n 0x0 0x0 EEPROM_PP_SIZE EEPROM Size 0 16 EEPROM_PP_SIZE_64 64 bytes of EEPROM 0x0 EEPROM_PP_SIZE_128 128 bytes of EEPROM 0x1 EEPROM_PP_SIZE_2K 2 KB of EEPROM 0x1f EEPROM_PP_SIZE_6K 6 KB of EEPROM 0x1ff EEPROM_PP_SIZE_256 256 bytes of EEPROM 0x3 EEPROM_PP_SIZE_3K 3 KB of EEPROM 0x3f EEPROM_PP_SIZE_512 512 bytes of EEPROM 0x7 EEPROM_PP_SIZE_4K 4 KB of EEPROM 0x7f EEPROM_PP_SIZE_1K 1 KB of EEPROM 0xf EEPROM_PP_SIZE_5K 5 KB of EEPROM 0xff EEPROT EEPROM Protection 0x30 -1 read-write n 0x0 0x0 EEPROM_EEPROT_ACC Access Control 3 4 EEPROM_EEPROT_PROT Protection Control 0 3 EEPROM_EEPROT_PROT_RWNPW This setting is the default. If there is no password, the block is not protected and is readable and writable 0x0 EEPROM_EEPROT_PROT_RWPW If there is a password, the block is readable or writable only when unlocked 0x1 EEPROM_EEPROT_PROT_RONPW If there is no password, the block is readable, not writable 0x2 EERDWR EEPROM Read-Write 0x10 -1 read-write n 0x0 0x0 EEPROM_EERDWR_VALUE EEPROM Read or Write Data 0 32 EERDWRINC EEPROM Read-Write with Increment 0x14 -1 read-write n 0x0 0x0 EEPROM_EERDWRINC_VALUE EEPROM Read or Write Data with Increment 0 32 EESIZE EEPROM Size Information 0x0 -1 read-write n 0x0 0x0 EEPROM_EESIZE_BLKCNT Number of 16-Word Blocks 16 27 EEPROM_EESIZE_WORDCNT Number of 32-Bit Words 0 16 EESUPP EEPROM Support Control and Status 0x1C -1 read-write n 0x0 0x0 EEPROM_EESUPP_ERETRY Erase Must Be Retried 2 3 EEPROM_EESUPP_PRETRY Programming Must Be Retried 3 4 EEUNLOCK EEPROM Unlock 0x20 -1 read-write n 0x0 0x0 EEPROM_EEUNLOCK_UNLOCK EEPROM Unlock 0 32 PP EEPROM Peripheral Properties 0xFC0 -1 read-write n 0x0 0x0 EEPROM_PP_SIZE EEPROM Size 0 16 EEPROM_PP_SIZE_64 64 bytes of EEPROM 0x0 EEPROM_PP_SIZE_128 128 bytes of EEPROM 0x1 EEPROM_PP_SIZE_2K 2 KB of EEPROM 0x1f EEPROM_PP_SIZE_6K 6 KB of EEPROM 0x1ff EEPROM_PP_SIZE_256 256 bytes of EEPROM 0x3 EEPROM_PP_SIZE_3K 3 KB of EEPROM 0x3f EEPROM_PP_SIZE_512 512 bytes of EEPROM 0x7 EEPROM_PP_SIZE_4K 4 KB of EEPROM 0x7f EEPROM_PP_SIZE_1K 1 KB of EEPROM 0xf EEPROM_PP_SIZE_5K 5 KB of EEPROM 0xff EPI0 Register map for EPI0 peripheral EPI 0x0 0x0 0x1000 registers n EPI0 50 ADDRMAP EPI Address Map 0x1C -1 read-write n 0x0 0x0 EPI_ADDRMAP_ECADR External Code Address 8 10 EPI_ADDRMAP_ECADR_NONE Not mapped 0x0 EPI_ADDRMAP_ECADR_1000 At 0x1000.0000 0x1 EPI_ADDRMAP_ECSZ External Code Size 10 12 EPI_ADDRMAP_ECSZ_256B 256 bytes lower address range: 0x00 to 0xFF 0x0 EPI_ADDRMAP_ECSZ_64KB 64 KB lower address range: 0x0000 to 0xFFFF 0x1 EPI_ADDRMAP_ECSZ_16MB 16 MB lower address range: 0x00.0000 to 0xFF.FFFF 0x2 EPI_ADDRMAP_ECSZ_256MB 256MB lower address range: 0x000.0000 to 0x0FFF.FFFF 0x3 EPI_ADDRMAP_EPADR External Peripheral Address 4 6 EPI_ADDRMAP_EPADR_NONE Not mapped 0x0 EPI_ADDRMAP_EPADR_A000 At 0xA000.0000 0x1 EPI_ADDRMAP_EPADR_C000 At 0xC000.0000 0x2 EPI_ADDRMAP_EPADR_HBQS Only to be used with Host Bus quad chip select. In quad chip select mode, CS2n maps to 0xA000.0000 and CS3n maps to 0xC000.0000 0x3 EPI_ADDRMAP_EPSZ External Peripheral Size 6 8 EPI_ADDRMAP_EPSZ_256B 256 bytes lower address range: 0x00 to 0xFF 0x0 EPI_ADDRMAP_EPSZ_64KB 64 KB lower address range: 0x0000 to 0xFFFF 0x1 EPI_ADDRMAP_EPSZ_16MB 16 MB lower address range: 0x00.0000 to 0xFF.FFFF 0x2 EPI_ADDRMAP_EPSZ_256MB 256 MB lower address range: 0x000.0000 to 0xFFF.FFFF 0x3 EPI_ADDRMAP_ERADR External RAM Address 0 2 EPI_ADDRMAP_ERADR_NONE Not mapped 0x0 EPI_ADDRMAP_ERADR_6000 At 0x6000.0000 0x1 EPI_ADDRMAP_ERADR_8000 At 0x8000.0000 0x2 EPI_ADDRMAP_ERADR_HBQS Only to be used with Host Bus quad chip select. In quad chip select mode, CS0n maps to 0x6000.0000 and CS1n maps to 0x8000.0000 0x3 EPI_ADDRMAP_ERSZ External RAM Size 2 4 EPI_ADDRMAP_ERSZ_256B 256 bytes lower address range: 0x00 to 0xFF 0x0 EPI_ADDRMAP_ERSZ_64KB 64 KB lower address range: 0x0000 to 0xFFFF 0x1 EPI_ADDRMAP_ERSZ_16MB 16 MB lower address range: 0x00.0000 to 0xFF.FFFF 0x2 EPI_ADDRMAP_ERSZ_256MB 256 MB lower address range: 0x000.0000 to 0xFFF.FFFF 0x3 BAUD EPI Main Baud Rate 0x4 -1 read-write n 0x0 0x0 EPI_BAUD_COUNT0 Baud Rate Counter 0 0 16 EPI_BAUD_COUNT1 Baud Rate Counter 1 16 32 BAUD2 EPI Main Baud Rate 0x8 -1 read-write n 0x0 0x0 EPI_BAUD2_COUNT0 CS2n Baud Rate Counter 0 0 16 EPI_BAUD2_COUNT1 CS3n Baud Rate Counter 1 16 32 CFG EPI Configuration 0x0 -1 read-write n 0x0 0x0 EPI_CFG_BLKEN Block Enable 4 5 EPI_CFG_INTDIV Integer Clock Divider Enable 8 9 EPI_CFG_MODE Mode Select 0 4 EPI_CFG_MODE_NONE General Purpose 0x0 EPI_CFG_MODE_SDRAM SDRAM 0x1 EPI_CFG_MODE_HB8 8-Bit Host-Bus (HB8) 0x2 EPI_CFG_MODE_HB16 16-Bit Host-Bus (HB16) 0x3 DMATXCNT EPI DMA Transmit Count 0x208 -1 read-write n 0x0 0x0 EPI_DMATXCNT_TXCNT DMA Count 0 16 EISC EPI Error and Interrupt Status and Clear 0x21C -1 read-write n 0x0 0x0 EPI_EISC_DMARDIC Read uDMA Interrupt Clear 3 4 EPI_EISC_DMAWRIC Write uDMA Interrupt Clear 4 5 EPI_EISC_RSTALL Read Stalled Error 1 2 EPI_EISC_TOUT Timeout Error 0 1 EPI_EISC_WTFULL Write FIFO Full Error 2 3 EPI0ADDRMAP EPI Address Map 0x1C read-write n 0x0 0x0 EPI_ADDRMAP_ECADR External Code Address 8 10 EPI_ADDRMAP_ECADR_NONE Not mapped 0x0 EPI_ADDRMAP_ECADR_1000 At 0x1000.0000 0x1 EPI_ADDRMAP_ECSZ External Code Size 10 12 EPI_ADDRMAP_ECSZ_256B 256 bytes; lower address range: 0x00 to 0xFF 0x0 EPI_ADDRMAP_ECSZ_64KB 64 KB; lower address range: 0x0000 to 0xFFFF 0x1 EPI_ADDRMAP_ECSZ_16MB 16 MB; lower address range: 0x00.0000 to 0xFF.FFFF 0x2 EPI_ADDRMAP_ECSZ_256MB 256MB; lower address range: 0x000.0000 to 0x0FFF.FFFF 0x3 EPI_ADDRMAP_EPADR External Peripheral Address 4 6 EPI_ADDRMAP_EPADR_NONE Not mapped 0x0 EPI_ADDRMAP_EPADR_A000 At 0xA000.0000 0x1 EPI_ADDRMAP_EPADR_C000 At 0xC000.0000 0x2 EPI_ADDRMAP_EPADR_HBQS Only to be used with Host Bus quad chip select. In quad chip select mode, CS2n maps to 0xA000.0000 and CS3n maps to 0xC000.0000 0x3 EPI_ADDRMAP_EPSZ External Peripheral Size 6 8 EPI_ADDRMAP_EPSZ_256B 256 bytes; lower address range: 0x00 to 0xFF 0x0 EPI_ADDRMAP_EPSZ_64KB 64 KB; lower address range: 0x0000 to 0xFFFF 0x1 EPI_ADDRMAP_EPSZ_16MB 16 MB; lower address range: 0x00.0000 to 0xFF.FFFF 0x2 EPI_ADDRMAP_EPSZ_256MB 256 MB; lower address range: 0x000.0000 to 0xFFF.FFFF 0x3 EPI_ADDRMAP_ERADR External RAM Address 0 2 EPI_ADDRMAP_ERADR_NONE Not mapped 0x0 EPI_ADDRMAP_ERADR_6000 At 0x6000.0000 0x1 EPI_ADDRMAP_ERADR_8000 At 0x8000.0000 0x2 EPI_ADDRMAP_ERADR_HBQS Only to be used with Host Bus quad chip select. In quad chip select mode, CS0n maps to 0x6000.0000 and CS1n maps to 0x8000.0000 0x3 EPI_ADDRMAP_ERSZ External RAM Size 2 4 EPI_ADDRMAP_ERSZ_256B 256 bytes; lower address range: 0x00 to 0xFF 0x0 EPI_ADDRMAP_ERSZ_64KB 64 KB; lower address range: 0x0000 to 0xFFFF 0x1 EPI_ADDRMAP_ERSZ_16MB 16 MB; lower address range: 0x00.0000 to 0xFF.FFFF 0x2 EPI_ADDRMAP_ERSZ_256MB 256 MB; lower address range: 0x000.0000 to 0xFFF.FFFF 0x3 EPI0BAUD EPI Main Baud Rate 0x4 read-write n 0x0 0x0 EPI_BAUD_COUNT0 Baud Rate Counter 0 0 16 EPI_BAUD_COUNT1 Baud Rate Counter 1 16 32 EPI0BAUD2 EPI Main Baud Rate 0x8 read-write n 0x0 0x0 EPI_BAUD2_COUNT0 CS2n Baud Rate Counter 0 0 16 EPI_BAUD2_COUNT1 CS3n Baud Rate Counter 1 16 32 EPI0CFG EPI Configuration 0x0 read-write n 0x0 0x0 EPI_CFG_BLKEN Block Enable 4 5 EPI_CFG_INTDIV Integer Clock Divider Enable 8 9 EPI_CFG_MODE Mode Select 0 4 EPI_CFG_MODE_NONE General Purpose 0x0 EPI_CFG_MODE_SDRAM SDRAM 0x1 EPI_CFG_MODE_HB8 8-Bit Host-Bus (HB8) 0x2 EPI_CFG_MODE_HB16 16-Bit Host-Bus (HB16) 0x3 EPI0DMATXCNT EPI DMA Transmit Count 0x208 read-write n 0x0 0x0 EPI_DMATXCNT_TXCNT DMA Count 0 16 EPI0EISC EPI Error and Interrupt Status and Clear 0x21C read-write n 0x0 0x0 EPI_EISC_DMARDIC Read uDMA Interrupt Clear 3 4 EPI_EISC_DMAWRIC Write uDMA Interrupt Clear 4 5 EPI_EISC_RSTALL Read Stalled Error 1 2 EPI_EISC_TOUT Timeout Error 0 1 EPI_EISC_WTFULL Write FIFO Full Error 2 3 EPI0FIFOLVL EPI FIFO Level Selects 0x200 read-write n 0x0 0x0 EPI_FIFOLVL_RDFIFO Read FIFO 0 3 EPI_FIFOLVL_RDFIFO_1 Trigger when there are 1 or more entries in the NBRFIFO 0x1 EPI_FIFOLVL_RDFIFO_2 Trigger when there are 2 or more entries in the NBRFIFO 0x2 EPI_FIFOLVL_RDFIFO_4 Trigger when there are 4 or more entries in the NBRFIFO 0x3 EPI_FIFOLVL_RDFIFO_6 Trigger when there are 6 or more entries in the NBRFIFO 0x4 EPI_FIFOLVL_RDFIFO_7 Trigger when there are 7 or more entries in the NBRFIFO 0x5 EPI_FIFOLVL_RDFIFO_8 Trigger when there are 8 entries in the NBRFIFO 0x6 EPI_FIFOLVL_RSERR Read Stall Error 16 17 EPI_FIFOLVL_WFERR Write Full Error 17 18 EPI_FIFOLVL_WRFIFO Write FIFO 4 7 EPI_FIFOLVL_WRFIFO_EMPT Interrupt is triggered while WRFIFO is empty. 0x0 EPI_FIFOLVL_WRFIFO_2 Interrupt is triggered until there are only two slots available. Thus, trigger is deasserted when there are two WRFIFO entries present. This configuration is optimized for bursts of 2 0x2 EPI_FIFOLVL_WRFIFO_1 Interrupt is triggered until there is one WRFIFO entry available. This configuration expects only single writes 0x3 EPI_FIFOLVL_WRFIFO_NFULL Trigger interrupt when WRFIFO is not full, meaning trigger will continue to assert until there are four entries in the WRFIFO 0x4 EPI0GPCFG EPI General-Purpose Configuration 0x10 read-write n 0x0 0x0 EPI_GPCFG_ASIZE Address Bus Size 4 6 EPI_GPCFG_ASIZE_NONE No address 0x0 EPI_GPCFG_ASIZE_4BIT Up to 4 bits wide 0x1 EPI_GPCFG_ASIZE_12BIT Up to 12 bits wide. This size cannot be used with 24-bit data 0x2 EPI_GPCFG_ASIZE_20BIT Up to 20 bits wide. This size cannot be used with data sizes other than 8 0x3 EPI_GPCFG_CLKGATE Clock Gated 30 31 EPI_GPCFG_CLKPIN Clock Pin 31 32 EPI_GPCFG_DSIZE Size of Data Bus 0 2 EPI_GPCFG_DSIZE_4BIT 8 Bits Wide (EPI0S0 to EPI0S7) 0x0 EPI_GPCFG_DSIZE_16BIT 16 Bits Wide (EPI0S0 to EPI0S15) 0x1 EPI_GPCFG_DSIZE_24BIT 24 Bits Wide (EPI0S0 to EPI0S23) 0x2 EPI_GPCFG_DSIZE_32BIT 32 Bits Wide (EPI0S0 to EPI0S31) 0x3 EPI_GPCFG_FRM50 50/50 Frame 26 27 EPI_GPCFG_FRMCNT Frame Count 22 26 EPI_GPCFG_WR2CYC 2-Cycle Writes 19 20 EPI0HB16CFG EPI Host-Bus 16 Configuration EPI_ALT16 0x10 read-write n 0x0 0x0 EPI_HB16CFG_ALEHIGH ALE Strobe Polarity 19 20 EPI_HB16CFG_BSEL Byte Select Configuration 2 3 EPI_HB16CFG_BURST Burst Mode 16 17 EPI_HB16CFG_CLKGATE Clock Gated 31 32 EPI_HB16CFG_CLKGATEI Clock Gated Idle 30 31 EPI_HB16CFG_CLKINV Invert Output Clock Enable 29 30 EPI_HB16CFG_IRDYINV Input Ready Invert 27 28 EPI_HB16CFG_MAXWAIT Maximum Wait 8 16 EPI_HB16CFG_MODE Host Bus Sub-Mode 0 2 EPI_HB16CFG_MODE_ADMUX ADMUX - AD[15:0] 0x0 EPI_HB16CFG_MODE_ADNMUX ADNONMUX - D[15:0] 0x1 EPI_HB16CFG_MODE_SRAM Continuous Read - D[15:0] 0x2 EPI_HB16CFG_MODE_XFIFO XFIFO - D[15:0] 0x3 EPI_HB16CFG_RDCRE PSRAM Configuration Register Read 17 18 EPI_HB16CFG_RDHIGH READ Strobe Polarity 20 21 EPI_HB16CFG_RDWS Read Wait States 4 6 EPI_HB16CFG_RDWS_2 Active RDn is 2 EPI clocks 0x0 EPI_HB16CFG_RDWS_4 Active RDn is 4 EPI clocks 0x1 EPI_HB16CFG_RDWS_6 Active RDn is 6 EPI clocks 0x2 EPI_HB16CFG_RDWS_8 Active RDn is 8 EPI clocks 0x3 EPI_HB16CFG_RDYEN Input Ready Enable 28 29 EPI_HB16CFG_WRCRE PSRAM Configuration Register Write 18 19 EPI_HB16CFG_WRHIGH WRITE Strobe Polarity 21 22 EPI_HB16CFG_WRWS Write Wait States 6 8 EPI_HB16CFG_WRWS_2 Active WRn is 2 EPI clocks 0x0 EPI_HB16CFG_WRWS_4 Active WRn is 4 EPI clocks 0x1 EPI_HB16CFG_WRWS_6 Active WRn is 6 EPI clocks 0x2 EPI_HB16CFG_WRWS_8 Active WRn is 8 EPI clocks 0x3 EPI_HB16CFG_XFEEN External FIFO EMPTY Enable 22 23 EPI_HB16CFG_XFFEN External FIFO FULL Enable 23 24 EPI0HB16CFG2 EPI Host-Bus 16 Configuration 2 EPI_ALT16 0x14 read-write n 0x0 0x0 EPI_HB16CFG2_ALEHIGH CS1n ALE Strobe Polarity 19 20 EPI_HB16CFG2_BURST CS1n Burst Mode 16 17 EPI_HB16CFG2_CSBAUD Chip Select Baud Rate and Multiple Sub-Mode Configuration enable 26 27 EPI_HB16CFG2_CSCFG Chip Select Configuration 24 26 EPI_HB16CFG2_CSCFG_ALE ALE Configuration 0x0 EPI_HB16CFG2_CSCFG_CS CSn Configuration 0x1 EPI_HB16CFG2_CSCFG_DCS Dual CSn Configuration 0x2 EPI_HB16CFG2_CSCFG_ADCS ALE with Dual CSn Configuration 0x3 EPI_HB16CFG2_CSCFGEXT Chip Select Extended Configuration 27 28 EPI_HB16CFG2_MODE CS1n Host Bus Sub-Mode 0 2 EPI_HB16CFG2_MODE_ADMUX ADMUX - AD[15:0] 0x0 EPI_HB16CFG2_MODE_AD ADNONMUX - D[15:0] 0x1 EPI_HB16CFG2_RDCRE CS1n PSRAM Configuration Register Read 17 18 EPI_HB16CFG2_RDHIGH CS1n READ Strobe Polarity 20 21 EPI_HB16CFG2_RDWS CS1n Read Wait States 4 6 EPI_HB16CFG2_RDWS_2 Active RDn is 2 EPI clocks 0x0 EPI_HB16CFG2_RDWS_4 Active RDn is 4 EPI clocks 0x1 EPI_HB16CFG2_RDWS_6 Active RDn is 6 EPI clocks 0x2 EPI_HB16CFG2_RDWS_8 Active RDn is 8 EPI clocks 0x3 EPI_HB16CFG2_WRCRE CS1n PSRAM Configuration Register Write 18 19 EPI_HB16CFG2_WRHIGH CS1n WRITE Strobe Polarity 21 22 EPI_HB16CFG2_WRWS CS1n Write Wait States 6 8 EPI_HB16CFG2_WRWS_2 Active WRn is 2 EPI clocks 0x0 EPI_HB16CFG2_WRWS_4 Active WRn is 4 EPI clocks 0x1 EPI_HB16CFG2_WRWS_6 Active WRn is 6 EPI clocks 0x2 EPI_HB16CFG2_WRWS_8 Active WRn is 8 EPI clocks 0x3 EPI0HB16CFG3 EPI Host-Bus 16 Configuration 3 EPI_ALT16 0x308 read-write n 0x0 0x0 EPI_HB16CFG3_ALEHIGH CS2n ALE Strobe Polarity 19 20 EPI_HB16CFG3_BURST CS2n Burst Mode 16 17 EPI_HB16CFG3_MODE CS2n Host Bus Sub-Mode 0 2 EPI_HB16CFG3_MODE_ADMUX ADMUX - AD[15:0] 0x0 EPI_HB16CFG3_MODE_AD ADNONMUX - D[15:0] 0x1 EPI_HB16CFG3_RDCRE CS2n PSRAM Configuration Register Read 17 18 EPI_HB16CFG3_RDHIGH CS2n READ Strobe Polarity 20 21 EPI_HB16CFG3_RDWS CS2n Read Wait States 4 6 EPI_HB16CFG3_RDWS_2 Active RDn is 2 EPI clocks 0x0 EPI_HB16CFG3_RDWS_4 Active RDn is 4 EPI clocks 0x1 EPI_HB16CFG3_RDWS_6 Active RDn is 6 EPI clocks 0x2 EPI_HB16CFG3_RDWS_8 Active RDn is 8 EPI clocks 0x3 EPI_HB16CFG3_WRCRE CS2n PSRAM Configuration Register Write 18 19 EPI_HB16CFG3_WRHIGH CS2n WRITE Strobe Polarity 21 22 EPI_HB16CFG3_WRWS CS2n Write Wait States 6 8 EPI_HB16CFG3_WRWS_2 Active WRn is 2 EPI clocks 0x0 EPI_HB16CFG3_WRWS_4 Active WRn is 4 EPI clocks 0x1 EPI_HB16CFG3_WRWS_6 Active WRn is 6 EPI clocks 0x2 EPI_HB16CFG3_WRWS_8 Active WRn is 8 EPI clocks 0x3 EPI0HB16CFG4 EPI Host-Bus 16 Configuration 4 0x30C read-write n 0x0 0x0 EPI_HB16CFG4_ALEHIGH CS3n ALE Strobe Polarity 19 20 EPI_HB16CFG4_BURST CS3n Burst Mode 16 17 EPI_HB16CFG4_MODE CS3n Host Bus Sub-Mode 0 2 EPI_HB16CFG4_MODE_ADMUX ADMUX - AD[15:0] 0x0 EPI_HB16CFG4_MODE_AD ADNONMUX - D[15:0] 0x1 EPI_HB16CFG4_RDCRE CS3n PSRAM Configuration Register Read 17 18 EPI_HB16CFG4_RDHIGH CS3n READ Strobe Polarity 20 21 EPI_HB16CFG4_RDWS CS3n Read Wait States 4 6 EPI_HB16CFG4_RDWS_2 Active RDn is 2 EPI clocks 0x0 EPI_HB16CFG4_RDWS_4 Active RDn is 4 EPI clocks 0x1 EPI_HB16CFG4_RDWS_6 Active RDn is 6 EPI clocks 0x2 EPI_HB16CFG4_RDWS_8 Active RDn is 8 EPI clocks 0x3 EPI_HB16CFG4_WRCRE CS3n PSRAM Configuration Register Write 18 19 EPI_HB16CFG4_WRHIGH CS3n WRITE Strobe Polarity 21 22 EPI_HB16CFG4_WRWS CS3n Write Wait States 6 8 EPI_HB16CFG4_WRWS_2 Active WRn is 2 EPI clocks 0x0 EPI_HB16CFG4_WRWS_4 Active WRn is 4 EPI clocks 0x1 EPI_HB16CFG4_WRWS_6 Active WRn is 6 EPI clocks 0x2 EPI_HB16CFG4_WRWS_8 Active WRn is 8 EPI clocks 0x3 EPI0HB16TIME EPI Host-Bus 16 Timing Extension EPI_ALT16 0x310 read-write n 0x0 0x0 EPI_HB16TIME_CAPWIDTH CS0n Inter-transfer Capture Width 12 14 EPI_HB16TIME_IRDYDLY CS0n Input Ready Delay 24 26 EPI_HB16TIME_PSRAMSZ PSRAM Row Size 16 19 EPI_HB16TIME_PSRAMSZ_0 No row size limitation 0x0 EPI_HB16TIME_PSRAMSZ_128B 128 B 0x1 EPI_HB16TIME_PSRAMSZ_256B 256 B 0x2 EPI_HB16TIME_PSRAMSZ_512B 512 B 0x3 EPI_HB16TIME_PSRAMSZ_1KB 1024 B 0x4 EPI_HB16TIME_PSRAMSZ_2KB 2048 B 0x5 EPI_HB16TIME_PSRAMSZ_4KB 4096 B 0x6 EPI_HB16TIME_PSRAMSZ_8KB 8192 B 0x7 EPI_HB16TIME_RDWSM Read Wait State Minus One 0 1 EPI_HB16TIME_WRWSM Write Wait State Minus One 4 5 EPI0HB16TIME2 EPI Host-Bus 16 Timing Extension EPI_ALT16 0x314 read-write n 0x0 0x0 EPI_HB16TIME2_CAPWIDTH CS1n Inter-transfer Capture Width 12 14 EPI_HB16TIME2_IRDYDLY CS1n Input Ready Delay 24 26 EPI_HB16TIME2_PSRAMSZ PSRAM Row Size 16 19 EPI_HB16TIME2_PSRAMSZ_0 No row size limitation 0x0 EPI_HB16TIME2_PSRAMSZ_128B 128 B 0x1 EPI_HB16TIME2_PSRAMSZ_256B 256 B 0x2 EPI_HB16TIME2_PSRAMSZ_512B 512 B 0x3 EPI_HB16TIME2_PSRAMSZ_1KB 1024 B 0x4 EPI_HB16TIME2_PSRAMSZ_2KB 2048 B 0x5 EPI_HB16TIME2_PSRAMSZ_4KB 4096 B 0x6 EPI_HB16TIME2_PSRAMSZ_8KB 8192 B 0x7 EPI_HB16TIME2_RDWSM CS1n Read Wait State Minus One 0 1 EPI_HB16TIME2_WRWSM CS1n Write Wait State Minus One 4 5 EPI0HB16TIME3 EPI Host-Bus 16 Timing Extension 0x318 read-write n 0x0 0x0 EPI_HB16TIME3_CAPWIDTH CS2n Inter-transfer Capture Width 12 14 EPI_HB16TIME3_IRDYDLY CS2n Input Ready Delay 24 26 EPI_HB16TIME3_PSRAMSZ PSRAM Row Size 16 19 EPI_HB16TIME3_PSRAMSZ_0 No row size limitation 0x0 EPI_HB16TIME3_PSRAMSZ_128B 128 B 0x1 EPI_HB16TIME3_PSRAMSZ_256B 256 B 0x2 EPI_HB16TIME3_PSRAMSZ_512B 512 B 0x3 EPI_HB16TIME3_PSRAMSZ_1KB 1024 B 0x4 EPI_HB16TIME3_PSRAMSZ_2KB 2048 B 0x5 EPI_HB16TIME3_PSRAMSZ_4KB 4096 B 0x6 EPI_HB16TIME3_PSRAMSZ_8KB 8192 B 0x7 EPI_HB16TIME3_RDWSM CS2n Read Wait State Minus One 0 1 EPI_HB16TIME3_WRWSM CS2n Write Wait State Minus One 4 5 EPI0HB16TIME4 EPI Host-Bus 16 Timing Extension 0x31C read-write n 0x0 0x0 EPI_HB16TIME4_CAPWIDTH CS3n Inter-transfer Capture Width 12 14 EPI_HB16TIME4_IRDYDLY CS3n Input Ready Delay 24 26 EPI_HB16TIME4_PSRAMSZ PSRAM Row Size 16 19 EPI_HB16TIME4_PSRAMSZ_0 No row size limitation 0x0 EPI_HB16TIME4_PSRAMSZ_128B 128 B 0x1 EPI_HB16TIME4_PSRAMSZ_256B 256 B 0x2 EPI_HB16TIME4_PSRAMSZ_512B 512 B 0x3 EPI_HB16TIME4_PSRAMSZ_1KB 1024 B 0x4 EPI_HB16TIME4_PSRAMSZ_2KB 2048 B 0x5 EPI_HB16TIME4_PSRAMSZ_4KB 4096 B 0x6 EPI_HB16TIME4_PSRAMSZ_8KB 8192 B 0x7 EPI_HB16TIME4_RDWSM CS3n Read Wait State Minus One 0 1 EPI_HB16TIME4_WRWSM CS3n Write Wait State Minus One 4 5 EPI0HB8CFG EPI Host-Bus 8 Configuration EPI_ALT8 0x10 read-write n 0x0 0x0 EPI_HB8CFG_ALEHIGH ALE Strobe Polarity 19 20 EPI_HB8CFG_CLKGATE Clock Gated 31 32 EPI_HB8CFG_CLKGATEI Clock Gated when Idle 30 31 EPI_HB8CFG_CLKINV Invert Output Clock Enable 29 30 EPI_HB8CFG_IRDYINV Input Ready Invert 27 28 EPI_HB8CFG_MAXWAIT Maximum Wait 8 16 EPI_HB8CFG_MODE Host Bus Sub-Mode 0 2 EPI_HB8CFG_MODE_MUX ADMUX - AD[7:0] 0x0 EPI_HB8CFG_MODE_NMUX ADNONMUX - D[7:0] 0x1 EPI_HB8CFG_MODE_SRAM Continuous Read - D[7:0] 0x2 EPI_HB8CFG_MODE_FIFO XFIFO - D[7:0] 0x3 EPI_HB8CFG_RDHIGH READ Strobe Polarity 20 21 EPI_HB8CFG_RDWS Read Wait States 4 6 EPI_HB8CFG_RDWS_2 Active RDn is 2 EPI clocks 0x0 EPI_HB8CFG_RDWS_4 Active RDn is 4 EPI clocks 0x1 EPI_HB8CFG_RDWS_6 Active RDn is 6 EPI clocks 0x2 EPI_HB8CFG_RDWS_8 Active RDn is 8 EPI clocks 0x3 EPI_HB8CFG_RDYEN Input Ready Enable 28 29 EPI_HB8CFG_WRHIGH WRITE Strobe Polarity 21 22 EPI_HB8CFG_WRWS Write Wait States 6 8 EPI_HB8CFG_WRWS_2 Active WRn is 2 EPI clocks 0x0 EPI_HB8CFG_WRWS_4 Active WRn is 4 EPI clocks 0x1 EPI_HB8CFG_WRWS_6 Active WRn is 6 EPI clocks 0x2 EPI_HB8CFG_WRWS_8 Active WRn is 8 EPI clocks 0x3 EPI_HB8CFG_XFEEN External FIFO EMPTY Enable 22 23 EPI_HB8CFG_XFFEN External FIFO FULL Enable 23 24 EPI0HB8CFG2 EPI Host-Bus 8 Configuration 2 EPI_ALT8 0x14 read-write n 0x0 0x0 EPI_HB8CFG2_ALEHIGH CS1n ALE Strobe Polarity 19 20 EPI_HB8CFG2_CSBAUD Chip Select Baud Rate and Multiple Sub-Mode Configuration enable 26 27 EPI_HB8CFG2_CSCFG Chip Select Configuration 24 26 EPI_HB8CFG2_CSCFG_ALE ALE Configuration 0x0 EPI_HB8CFG2_CSCFG_CS CSn Configuration 0x1 EPI_HB8CFG2_CSCFG_DCS Dual CSn Configuration 0x2 EPI_HB8CFG2_CSCFG_ADCS ALE with Dual CSn Configuration 0x3 EPI_HB8CFG2_CSCFGEXT Chip Select Extended Configuration 27 28 EPI_HB8CFG2_MODE CS1n Host Bus Sub-Mode 0 2 EPI_HB8CFG2_MODE_ADMUX ADMUX - AD[7:0] 0x0 EPI_HB8CFG2_MODE_AD ADNONMUX - D[7:0] 0x1 EPI_HB8CFG2_RDHIGH CS1n READ Strobe Polarity 20 21 EPI_HB8CFG2_RDWS CS1n Read Wait States 4 6 EPI_HB8CFG2_RDWS_2 Active RDn is 2 EPI clocks 0x0 EPI_HB8CFG2_RDWS_4 Active RDn is 4 EPI clocks 0x1 EPI_HB8CFG2_RDWS_6 Active RDn is 6 EPI clocks 0x2 EPI_HB8CFG2_RDWS_8 Active RDn is 8 EPI clocks 0x3 EPI_HB8CFG2_WRHIGH CS1n WRITE Strobe Polarity 21 22 EPI_HB8CFG2_WRWS CS1n Write Wait States 6 8 EPI_HB8CFG2_WRWS_2 Active WRn is 2 EPI clocks 0x0 EPI_HB8CFG2_WRWS_4 Active WRn is 4 EPI clocks 0x1 EPI_HB8CFG2_WRWS_6 Active WRn is 6 EPI clocks 0x2 EPI_HB8CFG2_WRWS_8 Active WRn is 8 EPI clocks 0x3 EPI0HB8CFG3 EPI Host-Bus 8 Configuration 3 0x308 read-write n 0x0 0x0 EPI_HB8CFG3_ALEHIGH CS2n ALE Strobe Polarity 19 20 EPI_HB8CFG3_MODE CS2n Host Bus Sub-Mode 0 2 EPI_HB8CFG3_MODE_ADMUX ADMUX - AD[7:0] 0x0 EPI_HB8CFG3_MODE_AD ADNONMUX - D[7:0] 0x1 EPI_HB8CFG3_RDHIGH CS2n READ Strobe Polarity 20 21 EPI_HB8CFG3_RDWS CS2n Read Wait States 4 6 EPI_HB8CFG3_RDWS_2 Active RDn is 2 EPI clocks 0x0 EPI_HB8CFG3_RDWS_4 Active RDn is 4 EPI clocks 0x1 EPI_HB8CFG3_RDWS_6 Active RDn is 6 EPI clocks 0x2 EPI_HB8CFG3_RDWS_8 Active RDn is 8 EPI clocks 0x3 EPI_HB8CFG3_WRHIGH CS2n WRITE Strobe Polarity 21 22 EPI_HB8CFG3_WRWS CS2n Write Wait States 6 8 EPI_HB8CFG3_WRWS_2 Active WRn is 2 EPI clocks 0x0 EPI_HB8CFG3_WRWS_4 Active WRn is 4 EPI clocks 0x1 EPI_HB8CFG3_WRWS_6 Active WRn is 6 EPI clocks 0x2 EPI_HB8CFG3_WRWS_8 Active WRn is 8 EPI clocks 0x3 EPI0HB8CFG4 EPI Host-Bus 8 Configuration 4 EPI_ALT8 0x30C read-write n 0x0 0x0 EPI_HB8CFG4_ALEHIGH CS3n ALE Strobe Polarity 19 20 EPI_HB8CFG4_MODE CS3n Host Bus Sub-Mode 0 2 EPI_HB8CFG4_MODE_ADMUX ADMUX - AD[7:0] 0x0 EPI_HB8CFG4_MODE_AD ADNONMUX - D[7:0] 0x1 EPI_HB8CFG4_RDHIGH CS2n READ Strobe Polarity 20 21 EPI_HB8CFG4_RDWS CS3n Read Wait States 4 6 EPI_HB8CFG4_RDWS_2 Active RDn is 2 EPI clocks 0x0 EPI_HB8CFG4_RDWS_4 Active RDn is 4 EPI clocks 0x1 EPI_HB8CFG4_RDWS_6 Active RDn is 6 EPI clocks 0x2 EPI_HB8CFG4_RDWS_8 Active RDn is 8 EPI clocks 0x3 EPI_HB8CFG4_WRHIGH CS3n WRITE Strobe Polarity 21 22 EPI_HB8CFG4_WRWS CS3n Write Wait States 6 8 EPI_HB8CFG4_WRWS_2 Active WRn is 2 EPI clocks 0x0 EPI_HB8CFG4_WRWS_4 Active WRn is 4 EPI clocks 0x1 EPI_HB8CFG4_WRWS_6 Active WRn is 6 EPI clocks 0x2 EPI_HB8CFG4_WRWS_8 Active WRn is 8 EPI clocks 0x3 EPI0HB8TIME EPI Host-Bus 8 Timing Extension 0x310 read-write n 0x0 0x0 EPI_HB8TIME_CAPWIDTH CS0n Inter-transfer Capture Width 12 14 EPI_HB8TIME_IRDYDLY CS0n Input Ready Delay 24 26 EPI_HB8TIME_RDWSM Read Wait State Minus One 0 1 EPI_HB8TIME_WRWSM Write Wait State Minus One 4 5 EPI0HB8TIME2 EPI Host-Bus 8 Timing Extension 0x314 read-write n 0x0 0x0 EPI_HB8TIME2_CAPWIDTH CS1n Inter-transfer Capture Width 12 14 EPI_HB8TIME2_IRDYDLY CS1n Input Ready Delay 24 26 EPI_HB8TIME2_RDWSM CS1n Read Wait State Minus One 0 1 EPI_HB8TIME2_WRWSM CS1n Write Wait State Minus One 4 5 EPI0HB8TIME3 EPI Host-Bus 8 Timing Extension EPI_ALT8 0x318 read-write n 0x0 0x0 EPI_HB8TIME3_CAPWIDTH CS2n Inter-transfer Capture Width 12 14 EPI_HB8TIME3_IRDYDLY CS2n Input Ready Delay 24 26 EPI_HB8TIME3_RDWSM CS2n Read Wait State Minus One 0 1 EPI_HB8TIME3_WRWSM CS2n Write Wait State Minus One 4 5 EPI0HB8TIME4 EPI Host-Bus 8 Timing Extension EPI_ALT8 0x31C read-write n 0x0 0x0 EPI_HB8TIME4_CAPWIDTH CS3n Inter-transfer Capture Width 12 14 EPI_HB8TIME4_IRDYDLY CS3n Input Ready Delay 24 26 EPI_HB8TIME4_RDWSM CS3n Read Wait State Minus One 0 1 EPI_HB8TIME4_WRWSM CS3n Write Wait State Minus One 4 5 EPI0HBPSRAM EPI Host-Bus PSRAM 0x360 read-write n 0x0 0x0 EPI_HBPSRAM_CR PSRAM Config Register 0 21 EPI0IM EPI Interrupt Mask 0x210 read-write n 0x0 0x0 EPI_IM_DMARDIM Read uDMA Interrupt Mask 3 4 EPI_IM_DMAWRIM Write uDMA Interrupt Mask 4 5 EPI_IM_ERRIM Error Interrupt Mask 0 1 EPI_IM_RDIM Read FIFO Full Interrupt Mask 1 2 EPI_IM_WRIM Write FIFO Empty Interrupt Mask 2 3 EPI0MIS EPI Masked Interrupt Status 0x218 read-write n 0x0 0x0 EPI_MIS_DMARDMIS Read uDMA Masked Interrupt Status 3 4 EPI_MIS_DMAWRMIS Write uDMA Masked Interrupt Status 4 5 EPI_MIS_ERRMIS Error Masked Interrupt Status 0 1 EPI_MIS_RDMIS Read Masked Interrupt Status 1 2 EPI_MIS_WRMIS Write Masked Interrupt Status 2 3 EPI0RADDR0 EPI Read Address 0 0x24 read-write n 0x0 0x0 EPI_RADDR0_ADDR Current Address 0 32 EPI0RADDR1 EPI Read Address 1 0x34 read-write n 0x0 0x0 EPI_RADDR1_ADDR Current Address 0 32 EPI0READFIFO0 EPI Read FIFO 0x70 read-write n 0x0 0x0 EPI_READFIFO0_DATA Reads Data 0 32 EPI0READFIFO1 EPI Read FIFO Alias 1 0x74 read-write n 0x0 0x0 EPI_READFIFO1_DATA Reads Data 0 32 EPI0READFIFO2 EPI Read FIFO Alias 2 0x78 read-write n 0x0 0x0 EPI_READFIFO2_DATA Reads Data 0 32 EPI0READFIFO3 EPI Read FIFO Alias 3 0x7C read-write n 0x0 0x0 EPI_READFIFO3_DATA Reads Data 0 32 EPI0READFIFO4 EPI Read FIFO Alias 4 0x80 read-write n 0x0 0x0 EPI_READFIFO4_DATA Reads Data 0 32 EPI0READFIFO5 EPI Read FIFO Alias 5 0x84 read-write n 0x0 0x0 EPI_READFIFO5_DATA Reads Data 0 32 EPI0READFIFO6 EPI Read FIFO Alias 6 0x88 read-write n 0x0 0x0 EPI_READFIFO6_DATA Reads Data 0 32 EPI0READFIFO7 EPI Read FIFO Alias 7 0x8C read-write n 0x0 0x0 EPI_READFIFO7_DATA Reads Data 0 32 EPI0RFIFOCNT EPI Read FIFO Count 0x6C read-write n 0x0 0x0 EPI_RFIFOCNT_COUNT FIFO Count 0 4 EPI0RIS EPI Raw Interrupt Status 0x214 read-write n 0x0 0x0 EPI_RIS_DMARDRIS Read uDMA Raw Interrupt Status 3 4 EPI_RIS_DMAWRRIS Write uDMA Raw Interrupt Status 4 5 EPI_RIS_ERRRIS Error Raw Interrupt Status 0 1 EPI_RIS_RDRIS Read Raw Interrupt Status 1 2 EPI_RIS_WRRIS Write Raw Interrupt Status 2 3 EPI0RPSTD0 EPI Non-Blocking Read Data 0 0x28 read-write n 0x0 0x0 EPI_RPSTD0_POSTCNT Post Count 0 13 EPI0RPSTD1 EPI Non-Blocking Read Data 1 0x38 read-write n 0x0 0x0 EPI_RPSTD1_POSTCNT Post Count 0 13 EPI0RSIZE0 EPI Read Size 0 0x20 read-write n 0x0 0x0 EPI_RSIZE0_SIZE Current Size 0 2 EPI_RSIZE0_SIZE_8BIT Byte (8 bits) 0x1 EPI_RSIZE0_SIZE_16BIT Half-word (16 bits) 0x2 EPI_RSIZE0_SIZE_32BIT Word (32 bits) 0x3 EPI0RSIZE1 EPI Read Size 1 0x30 read-write n 0x0 0x0 EPI_RSIZE1_SIZE Current Size 0 2 EPI_RSIZE1_SIZE_8BIT Byte (8 bits) 0x1 EPI_RSIZE1_SIZE_16BIT Half-word (16 bits) 0x2 EPI_RSIZE1_SIZE_32BIT Word (32 bits) 0x3 EPI0SDRAMCFG EPI SDRAM Configuration EPI_ALTSD 0x10 read-write n 0x0 0x0 EPI_SDRAMCFG_FREQ EPI Frequency Range 30 32 EPI_SDRAMCFG_FREQ_NONE 0 - 15 MHz 0x0 EPI_SDRAMCFG_FREQ_15MHZ 15 - 30 MHz 0x1 EPI_SDRAMCFG_FREQ_30MHZ 30 - 50 MHz 0x2 EPI_SDRAMCFG_RFSH Refresh Counter 16 27 EPI_SDRAMCFG_SIZE Size of SDRAM 0 2 EPI_SDRAMCFG_SIZE_8MB 64 megabits (8MB) 0x0 EPI_SDRAMCFG_SIZE_16MB 128 megabits (16MB) 0x1 EPI_SDRAMCFG_SIZE_32MB 256 megabits (32MB) 0x2 EPI_SDRAMCFG_SIZE_64MB 512 megabits (64MB) 0x3 EPI_SDRAMCFG_SLEEP Sleep Mode 9 10 EPI0STAT EPI Status 0x60 read-write n 0x0 0x0 EPI_STAT_ACTIVE Register Active 0 1 EPI_STAT_INITSEQ Initialization Sequence 6 7 EPI_STAT_NBRBUSY Non-Blocking Read Busy 4 5 EPI_STAT_WBUSY Write Busy 5 6 EPI_STAT_XFEMPTY External FIFO Empty 7 8 EPI_STAT_XFFULL External FIFO Full 8 9 EPI0WFIFOCNT EPI Write FIFO Count 0x204 read-write n 0x0 0x0 EPI_WFIFOCNT_WTAV Available Write Transactions 0 3 FIFOLVL EPI FIFO Level Selects 0x200 -1 read-write n 0x0 0x0 EPI_FIFOLVL_RDFIFO Read FIFO 0 3 EPI_FIFOLVL_RDFIFO_1 Trigger when there are 1 or more entries in the NBRFIFO 0x1 EPI_FIFOLVL_RDFIFO_2 Trigger when there are 2 or more entries in the NBRFIFO 0x2 EPI_FIFOLVL_RDFIFO_4 Trigger when there are 4 or more entries in the NBRFIFO 0x3 EPI_FIFOLVL_RDFIFO_6 Trigger when there are 6 or more entries in the NBRFIFO 0x4 EPI_FIFOLVL_RDFIFO_7 Trigger when there are 7 or more entries in the NBRFIFO 0x5 EPI_FIFOLVL_RDFIFO_8 Trigger when there are 8 entries in the NBRFIFO 0x6 EPI_FIFOLVL_RSERR Read Stall Error 16 17 EPI_FIFOLVL_WFERR Write Full Error 17 18 EPI_FIFOLVL_WRFIFO Write FIFO 4 7 EPI_FIFOLVL_WRFIFO_EMPT Interrupt is triggered while WRFIFO is empty. 0x0 EPI_FIFOLVL_WRFIFO_2 Interrupt is triggered until there are only two slots available. Thus, trigger is deasserted when there are two WRFIFO entries present. This configuration is optimized for bursts of 2 0x2 EPI_FIFOLVL_WRFIFO_1 Interrupt is triggered until there is one WRFIFO entry available. This configuration expects only single writes 0x3 EPI_FIFOLVL_WRFIFO_NFULL Trigger interrupt when WRFIFO is not full, meaning trigger will continue to assert until there are four entries in the WRFIFO 0x4 GPCFG EPI General-Purpose Configuration 0x10 -1 read-write n 0x0 0x0 EPI_GPCFG_ASIZE Address Bus Size 4 6 EPI_GPCFG_ASIZE_NONE No address 0x0 EPI_GPCFG_ASIZE_4BIT Up to 4 bits wide 0x1 EPI_GPCFG_ASIZE_12BIT Up to 12 bits wide. This size cannot be used with 24-bit data 0x2 EPI_GPCFG_ASIZE_20BIT Up to 20 bits wide. This size cannot be used with data sizes other than 8 0x3 EPI_GPCFG_CLKGATE Clock Gated 30 31 EPI_GPCFG_CLKPIN Clock Pin 31 32 EPI_GPCFG_DSIZE Size of Data Bus 0 2 EPI_GPCFG_DSIZE_4BIT 8 Bits Wide (EPI0S0 to EPI0S7) 0x0 EPI_GPCFG_DSIZE_16BIT 16 Bits Wide (EPI0S0 to EPI0S15) 0x1 EPI_GPCFG_DSIZE_24BIT 24 Bits Wide (EPI0S0 to EPI0S23) 0x2 EPI_GPCFG_DSIZE_32BIT 32 Bits Wide (EPI0S0 to EPI0S31) 0x3 EPI_GPCFG_FRM50 50/50 Frame 26 27 EPI_GPCFG_FRMCNT Frame Count 22 26 EPI_GPCFG_WR2CYC 2-Cycle Writes 19 20 HB16CFG EPI Host-Bus 16 Configuration 0x10 -1 read-write n 0x0 0x0 EPI_HB16CFG_ALEHIGH ALE Strobe Polarity 19 20 EPI_HB16CFG_BSEL Byte Select Configuration 2 3 EPI_HB16CFG_BURST Burst Mode 16 17 EPI_HB16CFG_CLKGATE Clock Gated 31 32 EPI_HB16CFG_CLKGATEI Clock Gated Idle 30 31 EPI_HB16CFG_CLKINV Invert Output Clock Enable 29 30 EPI_HB16CFG_IRDYINV Input Ready Invert 27 28 EPI_HB16CFG_MAXWAIT Maximum Wait 8 16 EPI_HB16CFG_MODE Host Bus Sub-Mode 0 2 EPI_HB16CFG_MODE_ADMUX ADMUX - AD[15:0] 0x0 EPI_HB16CFG_MODE_ADNMUX ADNONMUX - D[15:0] 0x1 EPI_HB16CFG_MODE_SRAM Continuous Read - D[15:0] 0x2 EPI_HB16CFG_MODE_XFIFO XFIFO - D[15:0] 0x3 EPI_HB16CFG_RDCRE PSRAM Configuration Register Read 17 18 EPI_HB16CFG_RDHIGH READ Strobe Polarity 20 21 EPI_HB16CFG_RDWS Read Wait States 4 6 EPI_HB16CFG_RDWS_2 Active RDn is 2 EPI clocks 0x0 EPI_HB16CFG_RDWS_4 Active RDn is 4 EPI clocks 0x1 EPI_HB16CFG_RDWS_6 Active RDn is 6 EPI clocks 0x2 EPI_HB16CFG_RDWS_8 Active RDn is 8 EPI clocks 0x3 EPI_HB16CFG_RDYEN Input Ready Enable 28 29 EPI_HB16CFG_WRCRE PSRAM Configuration Register Write 18 19 EPI_HB16CFG_WRHIGH WRITE Strobe Polarity 21 22 EPI_HB16CFG_WRWS Write Wait States 6 8 EPI_HB16CFG_WRWS_2 Active WRn is 2 EPI clocks 0x0 EPI_HB16CFG_WRWS_4 Active WRn is 4 EPI clocks 0x1 EPI_HB16CFG_WRWS_6 Active WRn is 6 EPI clocks 0x2 EPI_HB16CFG_WRWS_8 Active WRn is 8 EPI clocks 0x3 EPI_HB16CFG_XFEEN External FIFO EMPTY Enable 22 23 EPI_HB16CFG_XFFEN External FIFO FULL Enable 23 24 HB16CFG2 EPI Host-Bus 16 Configuration 2 0x14 -1 read-write n 0x0 0x0 EPI_HB16CFG2_ALEHIGH CS1n ALE Strobe Polarity 19 20 EPI_HB16CFG2_BURST CS1n Burst Mode 16 17 EPI_HB16CFG2_CSBAUD Chip Select Baud Rate and Multiple Sub-Mode Configuration enable 26 27 EPI_HB16CFG2_CSCFG Chip Select Configuration 24 26 EPI_HB16CFG2_CSCFG_ALE ALE Configuration 0x0 EPI_HB16CFG2_CSCFG_CS CSn Configuration 0x1 EPI_HB16CFG2_CSCFG_DCS Dual CSn Configuration 0x2 EPI_HB16CFG2_CSCFG_ADCS ALE with Dual CSn Configuration 0x3 EPI_HB16CFG2_CSCFGEXT Chip Select Extended Configuration 27 28 EPI_HB16CFG2_MODE CS1n Host Bus Sub-Mode 0 2 EPI_HB16CFG2_MODE_ADMUX ADMUX - AD[15:0] 0x0 EPI_HB16CFG2_MODE_AD ADNONMUX - D[15:0] 0x1 EPI_HB16CFG2_RDCRE CS1n PSRAM Configuration Register Read 17 18 EPI_HB16CFG2_RDHIGH CS1n READ Strobe Polarity 20 21 EPI_HB16CFG2_RDWS CS1n Read Wait States 4 6 EPI_HB16CFG2_RDWS_2 Active RDn is 2 EPI clocks 0x0 EPI_HB16CFG2_RDWS_4 Active RDn is 4 EPI clocks 0x1 EPI_HB16CFG2_RDWS_6 Active RDn is 6 EPI clocks 0x2 EPI_HB16CFG2_RDWS_8 Active RDn is 8 EPI clocks 0x3 EPI_HB16CFG2_WRCRE CS1n PSRAM Configuration Register Write 18 19 EPI_HB16CFG2_WRHIGH CS1n WRITE Strobe Polarity 21 22 EPI_HB16CFG2_WRWS CS1n Write Wait States 6 8 EPI_HB16CFG2_WRWS_2 Active WRn is 2 EPI clocks 0x0 EPI_HB16CFG2_WRWS_4 Active WRn is 4 EPI clocks 0x1 EPI_HB16CFG2_WRWS_6 Active WRn is 6 EPI clocks 0x2 EPI_HB16CFG2_WRWS_8 Active WRn is 8 EPI clocks 0x3 HB16CFG3 EPI Host-Bus 16 Configuration 3 0x308 -1 read-write n 0x0 0x0 EPI_HB16CFG3_ALEHIGH CS2n ALE Strobe Polarity 19 20 EPI_HB16CFG3_BURST CS2n Burst Mode 16 17 EPI_HB16CFG3_MODE CS2n Host Bus Sub-Mode 0 2 EPI_HB16CFG3_MODE_ADMUX ADMUX - AD[15:0] 0x0 EPI_HB16CFG3_MODE_AD ADNONMUX - D[15:0] 0x1 EPI_HB16CFG3_RDCRE CS2n PSRAM Configuration Register Read 17 18 EPI_HB16CFG3_RDHIGH CS2n READ Strobe Polarity 20 21 EPI_HB16CFG3_RDWS CS2n Read Wait States 4 6 EPI_HB16CFG3_RDWS_2 Active RDn is 2 EPI clocks 0x0 EPI_HB16CFG3_RDWS_4 Active RDn is 4 EPI clocks 0x1 EPI_HB16CFG3_RDWS_6 Active RDn is 6 EPI clocks 0x2 EPI_HB16CFG3_RDWS_8 Active RDn is 8 EPI clocks 0x3 EPI_HB16CFG3_WRCRE CS2n PSRAM Configuration Register Write 18 19 EPI_HB16CFG3_WRHIGH CS2n WRITE Strobe Polarity 21 22 EPI_HB16CFG3_WRWS CS2n Write Wait States 6 8 EPI_HB16CFG3_WRWS_2 Active WRn is 2 EPI clocks 0x0 EPI_HB16CFG3_WRWS_4 Active WRn is 4 EPI clocks 0x1 EPI_HB16CFG3_WRWS_6 Active WRn is 6 EPI clocks 0x2 EPI_HB16CFG3_WRWS_8 Active WRn is 8 EPI clocks 0x3 HB16CFG4 EPI Host-Bus 16 Configuration 4 0x30C -1 read-write n 0x0 0x0 EPI_HB16CFG4_ALEHIGH CS3n ALE Strobe Polarity 19 20 EPI_HB16CFG4_BURST CS3n Burst Mode 16 17 EPI_HB16CFG4_MODE CS3n Host Bus Sub-Mode 0 2 EPI_HB16CFG4_MODE_ADMUX ADMUX - AD[15:0] 0x0 EPI_HB16CFG4_MODE_AD ADNONMUX - D[15:0] 0x1 EPI_HB16CFG4_RDCRE CS3n PSRAM Configuration Register Read 17 18 EPI_HB16CFG4_RDHIGH CS3n READ Strobe Polarity 20 21 EPI_HB16CFG4_RDWS CS3n Read Wait States 4 6 EPI_HB16CFG4_RDWS_2 Active RDn is 2 EPI clocks 0x0 EPI_HB16CFG4_RDWS_4 Active RDn is 4 EPI clocks 0x1 EPI_HB16CFG4_RDWS_6 Active RDn is 6 EPI clocks 0x2 EPI_HB16CFG4_RDWS_8 Active RDn is 8 EPI clocks 0x3 EPI_HB16CFG4_WRCRE CS3n PSRAM Configuration Register Write 18 19 EPI_HB16CFG4_WRHIGH CS3n WRITE Strobe Polarity 21 22 EPI_HB16CFG4_WRWS CS3n Write Wait States 6 8 EPI_HB16CFG4_WRWS_2 Active WRn is 2 EPI clocks 0x0 EPI_HB16CFG4_WRWS_4 Active WRn is 4 EPI clocks 0x1 EPI_HB16CFG4_WRWS_6 Active WRn is 6 EPI clocks 0x2 EPI_HB16CFG4_WRWS_8 Active WRn is 8 EPI clocks 0x3 HB16TIME EPI Host-Bus 16 Timing Extension 0x310 -1 read-write n 0x0 0x0 EPI_HB16TIME_CAPWIDTH CS0n Inter-transfer Capture Width 12 14 EPI_HB16TIME_IRDYDLY CS0n Input Ready Delay 24 26 EPI_HB16TIME_PSRAMSZ PSRAM Row Size 16 19 EPI_HB16TIME_PSRAMSZ_0 No row size limitation 0x0 EPI_HB16TIME_PSRAMSZ_128B 128 B 0x1 EPI_HB16TIME_PSRAMSZ_256B 256 B 0x2 EPI_HB16TIME_PSRAMSZ_512B 512 B 0x3 EPI_HB16TIME_PSRAMSZ_1KB 1024 B 0x4 EPI_HB16TIME_PSRAMSZ_2KB 2048 B 0x5 EPI_HB16TIME_PSRAMSZ_4KB 4096 B 0x6 EPI_HB16TIME_PSRAMSZ_8KB 8192 B 0x7 EPI_HB16TIME_RDWSM Read Wait State Minus One 0 1 EPI_HB16TIME_WRWSM Write Wait State Minus One 4 5 HB16TIME2 EPI Host-Bus 16 Timing Extension 0x314 -1 read-write n 0x0 0x0 EPI_HB16TIME2_CAPWIDTH CS1n Inter-transfer Capture Width 12 14 EPI_HB16TIME2_IRDYDLY CS1n Input Ready Delay 24 26 EPI_HB16TIME2_PSRAMSZ PSRAM Row Size 16 19 EPI_HB16TIME2_PSRAMSZ_0 No row size limitation 0x0 EPI_HB16TIME2_PSRAMSZ_128B 128 B 0x1 EPI_HB16TIME2_PSRAMSZ_256B 256 B 0x2 EPI_HB16TIME2_PSRAMSZ_512B 512 B 0x3 EPI_HB16TIME2_PSRAMSZ_1KB 1024 B 0x4 EPI_HB16TIME2_PSRAMSZ_2KB 2048 B 0x5 EPI_HB16TIME2_PSRAMSZ_4KB 4096 B 0x6 EPI_HB16TIME2_PSRAMSZ_8KB 8192 B 0x7 EPI_HB16TIME2_RDWSM CS1n Read Wait State Minus One 0 1 EPI_HB16TIME2_WRWSM CS1n Write Wait State Minus One 4 5 HB16TIME3 EPI Host-Bus 16 Timing Extension 0x318 -1 read-write n 0x0 0x0 EPI_HB16TIME3_CAPWIDTH CS2n Inter-transfer Capture Width 12 14 EPI_HB16TIME3_IRDYDLY CS2n Input Ready Delay 24 26 EPI_HB16TIME3_PSRAMSZ PSRAM Row Size 16 19 EPI_HB16TIME3_PSRAMSZ_0 No row size limitation 0x0 EPI_HB16TIME3_PSRAMSZ_128B 128 B 0x1 EPI_HB16TIME3_PSRAMSZ_256B 256 B 0x2 EPI_HB16TIME3_PSRAMSZ_512B 512 B 0x3 EPI_HB16TIME3_PSRAMSZ_1KB 1024 B 0x4 EPI_HB16TIME3_PSRAMSZ_2KB 2048 B 0x5 EPI_HB16TIME3_PSRAMSZ_4KB 4096 B 0x6 EPI_HB16TIME3_PSRAMSZ_8KB 8192 B 0x7 EPI_HB16TIME3_RDWSM CS2n Read Wait State Minus One 0 1 EPI_HB16TIME3_WRWSM CS2n Write Wait State Minus One 4 5 HB16TIME4 EPI Host-Bus 16 Timing Extension 0x31C -1 read-write n 0x0 0x0 EPI_HB16TIME4_CAPWIDTH CS3n Inter-transfer Capture Width 12 14 EPI_HB16TIME4_IRDYDLY CS3n Input Ready Delay 24 26 EPI_HB16TIME4_PSRAMSZ PSRAM Row Size 16 19 EPI_HB16TIME4_PSRAMSZ_0 No row size limitation 0x0 EPI_HB16TIME4_PSRAMSZ_128B 128 B 0x1 EPI_HB16TIME4_PSRAMSZ_256B 256 B 0x2 EPI_HB16TIME4_PSRAMSZ_512B 512 B 0x3 EPI_HB16TIME4_PSRAMSZ_1KB 1024 B 0x4 EPI_HB16TIME4_PSRAMSZ_2KB 2048 B 0x5 EPI_HB16TIME4_PSRAMSZ_4KB 4096 B 0x6 EPI_HB16TIME4_PSRAMSZ_8KB 8192 B 0x7 EPI_HB16TIME4_RDWSM CS3n Read Wait State Minus One 0 1 EPI_HB16TIME4_WRWSM CS3n Write Wait State Minus One 4 5 HB8CFG EPI Host-Bus 8 Configuration 0x10 -1 read-write n 0x0 0x0 EPI_HB8CFG_ALEHIGH ALE Strobe Polarity 19 20 EPI_HB8CFG_CLKGATE Clock Gated 31 32 EPI_HB8CFG_CLKGATEI Clock Gated when Idle 30 31 EPI_HB8CFG_CLKINV Invert Output Clock Enable 29 30 EPI_HB8CFG_IRDYINV Input Ready Invert 27 28 EPI_HB8CFG_MAXWAIT Maximum Wait 8 16 EPI_HB8CFG_MODE Host Bus Sub-Mode 0 2 EPI_HB8CFG_MODE_MUX ADMUX - AD[7:0] 0x0 EPI_HB8CFG_MODE_NMUX ADNONMUX - D[7:0] 0x1 EPI_HB8CFG_MODE_SRAM Continuous Read - D[7:0] 0x2 EPI_HB8CFG_MODE_FIFO XFIFO - D[7:0] 0x3 EPI_HB8CFG_RDHIGH READ Strobe Polarity 20 21 EPI_HB8CFG_RDWS Read Wait States 4 6 EPI_HB8CFG_RDWS_2 Active RDn is 2 EPI clocks 0x0 EPI_HB8CFG_RDWS_4 Active RDn is 4 EPI clocks 0x1 EPI_HB8CFG_RDWS_6 Active RDn is 6 EPI clocks 0x2 EPI_HB8CFG_RDWS_8 Active RDn is 8 EPI clocks 0x3 EPI_HB8CFG_RDYEN Input Ready Enable 28 29 EPI_HB8CFG_WRHIGH WRITE Strobe Polarity 21 22 EPI_HB8CFG_WRWS Write Wait States 6 8 EPI_HB8CFG_WRWS_2 Active WRn is 2 EPI clocks 0x0 EPI_HB8CFG_WRWS_4 Active WRn is 4 EPI clocks 0x1 EPI_HB8CFG_WRWS_6 Active WRn is 6 EPI clocks 0x2 EPI_HB8CFG_WRWS_8 Active WRn is 8 EPI clocks 0x3 EPI_HB8CFG_XFEEN External FIFO EMPTY Enable 22 23 EPI_HB8CFG_XFFEN External FIFO FULL Enable 23 24 HB8CFG2 EPI Host-Bus 8 Configuration 2 0x14 -1 read-write n 0x0 0x0 EPI_HB8CFG2_ALEHIGH CS1n ALE Strobe Polarity 19 20 EPI_HB8CFG2_CSBAUD Chip Select Baud Rate and Multiple Sub-Mode Configuration enable 26 27 EPI_HB8CFG2_CSCFG Chip Select Configuration 24 26 EPI_HB8CFG2_CSCFG_ALE ALE Configuration 0x0 EPI_HB8CFG2_CSCFG_CS CSn Configuration 0x1 EPI_HB8CFG2_CSCFG_DCS Dual CSn Configuration 0x2 EPI_HB8CFG2_CSCFG_ADCS ALE with Dual CSn Configuration 0x3 EPI_HB8CFG2_CSCFGEXT Chip Select Extended Configuration 27 28 EPI_HB8CFG2_MODE CS1n Host Bus Sub-Mode 0 2 EPI_HB8CFG2_MODE_ADMUX ADMUX - AD[7:0] 0x0 EPI_HB8CFG2_MODE_AD ADNONMUX - D[7:0] 0x1 EPI_HB8CFG2_RDHIGH CS1n READ Strobe Polarity 20 21 EPI_HB8CFG2_RDWS CS1n Read Wait States 4 6 EPI_HB8CFG2_RDWS_2 Active RDn is 2 EPI clocks 0x0 EPI_HB8CFG2_RDWS_4 Active RDn is 4 EPI clocks 0x1 EPI_HB8CFG2_RDWS_6 Active RDn is 6 EPI clocks 0x2 EPI_HB8CFG2_RDWS_8 Active RDn is 8 EPI clocks 0x3 EPI_HB8CFG2_WRHIGH CS1n WRITE Strobe Polarity 21 22 EPI_HB8CFG2_WRWS CS1n Write Wait States 6 8 EPI_HB8CFG2_WRWS_2 Active WRn is 2 EPI clocks 0x0 EPI_HB8CFG2_WRWS_4 Active WRn is 4 EPI clocks 0x1 EPI_HB8CFG2_WRWS_6 Active WRn is 6 EPI clocks 0x2 EPI_HB8CFG2_WRWS_8 Active WRn is 8 EPI clocks 0x3 HB8CFG3 EPI Host-Bus 8 Configuration 3 0x308 -1 read-write n 0x0 0x0 EPI_HB8CFG3_ALEHIGH CS2n ALE Strobe Polarity 19 20 EPI_HB8CFG3_MODE CS2n Host Bus Sub-Mode 0 2 EPI_HB8CFG3_MODE_ADMUX ADMUX - AD[7:0] 0x0 EPI_HB8CFG3_MODE_AD ADNONMUX - D[7:0] 0x1 EPI_HB8CFG3_RDHIGH CS2n READ Strobe Polarity 20 21 EPI_HB8CFG3_RDWS CS2n Read Wait States 4 6 EPI_HB8CFG3_RDWS_2 Active RDn is 2 EPI clocks 0x0 EPI_HB8CFG3_RDWS_4 Active RDn is 4 EPI clocks 0x1 EPI_HB8CFG3_RDWS_6 Active RDn is 6 EPI clocks 0x2 EPI_HB8CFG3_RDWS_8 Active RDn is 8 EPI clocks 0x3 EPI_HB8CFG3_WRHIGH CS2n WRITE Strobe Polarity 21 22 EPI_HB8CFG3_WRWS CS2n Write Wait States 6 8 EPI_HB8CFG3_WRWS_2 Active WRn is 2 EPI clocks 0x0 EPI_HB8CFG3_WRWS_4 Active WRn is 4 EPI clocks 0x1 EPI_HB8CFG3_WRWS_6 Active WRn is 6 EPI clocks 0x2 EPI_HB8CFG3_WRWS_8 Active WRn is 8 EPI clocks 0x3 HB8CFG4 EPI Host-Bus 8 Configuration 4 0x30C -1 read-write n 0x0 0x0 EPI_HB8CFG4_ALEHIGH CS3n ALE Strobe Polarity 19 20 EPI_HB8CFG4_MODE CS3n Host Bus Sub-Mode 0 2 EPI_HB8CFG4_MODE_ADMUX ADMUX - AD[7:0] 0x0 EPI_HB8CFG4_MODE_AD ADNONMUX - D[7:0] 0x1 EPI_HB8CFG4_RDHIGH CS2n READ Strobe Polarity 20 21 EPI_HB8CFG4_RDWS CS3n Read Wait States 4 6 EPI_HB8CFG4_RDWS_2 Active RDn is 2 EPI clocks 0x0 EPI_HB8CFG4_RDWS_4 Active RDn is 4 EPI clocks 0x1 EPI_HB8CFG4_RDWS_6 Active RDn is 6 EPI clocks 0x2 EPI_HB8CFG4_RDWS_8 Active RDn is 8 EPI clocks 0x3 EPI_HB8CFG4_WRHIGH CS3n WRITE Strobe Polarity 21 22 EPI_HB8CFG4_WRWS CS3n Write Wait States 6 8 EPI_HB8CFG4_WRWS_2 Active WRn is 2 EPI clocks 0x0 EPI_HB8CFG4_WRWS_4 Active WRn is 4 EPI clocks 0x1 EPI_HB8CFG4_WRWS_6 Active WRn is 6 EPI clocks 0x2 EPI_HB8CFG4_WRWS_8 Active WRn is 8 EPI clocks 0x3 HB8TIME EPI Host-Bus 8 Timing Extension 0x310 -1 read-write n 0x0 0x0 EPI_HB8TIME_CAPWIDTH CS0n Inter-transfer Capture Width 12 14 EPI_HB8TIME_IRDYDLY CS0n Input Ready Delay 24 26 EPI_HB8TIME_RDWSM Read Wait State Minus One 0 1 EPI_HB8TIME_WRWSM Write Wait State Minus One 4 5 HB8TIME2 EPI Host-Bus 8 Timing Extension 0x314 -1 read-write n 0x0 0x0 EPI_HB8TIME2_CAPWIDTH CS1n Inter-transfer Capture Width 12 14 EPI_HB8TIME2_IRDYDLY CS1n Input Ready Delay 24 26 EPI_HB8TIME2_RDWSM CS1n Read Wait State Minus One 0 1 EPI_HB8TIME2_WRWSM CS1n Write Wait State Minus One 4 5 HB8TIME3 EPI Host-Bus 8 Timing Extension 0x318 -1 read-write n 0x0 0x0 EPI_HB8TIME3_CAPWIDTH CS2n Inter-transfer Capture Width 12 14 EPI_HB8TIME3_IRDYDLY CS2n Input Ready Delay 24 26 EPI_HB8TIME3_RDWSM CS2n Read Wait State Minus One 0 1 EPI_HB8TIME3_WRWSM CS2n Write Wait State Minus One 4 5 HB8TIME4 EPI Host-Bus 8 Timing Extension 0x31C -1 read-write n 0x0 0x0 EPI_HB8TIME4_CAPWIDTH CS3n Inter-transfer Capture Width 12 14 EPI_HB8TIME4_IRDYDLY CS3n Input Ready Delay 24 26 EPI_HB8TIME4_RDWSM CS3n Read Wait State Minus One 0 1 EPI_HB8TIME4_WRWSM CS3n Write Wait State Minus One 4 5 HBPSRAM EPI Host-Bus PSRAM 0x360 -1 read-write n 0x0 0x0 EPI_HBPSRAM_CR PSRAM Config Register 0 21 IM EPI Interrupt Mask 0x210 -1 read-write n 0x0 0x0 EPI_IM_DMARDIM Read uDMA Interrupt Mask 3 4 EPI_IM_DMAWRIM Write uDMA Interrupt Mask 4 5 EPI_IM_ERRIM Error Interrupt Mask 0 1 EPI_IM_RDIM Read FIFO Full Interrupt Mask 1 2 EPI_IM_WRIM Write FIFO Empty Interrupt Mask 2 3 MIS EPI Masked Interrupt Status 0x218 -1 read-write n 0x0 0x0 EPI_MIS_DMARDMIS Read uDMA Masked Interrupt Status 3 4 EPI_MIS_DMAWRMIS Write uDMA Masked Interrupt Status 4 5 EPI_MIS_ERRMIS Error Masked Interrupt Status 0 1 EPI_MIS_RDMIS Read Masked Interrupt Status 1 2 EPI_MIS_WRMIS Write Masked Interrupt Status 2 3 RADDR0 EPI Read Address 0 0x24 -1 read-write n 0x0 0x0 EPI_RADDR0_ADDR Current Address 0 32 RADDR1 EPI Read Address 1 0x34 -1 read-write n 0x0 0x0 EPI_RADDR1_ADDR Current Address 0 32 READFIFO0 EPI Read FIFO 0x70 -1 read-write n 0x0 0x0 EPI_READFIFO0_DATA Reads Data 0 32 READFIFO1 EPI Read FIFO Alias 1 0x74 -1 read-write n 0x0 0x0 EPI_READFIFO1_DATA Reads Data 0 32 READFIFO2 EPI Read FIFO Alias 2 0x78 -1 read-write n 0x0 0x0 EPI_READFIFO2_DATA Reads Data 0 32 READFIFO3 EPI Read FIFO Alias 3 0x7C -1 read-write n 0x0 0x0 EPI_READFIFO3_DATA Reads Data 0 32 READFIFO4 EPI Read FIFO Alias 4 0x80 -1 read-write n 0x0 0x0 EPI_READFIFO4_DATA Reads Data 0 32 READFIFO5 EPI Read FIFO Alias 5 0x84 -1 read-write n 0x0 0x0 EPI_READFIFO5_DATA Reads Data 0 32 READFIFO6 EPI Read FIFO Alias 6 0x88 -1 read-write n 0x0 0x0 EPI_READFIFO6_DATA Reads Data 0 32 READFIFO7 EPI Read FIFO Alias 7 0x8C -1 read-write n 0x0 0x0 EPI_READFIFO7_DATA Reads Data 0 32 RFIFOCNT EPI Read FIFO Count 0x6C -1 read-write n 0x0 0x0 EPI_RFIFOCNT_COUNT FIFO Count 0 4 RIS EPI Raw Interrupt Status 0x214 -1 read-write n 0x0 0x0 EPI_RIS_DMARDRIS Read uDMA Raw Interrupt Status 3 4 EPI_RIS_DMAWRRIS Write uDMA Raw Interrupt Status 4 5 EPI_RIS_ERRRIS Error Raw Interrupt Status 0 1 EPI_RIS_RDRIS Read Raw Interrupt Status 1 2 EPI_RIS_WRRIS Write Raw Interrupt Status 2 3 RPSTD0 EPI Non-Blocking Read Data 0 0x28 -1 read-write n 0x0 0x0 EPI_RPSTD0_POSTCNT Post Count 0 13 RPSTD1 EPI Non-Blocking Read Data 1 0x38 -1 read-write n 0x0 0x0 EPI_RPSTD1_POSTCNT Post Count 0 13 RSIZE0 EPI Read Size 0 0x20 -1 read-write n 0x0 0x0 EPI_RSIZE0_SIZE Current Size 0 2 EPI_RSIZE0_SIZE_8BIT Byte (8 bits) 0x1 EPI_RSIZE0_SIZE_16BIT Half-word (16 bits) 0x2 EPI_RSIZE0_SIZE_32BIT Word (32 bits) 0x3 RSIZE1 EPI Read Size 1 0x30 -1 read-write n 0x0 0x0 EPI_RSIZE1_SIZE Current Size 0 2 EPI_RSIZE1_SIZE_8BIT Byte (8 bits) 0x1 EPI_RSIZE1_SIZE_16BIT Half-word (16 bits) 0x2 EPI_RSIZE1_SIZE_32BIT Word (32 bits) 0x3 SDRAMCFG EPI SDRAM Configuration 0x10 -1 read-write n 0x0 0x0 EPI_SDRAMCFG_FREQ EPI Frequency Range 30 32 EPI_SDRAMCFG_FREQ_NONE 0 - 15 MHz 0x0 EPI_SDRAMCFG_FREQ_15MHZ 15 - 30 MHz 0x1 EPI_SDRAMCFG_FREQ_30MHZ 30 - 50 MHz 0x2 EPI_SDRAMCFG_RFSH Refresh Counter 16 27 EPI_SDRAMCFG_SIZE Size of SDRAM 0 2 EPI_SDRAMCFG_SIZE_8MB 64 megabits (8MB) 0x0 EPI_SDRAMCFG_SIZE_16MB 128 megabits (16MB) 0x1 EPI_SDRAMCFG_SIZE_32MB 256 megabits (32MB) 0x2 EPI_SDRAMCFG_SIZE_64MB 512 megabits (64MB) 0x3 EPI_SDRAMCFG_SLEEP Sleep Mode 9 10 STAT EPI Status 0x60 -1 read-write n 0x0 0x0 EPI_STAT_ACTIVE Register Active 0 1 EPI_STAT_INITSEQ Initialization Sequence 6 7 EPI_STAT_NBRBUSY Non-Blocking Read Busy 4 5 EPI_STAT_WBUSY Write Busy 5 6 EPI_STAT_XFEMPTY External FIFO Empty 7 8 EPI_STAT_XFFULL External FIFO Full 8 9 WFIFOCNT EPI Write FIFO Count 0x204 -1 read-write n 0x0 0x0 EPI_WFIFOCNT_WTAV Available Write Transactions 0 3 FLASH_CTRL Register map for FLASH_CTRL peripheral FLASH_CTRL 0x0 0x0 0x1000 registers n 0x1000 0x1000 registers n FLASH_CTRL 29 BOOTCFG Boot Configuration 0x11D0 -1 read-write n 0x0 0x0 FLASH_BOOTCFG_DBG0 Debug Control 0 0 1 FLASH_BOOTCFG_DBG1 Debug Control 1 1 2 FLASH_BOOTCFG_EN Boot GPIO Enable 8 9 FLASH_BOOTCFG_KEY KEY Select 4 5 FLASH_BOOTCFG_NW Not Written 31 32 FLASH_BOOTCFG_PIN Boot GPIO Pin 10 13 FLASH_BOOTCFG_PIN_0 Pin 0 0x0 FLASH_BOOTCFG_PIN_1 Pin 1 0x1 FLASH_BOOTCFG_PIN_2 Pin 2 0x2 FLASH_BOOTCFG_PIN_3 Pin 3 0x3 FLASH_BOOTCFG_PIN_4 Pin 4 0x4 FLASH_BOOTCFG_PIN_5 Pin 5 0x5 FLASH_BOOTCFG_PIN_6 Pin 6 0x6 FLASH_BOOTCFG_PIN_7 Pin 7 0x7 FLASH_BOOTCFG_POL Boot GPIO Polarity 9 10 FLASH_BOOTCFG_PORT Boot GPIO Port 13 16 FLASH_BOOTCFG_PORT_A Port A 0x0 FLASH_BOOTCFG_PORT_B Port B 0x1 FLASH_BOOTCFG_PORT_C Port C 0x2 FLASH_BOOTCFG_PORT_D Port D 0x3 FLASH_BOOTCFG_PORT_E Port E 0x4 FLASH_BOOTCFG_PORT_F Port F 0x5 FLASH_BOOTCFG_PORT_G Port G 0x6 FLASH_BOOTCFG_PORT_H Port H 0x7 CONF Flash Configuration Register 0xFC8 -1 read-write n 0x0 0x0 FLASH_CONF_CLRTV Clear Valid Tags 20 21 FLASH_CONF_FMME Flash Mirror Mode Enable 30 31 FLASH_CONF_FPFOFF Force Prefetch Off 16 17 FLASH_CONF_FPFON Force Prefetch On 17 18 FLASH_CONF_SPFE Single Prefetch Mode Enable 29 30 DMAST Flash DMA Starting Address 0xFD4 -1 read-write n 0x0 0x0 FLASH_DMAST_ADDR Contains the starting address of the flash region accessible by uDMA if the FLASHPP register DFA bit is set 11 29 DMASZ Flash DMA Address Size 0xFD0 -1 read-write n 0x0 0x0 FLASH_DMASZ_SIZE uDMA-accessible Memory Size 0 18 FCIM Flash Controller Interrupt Mask 0x10 -1 read-write n 0x0 0x0 FLASH_FCIM_AMASK Access Interrupt Mask 0 1 FLASH_FCIM_EMASK EEPROM Interrupt Mask 2 3 FLASH_FCIM_ERMASK ERVER Interrupt Mask 11 12 FLASH_FCIM_INVDMASK Invalid Data Interrupt Mask 10 11 FLASH_FCIM_PMASK Programming Interrupt Mask 1 2 FLASH_FCIM_PROGMASK PROGVER Interrupt Mask 13 14 FLASH_FCIM_VOLTMASK VOLT Interrupt Mask 9 10 FCMISC Flash Controller Masked Interrupt Status and Clear 0x14 -1 read-write n 0x0 0x0 FLASH_FCMISC_AMISC Access Masked Interrupt Status and Clear 0 1 FLASH_FCMISC_EMISC EEPROM Masked Interrupt Status and Clear 2 3 FLASH_FCMISC_ERMISC ERVER Masked Interrupt Status and Clear 11 12 FLASH_FCMISC_INVDMISC Invalid Data Masked Interrupt Status and Clear 10 11 FLASH_FCMISC_PMISC Programming Masked Interrupt Status and Clear 1 2 FLASH_FCMISC_PROGMISC PROGVER Masked Interrupt Status and Clear 13 14 FLASH_FCMISC_VOLTMISC VOLT Masked Interrupt Status and Clear 9 10 FCRIS Flash Controller Raw Interrupt Status 0xC -1 read-write n 0x0 0x0 FLASH_FCRIS_ARIS Access Raw Interrupt Status 0 1 FLASH_FCRIS_ERIS EEPROM Raw Interrupt Status 2 3 FLASH_FCRIS_ERRIS Erase Verify Error Raw Interrupt Status 11 12 FLASH_FCRIS_INVDRIS Invalid Data Raw Interrupt Status 10 11 FLASH_FCRIS_PRIS Programming Raw Interrupt Status 1 2 FLASH_FCRIS_PROGRIS Program Verify Error Raw Interrupt Status 13 14 FLASH_FCRIS_VOLTRIS Pump Voltage Raw Interrupt Status 9 10 FLASH_CTRLBOOTCFG Boot Configuration 0x11D0 read-write n 0x0 0x0 FLASH_BOOTCFG_DBG0 Debug Control 0 0 1 FLASH_BOOTCFG_DBG1 Debug Control 1 1 2 FLASH_BOOTCFG_EN Boot GPIO Enable 8 9 FLASH_BOOTCFG_KEY KEY Select 4 5 FLASH_BOOTCFG_NW Not Written 31 32 FLASH_BOOTCFG_PIN Boot GPIO Pin 10 13 FLASH_BOOTCFG_PIN_0 Pin 0 0x0 FLASH_BOOTCFG_PIN_1 Pin 1 0x1 FLASH_BOOTCFG_PIN_2 Pin 2 0x2 FLASH_BOOTCFG_PIN_3 Pin 3 0x3 FLASH_BOOTCFG_PIN_4 Pin 4 0x4 FLASH_BOOTCFG_PIN_5 Pin 5 0x5 FLASH_BOOTCFG_PIN_6 Pin 6 0x6 FLASH_BOOTCFG_PIN_7 Pin 7 0x7 FLASH_BOOTCFG_POL Boot GPIO Polarity 9 10 FLASH_BOOTCFG_PORT Boot GPIO Port 13 16 FLASH_BOOTCFG_PORT_A Port A 0x0 FLASH_BOOTCFG_PORT_B Port B 0x1 FLASH_BOOTCFG_PORT_C Port C 0x2 FLASH_BOOTCFG_PORT_D Port D 0x3 FLASH_BOOTCFG_PORT_E Port E 0x4 FLASH_BOOTCFG_PORT_F Port F 0x5 FLASH_BOOTCFG_PORT_G Port G 0x6 FLASH_BOOTCFG_PORT_H Port H 0x7 FLASH_CTRLCONF Flash Configuration Register 0xFC8 read-write n 0x0 0x0 FLASH_CONF_CLRTV Clear Valid Tags 20 21 FLASH_CONF_FMME Flash Mirror Mode Enable 30 31 FLASH_CONF_FPFOFF Force Prefetch Off 16 17 FLASH_CONF_FPFON Force Prefetch On 17 18 FLASH_CONF_SPFE Single Prefetch Mode Enable 29 30 FLASH_CTRLDMAST Flash DMA Starting Address 0xFD4 read-write n 0x0 0x0 FLASH_DMAST_ADDR Contains the starting address of the flash region accessible by uDMA if the FLASHPP register DFA bit is set 11 29 FLASH_CTRLDMASZ Flash DMA Address Size 0xFD0 read-write n 0x0 0x0 FLASH_DMASZ_SIZE uDMA-accessible Memory Size 0 18 FLASH_CTRLFCIM Flash Controller Interrupt Mask 0x10 read-write n 0x0 0x0 FLASH_FCIM_AMASK Access Interrupt Mask 0 1 FLASH_FCIM_EMASK EEPROM Interrupt Mask 2 3 FLASH_FCIM_ERMASK ERVER Interrupt Mask 11 12 FLASH_FCIM_INVDMASK Invalid Data Interrupt Mask 10 11 FLASH_FCIM_PMASK Programming Interrupt Mask 1 2 FLASH_FCIM_PROGMASK PROGVER Interrupt Mask 13 14 FLASH_FCIM_VOLTMASK VOLT Interrupt Mask 9 10 FLASH_CTRLFCMISC Flash Controller Masked Interrupt Status and Clear 0x14 read-write n 0x0 0x0 FLASH_FCMISC_AMISC Access Masked Interrupt Status and Clear 0 1 FLASH_FCMISC_EMISC EEPROM Masked Interrupt Status and Clear 2 3 FLASH_FCMISC_ERMISC ERVER Masked Interrupt Status and Clear 11 12 FLASH_FCMISC_INVDMISC Invalid Data Masked Interrupt Status and Clear 10 11 FLASH_FCMISC_PMISC Programming Masked Interrupt Status and Clear 1 2 FLASH_FCMISC_PROGMISC PROGVER Masked Interrupt Status and Clear 13 14 FLASH_FCMISC_VOLTMISC VOLT Masked Interrupt Status and Clear 9 10 FLASH_CTRLFCRIS Flash Controller Raw Interrupt Status 0xC read-write n 0x0 0x0 FLASH_FCRIS_ARIS Access Raw Interrupt Status 0 1 FLASH_FCRIS_ERIS EEPROM Raw Interrupt Status 2 3 FLASH_FCRIS_ERRIS Erase Verify Error Raw Interrupt Status 11 12 FLASH_FCRIS_INVDRIS Invalid Data Raw Interrupt Status 10 11 FLASH_FCRIS_PRIS Programming Raw Interrupt Status 1 2 FLASH_FCRIS_PROGRIS Program Verify Error Raw Interrupt Status 13 14 FLASH_FCRIS_VOLTRIS Pump Voltage Raw Interrupt Status 9 10 FLASH_CTRLFLPEKEY Flash Program/Erase Key 0x3C read-write n 0x0 0x0 FLASH_FLPEKEY_PEKEY Key Value 0 16 FLASH_CTRLFMA Flash Memory Address 0x0 read-write n 0x0 0x0 FLASH_FMA_OFFSET Address Offset 0 20 FLASH_CTRLFMC Flash Memory Control 0x8 read-write n 0x0 0x0 FLASH_FMC_COMT Commit Register Value 3 4 FLASH_FMC_ERASE Erase a Page of Flash Memory 1 2 FLASH_FMC_MERASE Mass Erase Flash Memory 2 3 FLASH_FMC_WRITE Write a Word into Flash Memory 0 1 FLASH_FMC_WRKEY FLASH write key 17 32 FLASH_CTRLFMC2 Flash Memory Control 2 0x20 read-write n 0x0 0x0 FLASH_FMC2_WRBUF Buffered Flash Memory Write 0 1 FLASH_CTRLFMD Flash Memory Data 0x4 read-write n 0x0 0x0 FLASH_FMD_DATA Data Value 0 32 FLASH_CTRLFMPPE0 Flash Memory Protection Program Enable 0 0x1400 read-write n 0x0 0x0 FLASH_CTRLFMPPE1 Flash Memory Protection Program Enable 1 0x1404 read-write n 0x0 0x0 FLASH_CTRLFMPPE10 Flash Memory Protection Program Enable 10 0x1428 read-write n 0x0 0x0 FLASH_FMPPE10_PROG_ENABLE Flash Programming Enable 0 32 FLASH_CTRLFMPPE11 Flash Memory Protection Program Enable 11 0x142C read-write n 0x0 0x0 FLASH_FMPPE11_PROG_ENABLE Flash Programming Enable 0 32 FLASH_CTRLFMPPE12 Flash Memory Protection Program Enable 12 0x1430 read-write n 0x0 0x0 FLASH_FMPPE12_PROG_ENABLE Flash Programming Enable 0 32 FLASH_CTRLFMPPE13 Flash Memory Protection Program Enable 13 0x1434 read-write n 0x0 0x0 FLASH_FMPPE13_PROG_ENABLE Flash Programming Enable 0 32 FLASH_CTRLFMPPE14 Flash Memory Protection Program Enable 14 0x1438 read-write n 0x0 0x0 FLASH_FMPPE14_PROG_ENABLE Flash Programming Enable 0 32 FLASH_CTRLFMPPE15 Flash Memory Protection Program Enable 15 0x143C read-write n 0x0 0x0 FLASH_FMPPE15_PROG_ENABLE Flash Programming Enable 0 32 FLASH_CTRLFMPPE2 Flash Memory Protection Program Enable 2 0x1408 read-write n 0x0 0x0 FLASH_CTRLFMPPE3 Flash Memory Protection Program Enable 3 0x140C read-write n 0x0 0x0 FLASH_CTRLFMPPE4 Flash Memory Protection Program Enable 4 0x1410 read-write n 0x0 0x0 FLASH_CTRLFMPPE5 Flash Memory Protection Program Enable 5 0x1414 read-write n 0x0 0x0 FLASH_CTRLFMPPE6 Flash Memory Protection Program Enable 6 0x1418 read-write n 0x0 0x0 FLASH_CTRLFMPPE7 Flash Memory Protection Program Enable 7 0x141C read-write n 0x0 0x0 FLASH_CTRLFMPPE8 Flash Memory Protection Program Enable 8 0x1420 read-write n 0x0 0x0 FLASH_FMPPE8_PROG_ENABLE Flash Programming Enable 0 32 FLASH_CTRLFMPPE9 Flash Memory Protection Program Enable 9 0x1424 read-write n 0x0 0x0 FLASH_FMPPE9_PROG_ENABLE Flash Programming Enable 0 32 FLASH_CTRLFMPRE0 Flash Memory Protection Read Enable 0 0x1200 read-write n 0x0 0x0 FLASH_CTRLFMPRE1 Flash Memory Protection Read Enable 1 0x1204 read-write n 0x0 0x0 FLASH_CTRLFMPRE10 Flash Memory Protection Read Enable 10 0x1228 read-write n 0x0 0x0 FLASH_FMPRE10_READ_ENABLE Flash Read Enable 0 32 FLASH_CTRLFMPRE11 Flash Memory Protection Read Enable 11 0x122C read-write n 0x0 0x0 FLASH_FMPRE11_READ_ENABLE Flash Read Enable 0 32 FLASH_CTRLFMPRE12 Flash Memory Protection Read Enable 12 0x1230 read-write n 0x0 0x0 FLASH_FMPRE12_READ_ENABLE Flash Read Enable 0 32 FLASH_CTRLFMPRE13 Flash Memory Protection Read Enable 13 0x1234 read-write n 0x0 0x0 FLASH_FMPRE13_READ_ENABLE Flash Read Enable 0 32 FLASH_CTRLFMPRE14 Flash Memory Protection Read Enable 14 0x1238 read-write n 0x0 0x0 FLASH_FMPRE14_READ_ENABLE Flash Read Enable 0 32 FLASH_CTRLFMPRE15 Flash Memory Protection Read Enable 15 0x123C read-write n 0x0 0x0 FLASH_FMPRE15_READ_ENABLE Flash Read Enable 0 32 FLASH_CTRLFMPRE2 Flash Memory Protection Read Enable 2 0x1208 read-write n 0x0 0x0 FLASH_CTRLFMPRE3 Flash Memory Protection Read Enable 3 0x120C read-write n 0x0 0x0 FLASH_CTRLFMPRE4 Flash Memory Protection Read Enable 4 0x1210 read-write n 0x0 0x0 FLASH_CTRLFMPRE5 Flash Memory Protection Read Enable 5 0x1214 read-write n 0x0 0x0 FLASH_CTRLFMPRE6 Flash Memory Protection Read Enable 6 0x1218 read-write n 0x0 0x0 FLASH_CTRLFMPRE7 Flash Memory Protection Read Enable 7 0x121C read-write n 0x0 0x0 FLASH_CTRLFMPRE8 Flash Memory Protection Read Enable 8 0x1220 read-write n 0x0 0x0 FLASH_FMPRE8_READ_ENABLE Flash Read Enable 0 32 FLASH_CTRLFMPRE9 Flash Memory Protection Read Enable 9 0x1224 read-write n 0x0 0x0 FLASH_FMPRE9_READ_ENABLE Flash Read Enable 0 32 FLASH_CTRLFWBN Flash Write Buffer n 0x100 read-write n 0x0 0x0 FLASH_FWBN_DATA Data 0 32 FLASH_CTRLFWBVAL Flash Write Buffer Valid 0x30 read-write n 0x0 0x0 FLASH_FWBVAL_FWB Flash Memory Write Buffer 0 32 FLASH_CTRLPP Flash Peripheral Properties 0xFC0 read-write n 0x0 0x0 FLASH_PP_DFA DMA Flash Access 28 29 FLASH_PP_EESS EEPROM Sector Size of the physical bank 19 23 FLASH_PP_EESS_1KB 1 KB 0x0 FLASH_PP_EESS_2KB 2 KB 0x1 FLASH_PP_EESS_4KB 4 KB 0x2 FLASH_PP_EESS_8KB 8 KB 0x3 FLASH_PP_FMM Flash Mirror Mode 29 30 FLASH_PP_MAINSS Flash Sector Size of the physical bank 16 19 FLASH_PP_MAINSS_1KB 1 KB 0x0 FLASH_PP_MAINSS_2KB 2 KB 0x1 FLASH_PP_MAINSS_4KB 4 KB 0x2 FLASH_PP_MAINSS_8KB 8 KB 0x3 FLASH_PP_MAINSS_16KB 16 KB 0x4 FLASH_PP_PFC Prefetch Buffer Mode 30 31 FLASH_PP_SIZE Flash Size 0 16 FLASH_PP_SIZE_1MB 1024 KB of Flash 0x1ff FLASH_CTRLROMSWMAP ROM Software Map 0xFCC read-write n 0x0 0x0 FLASH_ROMSWMAP_SW0EN ROM SW Region 0 Availability 0 2 FLASH_ROMSWMAP_SW0EN_NOTVIS Software region not available to the core 0x0 FLASH_ROMSWMAP_SW0EN_CORE Region available to core 0x1 FLASH_ROMSWMAP_SW1EN ROM SW Region 1 Availability 2 4 FLASH_ROMSWMAP_SW1EN_NOTVIS Software region not available to the core 0x0 FLASH_ROMSWMAP_SW1EN_CORE Region available to core 0x1 FLASH_ROMSWMAP_SW2EN ROM SW Region 2 Availability 4 6 FLASH_ROMSWMAP_SW2EN_NOTVIS Software region not available to the core 0x0 FLASH_ROMSWMAP_SW2EN_CORE Region available to core 0x1 FLASH_ROMSWMAP_SW3EN ROM SW Region 3 Availability 6 8 FLASH_ROMSWMAP_SW3EN_NOTVIS Software region not available to the core 0x0 FLASH_ROMSWMAP_SW3EN_CORE Region available to core 0x1 FLASH_ROMSWMAP_SW4EN ROM SW Region 4 Availability 8 10 FLASH_ROMSWMAP_SW4EN_NOTVIS Software region not available to the core 0x0 FLASH_ROMSWMAP_SW4EN_CORE Region available to core 0x1 FLASH_ROMSWMAP_SW5EN ROM SW Region 5 Availability 10 12 FLASH_ROMSWMAP_SW5EN_NOTVIS Software region not available to the core 0x0 FLASH_ROMSWMAP_SW5EN_CORE Region available to core 0x1 FLASH_ROMSWMAP_SW6EN ROM SW Region 6 Availability 12 14 FLASH_ROMSWMAP_SW6EN_NOTVIS Software region not available to the core 0x0 FLASH_ROMSWMAP_SW6EN_CORE Region available to core 0x1 FLASH_ROMSWMAP_SW7EN ROM SW Region 7 Availability 14 16 FLASH_ROMSWMAP_SW7EN_NOTVIS Software region not available to the core 0x0 FLASH_ROMSWMAP_SW7EN_CORE Region available to core 0x1 FLASH_CTRLRVP Reset Vector Pointer 0x10D4 read-write n 0x0 0x0 FLASH_RVP_RV Reset Vector Pointer Address 0 32 FLASH_CTRLSSIZE SRAM Size 0xFC4 read-write n 0x0 0x0 FLASH_SSIZE_SIZE SRAM Size 0 16 FLASH_SSIZE_SIZE_256KB 256 KB of SRAM 0x3ff FLASH_CTRLUSERREG0 User Register 0 0x11E0 read-write n 0x0 0x0 FLASH_USERREG0_DATA User Data 0 32 FLASH_CTRLUSERREG1 User Register 1 0x11E4 read-write n 0x0 0x0 FLASH_USERREG1_DATA User Data 0 32 FLASH_CTRLUSERREG2 User Register 2 0x11E8 read-write n 0x0 0x0 FLASH_USERREG2_DATA User Data 0 32 FLASH_CTRLUSERREG3 User Register 3 0x11EC read-write n 0x0 0x0 FLASH_USERREG3_DATA User Data 0 32 FLPEKEY Flash Program/Erase Key 0x3C -1 read-write n 0x0 0x0 FLASH_FLPEKEY_PEKEY Key Value 0 16 FMA Flash Memory Address 0x0 -1 read-write n 0x0 0x0 FLASH_FMA_OFFSET Address Offset 0 20 FMC Flash Memory Control 0x8 -1 read-write n 0x0 0x0 FLASH_FMC_COMT Commit Register Value 3 4 FLASH_FMC_ERASE Erase a Page of Flash Memory 1 2 FLASH_FMC_MERASE Mass Erase Flash Memory 2 3 FLASH_FMC_WRITE Write a Word into Flash Memory 0 1 FLASH_FMC_WRKEY FLASH write key 17 32 FMC2 Flash Memory Control 2 0x20 -1 read-write n 0x0 0x0 FLASH_FMC2_WRBUF Buffered Flash Memory Write 0 1 FMD Flash Memory Data 0x4 -1 read-write n 0x0 0x0 FLASH_FMD_DATA Data Value 0 32 FMPPE0 Flash Memory Protection Program Enable 0 0x1400 -1 read-write n 0x0 0x0 FMPPE1 Flash Memory Protection Program Enable 1 0x1404 -1 read-write n 0x0 0x0 FMPPE10 Flash Memory Protection Program Enable 10 0x1428 -1 read-write n 0x0 0x0 FLASH_FMPPE10_PROG_ENABLE Flash Programming Enable 0 32 FMPPE11 Flash Memory Protection Program Enable 11 0x142C -1 read-write n 0x0 0x0 FLASH_FMPPE11_PROG_ENABLE Flash Programming Enable 0 32 FMPPE12 Flash Memory Protection Program Enable 12 0x1430 -1 read-write n 0x0 0x0 FLASH_FMPPE12_PROG_ENABLE Flash Programming Enable 0 32 FMPPE13 Flash Memory Protection Program Enable 13 0x1434 -1 read-write n 0x0 0x0 FLASH_FMPPE13_PROG_ENABLE Flash Programming Enable 0 32 FMPPE14 Flash Memory Protection Program Enable 14 0x1438 -1 read-write n 0x0 0x0 FLASH_FMPPE14_PROG_ENABLE Flash Programming Enable 0 32 FMPPE15 Flash Memory Protection Program Enable 15 0x143C -1 read-write n 0x0 0x0 FLASH_FMPPE15_PROG_ENABLE Flash Programming Enable 0 32 FMPPE2 Flash Memory Protection Program Enable 2 0x1408 -1 read-write n 0x0 0x0 FMPPE3 Flash Memory Protection Program Enable 3 0x140C -1 read-write n 0x0 0x0 FMPPE4 Flash Memory Protection Program Enable 4 0x1410 -1 read-write n 0x0 0x0 FMPPE5 Flash Memory Protection Program Enable 5 0x1414 -1 read-write n 0x0 0x0 FMPPE6 Flash Memory Protection Program Enable 6 0x1418 -1 read-write n 0x0 0x0 FMPPE7 Flash Memory Protection Program Enable 7 0x141C -1 read-write n 0x0 0x0 FMPPE8 Flash Memory Protection Program Enable 8 0x1420 -1 read-write n 0x0 0x0 FLASH_FMPPE8_PROG_ENABLE Flash Programming Enable 0 32 FMPPE9 Flash Memory Protection Program Enable 9 0x1424 -1 read-write n 0x0 0x0 FLASH_FMPPE9_PROG_ENABLE Flash Programming Enable 0 32 FMPRE0 Flash Memory Protection Read Enable 0 0x1200 -1 read-write n 0x0 0x0 FMPRE1 Flash Memory Protection Read Enable 1 0x1204 -1 read-write n 0x0 0x0 FMPRE10 Flash Memory Protection Read Enable 10 0x1228 -1 read-write n 0x0 0x0 FLASH_FMPRE10_READ_ENABLE Flash Read Enable 0 32 FMPRE11 Flash Memory Protection Read Enable 11 0x122C -1 read-write n 0x0 0x0 FLASH_FMPRE11_READ_ENABLE Flash Read Enable 0 32 FMPRE12 Flash Memory Protection Read Enable 12 0x1230 -1 read-write n 0x0 0x0 FLASH_FMPRE12_READ_ENABLE Flash Read Enable 0 32 FMPRE13 Flash Memory Protection Read Enable 13 0x1234 -1 read-write n 0x0 0x0 FLASH_FMPRE13_READ_ENABLE Flash Read Enable 0 32 FMPRE14 Flash Memory Protection Read Enable 14 0x1238 -1 read-write n 0x0 0x0 FLASH_FMPRE14_READ_ENABLE Flash Read Enable 0 32 FMPRE15 Flash Memory Protection Read Enable 15 0x123C -1 read-write n 0x0 0x0 FLASH_FMPRE15_READ_ENABLE Flash Read Enable 0 32 FMPRE2 Flash Memory Protection Read Enable 2 0x1208 -1 read-write n 0x0 0x0 FMPRE3 Flash Memory Protection Read Enable 3 0x120C -1 read-write n 0x0 0x0 FMPRE4 Flash Memory Protection Read Enable 4 0x1210 -1 read-write n 0x0 0x0 FMPRE5 Flash Memory Protection Read Enable 5 0x1214 -1 read-write n 0x0 0x0 FMPRE6 Flash Memory Protection Read Enable 6 0x1218 -1 read-write n 0x0 0x0 FMPRE7 Flash Memory Protection Read Enable 7 0x121C -1 read-write n 0x0 0x0 FMPRE8 Flash Memory Protection Read Enable 8 0x1220 -1 read-write n 0x0 0x0 FLASH_FMPRE8_READ_ENABLE Flash Read Enable 0 32 FMPRE9 Flash Memory Protection Read Enable 9 0x1224 -1 read-write n 0x0 0x0 FLASH_FMPRE9_READ_ENABLE Flash Read Enable 0 32 FWBN Flash Write Buffer n 0x100 -1 read-write n 0x0 0x0 FLASH_FWBN_DATA Data 0 32 FWBVAL Flash Write Buffer Valid 0x30 -1 read-write n 0x0 0x0 FLASH_FWBVAL_FWB Flash Memory Write Buffer 0 32 PP Flash Peripheral Properties 0xFC0 -1 read-write n 0x0 0x0 FLASH_PP_DFA DMA Flash Access 28 29 FLASH_PP_EESS EEPROM Sector Size of the physical bank 19 23 FLASH_PP_EESS_1KB 1 KB 0x0 FLASH_PP_EESS_2KB 2 KB 0x1 FLASH_PP_EESS_4KB 4 KB 0x2 FLASH_PP_EESS_8KB 8 KB 0x3 FLASH_PP_FMM Flash Mirror Mode 29 30 FLASH_PP_MAINSS Flash Sector Size of the physical bank 16 19 FLASH_PP_MAINSS_1KB 1 KB 0x0 FLASH_PP_MAINSS_2KB 2 KB 0x1 FLASH_PP_MAINSS_4KB 4 KB 0x2 FLASH_PP_MAINSS_8KB 8 KB 0x3 FLASH_PP_MAINSS_16KB 16 KB 0x4 FLASH_PP_PFC Prefetch Buffer Mode 30 31 FLASH_PP_SIZE Flash Size 0 16 FLASH_PP_SIZE_1MB 1024 KB of Flash 0x1ff ROMSWMAP ROM Software Map 0xFCC -1 read-write n 0x0 0x0 FLASH_ROMSWMAP_SW0EN ROM SW Region 0 Availability 0 2 FLASH_ROMSWMAP_SW0EN_NOTVIS Software region not available to the core 0x0 FLASH_ROMSWMAP_SW0EN_CORE Region available to core 0x1 FLASH_ROMSWMAP_SW1EN ROM SW Region 1 Availability 2 4 FLASH_ROMSWMAP_SW1EN_NOTVIS Software region not available to the core 0x0 FLASH_ROMSWMAP_SW1EN_CORE Region available to core 0x1 FLASH_ROMSWMAP_SW2EN ROM SW Region 2 Availability 4 6 FLASH_ROMSWMAP_SW2EN_NOTVIS Software region not available to the core 0x0 FLASH_ROMSWMAP_SW2EN_CORE Region available to core 0x1 FLASH_ROMSWMAP_SW3EN ROM SW Region 3 Availability 6 8 FLASH_ROMSWMAP_SW3EN_NOTVIS Software region not available to the core 0x0 FLASH_ROMSWMAP_SW3EN_CORE Region available to core 0x1 FLASH_ROMSWMAP_SW4EN ROM SW Region 4 Availability 8 10 FLASH_ROMSWMAP_SW4EN_NOTVIS Software region not available to the core 0x0 FLASH_ROMSWMAP_SW4EN_CORE Region available to core 0x1 FLASH_ROMSWMAP_SW5EN ROM SW Region 5 Availability 10 12 FLASH_ROMSWMAP_SW5EN_NOTVIS Software region not available to the core 0x0 FLASH_ROMSWMAP_SW5EN_CORE Region available to core 0x1 FLASH_ROMSWMAP_SW6EN ROM SW Region 6 Availability 12 14 FLASH_ROMSWMAP_SW6EN_NOTVIS Software region not available to the core 0x0 FLASH_ROMSWMAP_SW6EN_CORE Region available to core 0x1 FLASH_ROMSWMAP_SW7EN ROM SW Region 7 Availability 14 16 FLASH_ROMSWMAP_SW7EN_NOTVIS Software region not available to the core 0x0 FLASH_ROMSWMAP_SW7EN_CORE Region available to core 0x1 RVP Reset Vector Pointer 0x10D4 -1 read-write n 0x0 0x0 FLASH_RVP_RV Reset Vector Pointer Address 0 32 SSIZE SRAM Size 0xFC4 -1 read-write n 0x0 0x0 FLASH_SSIZE_SIZE SRAM Size 0 16 FLASH_SSIZE_SIZE_256KB 256 KB of SRAM 0x3ff USERREG0 User Register 0 0x11E0 -1 read-write n 0x0 0x0 FLASH_USERREG0_DATA User Data 0 32 USERREG1 User Register 1 0x11E4 -1 read-write n 0x0 0x0 FLASH_USERREG1_DATA User Data 0 32 USERREG2 User Register 2 0x11E8 -1 read-write n 0x0 0x0 FLASH_USERREG2_DATA User Data 0 32 USERREG3 User Register 3 0x11EC -1 read-write n 0x0 0x0 FLASH_USERREG3_DATA User Data 0 32 GPIOA_AHB Register map for GPIOA_AHB peripheral GPIO 0x0 0x0 0x1000 registers n GPIOA 0 ADCCTL GPIO ADC Control 0x530 -1 read-write n 0x0 0x0 AFSEL GPIO Alternate Function Select 0x420 -1 read-write n 0x0 0x0 AMSEL GPIO Analog Mode Select 0x528 -1 read-write n 0x0 0x0 CR GPIO Commit 0x524 -1 read-only n 0x0 0x0 DATA GPIO Data 0x3FC -1 read-write n 0x0 0x0 DEN GPIO Digital Enable 0x51C -1 read-write n 0x0 0x0 DIR GPIO Direction 0x400 -1 read-write n 0x0 0x0 DMACTL GPIO DMA Control 0x534 -1 read-write n 0x0 0x0 DR12R GPIO 12-mA Drive Select 0x53C -1 read-write n 0x0 0x0 GPIO_DR12R_DRV12 Output Pad 12-mA Drive Enable 0 8 GPIO_DR12R_DRV12_12MA The corresponding GPIO pin has 12-mA drive. This encoding is only valid if the GPIOPP EDE bit is set and the appropriate GPIOPC EDM bit field is programmed to 0x3 0x1 DR2R GPIO 2-mA Drive Select 0x500 -1 read-write n 0x0 0x0 DR4R GPIO 4-mA Drive Select 0x504 -1 read-write n 0x0 0x0 DR8R GPIO 8-mA Drive Select 0x508 -1 read-write n 0x0 0x0 GPIOA_AHBADCCTL GPIO ADC Control 0x530 read-write n 0x0 0x0 GPIOA_AHBAFSEL GPIO Alternate Function Select 0x420 read-write n 0x0 0x0 GPIOA_AHBAMSEL GPIO Analog Mode Select 0x528 read-write n 0x0 0x0 GPIOA_AHBCR GPIO Commit 0x524 read-only n 0x0 0x0 GPIOA_AHBDATA GPIO Data 0x3FC read-write n 0x0 0x0 GPIOA_AHBDEN GPIO Digital Enable 0x51C read-write n 0x0 0x0 GPIOA_AHBDIR GPIO Direction 0x400 read-write n 0x0 0x0 GPIOA_AHBDMACTL GPIO DMA Control 0x534 read-write n 0x0 0x0 GPIOA_AHBDR12R GPIO 12-mA Drive Select 0x53C read-write n 0x0 0x0 GPIO_DR12R_DRV12 Output Pad 12-mA Drive Enable 0 8 GPIO_DR12R_DRV12_12MA The corresponding GPIO pin has 12-mA drive. This encoding is only valid if the GPIOPP EDE bit is set and the appropriate GPIOPC EDM bit field is programmed to 0x3 0x1 GPIOA_AHBDR2R GPIO 2-mA Drive Select 0x500 read-write n 0x0 0x0 GPIOA_AHBDR4R GPIO 4-mA Drive Select 0x504 read-write n 0x0 0x0 GPIOA_AHBDR8R GPIO 8-mA Drive Select 0x508 read-write n 0x0 0x0 GPIOA_AHBIBE GPIO Interrupt Both Edges 0x408 read-write n 0x0 0x0 GPIOA_AHBICR GPIO Interrupt Clear 0x41C write-only n 0x0 0x0 GPIO_ICR_DMAIC GPIO uDMA Interrupt Clear 8 9 write-only GPIO_ICR_GPIO GPIO Interrupt Clear 0 8 write-only GPIOA_AHBIEV GPIO Interrupt Event 0x40C read-write n 0x0 0x0 GPIOA_AHBIM GPIO Interrupt Mask 0x410 read-write n 0x0 0x0 GPIO_IM_DMAIME GPIO uDMA Done Interrupt Mask Enable 8 9 GPIO_IM_GPIO GPIO Interrupt Mask Enable 0 8 GPIOA_AHBIS GPIO Interrupt Sense 0x404 read-write n 0x0 0x0 GPIOA_AHBLOCK GPIO Lock 0x520 read-write n 0x0 0x0 GPIO_LOCK GPIO Lock 0 32 GPIO_LOCK_UNLOCKED The GPIOCR register is unlocked and may be modified 0x0 GPIO_LOCK_LOCKED The GPIOCR register is locked and may not be modified 0x1 GPIO_LOCK_KEY Unlocks the GPIO_CR register 0x4c4f434b GPIOA_AHBMIS GPIO Masked Interrupt Status 0x418 read-write n 0x0 0x0 GPIO_MIS_DMAMIS GPIO uDMA Done Masked Interrupt Status 8 9 GPIO_MIS_GPIO GPIO Masked Interrupt Status 0 8 GPIOA_AHBODR GPIO Open Drain Select 0x50C read-write n 0x0 0x0 GPIOA_AHBPC GPIO Peripheral Configuration 0xFC4 read-write n 0x0 0x0 GPIO_PC_EDM0 Extended Drive Mode Bit 0 0 2 GPIO_PC_EDM0_DISABLE Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive Select (GPIODRnR) registers function as normal 0x0 GPIO_PC_EDM0_6MA An additional 6 mA option is provided 0x1 GPIO_PC_EDM0_PLUS2MA A 2 mA driver is always enabled; setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R of GPIODR12R register bit adds an additional 4 mA 0x3 GPIO_PC_EDM1 Extended Drive Mode Bit 1 2 4 GPIO_PC_EDM2 Extended Drive Mode Bit 2 4 6 GPIO_PC_EDM3 Extended Drive Mode Bit 3 6 8 GPIO_PC_EDM4 Extended Drive Mode Bit 4 8 10 GPIO_PC_EDM5 Extended Drive Mode Bit 5 10 12 GPIO_PC_EDM6 Extended Drive Mode Bit 6 12 14 GPIO_PC_EDM7 Extended Drive Mode Bit 7 14 16 GPIOA_AHBPCTL GPIO Port Control 0x52C read-write n 0x0 0x0 GPIOA_AHBPDR GPIO Pull-Down Select 0x514 read-write n 0x0 0x0 GPIOA_AHBPP GPIO Peripheral Property 0xFC0 read-write n 0x0 0x0 GPIO_PP_EDE Extended Drive Enable 0 1 GPIOA_AHBPUR GPIO Pull-Up Select 0x510 read-write n 0x0 0x0 GPIOA_AHBRIS GPIO Raw Interrupt Status 0x414 read-write n 0x0 0x0 GPIO_RIS_DMARIS GPIO uDMA Done Interrupt Raw Status 8 9 GPIO_RIS_GPIO GPIO Interrupt Raw Status 0 8 GPIOA_AHBSI GPIO Select Interrupt 0x538 read-write n 0x0 0x0 GPIO_SI_SUM Summary Interrupt 0 1 GPIOA_AHBSLR GPIO Slew Rate Control Select 0x518 read-write n 0x0 0x0 GPIOA_AHBWAKELVL GPIO Wake Level 0x544 read-write n 0x0 0x0 GPIO_WAKELVL_WAKELVL4 P[4] Wake Level 4 5 GPIOA_AHBWAKEPEN GPIO Wake Pin Enable 0x540 read-write n 0x0 0x0 GPIO_WAKEPEN_WAKEP4 P[4] Wake Enable 4 5 GPIOA_AHBWAKESTAT GPIO Wake Status 0x548 read-write n 0x0 0x0 GPIO_WAKESTAT_STAT4 P[4] Wake Status 4 5 IBE GPIO Interrupt Both Edges 0x408 -1 read-write n 0x0 0x0 ICR GPIO Interrupt Clear 0x41C -1 write-only n 0x0 0x0 GPIO_ICR_DMAIC GPIO uDMA Interrupt Clear 8 9 write-only GPIO_ICR_GPIO GPIO Interrupt Clear 0 8 write-only IEV GPIO Interrupt Event 0x40C -1 read-write n 0x0 0x0 IM GPIO Interrupt Mask 0x410 -1 read-write n 0x0 0x0 GPIO_IM_DMAIME GPIO uDMA Done Interrupt Mask Enable 8 9 GPIO_IM_GPIO GPIO Interrupt Mask Enable 0 8 IS GPIO Interrupt Sense 0x404 -1 read-write n 0x0 0x0 LOCK GPIO Lock 0x520 -1 read-write n 0x0 0x0 GPIO_LOCK GPIO Lock 0 32 GPIO_LOCK_UNLOCKED The GPIOCR register is unlocked and may be modified 0x0 GPIO_LOCK_LOCKED The GPIOCR register is locked and may not be modified 0x1 GPIO_LOCK_KEY Unlocks the GPIO_CR register 0x4c4f434b MIS GPIO Masked Interrupt Status 0x418 -1 read-write n 0x0 0x0 GPIO_MIS_DMAMIS GPIO uDMA Done Masked Interrupt Status 8 9 GPIO_MIS_GPIO GPIO Masked Interrupt Status 0 8 ODR GPIO Open Drain Select 0x50C -1 read-write n 0x0 0x0 PC GPIO Peripheral Configuration 0xFC4 -1 read-write n 0x0 0x0 GPIO_PC_EDM0 Extended Drive Mode Bit 0 0 2 GPIO_PC_EDM0_DISABLE Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive Select (GPIODRnR) registers function as normal 0x0 GPIO_PC_EDM0_6MA An additional 6 mA option is provided 0x1 GPIO_PC_EDM0_PLUS2MA A 2 mA driver is always enabled setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R of GPIODR12R register bit adds an additional 4 mA 0x3 GPIO_PC_EDM1 Extended Drive Mode Bit 1 2 4 GPIO_PC_EDM2 Extended Drive Mode Bit 2 4 6 GPIO_PC_EDM3 Extended Drive Mode Bit 3 6 8 GPIO_PC_EDM4 Extended Drive Mode Bit 4 8 10 GPIO_PC_EDM5 Extended Drive Mode Bit 5 10 12 GPIO_PC_EDM6 Extended Drive Mode Bit 6 12 14 GPIO_PC_EDM7 Extended Drive Mode Bit 7 14 16 PCTL GPIO Port Control 0x52C -1 read-write n 0x0 0x0 PDR GPIO Pull-Down Select 0x514 -1 read-write n 0x0 0x0 PP GPIO Peripheral Property 0xFC0 -1 read-write n 0x0 0x0 GPIO_PP_EDE Extended Drive Enable 0 1 PUR GPIO Pull-Up Select 0x510 -1 read-write n 0x0 0x0 RIS GPIO Raw Interrupt Status 0x414 -1 read-write n 0x0 0x0 GPIO_RIS_DMARIS GPIO uDMA Done Interrupt Raw Status 8 9 GPIO_RIS_GPIO GPIO Interrupt Raw Status 0 8 SI GPIO Select Interrupt 0x538 -1 read-write n 0x0 0x0 GPIO_SI_SUM Summary Interrupt 0 1 SLR GPIO Slew Rate Control Select 0x518 -1 read-write n 0x0 0x0 WAKELVL GPIO Wake Level 0x544 -1 read-write n 0x0 0x0 GPIO_WAKELVL_WAKELVL4 P[4] Wake Level 4 5 WAKEPEN GPIO Wake Pin Enable 0x540 -1 read-write n 0x0 0x0 GPIO_WAKEPEN_WAKEP4 P[4] Wake Enable 4 5 WAKESTAT GPIO Wake Status 0x548 -1 read-write n 0x0 0x0 GPIO_WAKESTAT_STAT4 P[4] Wake Status 4 5 GPIOB_AHB Register map for GPIOA_AHB peripheral GPIO 0x0 0x0 0x1000 registers n GPIOB 1 ADCCTL GPIO ADC Control 0x530 -1 read-write n 0x0 0x0 AFSEL GPIO Alternate Function Select 0x420 -1 read-write n 0x0 0x0 AMSEL GPIO Analog Mode Select 0x528 -1 read-write n 0x0 0x0 CR GPIO Commit 0x524 -1 read-only n 0x0 0x0 DATA GPIO Data 0x3FC -1 read-write n 0x0 0x0 DEN GPIO Digital Enable 0x51C -1 read-write n 0x0 0x0 DIR GPIO Direction 0x400 -1 read-write n 0x0 0x0 DMACTL GPIO DMA Control 0x534 -1 read-write n 0x0 0x0 DR12R GPIO 12-mA Drive Select 0x53C -1 read-write n 0x0 0x0 GPIO_DR12R_DRV12 Output Pad 12-mA Drive Enable 0 8 GPIO_DR12R_DRV12_12MA The corresponding GPIO pin has 12-mA drive. This encoding is only valid if the GPIOPP EDE bit is set and the appropriate GPIOPC EDM bit field is programmed to 0x3 0x1 DR2R GPIO 2-mA Drive Select 0x500 -1 read-write n 0x0 0x0 DR4R GPIO 4-mA Drive Select 0x504 -1 read-write n 0x0 0x0 DR8R GPIO 8-mA Drive Select 0x508 -1 read-write n 0x0 0x0 GPIOA_AHBADCCTL GPIO ADC Control 0x530 read-write n 0x0 0x0 GPIOA_AHBAFSEL GPIO Alternate Function Select 0x420 read-write n 0x0 0x0 GPIOA_AHBAMSEL GPIO Analog Mode Select 0x528 read-write n 0x0 0x0 GPIOA_AHBCR GPIO Commit 0x524 read-only n 0x0 0x0 GPIOA_AHBDATA GPIO Data 0x3FC read-write n 0x0 0x0 GPIOA_AHBDEN GPIO Digital Enable 0x51C read-write n 0x0 0x0 GPIOA_AHBDIR GPIO Direction 0x400 read-write n 0x0 0x0 GPIOA_AHBDMACTL GPIO DMA Control 0x534 read-write n 0x0 0x0 GPIOA_AHBDR12R GPIO 12-mA Drive Select 0x53C read-write n 0x0 0x0 GPIO_DR12R_DRV12 Output Pad 12-mA Drive Enable 0 8 GPIO_DR12R_DRV12_12MA The corresponding GPIO pin has 12-mA drive. This encoding is only valid if the GPIOPP EDE bit is set and the appropriate GPIOPC EDM bit field is programmed to 0x3 0x1 GPIOA_AHBDR2R GPIO 2-mA Drive Select 0x500 read-write n 0x0 0x0 GPIOA_AHBDR4R GPIO 4-mA Drive Select 0x504 read-write n 0x0 0x0 GPIOA_AHBDR8R GPIO 8-mA Drive Select 0x508 read-write n 0x0 0x0 GPIOA_AHBIBE GPIO Interrupt Both Edges 0x408 read-write n 0x0 0x0 GPIOA_AHBICR GPIO Interrupt Clear 0x41C write-only n 0x0 0x0 GPIO_ICR_DMAIC GPIO uDMA Interrupt Clear 8 9 write-only GPIO_ICR_GPIO GPIO Interrupt Clear 0 8 write-only GPIOA_AHBIEV GPIO Interrupt Event 0x40C read-write n 0x0 0x0 GPIOA_AHBIM GPIO Interrupt Mask 0x410 read-write n 0x0 0x0 GPIO_IM_DMAIME GPIO uDMA Done Interrupt Mask Enable 8 9 GPIO_IM_GPIO GPIO Interrupt Mask Enable 0 8 GPIOA_AHBIS GPIO Interrupt Sense 0x404 read-write n 0x0 0x0 GPIOA_AHBLOCK GPIO Lock 0x520 read-write n 0x0 0x0 GPIO_LOCK GPIO Lock 0 32 GPIO_LOCK_UNLOCKED The GPIOCR register is unlocked and may be modified 0x0 GPIO_LOCK_LOCKED The GPIOCR register is locked and may not be modified 0x1 GPIO_LOCK_KEY Unlocks the GPIO_CR register 0x4c4f434b GPIOA_AHBMIS GPIO Masked Interrupt Status 0x418 read-write n 0x0 0x0 GPIO_MIS_DMAMIS GPIO uDMA Done Masked Interrupt Status 8 9 GPIO_MIS_GPIO GPIO Masked Interrupt Status 0 8 GPIOA_AHBODR GPIO Open Drain Select 0x50C read-write n 0x0 0x0 GPIOA_AHBPC GPIO Peripheral Configuration 0xFC4 read-write n 0x0 0x0 GPIO_PC_EDM0 Extended Drive Mode Bit 0 0 2 GPIO_PC_EDM0_DISABLE Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive Select (GPIODRnR) registers function as normal 0x0 GPIO_PC_EDM0_6MA An additional 6 mA option is provided 0x1 GPIO_PC_EDM0_PLUS2MA A 2 mA driver is always enabled; setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R of GPIODR12R register bit adds an additional 4 mA 0x3 GPIO_PC_EDM1 Extended Drive Mode Bit 1 2 4 GPIO_PC_EDM2 Extended Drive Mode Bit 2 4 6 GPIO_PC_EDM3 Extended Drive Mode Bit 3 6 8 GPIO_PC_EDM4 Extended Drive Mode Bit 4 8 10 GPIO_PC_EDM5 Extended Drive Mode Bit 5 10 12 GPIO_PC_EDM6 Extended Drive Mode Bit 6 12 14 GPIO_PC_EDM7 Extended Drive Mode Bit 7 14 16 GPIOA_AHBPCTL GPIO Port Control 0x52C read-write n 0x0 0x0 GPIOA_AHBPDR GPIO Pull-Down Select 0x514 read-write n 0x0 0x0 GPIOA_AHBPP GPIO Peripheral Property 0xFC0 read-write n 0x0 0x0 GPIO_PP_EDE Extended Drive Enable 0 1 GPIOA_AHBPUR GPIO Pull-Up Select 0x510 read-write n 0x0 0x0 GPIOA_AHBRIS GPIO Raw Interrupt Status 0x414 read-write n 0x0 0x0 GPIO_RIS_DMARIS GPIO uDMA Done Interrupt Raw Status 8 9 GPIO_RIS_GPIO GPIO Interrupt Raw Status 0 8 GPIOA_AHBSI GPIO Select Interrupt 0x538 read-write n 0x0 0x0 GPIO_SI_SUM Summary Interrupt 0 1 GPIOA_AHBSLR GPIO Slew Rate Control Select 0x518 read-write n 0x0 0x0 GPIOA_AHBWAKELVL GPIO Wake Level 0x544 read-write n 0x0 0x0 GPIO_WAKELVL_WAKELVL4 P[4] Wake Level 4 5 GPIOA_AHBWAKEPEN GPIO Wake Pin Enable 0x540 read-write n 0x0 0x0 GPIO_WAKEPEN_WAKEP4 P[4] Wake Enable 4 5 GPIOA_AHBWAKESTAT GPIO Wake Status 0x548 read-write n 0x0 0x0 GPIO_WAKESTAT_STAT4 P[4] Wake Status 4 5 IBE GPIO Interrupt Both Edges 0x408 -1 read-write n 0x0 0x0 ICR GPIO Interrupt Clear 0x41C -1 write-only n 0x0 0x0 GPIO_ICR_DMAIC GPIO uDMA Interrupt Clear 8 9 write-only GPIO_ICR_GPIO GPIO Interrupt Clear 0 8 write-only IEV GPIO Interrupt Event 0x40C -1 read-write n 0x0 0x0 IM GPIO Interrupt Mask 0x410 -1 read-write n 0x0 0x0 GPIO_IM_DMAIME GPIO uDMA Done Interrupt Mask Enable 8 9 GPIO_IM_GPIO GPIO Interrupt Mask Enable 0 8 IS GPIO Interrupt Sense 0x404 -1 read-write n 0x0 0x0 LOCK GPIO Lock 0x520 -1 read-write n 0x0 0x0 GPIO_LOCK GPIO Lock 0 32 GPIO_LOCK_UNLOCKED The GPIOCR register is unlocked and may be modified 0x0 GPIO_LOCK_LOCKED The GPIOCR register is locked and may not be modified 0x1 GPIO_LOCK_KEY Unlocks the GPIO_CR register 0x4c4f434b MIS GPIO Masked Interrupt Status 0x418 -1 read-write n 0x0 0x0 GPIO_MIS_DMAMIS GPIO uDMA Done Masked Interrupt Status 8 9 GPIO_MIS_GPIO GPIO Masked Interrupt Status 0 8 ODR GPIO Open Drain Select 0x50C -1 read-write n 0x0 0x0 PC GPIO Peripheral Configuration 0xFC4 -1 read-write n 0x0 0x0 GPIO_PC_EDM0 Extended Drive Mode Bit 0 0 2 GPIO_PC_EDM0_DISABLE Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive Select (GPIODRnR) registers function as normal 0x0 GPIO_PC_EDM0_6MA An additional 6 mA option is provided 0x1 GPIO_PC_EDM0_PLUS2MA A 2 mA driver is always enabled setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R of GPIODR12R register bit adds an additional 4 mA 0x3 GPIO_PC_EDM1 Extended Drive Mode Bit 1 2 4 GPIO_PC_EDM2 Extended Drive Mode Bit 2 4 6 GPIO_PC_EDM3 Extended Drive Mode Bit 3 6 8 GPIO_PC_EDM4 Extended Drive Mode Bit 4 8 10 GPIO_PC_EDM5 Extended Drive Mode Bit 5 10 12 GPIO_PC_EDM6 Extended Drive Mode Bit 6 12 14 GPIO_PC_EDM7 Extended Drive Mode Bit 7 14 16 PCTL GPIO Port Control 0x52C -1 read-write n 0x0 0x0 PDR GPIO Pull-Down Select 0x514 -1 read-write n 0x0 0x0 PP GPIO Peripheral Property 0xFC0 -1 read-write n 0x0 0x0 GPIO_PP_EDE Extended Drive Enable 0 1 PUR GPIO Pull-Up Select 0x510 -1 read-write n 0x0 0x0 RIS GPIO Raw Interrupt Status 0x414 -1 read-write n 0x0 0x0 GPIO_RIS_DMARIS GPIO uDMA Done Interrupt Raw Status 8 9 GPIO_RIS_GPIO GPIO Interrupt Raw Status 0 8 SI GPIO Select Interrupt 0x538 -1 read-write n 0x0 0x0 GPIO_SI_SUM Summary Interrupt 0 1 SLR GPIO Slew Rate Control Select 0x518 -1 read-write n 0x0 0x0 WAKELVL GPIO Wake Level 0x544 -1 read-write n 0x0 0x0 GPIO_WAKELVL_WAKELVL4 P[4] Wake Level 4 5 WAKEPEN GPIO Wake Pin Enable 0x540 -1 read-write n 0x0 0x0 GPIO_WAKEPEN_WAKEP4 P[4] Wake Enable 4 5 WAKESTAT GPIO Wake Status 0x548 -1 read-write n 0x0 0x0 GPIO_WAKESTAT_STAT4 P[4] Wake Status 4 5 GPIOC_AHB Register map for GPIOA_AHB peripheral GPIO 0x0 0x0 0x1000 registers n GPIOC 2 ADCCTL GPIO ADC Control 0x530 -1 read-write n 0x0 0x0 AFSEL GPIO Alternate Function Select 0x420 -1 read-write n 0x0 0x0 AMSEL GPIO Analog Mode Select 0x528 -1 read-write n 0x0 0x0 CR GPIO Commit 0x524 -1 read-only n 0x0 0x0 DATA GPIO Data 0x3FC -1 read-write n 0x0 0x0 DEN GPIO Digital Enable 0x51C -1 read-write n 0x0 0x0 DIR GPIO Direction 0x400 -1 read-write n 0x0 0x0 DMACTL GPIO DMA Control 0x534 -1 read-write n 0x0 0x0 DR12R GPIO 12-mA Drive Select 0x53C -1 read-write n 0x0 0x0 GPIO_DR12R_DRV12 Output Pad 12-mA Drive Enable 0 8 GPIO_DR12R_DRV12_12MA The corresponding GPIO pin has 12-mA drive. This encoding is only valid if the GPIOPP EDE bit is set and the appropriate GPIOPC EDM bit field is programmed to 0x3 0x1 DR2R GPIO 2-mA Drive Select 0x500 -1 read-write n 0x0 0x0 DR4R GPIO 4-mA Drive Select 0x504 -1 read-write n 0x0 0x0 DR8R GPIO 8-mA Drive Select 0x508 -1 read-write n 0x0 0x0 GPIOA_AHBADCCTL GPIO ADC Control 0x530 read-write n 0x0 0x0 GPIOA_AHBAFSEL GPIO Alternate Function Select 0x420 read-write n 0x0 0x0 GPIOA_AHBAMSEL GPIO Analog Mode Select 0x528 read-write n 0x0 0x0 GPIOA_AHBCR GPIO Commit 0x524 read-only n 0x0 0x0 GPIOA_AHBDATA GPIO Data 0x3FC read-write n 0x0 0x0 GPIOA_AHBDEN GPIO Digital Enable 0x51C read-write n 0x0 0x0 GPIOA_AHBDIR GPIO Direction 0x400 read-write n 0x0 0x0 GPIOA_AHBDMACTL GPIO DMA Control 0x534 read-write n 0x0 0x0 GPIOA_AHBDR12R GPIO 12-mA Drive Select 0x53C read-write n 0x0 0x0 GPIO_DR12R_DRV12 Output Pad 12-mA Drive Enable 0 8 GPIO_DR12R_DRV12_12MA The corresponding GPIO pin has 12-mA drive. This encoding is only valid if the GPIOPP EDE bit is set and the appropriate GPIOPC EDM bit field is programmed to 0x3 0x1 GPIOA_AHBDR2R GPIO 2-mA Drive Select 0x500 read-write n 0x0 0x0 GPIOA_AHBDR4R GPIO 4-mA Drive Select 0x504 read-write n 0x0 0x0 GPIOA_AHBDR8R GPIO 8-mA Drive Select 0x508 read-write n 0x0 0x0 GPIOA_AHBIBE GPIO Interrupt Both Edges 0x408 read-write n 0x0 0x0 GPIOA_AHBICR GPIO Interrupt Clear 0x41C write-only n 0x0 0x0 GPIO_ICR_DMAIC GPIO uDMA Interrupt Clear 8 9 write-only GPIO_ICR_GPIO GPIO Interrupt Clear 0 8 write-only GPIOA_AHBIEV GPIO Interrupt Event 0x40C read-write n 0x0 0x0 GPIOA_AHBIM GPIO Interrupt Mask 0x410 read-write n 0x0 0x0 GPIO_IM_DMAIME GPIO uDMA Done Interrupt Mask Enable 8 9 GPIO_IM_GPIO GPIO Interrupt Mask Enable 0 8 GPIOA_AHBIS GPIO Interrupt Sense 0x404 read-write n 0x0 0x0 GPIOA_AHBLOCK GPIO Lock 0x520 read-write n 0x0 0x0 GPIO_LOCK GPIO Lock 0 32 GPIO_LOCK_UNLOCKED The GPIOCR register is unlocked and may be modified 0x0 GPIO_LOCK_LOCKED The GPIOCR register is locked and may not be modified 0x1 GPIO_LOCK_KEY Unlocks the GPIO_CR register 0x4c4f434b GPIOA_AHBMIS GPIO Masked Interrupt Status 0x418 read-write n 0x0 0x0 GPIO_MIS_DMAMIS GPIO uDMA Done Masked Interrupt Status 8 9 GPIO_MIS_GPIO GPIO Masked Interrupt Status 0 8 GPIOA_AHBODR GPIO Open Drain Select 0x50C read-write n 0x0 0x0 GPIOA_AHBPC GPIO Peripheral Configuration 0xFC4 read-write n 0x0 0x0 GPIO_PC_EDM0 Extended Drive Mode Bit 0 0 2 GPIO_PC_EDM0_DISABLE Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive Select (GPIODRnR) registers function as normal 0x0 GPIO_PC_EDM0_6MA An additional 6 mA option is provided 0x1 GPIO_PC_EDM0_PLUS2MA A 2 mA driver is always enabled; setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R of GPIODR12R register bit adds an additional 4 mA 0x3 GPIO_PC_EDM1 Extended Drive Mode Bit 1 2 4 GPIO_PC_EDM2 Extended Drive Mode Bit 2 4 6 GPIO_PC_EDM3 Extended Drive Mode Bit 3 6 8 GPIO_PC_EDM4 Extended Drive Mode Bit 4 8 10 GPIO_PC_EDM5 Extended Drive Mode Bit 5 10 12 GPIO_PC_EDM6 Extended Drive Mode Bit 6 12 14 GPIO_PC_EDM7 Extended Drive Mode Bit 7 14 16 GPIOA_AHBPCTL GPIO Port Control 0x52C read-write n 0x0 0x0 GPIOA_AHBPDR GPIO Pull-Down Select 0x514 read-write n 0x0 0x0 GPIOA_AHBPP GPIO Peripheral Property 0xFC0 read-write n 0x0 0x0 GPIO_PP_EDE Extended Drive Enable 0 1 GPIOA_AHBPUR GPIO Pull-Up Select 0x510 read-write n 0x0 0x0 GPIOA_AHBRIS GPIO Raw Interrupt Status 0x414 read-write n 0x0 0x0 GPIO_RIS_DMARIS GPIO uDMA Done Interrupt Raw Status 8 9 GPIO_RIS_GPIO GPIO Interrupt Raw Status 0 8 GPIOA_AHBSI GPIO Select Interrupt 0x538 read-write n 0x0 0x0 GPIO_SI_SUM Summary Interrupt 0 1 GPIOA_AHBSLR GPIO Slew Rate Control Select 0x518 read-write n 0x0 0x0 GPIOA_AHBWAKELVL GPIO Wake Level 0x544 read-write n 0x0 0x0 GPIO_WAKELVL_WAKELVL4 P[4] Wake Level 4 5 GPIOA_AHBWAKEPEN GPIO Wake Pin Enable 0x540 read-write n 0x0 0x0 GPIO_WAKEPEN_WAKEP4 P[4] Wake Enable 4 5 GPIOA_AHBWAKESTAT GPIO Wake Status 0x548 read-write n 0x0 0x0 GPIO_WAKESTAT_STAT4 P[4] Wake Status 4 5 IBE GPIO Interrupt Both Edges 0x408 -1 read-write n 0x0 0x0 ICR GPIO Interrupt Clear 0x41C -1 write-only n 0x0 0x0 GPIO_ICR_DMAIC GPIO uDMA Interrupt Clear 8 9 write-only GPIO_ICR_GPIO GPIO Interrupt Clear 0 8 write-only IEV GPIO Interrupt Event 0x40C -1 read-write n 0x0 0x0 IM GPIO Interrupt Mask 0x410 -1 read-write n 0x0 0x0 GPIO_IM_DMAIME GPIO uDMA Done Interrupt Mask Enable 8 9 GPIO_IM_GPIO GPIO Interrupt Mask Enable 0 8 IS GPIO Interrupt Sense 0x404 -1 read-write n 0x0 0x0 LOCK GPIO Lock 0x520 -1 read-write n 0x0 0x0 GPIO_LOCK GPIO Lock 0 32 GPIO_LOCK_UNLOCKED The GPIOCR register is unlocked and may be modified 0x0 GPIO_LOCK_LOCKED The GPIOCR register is locked and may not be modified 0x1 GPIO_LOCK_KEY Unlocks the GPIO_CR register 0x4c4f434b MIS GPIO Masked Interrupt Status 0x418 -1 read-write n 0x0 0x0 GPIO_MIS_DMAMIS GPIO uDMA Done Masked Interrupt Status 8 9 GPIO_MIS_GPIO GPIO Masked Interrupt Status 0 8 ODR GPIO Open Drain Select 0x50C -1 read-write n 0x0 0x0 PC GPIO Peripheral Configuration 0xFC4 -1 read-write n 0x0 0x0 GPIO_PC_EDM0 Extended Drive Mode Bit 0 0 2 GPIO_PC_EDM0_DISABLE Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive Select (GPIODRnR) registers function as normal 0x0 GPIO_PC_EDM0_6MA An additional 6 mA option is provided 0x1 GPIO_PC_EDM0_PLUS2MA A 2 mA driver is always enabled setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R of GPIODR12R register bit adds an additional 4 mA 0x3 GPIO_PC_EDM1 Extended Drive Mode Bit 1 2 4 GPIO_PC_EDM2 Extended Drive Mode Bit 2 4 6 GPIO_PC_EDM3 Extended Drive Mode Bit 3 6 8 GPIO_PC_EDM4 Extended Drive Mode Bit 4 8 10 GPIO_PC_EDM5 Extended Drive Mode Bit 5 10 12 GPIO_PC_EDM6 Extended Drive Mode Bit 6 12 14 GPIO_PC_EDM7 Extended Drive Mode Bit 7 14 16 PCTL GPIO Port Control 0x52C -1 read-write n 0x0 0x0 PDR GPIO Pull-Down Select 0x514 -1 read-write n 0x0 0x0 PP GPIO Peripheral Property 0xFC0 -1 read-write n 0x0 0x0 GPIO_PP_EDE Extended Drive Enable 0 1 PUR GPIO Pull-Up Select 0x510 -1 read-write n 0x0 0x0 RIS GPIO Raw Interrupt Status 0x414 -1 read-write n 0x0 0x0 GPIO_RIS_DMARIS GPIO uDMA Done Interrupt Raw Status 8 9 GPIO_RIS_GPIO GPIO Interrupt Raw Status 0 8 SI GPIO Select Interrupt 0x538 -1 read-write n 0x0 0x0 GPIO_SI_SUM Summary Interrupt 0 1 SLR GPIO Slew Rate Control Select 0x518 -1 read-write n 0x0 0x0 WAKELVL GPIO Wake Level 0x544 -1 read-write n 0x0 0x0 GPIO_WAKELVL_WAKELVL4 P[4] Wake Level 4 5 WAKEPEN GPIO Wake Pin Enable 0x540 -1 read-write n 0x0 0x0 GPIO_WAKEPEN_WAKEP4 P[4] Wake Enable 4 5 WAKESTAT GPIO Wake Status 0x548 -1 read-write n 0x0 0x0 GPIO_WAKESTAT_STAT4 P[4] Wake Status 4 5 GPIOD_AHB Register map for GPIOA_AHB peripheral GPIO 0x0 0x0 0x1000 registers n GPIOD 3 ADCCTL GPIO ADC Control 0x530 -1 read-write n 0x0 0x0 AFSEL GPIO Alternate Function Select 0x420 -1 read-write n 0x0 0x0 AMSEL GPIO Analog Mode Select 0x528 -1 read-write n 0x0 0x0 CR GPIO Commit 0x524 -1 read-only n 0x0 0x0 DATA GPIO Data 0x3FC -1 read-write n 0x0 0x0 DEN GPIO Digital Enable 0x51C -1 read-write n 0x0 0x0 DIR GPIO Direction 0x400 -1 read-write n 0x0 0x0 DMACTL GPIO DMA Control 0x534 -1 read-write n 0x0 0x0 DR12R GPIO 12-mA Drive Select 0x53C -1 read-write n 0x0 0x0 GPIO_DR12R_DRV12 Output Pad 12-mA Drive Enable 0 8 GPIO_DR12R_DRV12_12MA The corresponding GPIO pin has 12-mA drive. This encoding is only valid if the GPIOPP EDE bit is set and the appropriate GPIOPC EDM bit field is programmed to 0x3 0x1 DR2R GPIO 2-mA Drive Select 0x500 -1 read-write n 0x0 0x0 DR4R GPIO 4-mA Drive Select 0x504 -1 read-write n 0x0 0x0 DR8R GPIO 8-mA Drive Select 0x508 -1 read-write n 0x0 0x0 GPIOA_AHBADCCTL GPIO ADC Control 0x530 read-write n 0x0 0x0 GPIOA_AHBAFSEL GPIO Alternate Function Select 0x420 read-write n 0x0 0x0 GPIOA_AHBAMSEL GPIO Analog Mode Select 0x528 read-write n 0x0 0x0 GPIOA_AHBCR GPIO Commit 0x524 read-only n 0x0 0x0 GPIOA_AHBDATA GPIO Data 0x3FC read-write n 0x0 0x0 GPIOA_AHBDEN GPIO Digital Enable 0x51C read-write n 0x0 0x0 GPIOA_AHBDIR GPIO Direction 0x400 read-write n 0x0 0x0 GPIOA_AHBDMACTL GPIO DMA Control 0x534 read-write n 0x0 0x0 GPIOA_AHBDR12R GPIO 12-mA Drive Select 0x53C read-write n 0x0 0x0 GPIO_DR12R_DRV12 Output Pad 12-mA Drive Enable 0 8 GPIO_DR12R_DRV12_12MA The corresponding GPIO pin has 12-mA drive. This encoding is only valid if the GPIOPP EDE bit is set and the appropriate GPIOPC EDM bit field is programmed to 0x3 0x1 GPIOA_AHBDR2R GPIO 2-mA Drive Select 0x500 read-write n 0x0 0x0 GPIOA_AHBDR4R GPIO 4-mA Drive Select 0x504 read-write n 0x0 0x0 GPIOA_AHBDR8R GPIO 8-mA Drive Select 0x508 read-write n 0x0 0x0 GPIOA_AHBIBE GPIO Interrupt Both Edges 0x408 read-write n 0x0 0x0 GPIOA_AHBICR GPIO Interrupt Clear 0x41C write-only n 0x0 0x0 GPIO_ICR_DMAIC GPIO uDMA Interrupt Clear 8 9 write-only GPIO_ICR_GPIO GPIO Interrupt Clear 0 8 write-only GPIOA_AHBIEV GPIO Interrupt Event 0x40C read-write n 0x0 0x0 GPIOA_AHBIM GPIO Interrupt Mask 0x410 read-write n 0x0 0x0 GPIO_IM_DMAIME GPIO uDMA Done Interrupt Mask Enable 8 9 GPIO_IM_GPIO GPIO Interrupt Mask Enable 0 8 GPIOA_AHBIS GPIO Interrupt Sense 0x404 read-write n 0x0 0x0 GPIOA_AHBLOCK GPIO Lock 0x520 read-write n 0x0 0x0 GPIO_LOCK GPIO Lock 0 32 GPIO_LOCK_UNLOCKED The GPIOCR register is unlocked and may be modified 0x0 GPIO_LOCK_LOCKED The GPIOCR register is locked and may not be modified 0x1 GPIO_LOCK_KEY Unlocks the GPIO_CR register 0x4c4f434b GPIOA_AHBMIS GPIO Masked Interrupt Status 0x418 read-write n 0x0 0x0 GPIO_MIS_DMAMIS GPIO uDMA Done Masked Interrupt Status 8 9 GPIO_MIS_GPIO GPIO Masked Interrupt Status 0 8 GPIOA_AHBODR GPIO Open Drain Select 0x50C read-write n 0x0 0x0 GPIOA_AHBPC GPIO Peripheral Configuration 0xFC4 read-write n 0x0 0x0 GPIO_PC_EDM0 Extended Drive Mode Bit 0 0 2 GPIO_PC_EDM0_DISABLE Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive Select (GPIODRnR) registers function as normal 0x0 GPIO_PC_EDM0_6MA An additional 6 mA option is provided 0x1 GPIO_PC_EDM0_PLUS2MA A 2 mA driver is always enabled; setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R of GPIODR12R register bit adds an additional 4 mA 0x3 GPIO_PC_EDM1 Extended Drive Mode Bit 1 2 4 GPIO_PC_EDM2 Extended Drive Mode Bit 2 4 6 GPIO_PC_EDM3 Extended Drive Mode Bit 3 6 8 GPIO_PC_EDM4 Extended Drive Mode Bit 4 8 10 GPIO_PC_EDM5 Extended Drive Mode Bit 5 10 12 GPIO_PC_EDM6 Extended Drive Mode Bit 6 12 14 GPIO_PC_EDM7 Extended Drive Mode Bit 7 14 16 GPIOA_AHBPCTL GPIO Port Control 0x52C read-write n 0x0 0x0 GPIOA_AHBPDR GPIO Pull-Down Select 0x514 read-write n 0x0 0x0 GPIOA_AHBPP GPIO Peripheral Property 0xFC0 read-write n 0x0 0x0 GPIO_PP_EDE Extended Drive Enable 0 1 GPIOA_AHBPUR GPIO Pull-Up Select 0x510 read-write n 0x0 0x0 GPIOA_AHBRIS GPIO Raw Interrupt Status 0x414 read-write n 0x0 0x0 GPIO_RIS_DMARIS GPIO uDMA Done Interrupt Raw Status 8 9 GPIO_RIS_GPIO GPIO Interrupt Raw Status 0 8 GPIOA_AHBSI GPIO Select Interrupt 0x538 read-write n 0x0 0x0 GPIO_SI_SUM Summary Interrupt 0 1 GPIOA_AHBSLR GPIO Slew Rate Control Select 0x518 read-write n 0x0 0x0 GPIOA_AHBWAKELVL GPIO Wake Level 0x544 read-write n 0x0 0x0 GPIO_WAKELVL_WAKELVL4 P[4] Wake Level 4 5 GPIOA_AHBWAKEPEN GPIO Wake Pin Enable 0x540 read-write n 0x0 0x0 GPIO_WAKEPEN_WAKEP4 P[4] Wake Enable 4 5 GPIOA_AHBWAKESTAT GPIO Wake Status 0x548 read-write n 0x0 0x0 GPIO_WAKESTAT_STAT4 P[4] Wake Status 4 5 IBE GPIO Interrupt Both Edges 0x408 -1 read-write n 0x0 0x0 ICR GPIO Interrupt Clear 0x41C -1 write-only n 0x0 0x0 GPIO_ICR_DMAIC GPIO uDMA Interrupt Clear 8 9 write-only GPIO_ICR_GPIO GPIO Interrupt Clear 0 8 write-only IEV GPIO Interrupt Event 0x40C -1 read-write n 0x0 0x0 IM GPIO Interrupt Mask 0x410 -1 read-write n 0x0 0x0 GPIO_IM_DMAIME GPIO uDMA Done Interrupt Mask Enable 8 9 GPIO_IM_GPIO GPIO Interrupt Mask Enable 0 8 IS GPIO Interrupt Sense 0x404 -1 read-write n 0x0 0x0 LOCK GPIO Lock 0x520 -1 read-write n 0x0 0x0 GPIO_LOCK GPIO Lock 0 32 GPIO_LOCK_UNLOCKED The GPIOCR register is unlocked and may be modified 0x0 GPIO_LOCK_LOCKED The GPIOCR register is locked and may not be modified 0x1 GPIO_LOCK_KEY Unlocks the GPIO_CR register 0x4c4f434b MIS GPIO Masked Interrupt Status 0x418 -1 read-write n 0x0 0x0 GPIO_MIS_DMAMIS GPIO uDMA Done Masked Interrupt Status 8 9 GPIO_MIS_GPIO GPIO Masked Interrupt Status 0 8 ODR GPIO Open Drain Select 0x50C -1 read-write n 0x0 0x0 PC GPIO Peripheral Configuration 0xFC4 -1 read-write n 0x0 0x0 GPIO_PC_EDM0 Extended Drive Mode Bit 0 0 2 GPIO_PC_EDM0_DISABLE Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive Select (GPIODRnR) registers function as normal 0x0 GPIO_PC_EDM0_6MA An additional 6 mA option is provided 0x1 GPIO_PC_EDM0_PLUS2MA A 2 mA driver is always enabled setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R of GPIODR12R register bit adds an additional 4 mA 0x3 GPIO_PC_EDM1 Extended Drive Mode Bit 1 2 4 GPIO_PC_EDM2 Extended Drive Mode Bit 2 4 6 GPIO_PC_EDM3 Extended Drive Mode Bit 3 6 8 GPIO_PC_EDM4 Extended Drive Mode Bit 4 8 10 GPIO_PC_EDM5 Extended Drive Mode Bit 5 10 12 GPIO_PC_EDM6 Extended Drive Mode Bit 6 12 14 GPIO_PC_EDM7 Extended Drive Mode Bit 7 14 16 PCTL GPIO Port Control 0x52C -1 read-write n 0x0 0x0 PDR GPIO Pull-Down Select 0x514 -1 read-write n 0x0 0x0 PP GPIO Peripheral Property 0xFC0 -1 read-write n 0x0 0x0 GPIO_PP_EDE Extended Drive Enable 0 1 PUR GPIO Pull-Up Select 0x510 -1 read-write n 0x0 0x0 RIS GPIO Raw Interrupt Status 0x414 -1 read-write n 0x0 0x0 GPIO_RIS_DMARIS GPIO uDMA Done Interrupt Raw Status 8 9 GPIO_RIS_GPIO GPIO Interrupt Raw Status 0 8 SI GPIO Select Interrupt 0x538 -1 read-write n 0x0 0x0 GPIO_SI_SUM Summary Interrupt 0 1 SLR GPIO Slew Rate Control Select 0x518 -1 read-write n 0x0 0x0 WAKELVL GPIO Wake Level 0x544 -1 read-write n 0x0 0x0 GPIO_WAKELVL_WAKELVL4 P[4] Wake Level 4 5 WAKEPEN GPIO Wake Pin Enable 0x540 -1 read-write n 0x0 0x0 GPIO_WAKEPEN_WAKEP4 P[4] Wake Enable 4 5 WAKESTAT GPIO Wake Status 0x548 -1 read-write n 0x0 0x0 GPIO_WAKESTAT_STAT4 P[4] Wake Status 4 5 GPIOE_AHB Register map for GPIOA_AHB peripheral GPIO 0x0 0x0 0x1000 registers n GPIOE 4 ADCCTL GPIO ADC Control 0x530 -1 read-write n 0x0 0x0 AFSEL GPIO Alternate Function Select 0x420 -1 read-write n 0x0 0x0 AMSEL GPIO Analog Mode Select 0x528 -1 read-write n 0x0 0x0 CR GPIO Commit 0x524 -1 read-only n 0x0 0x0 DATA GPIO Data 0x3FC -1 read-write n 0x0 0x0 DEN GPIO Digital Enable 0x51C -1 read-write n 0x0 0x0 DIR GPIO Direction 0x400 -1 read-write n 0x0 0x0 DMACTL GPIO DMA Control 0x534 -1 read-write n 0x0 0x0 DR12R GPIO 12-mA Drive Select 0x53C -1 read-write n 0x0 0x0 GPIO_DR12R_DRV12 Output Pad 12-mA Drive Enable 0 8 GPIO_DR12R_DRV12_12MA The corresponding GPIO pin has 12-mA drive. This encoding is only valid if the GPIOPP EDE bit is set and the appropriate GPIOPC EDM bit field is programmed to 0x3 0x1 DR2R GPIO 2-mA Drive Select 0x500 -1 read-write n 0x0 0x0 DR4R GPIO 4-mA Drive Select 0x504 -1 read-write n 0x0 0x0 DR8R GPIO 8-mA Drive Select 0x508 -1 read-write n 0x0 0x0 GPIOA_AHBADCCTL GPIO ADC Control 0x530 read-write n 0x0 0x0 GPIOA_AHBAFSEL GPIO Alternate Function Select 0x420 read-write n 0x0 0x0 GPIOA_AHBAMSEL GPIO Analog Mode Select 0x528 read-write n 0x0 0x0 GPIOA_AHBCR GPIO Commit 0x524 read-only n 0x0 0x0 GPIOA_AHBDATA GPIO Data 0x3FC read-write n 0x0 0x0 GPIOA_AHBDEN GPIO Digital Enable 0x51C read-write n 0x0 0x0 GPIOA_AHBDIR GPIO Direction 0x400 read-write n 0x0 0x0 GPIOA_AHBDMACTL GPIO DMA Control 0x534 read-write n 0x0 0x0 GPIOA_AHBDR12R GPIO 12-mA Drive Select 0x53C read-write n 0x0 0x0 GPIO_DR12R_DRV12 Output Pad 12-mA Drive Enable 0 8 GPIO_DR12R_DRV12_12MA The corresponding GPIO pin has 12-mA drive. This encoding is only valid if the GPIOPP EDE bit is set and the appropriate GPIOPC EDM bit field is programmed to 0x3 0x1 GPIOA_AHBDR2R GPIO 2-mA Drive Select 0x500 read-write n 0x0 0x0 GPIOA_AHBDR4R GPIO 4-mA Drive Select 0x504 read-write n 0x0 0x0 GPIOA_AHBDR8R GPIO 8-mA Drive Select 0x508 read-write n 0x0 0x0 GPIOA_AHBIBE GPIO Interrupt Both Edges 0x408 read-write n 0x0 0x0 GPIOA_AHBICR GPIO Interrupt Clear 0x41C write-only n 0x0 0x0 GPIO_ICR_DMAIC GPIO uDMA Interrupt Clear 8 9 write-only GPIO_ICR_GPIO GPIO Interrupt Clear 0 8 write-only GPIOA_AHBIEV GPIO Interrupt Event 0x40C read-write n 0x0 0x0 GPIOA_AHBIM GPIO Interrupt Mask 0x410 read-write n 0x0 0x0 GPIO_IM_DMAIME GPIO uDMA Done Interrupt Mask Enable 8 9 GPIO_IM_GPIO GPIO Interrupt Mask Enable 0 8 GPIOA_AHBIS GPIO Interrupt Sense 0x404 read-write n 0x0 0x0 GPIOA_AHBLOCK GPIO Lock 0x520 read-write n 0x0 0x0 GPIO_LOCK GPIO Lock 0 32 GPIO_LOCK_UNLOCKED The GPIOCR register is unlocked and may be modified 0x0 GPIO_LOCK_LOCKED The GPIOCR register is locked and may not be modified 0x1 GPIO_LOCK_KEY Unlocks the GPIO_CR register 0x4c4f434b GPIOA_AHBMIS GPIO Masked Interrupt Status 0x418 read-write n 0x0 0x0 GPIO_MIS_DMAMIS GPIO uDMA Done Masked Interrupt Status 8 9 GPIO_MIS_GPIO GPIO Masked Interrupt Status 0 8 GPIOA_AHBODR GPIO Open Drain Select 0x50C read-write n 0x0 0x0 GPIOA_AHBPC GPIO Peripheral Configuration 0xFC4 read-write n 0x0 0x0 GPIO_PC_EDM0 Extended Drive Mode Bit 0 0 2 GPIO_PC_EDM0_DISABLE Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive Select (GPIODRnR) registers function as normal 0x0 GPIO_PC_EDM0_6MA An additional 6 mA option is provided 0x1 GPIO_PC_EDM0_PLUS2MA A 2 mA driver is always enabled; setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R of GPIODR12R register bit adds an additional 4 mA 0x3 GPIO_PC_EDM1 Extended Drive Mode Bit 1 2 4 GPIO_PC_EDM2 Extended Drive Mode Bit 2 4 6 GPIO_PC_EDM3 Extended Drive Mode Bit 3 6 8 GPIO_PC_EDM4 Extended Drive Mode Bit 4 8 10 GPIO_PC_EDM5 Extended Drive Mode Bit 5 10 12 GPIO_PC_EDM6 Extended Drive Mode Bit 6 12 14 GPIO_PC_EDM7 Extended Drive Mode Bit 7 14 16 GPIOA_AHBPCTL GPIO Port Control 0x52C read-write n 0x0 0x0 GPIOA_AHBPDR GPIO Pull-Down Select 0x514 read-write n 0x0 0x0 GPIOA_AHBPP GPIO Peripheral Property 0xFC0 read-write n 0x0 0x0 GPIO_PP_EDE Extended Drive Enable 0 1 GPIOA_AHBPUR GPIO Pull-Up Select 0x510 read-write n 0x0 0x0 GPIOA_AHBRIS GPIO Raw Interrupt Status 0x414 read-write n 0x0 0x0 GPIO_RIS_DMARIS GPIO uDMA Done Interrupt Raw Status 8 9 GPIO_RIS_GPIO GPIO Interrupt Raw Status 0 8 GPIOA_AHBSI GPIO Select Interrupt 0x538 read-write n 0x0 0x0 GPIO_SI_SUM Summary Interrupt 0 1 GPIOA_AHBSLR GPIO Slew Rate Control Select 0x518 read-write n 0x0 0x0 GPIOA_AHBWAKELVL GPIO Wake Level 0x544 read-write n 0x0 0x0 GPIO_WAKELVL_WAKELVL4 P[4] Wake Level 4 5 GPIOA_AHBWAKEPEN GPIO Wake Pin Enable 0x540 read-write n 0x0 0x0 GPIO_WAKEPEN_WAKEP4 P[4] Wake Enable 4 5 GPIOA_AHBWAKESTAT GPIO Wake Status 0x548 read-write n 0x0 0x0 GPIO_WAKESTAT_STAT4 P[4] Wake Status 4 5 IBE GPIO Interrupt Both Edges 0x408 -1 read-write n 0x0 0x0 ICR GPIO Interrupt Clear 0x41C -1 write-only n 0x0 0x0 GPIO_ICR_DMAIC GPIO uDMA Interrupt Clear 8 9 write-only GPIO_ICR_GPIO GPIO Interrupt Clear 0 8 write-only IEV GPIO Interrupt Event 0x40C -1 read-write n 0x0 0x0 IM GPIO Interrupt Mask 0x410 -1 read-write n 0x0 0x0 GPIO_IM_DMAIME GPIO uDMA Done Interrupt Mask Enable 8 9 GPIO_IM_GPIO GPIO Interrupt Mask Enable 0 8 IS GPIO Interrupt Sense 0x404 -1 read-write n 0x0 0x0 LOCK GPIO Lock 0x520 -1 read-write n 0x0 0x0 GPIO_LOCK GPIO Lock 0 32 GPIO_LOCK_UNLOCKED The GPIOCR register is unlocked and may be modified 0x0 GPIO_LOCK_LOCKED The GPIOCR register is locked and may not be modified 0x1 GPIO_LOCK_KEY Unlocks the GPIO_CR register 0x4c4f434b MIS GPIO Masked Interrupt Status 0x418 -1 read-write n 0x0 0x0 GPIO_MIS_DMAMIS GPIO uDMA Done Masked Interrupt Status 8 9 GPIO_MIS_GPIO GPIO Masked Interrupt Status 0 8 ODR GPIO Open Drain Select 0x50C -1 read-write n 0x0 0x0 PC GPIO Peripheral Configuration 0xFC4 -1 read-write n 0x0 0x0 GPIO_PC_EDM0 Extended Drive Mode Bit 0 0 2 GPIO_PC_EDM0_DISABLE Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive Select (GPIODRnR) registers function as normal 0x0 GPIO_PC_EDM0_6MA An additional 6 mA option is provided 0x1 GPIO_PC_EDM0_PLUS2MA A 2 mA driver is always enabled setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R of GPIODR12R register bit adds an additional 4 mA 0x3 GPIO_PC_EDM1 Extended Drive Mode Bit 1 2 4 GPIO_PC_EDM2 Extended Drive Mode Bit 2 4 6 GPIO_PC_EDM3 Extended Drive Mode Bit 3 6 8 GPIO_PC_EDM4 Extended Drive Mode Bit 4 8 10 GPIO_PC_EDM5 Extended Drive Mode Bit 5 10 12 GPIO_PC_EDM6 Extended Drive Mode Bit 6 12 14 GPIO_PC_EDM7 Extended Drive Mode Bit 7 14 16 PCTL GPIO Port Control 0x52C -1 read-write n 0x0 0x0 PDR GPIO Pull-Down Select 0x514 -1 read-write n 0x0 0x0 PP GPIO Peripheral Property 0xFC0 -1 read-write n 0x0 0x0 GPIO_PP_EDE Extended Drive Enable 0 1 PUR GPIO Pull-Up Select 0x510 -1 read-write n 0x0 0x0 RIS GPIO Raw Interrupt Status 0x414 -1 read-write n 0x0 0x0 GPIO_RIS_DMARIS GPIO uDMA Done Interrupt Raw Status 8 9 GPIO_RIS_GPIO GPIO Interrupt Raw Status 0 8 SI GPIO Select Interrupt 0x538 -1 read-write n 0x0 0x0 GPIO_SI_SUM Summary Interrupt 0 1 SLR GPIO Slew Rate Control Select 0x518 -1 read-write n 0x0 0x0 WAKELVL GPIO Wake Level 0x544 -1 read-write n 0x0 0x0 GPIO_WAKELVL_WAKELVL4 P[4] Wake Level 4 5 WAKEPEN GPIO Wake Pin Enable 0x540 -1 read-write n 0x0 0x0 GPIO_WAKEPEN_WAKEP4 P[4] Wake Enable 4 5 WAKESTAT GPIO Wake Status 0x548 -1 read-write n 0x0 0x0 GPIO_WAKESTAT_STAT4 P[4] Wake Status 4 5 GPIOF_AHB Register map for GPIOA_AHB peripheral GPIO 0x0 0x0 0x1000 registers n GPIOF 30 ADCCTL GPIO ADC Control 0x530 -1 read-write n 0x0 0x0 AFSEL GPIO Alternate Function Select 0x420 -1 read-write n 0x0 0x0 AMSEL GPIO Analog Mode Select 0x528 -1 read-write n 0x0 0x0 CR GPIO Commit 0x524 -1 read-only n 0x0 0x0 DATA GPIO Data 0x3FC -1 read-write n 0x0 0x0 DEN GPIO Digital Enable 0x51C -1 read-write n 0x0 0x0 DIR GPIO Direction 0x400 -1 read-write n 0x0 0x0 DMACTL GPIO DMA Control 0x534 -1 read-write n 0x0 0x0 DR12R GPIO 12-mA Drive Select 0x53C -1 read-write n 0x0 0x0 GPIO_DR12R_DRV12 Output Pad 12-mA Drive Enable 0 8 GPIO_DR12R_DRV12_12MA The corresponding GPIO pin has 12-mA drive. This encoding is only valid if the GPIOPP EDE bit is set and the appropriate GPIOPC EDM bit field is programmed to 0x3 0x1 DR2R GPIO 2-mA Drive Select 0x500 -1 read-write n 0x0 0x0 DR4R GPIO 4-mA Drive Select 0x504 -1 read-write n 0x0 0x0 DR8R GPIO 8-mA Drive Select 0x508 -1 read-write n 0x0 0x0 GPIOA_AHBADCCTL GPIO ADC Control 0x530 read-write n 0x0 0x0 GPIOA_AHBAFSEL GPIO Alternate Function Select 0x420 read-write n 0x0 0x0 GPIOA_AHBAMSEL GPIO Analog Mode Select 0x528 read-write n 0x0 0x0 GPIOA_AHBCR GPIO Commit 0x524 read-only n 0x0 0x0 GPIOA_AHBDATA GPIO Data 0x3FC read-write n 0x0 0x0 GPIOA_AHBDEN GPIO Digital Enable 0x51C read-write n 0x0 0x0 GPIOA_AHBDIR GPIO Direction 0x400 read-write n 0x0 0x0 GPIOA_AHBDMACTL GPIO DMA Control 0x534 read-write n 0x0 0x0 GPIOA_AHBDR12R GPIO 12-mA Drive Select 0x53C read-write n 0x0 0x0 GPIO_DR12R_DRV12 Output Pad 12-mA Drive Enable 0 8 GPIO_DR12R_DRV12_12MA The corresponding GPIO pin has 12-mA drive. This encoding is only valid if the GPIOPP EDE bit is set and the appropriate GPIOPC EDM bit field is programmed to 0x3 0x1 GPIOA_AHBDR2R GPIO 2-mA Drive Select 0x500 read-write n 0x0 0x0 GPIOA_AHBDR4R GPIO 4-mA Drive Select 0x504 read-write n 0x0 0x0 GPIOA_AHBDR8R GPIO 8-mA Drive Select 0x508 read-write n 0x0 0x0 GPIOA_AHBIBE GPIO Interrupt Both Edges 0x408 read-write n 0x0 0x0 GPIOA_AHBICR GPIO Interrupt Clear 0x41C write-only n 0x0 0x0 GPIO_ICR_DMAIC GPIO uDMA Interrupt Clear 8 9 write-only GPIO_ICR_GPIO GPIO Interrupt Clear 0 8 write-only GPIOA_AHBIEV GPIO Interrupt Event 0x40C read-write n 0x0 0x0 GPIOA_AHBIM GPIO Interrupt Mask 0x410 read-write n 0x0 0x0 GPIO_IM_DMAIME GPIO uDMA Done Interrupt Mask Enable 8 9 GPIO_IM_GPIO GPIO Interrupt Mask Enable 0 8 GPIOA_AHBIS GPIO Interrupt Sense 0x404 read-write n 0x0 0x0 GPIOA_AHBLOCK GPIO Lock 0x520 read-write n 0x0 0x0 GPIO_LOCK GPIO Lock 0 32 GPIO_LOCK_UNLOCKED The GPIOCR register is unlocked and may be modified 0x0 GPIO_LOCK_LOCKED The GPIOCR register is locked and may not be modified 0x1 GPIO_LOCK_KEY Unlocks the GPIO_CR register 0x4c4f434b GPIOA_AHBMIS GPIO Masked Interrupt Status 0x418 read-write n 0x0 0x0 GPIO_MIS_DMAMIS GPIO uDMA Done Masked Interrupt Status 8 9 GPIO_MIS_GPIO GPIO Masked Interrupt Status 0 8 GPIOA_AHBODR GPIO Open Drain Select 0x50C read-write n 0x0 0x0 GPIOA_AHBPC GPIO Peripheral Configuration 0xFC4 read-write n 0x0 0x0 GPIO_PC_EDM0 Extended Drive Mode Bit 0 0 2 GPIO_PC_EDM0_DISABLE Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive Select (GPIODRnR) registers function as normal 0x0 GPIO_PC_EDM0_6MA An additional 6 mA option is provided 0x1 GPIO_PC_EDM0_PLUS2MA A 2 mA driver is always enabled; setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R of GPIODR12R register bit adds an additional 4 mA 0x3 GPIO_PC_EDM1 Extended Drive Mode Bit 1 2 4 GPIO_PC_EDM2 Extended Drive Mode Bit 2 4 6 GPIO_PC_EDM3 Extended Drive Mode Bit 3 6 8 GPIO_PC_EDM4 Extended Drive Mode Bit 4 8 10 GPIO_PC_EDM5 Extended Drive Mode Bit 5 10 12 GPIO_PC_EDM6 Extended Drive Mode Bit 6 12 14 GPIO_PC_EDM7 Extended Drive Mode Bit 7 14 16 GPIOA_AHBPCTL GPIO Port Control 0x52C read-write n 0x0 0x0 GPIOA_AHBPDR GPIO Pull-Down Select 0x514 read-write n 0x0 0x0 GPIOA_AHBPP GPIO Peripheral Property 0xFC0 read-write n 0x0 0x0 GPIO_PP_EDE Extended Drive Enable 0 1 GPIOA_AHBPUR GPIO Pull-Up Select 0x510 read-write n 0x0 0x0 GPIOA_AHBRIS GPIO Raw Interrupt Status 0x414 read-write n 0x0 0x0 GPIO_RIS_DMARIS GPIO uDMA Done Interrupt Raw Status 8 9 GPIO_RIS_GPIO GPIO Interrupt Raw Status 0 8 GPIOA_AHBSI GPIO Select Interrupt 0x538 read-write n 0x0 0x0 GPIO_SI_SUM Summary Interrupt 0 1 GPIOA_AHBSLR GPIO Slew Rate Control Select 0x518 read-write n 0x0 0x0 GPIOA_AHBWAKELVL GPIO Wake Level 0x544 read-write n 0x0 0x0 GPIO_WAKELVL_WAKELVL4 P[4] Wake Level 4 5 GPIOA_AHBWAKEPEN GPIO Wake Pin Enable 0x540 read-write n 0x0 0x0 GPIO_WAKEPEN_WAKEP4 P[4] Wake Enable 4 5 GPIOA_AHBWAKESTAT GPIO Wake Status 0x548 read-write n 0x0 0x0 GPIO_WAKESTAT_STAT4 P[4] Wake Status 4 5 IBE GPIO Interrupt Both Edges 0x408 -1 read-write n 0x0 0x0 ICR GPIO Interrupt Clear 0x41C -1 write-only n 0x0 0x0 GPIO_ICR_DMAIC GPIO uDMA Interrupt Clear 8 9 write-only GPIO_ICR_GPIO GPIO Interrupt Clear 0 8 write-only IEV GPIO Interrupt Event 0x40C -1 read-write n 0x0 0x0 IM GPIO Interrupt Mask 0x410 -1 read-write n 0x0 0x0 GPIO_IM_DMAIME GPIO uDMA Done Interrupt Mask Enable 8 9 GPIO_IM_GPIO GPIO Interrupt Mask Enable 0 8 IS GPIO Interrupt Sense 0x404 -1 read-write n 0x0 0x0 LOCK GPIO Lock 0x520 -1 read-write n 0x0 0x0 GPIO_LOCK GPIO Lock 0 32 GPIO_LOCK_UNLOCKED The GPIOCR register is unlocked and may be modified 0x0 GPIO_LOCK_LOCKED The GPIOCR register is locked and may not be modified 0x1 GPIO_LOCK_KEY Unlocks the GPIO_CR register 0x4c4f434b MIS GPIO Masked Interrupt Status 0x418 -1 read-write n 0x0 0x0 GPIO_MIS_DMAMIS GPIO uDMA Done Masked Interrupt Status 8 9 GPIO_MIS_GPIO GPIO Masked Interrupt Status 0 8 ODR GPIO Open Drain Select 0x50C -1 read-write n 0x0 0x0 PC GPIO Peripheral Configuration 0xFC4 -1 read-write n 0x0 0x0 GPIO_PC_EDM0 Extended Drive Mode Bit 0 0 2 GPIO_PC_EDM0_DISABLE Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive Select (GPIODRnR) registers function as normal 0x0 GPIO_PC_EDM0_6MA An additional 6 mA option is provided 0x1 GPIO_PC_EDM0_PLUS2MA A 2 mA driver is always enabled setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R of GPIODR12R register bit adds an additional 4 mA 0x3 GPIO_PC_EDM1 Extended Drive Mode Bit 1 2 4 GPIO_PC_EDM2 Extended Drive Mode Bit 2 4 6 GPIO_PC_EDM3 Extended Drive Mode Bit 3 6 8 GPIO_PC_EDM4 Extended Drive Mode Bit 4 8 10 GPIO_PC_EDM5 Extended Drive Mode Bit 5 10 12 GPIO_PC_EDM6 Extended Drive Mode Bit 6 12 14 GPIO_PC_EDM7 Extended Drive Mode Bit 7 14 16 PCTL GPIO Port Control 0x52C -1 read-write n 0x0 0x0 PDR GPIO Pull-Down Select 0x514 -1 read-write n 0x0 0x0 PP GPIO Peripheral Property 0xFC0 -1 read-write n 0x0 0x0 GPIO_PP_EDE Extended Drive Enable 0 1 PUR GPIO Pull-Up Select 0x510 -1 read-write n 0x0 0x0 RIS GPIO Raw Interrupt Status 0x414 -1 read-write n 0x0 0x0 GPIO_RIS_DMARIS GPIO uDMA Done Interrupt Raw Status 8 9 GPIO_RIS_GPIO GPIO Interrupt Raw Status 0 8 SI GPIO Select Interrupt 0x538 -1 read-write n 0x0 0x0 GPIO_SI_SUM Summary Interrupt 0 1 SLR GPIO Slew Rate Control Select 0x518 -1 read-write n 0x0 0x0 WAKELVL GPIO Wake Level 0x544 -1 read-write n 0x0 0x0 GPIO_WAKELVL_WAKELVL4 P[4] Wake Level 4 5 WAKEPEN GPIO Wake Pin Enable 0x540 -1 read-write n 0x0 0x0 GPIO_WAKEPEN_WAKEP4 P[4] Wake Enable 4 5 WAKESTAT GPIO Wake Status 0x548 -1 read-write n 0x0 0x0 GPIO_WAKESTAT_STAT4 P[4] Wake Status 4 5 GPIOG_AHB Register map for GPIOA_AHB peripheral GPIO 0x0 0x0 0x1000 registers n GPIOG 31 ADCCTL GPIO ADC Control 0x530 -1 read-write n 0x0 0x0 AFSEL GPIO Alternate Function Select 0x420 -1 read-write n 0x0 0x0 AMSEL GPIO Analog Mode Select 0x528 -1 read-write n 0x0 0x0 CR GPIO Commit 0x524 -1 read-only n 0x0 0x0 DATA GPIO Data 0x3FC -1 read-write n 0x0 0x0 DEN GPIO Digital Enable 0x51C -1 read-write n 0x0 0x0 DIR GPIO Direction 0x400 -1 read-write n 0x0 0x0 DMACTL GPIO DMA Control 0x534 -1 read-write n 0x0 0x0 DR12R GPIO 12-mA Drive Select 0x53C -1 read-write n 0x0 0x0 GPIO_DR12R_DRV12 Output Pad 12-mA Drive Enable 0 8 GPIO_DR12R_DRV12_12MA The corresponding GPIO pin has 12-mA drive. This encoding is only valid if the GPIOPP EDE bit is set and the appropriate GPIOPC EDM bit field is programmed to 0x3 0x1 DR2R GPIO 2-mA Drive Select 0x500 -1 read-write n 0x0 0x0 DR4R GPIO 4-mA Drive Select 0x504 -1 read-write n 0x0 0x0 DR8R GPIO 8-mA Drive Select 0x508 -1 read-write n 0x0 0x0 GPIOA_AHBADCCTL GPIO ADC Control 0x530 read-write n 0x0 0x0 GPIOA_AHBAFSEL GPIO Alternate Function Select 0x420 read-write n 0x0 0x0 GPIOA_AHBAMSEL GPIO Analog Mode Select 0x528 read-write n 0x0 0x0 GPIOA_AHBCR GPIO Commit 0x524 read-only n 0x0 0x0 GPIOA_AHBDATA GPIO Data 0x3FC read-write n 0x0 0x0 GPIOA_AHBDEN GPIO Digital Enable 0x51C read-write n 0x0 0x0 GPIOA_AHBDIR GPIO Direction 0x400 read-write n 0x0 0x0 GPIOA_AHBDMACTL GPIO DMA Control 0x534 read-write n 0x0 0x0 GPIOA_AHBDR12R GPIO 12-mA Drive Select 0x53C read-write n 0x0 0x0 GPIO_DR12R_DRV12 Output Pad 12-mA Drive Enable 0 8 GPIO_DR12R_DRV12_12MA The corresponding GPIO pin has 12-mA drive. This encoding is only valid if the GPIOPP EDE bit is set and the appropriate GPIOPC EDM bit field is programmed to 0x3 0x1 GPIOA_AHBDR2R GPIO 2-mA Drive Select 0x500 read-write n 0x0 0x0 GPIOA_AHBDR4R GPIO 4-mA Drive Select 0x504 read-write n 0x0 0x0 GPIOA_AHBDR8R GPIO 8-mA Drive Select 0x508 read-write n 0x0 0x0 GPIOA_AHBIBE GPIO Interrupt Both Edges 0x408 read-write n 0x0 0x0 GPIOA_AHBICR GPIO Interrupt Clear 0x41C write-only n 0x0 0x0 GPIO_ICR_DMAIC GPIO uDMA Interrupt Clear 8 9 write-only GPIO_ICR_GPIO GPIO Interrupt Clear 0 8 write-only GPIOA_AHBIEV GPIO Interrupt Event 0x40C read-write n 0x0 0x0 GPIOA_AHBIM GPIO Interrupt Mask 0x410 read-write n 0x0 0x0 GPIO_IM_DMAIME GPIO uDMA Done Interrupt Mask Enable 8 9 GPIO_IM_GPIO GPIO Interrupt Mask Enable 0 8 GPIOA_AHBIS GPIO Interrupt Sense 0x404 read-write n 0x0 0x0 GPIOA_AHBLOCK GPIO Lock 0x520 read-write n 0x0 0x0 GPIO_LOCK GPIO Lock 0 32 GPIO_LOCK_UNLOCKED The GPIOCR register is unlocked and may be modified 0x0 GPIO_LOCK_LOCKED The GPIOCR register is locked and may not be modified 0x1 GPIO_LOCK_KEY Unlocks the GPIO_CR register 0x4c4f434b GPIOA_AHBMIS GPIO Masked Interrupt Status 0x418 read-write n 0x0 0x0 GPIO_MIS_DMAMIS GPIO uDMA Done Masked Interrupt Status 8 9 GPIO_MIS_GPIO GPIO Masked Interrupt Status 0 8 GPIOA_AHBODR GPIO Open Drain Select 0x50C read-write n 0x0 0x0 GPIOA_AHBPC GPIO Peripheral Configuration 0xFC4 read-write n 0x0 0x0 GPIO_PC_EDM0 Extended Drive Mode Bit 0 0 2 GPIO_PC_EDM0_DISABLE Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive Select (GPIODRnR) registers function as normal 0x0 GPIO_PC_EDM0_6MA An additional 6 mA option is provided 0x1 GPIO_PC_EDM0_PLUS2MA A 2 mA driver is always enabled; setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R of GPIODR12R register bit adds an additional 4 mA 0x3 GPIO_PC_EDM1 Extended Drive Mode Bit 1 2 4 GPIO_PC_EDM2 Extended Drive Mode Bit 2 4 6 GPIO_PC_EDM3 Extended Drive Mode Bit 3 6 8 GPIO_PC_EDM4 Extended Drive Mode Bit 4 8 10 GPIO_PC_EDM5 Extended Drive Mode Bit 5 10 12 GPIO_PC_EDM6 Extended Drive Mode Bit 6 12 14 GPIO_PC_EDM7 Extended Drive Mode Bit 7 14 16 GPIOA_AHBPCTL GPIO Port Control 0x52C read-write n 0x0 0x0 GPIOA_AHBPDR GPIO Pull-Down Select 0x514 read-write n 0x0 0x0 GPIOA_AHBPP GPIO Peripheral Property 0xFC0 read-write n 0x0 0x0 GPIO_PP_EDE Extended Drive Enable 0 1 GPIOA_AHBPUR GPIO Pull-Up Select 0x510 read-write n 0x0 0x0 GPIOA_AHBRIS GPIO Raw Interrupt Status 0x414 read-write n 0x0 0x0 GPIO_RIS_DMARIS GPIO uDMA Done Interrupt Raw Status 8 9 GPIO_RIS_GPIO GPIO Interrupt Raw Status 0 8 GPIOA_AHBSI GPIO Select Interrupt 0x538 read-write n 0x0 0x0 GPIO_SI_SUM Summary Interrupt 0 1 GPIOA_AHBSLR GPIO Slew Rate Control Select 0x518 read-write n 0x0 0x0 GPIOA_AHBWAKELVL GPIO Wake Level 0x544 read-write n 0x0 0x0 GPIO_WAKELVL_WAKELVL4 P[4] Wake Level 4 5 GPIOA_AHBWAKEPEN GPIO Wake Pin Enable 0x540 read-write n 0x0 0x0 GPIO_WAKEPEN_WAKEP4 P[4] Wake Enable 4 5 GPIOA_AHBWAKESTAT GPIO Wake Status 0x548 read-write n 0x0 0x0 GPIO_WAKESTAT_STAT4 P[4] Wake Status 4 5 IBE GPIO Interrupt Both Edges 0x408 -1 read-write n 0x0 0x0 ICR GPIO Interrupt Clear 0x41C -1 write-only n 0x0 0x0 GPIO_ICR_DMAIC GPIO uDMA Interrupt Clear 8 9 write-only GPIO_ICR_GPIO GPIO Interrupt Clear 0 8 write-only IEV GPIO Interrupt Event 0x40C -1 read-write n 0x0 0x0 IM GPIO Interrupt Mask 0x410 -1 read-write n 0x0 0x0 GPIO_IM_DMAIME GPIO uDMA Done Interrupt Mask Enable 8 9 GPIO_IM_GPIO GPIO Interrupt Mask Enable 0 8 IS GPIO Interrupt Sense 0x404 -1 read-write n 0x0 0x0 LOCK GPIO Lock 0x520 -1 read-write n 0x0 0x0 GPIO_LOCK GPIO Lock 0 32 GPIO_LOCK_UNLOCKED The GPIOCR register is unlocked and may be modified 0x0 GPIO_LOCK_LOCKED The GPIOCR register is locked and may not be modified 0x1 GPIO_LOCK_KEY Unlocks the GPIO_CR register 0x4c4f434b MIS GPIO Masked Interrupt Status 0x418 -1 read-write n 0x0 0x0 GPIO_MIS_DMAMIS GPIO uDMA Done Masked Interrupt Status 8 9 GPIO_MIS_GPIO GPIO Masked Interrupt Status 0 8 ODR GPIO Open Drain Select 0x50C -1 read-write n 0x0 0x0 PC GPIO Peripheral Configuration 0xFC4 -1 read-write n 0x0 0x0 GPIO_PC_EDM0 Extended Drive Mode Bit 0 0 2 GPIO_PC_EDM0_DISABLE Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive Select (GPIODRnR) registers function as normal 0x0 GPIO_PC_EDM0_6MA An additional 6 mA option is provided 0x1 GPIO_PC_EDM0_PLUS2MA A 2 mA driver is always enabled setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R of GPIODR12R register bit adds an additional 4 mA 0x3 GPIO_PC_EDM1 Extended Drive Mode Bit 1 2 4 GPIO_PC_EDM2 Extended Drive Mode Bit 2 4 6 GPIO_PC_EDM3 Extended Drive Mode Bit 3 6 8 GPIO_PC_EDM4 Extended Drive Mode Bit 4 8 10 GPIO_PC_EDM5 Extended Drive Mode Bit 5 10 12 GPIO_PC_EDM6 Extended Drive Mode Bit 6 12 14 GPIO_PC_EDM7 Extended Drive Mode Bit 7 14 16 PCTL GPIO Port Control 0x52C -1 read-write n 0x0 0x0 PDR GPIO Pull-Down Select 0x514 -1 read-write n 0x0 0x0 PP GPIO Peripheral Property 0xFC0 -1 read-write n 0x0 0x0 GPIO_PP_EDE Extended Drive Enable 0 1 PUR GPIO Pull-Up Select 0x510 -1 read-write n 0x0 0x0 RIS GPIO Raw Interrupt Status 0x414 -1 read-write n 0x0 0x0 GPIO_RIS_DMARIS GPIO uDMA Done Interrupt Raw Status 8 9 GPIO_RIS_GPIO GPIO Interrupt Raw Status 0 8 SI GPIO Select Interrupt 0x538 -1 read-write n 0x0 0x0 GPIO_SI_SUM Summary Interrupt 0 1 SLR GPIO Slew Rate Control Select 0x518 -1 read-write n 0x0 0x0 WAKELVL GPIO Wake Level 0x544 -1 read-write n 0x0 0x0 GPIO_WAKELVL_WAKELVL4 P[4] Wake Level 4 5 WAKEPEN GPIO Wake Pin Enable 0x540 -1 read-write n 0x0 0x0 GPIO_WAKEPEN_WAKEP4 P[4] Wake Enable 4 5 WAKESTAT GPIO Wake Status 0x548 -1 read-write n 0x0 0x0 GPIO_WAKESTAT_STAT4 P[4] Wake Status 4 5 GPIOH_AHB Register map for GPIOA_AHB peripheral GPIO 0x0 0x0 0x1000 registers n GPIOH 32 ADCCTL GPIO ADC Control 0x530 -1 read-write n 0x0 0x0 AFSEL GPIO Alternate Function Select 0x420 -1 read-write n 0x0 0x0 AMSEL GPIO Analog Mode Select 0x528 -1 read-write n 0x0 0x0 CR GPIO Commit 0x524 -1 read-only n 0x0 0x0 DATA GPIO Data 0x3FC -1 read-write n 0x0 0x0 DEN GPIO Digital Enable 0x51C -1 read-write n 0x0 0x0 DIR GPIO Direction 0x400 -1 read-write n 0x0 0x0 DMACTL GPIO DMA Control 0x534 -1 read-write n 0x0 0x0 DR12R GPIO 12-mA Drive Select 0x53C -1 read-write n 0x0 0x0 GPIO_DR12R_DRV12 Output Pad 12-mA Drive Enable 0 8 GPIO_DR12R_DRV12_12MA The corresponding GPIO pin has 12-mA drive. This encoding is only valid if the GPIOPP EDE bit is set and the appropriate GPIOPC EDM bit field is programmed to 0x3 0x1 DR2R GPIO 2-mA Drive Select 0x500 -1 read-write n 0x0 0x0 DR4R GPIO 4-mA Drive Select 0x504 -1 read-write n 0x0 0x0 DR8R GPIO 8-mA Drive Select 0x508 -1 read-write n 0x0 0x0 GPIOA_AHBADCCTL GPIO ADC Control 0x530 read-write n 0x0 0x0 GPIOA_AHBAFSEL GPIO Alternate Function Select 0x420 read-write n 0x0 0x0 GPIOA_AHBAMSEL GPIO Analog Mode Select 0x528 read-write n 0x0 0x0 GPIOA_AHBCR GPIO Commit 0x524 read-only n 0x0 0x0 GPIOA_AHBDATA GPIO Data 0x3FC read-write n 0x0 0x0 GPIOA_AHBDEN GPIO Digital Enable 0x51C read-write n 0x0 0x0 GPIOA_AHBDIR GPIO Direction 0x400 read-write n 0x0 0x0 GPIOA_AHBDMACTL GPIO DMA Control 0x534 read-write n 0x0 0x0 GPIOA_AHBDR12R GPIO 12-mA Drive Select 0x53C read-write n 0x0 0x0 GPIO_DR12R_DRV12 Output Pad 12-mA Drive Enable 0 8 GPIO_DR12R_DRV12_12MA The corresponding GPIO pin has 12-mA drive. This encoding is only valid if the GPIOPP EDE bit is set and the appropriate GPIOPC EDM bit field is programmed to 0x3 0x1 GPIOA_AHBDR2R GPIO 2-mA Drive Select 0x500 read-write n 0x0 0x0 GPIOA_AHBDR4R GPIO 4-mA Drive Select 0x504 read-write n 0x0 0x0 GPIOA_AHBDR8R GPIO 8-mA Drive Select 0x508 read-write n 0x0 0x0 GPIOA_AHBIBE GPIO Interrupt Both Edges 0x408 read-write n 0x0 0x0 GPIOA_AHBICR GPIO Interrupt Clear 0x41C write-only n 0x0 0x0 GPIO_ICR_DMAIC GPIO uDMA Interrupt Clear 8 9 write-only GPIO_ICR_GPIO GPIO Interrupt Clear 0 8 write-only GPIOA_AHBIEV GPIO Interrupt Event 0x40C read-write n 0x0 0x0 GPIOA_AHBIM GPIO Interrupt Mask 0x410 read-write n 0x0 0x0 GPIO_IM_DMAIME GPIO uDMA Done Interrupt Mask Enable 8 9 GPIO_IM_GPIO GPIO Interrupt Mask Enable 0 8 GPIOA_AHBIS GPIO Interrupt Sense 0x404 read-write n 0x0 0x0 GPIOA_AHBLOCK GPIO Lock 0x520 read-write n 0x0 0x0 GPIO_LOCK GPIO Lock 0 32 GPIO_LOCK_UNLOCKED The GPIOCR register is unlocked and may be modified 0x0 GPIO_LOCK_LOCKED The GPIOCR register is locked and may not be modified 0x1 GPIO_LOCK_KEY Unlocks the GPIO_CR register 0x4c4f434b GPIOA_AHBMIS GPIO Masked Interrupt Status 0x418 read-write n 0x0 0x0 GPIO_MIS_DMAMIS GPIO uDMA Done Masked Interrupt Status 8 9 GPIO_MIS_GPIO GPIO Masked Interrupt Status 0 8 GPIOA_AHBODR GPIO Open Drain Select 0x50C read-write n 0x0 0x0 GPIOA_AHBPC GPIO Peripheral Configuration 0xFC4 read-write n 0x0 0x0 GPIO_PC_EDM0 Extended Drive Mode Bit 0 0 2 GPIO_PC_EDM0_DISABLE Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive Select (GPIODRnR) registers function as normal 0x0 GPIO_PC_EDM0_6MA An additional 6 mA option is provided 0x1 GPIO_PC_EDM0_PLUS2MA A 2 mA driver is always enabled; setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R of GPIODR12R register bit adds an additional 4 mA 0x3 GPIO_PC_EDM1 Extended Drive Mode Bit 1 2 4 GPIO_PC_EDM2 Extended Drive Mode Bit 2 4 6 GPIO_PC_EDM3 Extended Drive Mode Bit 3 6 8 GPIO_PC_EDM4 Extended Drive Mode Bit 4 8 10 GPIO_PC_EDM5 Extended Drive Mode Bit 5 10 12 GPIO_PC_EDM6 Extended Drive Mode Bit 6 12 14 GPIO_PC_EDM7 Extended Drive Mode Bit 7 14 16 GPIOA_AHBPCTL GPIO Port Control 0x52C read-write n 0x0 0x0 GPIOA_AHBPDR GPIO Pull-Down Select 0x514 read-write n 0x0 0x0 GPIOA_AHBPP GPIO Peripheral Property 0xFC0 read-write n 0x0 0x0 GPIO_PP_EDE Extended Drive Enable 0 1 GPIOA_AHBPUR GPIO Pull-Up Select 0x510 read-write n 0x0 0x0 GPIOA_AHBRIS GPIO Raw Interrupt Status 0x414 read-write n 0x0 0x0 GPIO_RIS_DMARIS GPIO uDMA Done Interrupt Raw Status 8 9 GPIO_RIS_GPIO GPIO Interrupt Raw Status 0 8 GPIOA_AHBSI GPIO Select Interrupt 0x538 read-write n 0x0 0x0 GPIO_SI_SUM Summary Interrupt 0 1 GPIOA_AHBSLR GPIO Slew Rate Control Select 0x518 read-write n 0x0 0x0 GPIOA_AHBWAKELVL GPIO Wake Level 0x544 read-write n 0x0 0x0 GPIO_WAKELVL_WAKELVL4 P[4] Wake Level 4 5 GPIOA_AHBWAKEPEN GPIO Wake Pin Enable 0x540 read-write n 0x0 0x0 GPIO_WAKEPEN_WAKEP4 P[4] Wake Enable 4 5 GPIOA_AHBWAKESTAT GPIO Wake Status 0x548 read-write n 0x0 0x0 GPIO_WAKESTAT_STAT4 P[4] Wake Status 4 5 IBE GPIO Interrupt Both Edges 0x408 -1 read-write n 0x0 0x0 ICR GPIO Interrupt Clear 0x41C -1 write-only n 0x0 0x0 GPIO_ICR_DMAIC GPIO uDMA Interrupt Clear 8 9 write-only GPIO_ICR_GPIO GPIO Interrupt Clear 0 8 write-only IEV GPIO Interrupt Event 0x40C -1 read-write n 0x0 0x0 IM GPIO Interrupt Mask 0x410 -1 read-write n 0x0 0x0 GPIO_IM_DMAIME GPIO uDMA Done Interrupt Mask Enable 8 9 GPIO_IM_GPIO GPIO Interrupt Mask Enable 0 8 IS GPIO Interrupt Sense 0x404 -1 read-write n 0x0 0x0 LOCK GPIO Lock 0x520 -1 read-write n 0x0 0x0 GPIO_LOCK GPIO Lock 0 32 GPIO_LOCK_UNLOCKED The GPIOCR register is unlocked and may be modified 0x0 GPIO_LOCK_LOCKED The GPIOCR register is locked and may not be modified 0x1 GPIO_LOCK_KEY Unlocks the GPIO_CR register 0x4c4f434b MIS GPIO Masked Interrupt Status 0x418 -1 read-write n 0x0 0x0 GPIO_MIS_DMAMIS GPIO uDMA Done Masked Interrupt Status 8 9 GPIO_MIS_GPIO GPIO Masked Interrupt Status 0 8 ODR GPIO Open Drain Select 0x50C -1 read-write n 0x0 0x0 PC GPIO Peripheral Configuration 0xFC4 -1 read-write n 0x0 0x0 GPIO_PC_EDM0 Extended Drive Mode Bit 0 0 2 GPIO_PC_EDM0_DISABLE Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive Select (GPIODRnR) registers function as normal 0x0 GPIO_PC_EDM0_6MA An additional 6 mA option is provided 0x1 GPIO_PC_EDM0_PLUS2MA A 2 mA driver is always enabled setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R of GPIODR12R register bit adds an additional 4 mA 0x3 GPIO_PC_EDM1 Extended Drive Mode Bit 1 2 4 GPIO_PC_EDM2 Extended Drive Mode Bit 2 4 6 GPIO_PC_EDM3 Extended Drive Mode Bit 3 6 8 GPIO_PC_EDM4 Extended Drive Mode Bit 4 8 10 GPIO_PC_EDM5 Extended Drive Mode Bit 5 10 12 GPIO_PC_EDM6 Extended Drive Mode Bit 6 12 14 GPIO_PC_EDM7 Extended Drive Mode Bit 7 14 16 PCTL GPIO Port Control 0x52C -1 read-write n 0x0 0x0 PDR GPIO Pull-Down Select 0x514 -1 read-write n 0x0 0x0 PP GPIO Peripheral Property 0xFC0 -1 read-write n 0x0 0x0 GPIO_PP_EDE Extended Drive Enable 0 1 PUR GPIO Pull-Up Select 0x510 -1 read-write n 0x0 0x0 RIS GPIO Raw Interrupt Status 0x414 -1 read-write n 0x0 0x0 GPIO_RIS_DMARIS GPIO uDMA Done Interrupt Raw Status 8 9 GPIO_RIS_GPIO GPIO Interrupt Raw Status 0 8 SI GPIO Select Interrupt 0x538 -1 read-write n 0x0 0x0 GPIO_SI_SUM Summary Interrupt 0 1 SLR GPIO Slew Rate Control Select 0x518 -1 read-write n 0x0 0x0 WAKELVL GPIO Wake Level 0x544 -1 read-write n 0x0 0x0 GPIO_WAKELVL_WAKELVL4 P[4] Wake Level 4 5 WAKEPEN GPIO Wake Pin Enable 0x540 -1 read-write n 0x0 0x0 GPIO_WAKEPEN_WAKEP4 P[4] Wake Enable 4 5 WAKESTAT GPIO Wake Status 0x548 -1 read-write n 0x0 0x0 GPIO_WAKESTAT_STAT4 P[4] Wake Status 4 5 GPIOJ_AHB Register map for GPIOA_AHB peripheral GPIO 0x0 0x0 0x1000 registers n GPIOJ 51 ADCCTL GPIO ADC Control 0x530 -1 read-write n 0x0 0x0 AFSEL GPIO Alternate Function Select 0x420 -1 read-write n 0x0 0x0 AMSEL GPIO Analog Mode Select 0x528 -1 read-write n 0x0 0x0 CR GPIO Commit 0x524 -1 read-only n 0x0 0x0 DATA GPIO Data 0x3FC -1 read-write n 0x0 0x0 DEN GPIO Digital Enable 0x51C -1 read-write n 0x0 0x0 DIR GPIO Direction 0x400 -1 read-write n 0x0 0x0 DMACTL GPIO DMA Control 0x534 -1 read-write n 0x0 0x0 DR12R GPIO 12-mA Drive Select 0x53C -1 read-write n 0x0 0x0 GPIO_DR12R_DRV12 Output Pad 12-mA Drive Enable 0 8 GPIO_DR12R_DRV12_12MA The corresponding GPIO pin has 12-mA drive. This encoding is only valid if the GPIOPP EDE bit is set and the appropriate GPIOPC EDM bit field is programmed to 0x3 0x1 DR2R GPIO 2-mA Drive Select 0x500 -1 read-write n 0x0 0x0 DR4R GPIO 4-mA Drive Select 0x504 -1 read-write n 0x0 0x0 DR8R GPIO 8-mA Drive Select 0x508 -1 read-write n 0x0 0x0 GPIOA_AHBADCCTL GPIO ADC Control 0x530 read-write n 0x0 0x0 GPIOA_AHBAFSEL GPIO Alternate Function Select 0x420 read-write n 0x0 0x0 GPIOA_AHBAMSEL GPIO Analog Mode Select 0x528 read-write n 0x0 0x0 GPIOA_AHBCR GPIO Commit 0x524 read-only n 0x0 0x0 GPIOA_AHBDATA GPIO Data 0x3FC read-write n 0x0 0x0 GPIOA_AHBDEN GPIO Digital Enable 0x51C read-write n 0x0 0x0 GPIOA_AHBDIR GPIO Direction 0x400 read-write n 0x0 0x0 GPIOA_AHBDMACTL GPIO DMA Control 0x534 read-write n 0x0 0x0 GPIOA_AHBDR12R GPIO 12-mA Drive Select 0x53C read-write n 0x0 0x0 GPIO_DR12R_DRV12 Output Pad 12-mA Drive Enable 0 8 GPIO_DR12R_DRV12_12MA The corresponding GPIO pin has 12-mA drive. This encoding is only valid if the GPIOPP EDE bit is set and the appropriate GPIOPC EDM bit field is programmed to 0x3 0x1 GPIOA_AHBDR2R GPIO 2-mA Drive Select 0x500 read-write n 0x0 0x0 GPIOA_AHBDR4R GPIO 4-mA Drive Select 0x504 read-write n 0x0 0x0 GPIOA_AHBDR8R GPIO 8-mA Drive Select 0x508 read-write n 0x0 0x0 GPIOA_AHBIBE GPIO Interrupt Both Edges 0x408 read-write n 0x0 0x0 GPIOA_AHBICR GPIO Interrupt Clear 0x41C write-only n 0x0 0x0 GPIO_ICR_DMAIC GPIO uDMA Interrupt Clear 8 9 write-only GPIO_ICR_GPIO GPIO Interrupt Clear 0 8 write-only GPIOA_AHBIEV GPIO Interrupt Event 0x40C read-write n 0x0 0x0 GPIOA_AHBIM GPIO Interrupt Mask 0x410 read-write n 0x0 0x0 GPIO_IM_DMAIME GPIO uDMA Done Interrupt Mask Enable 8 9 GPIO_IM_GPIO GPIO Interrupt Mask Enable 0 8 GPIOA_AHBIS GPIO Interrupt Sense 0x404 read-write n 0x0 0x0 GPIOA_AHBLOCK GPIO Lock 0x520 read-write n 0x0 0x0 GPIO_LOCK GPIO Lock 0 32 GPIO_LOCK_UNLOCKED The GPIOCR register is unlocked and may be modified 0x0 GPIO_LOCK_LOCKED The GPIOCR register is locked and may not be modified 0x1 GPIO_LOCK_KEY Unlocks the GPIO_CR register 0x4c4f434b GPIOA_AHBMIS GPIO Masked Interrupt Status 0x418 read-write n 0x0 0x0 GPIO_MIS_DMAMIS GPIO uDMA Done Masked Interrupt Status 8 9 GPIO_MIS_GPIO GPIO Masked Interrupt Status 0 8 GPIOA_AHBODR GPIO Open Drain Select 0x50C read-write n 0x0 0x0 GPIOA_AHBPC GPIO Peripheral Configuration 0xFC4 read-write n 0x0 0x0 GPIO_PC_EDM0 Extended Drive Mode Bit 0 0 2 GPIO_PC_EDM0_DISABLE Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive Select (GPIODRnR) registers function as normal 0x0 GPIO_PC_EDM0_6MA An additional 6 mA option is provided 0x1 GPIO_PC_EDM0_PLUS2MA A 2 mA driver is always enabled; setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R of GPIODR12R register bit adds an additional 4 mA 0x3 GPIO_PC_EDM1 Extended Drive Mode Bit 1 2 4 GPIO_PC_EDM2 Extended Drive Mode Bit 2 4 6 GPIO_PC_EDM3 Extended Drive Mode Bit 3 6 8 GPIO_PC_EDM4 Extended Drive Mode Bit 4 8 10 GPIO_PC_EDM5 Extended Drive Mode Bit 5 10 12 GPIO_PC_EDM6 Extended Drive Mode Bit 6 12 14 GPIO_PC_EDM7 Extended Drive Mode Bit 7 14 16 GPIOA_AHBPCTL GPIO Port Control 0x52C read-write n 0x0 0x0 GPIOA_AHBPDR GPIO Pull-Down Select 0x514 read-write n 0x0 0x0 GPIOA_AHBPP GPIO Peripheral Property 0xFC0 read-write n 0x0 0x0 GPIO_PP_EDE Extended Drive Enable 0 1 GPIOA_AHBPUR GPIO Pull-Up Select 0x510 read-write n 0x0 0x0 GPIOA_AHBRIS GPIO Raw Interrupt Status 0x414 read-write n 0x0 0x0 GPIO_RIS_DMARIS GPIO uDMA Done Interrupt Raw Status 8 9 GPIO_RIS_GPIO GPIO Interrupt Raw Status 0 8 GPIOA_AHBSI GPIO Select Interrupt 0x538 read-write n 0x0 0x0 GPIO_SI_SUM Summary Interrupt 0 1 GPIOA_AHBSLR GPIO Slew Rate Control Select 0x518 read-write n 0x0 0x0 GPIOA_AHBWAKELVL GPIO Wake Level 0x544 read-write n 0x0 0x0 GPIO_WAKELVL_WAKELVL4 P[4] Wake Level 4 5 GPIOA_AHBWAKEPEN GPIO Wake Pin Enable 0x540 read-write n 0x0 0x0 GPIO_WAKEPEN_WAKEP4 P[4] Wake Enable 4 5 GPIOA_AHBWAKESTAT GPIO Wake Status 0x548 read-write n 0x0 0x0 GPIO_WAKESTAT_STAT4 P[4] Wake Status 4 5 IBE GPIO Interrupt Both Edges 0x408 -1 read-write n 0x0 0x0 ICR GPIO Interrupt Clear 0x41C -1 write-only n 0x0 0x0 GPIO_ICR_DMAIC GPIO uDMA Interrupt Clear 8 9 write-only GPIO_ICR_GPIO GPIO Interrupt Clear 0 8 write-only IEV GPIO Interrupt Event 0x40C -1 read-write n 0x0 0x0 IM GPIO Interrupt Mask 0x410 -1 read-write n 0x0 0x0 GPIO_IM_DMAIME GPIO uDMA Done Interrupt Mask Enable 8 9 GPIO_IM_GPIO GPIO Interrupt Mask Enable 0 8 IS GPIO Interrupt Sense 0x404 -1 read-write n 0x0 0x0 LOCK GPIO Lock 0x520 -1 read-write n 0x0 0x0 GPIO_LOCK GPIO Lock 0 32 GPIO_LOCK_UNLOCKED The GPIOCR register is unlocked and may be modified 0x0 GPIO_LOCK_LOCKED The GPIOCR register is locked and may not be modified 0x1 GPIO_LOCK_KEY Unlocks the GPIO_CR register 0x4c4f434b MIS GPIO Masked Interrupt Status 0x418 -1 read-write n 0x0 0x0 GPIO_MIS_DMAMIS GPIO uDMA Done Masked Interrupt Status 8 9 GPIO_MIS_GPIO GPIO Masked Interrupt Status 0 8 ODR GPIO Open Drain Select 0x50C -1 read-write n 0x0 0x0 PC GPIO Peripheral Configuration 0xFC4 -1 read-write n 0x0 0x0 GPIO_PC_EDM0 Extended Drive Mode Bit 0 0 2 GPIO_PC_EDM0_DISABLE Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive Select (GPIODRnR) registers function as normal 0x0 GPIO_PC_EDM0_6MA An additional 6 mA option is provided 0x1 GPIO_PC_EDM0_PLUS2MA A 2 mA driver is always enabled setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R of GPIODR12R register bit adds an additional 4 mA 0x3 GPIO_PC_EDM1 Extended Drive Mode Bit 1 2 4 GPIO_PC_EDM2 Extended Drive Mode Bit 2 4 6 GPIO_PC_EDM3 Extended Drive Mode Bit 3 6 8 GPIO_PC_EDM4 Extended Drive Mode Bit 4 8 10 GPIO_PC_EDM5 Extended Drive Mode Bit 5 10 12 GPIO_PC_EDM6 Extended Drive Mode Bit 6 12 14 GPIO_PC_EDM7 Extended Drive Mode Bit 7 14 16 PCTL GPIO Port Control 0x52C -1 read-write n 0x0 0x0 PDR GPIO Pull-Down Select 0x514 -1 read-write n 0x0 0x0 PP GPIO Peripheral Property 0xFC0 -1 read-write n 0x0 0x0 GPIO_PP_EDE Extended Drive Enable 0 1 PUR GPIO Pull-Up Select 0x510 -1 read-write n 0x0 0x0 RIS GPIO Raw Interrupt Status 0x414 -1 read-write n 0x0 0x0 GPIO_RIS_DMARIS GPIO uDMA Done Interrupt Raw Status 8 9 GPIO_RIS_GPIO GPIO Interrupt Raw Status 0 8 SI GPIO Select Interrupt 0x538 -1 read-write n 0x0 0x0 GPIO_SI_SUM Summary Interrupt 0 1 SLR GPIO Slew Rate Control Select 0x518 -1 read-write n 0x0 0x0 WAKELVL GPIO Wake Level 0x544 -1 read-write n 0x0 0x0 GPIO_WAKELVL_WAKELVL4 P[4] Wake Level 4 5 WAKEPEN GPIO Wake Pin Enable 0x540 -1 read-write n 0x0 0x0 GPIO_WAKEPEN_WAKEP4 P[4] Wake Enable 4 5 WAKESTAT GPIO Wake Status 0x548 -1 read-write n 0x0 0x0 GPIO_WAKESTAT_STAT4 P[4] Wake Status 4 5 GPIOK Register map for GPIOA_AHB peripheral GPIO 0x0 0x0 0x1000 registers n GPIOK 52 ADCCTL GPIO ADC Control 0x530 -1 read-write n 0x0 0x0 AFSEL GPIO Alternate Function Select 0x420 -1 read-write n 0x0 0x0 AMSEL GPIO Analog Mode Select 0x528 -1 read-write n 0x0 0x0 CR GPIO Commit 0x524 -1 read-only n 0x0 0x0 DATA GPIO Data 0x3FC -1 read-write n 0x0 0x0 DEN GPIO Digital Enable 0x51C -1 read-write n 0x0 0x0 DIR GPIO Direction 0x400 -1 read-write n 0x0 0x0 DMACTL GPIO DMA Control 0x534 -1 read-write n 0x0 0x0 DR12R GPIO 12-mA Drive Select 0x53C -1 read-write n 0x0 0x0 GPIO_DR12R_DRV12 Output Pad 12-mA Drive Enable 0 8 GPIO_DR12R_DRV12_12MA The corresponding GPIO pin has 12-mA drive. This encoding is only valid if the GPIOPP EDE bit is set and the appropriate GPIOPC EDM bit field is programmed to 0x3 0x1 DR2R GPIO 2-mA Drive Select 0x500 -1 read-write n 0x0 0x0 DR4R GPIO 4-mA Drive Select 0x504 -1 read-write n 0x0 0x0 DR8R GPIO 8-mA Drive Select 0x508 -1 read-write n 0x0 0x0 GPIOA_AHBADCCTL GPIO ADC Control 0x530 read-write n 0x0 0x0 GPIOA_AHBAFSEL GPIO Alternate Function Select 0x420 read-write n 0x0 0x0 GPIOA_AHBAMSEL GPIO Analog Mode Select 0x528 read-write n 0x0 0x0 GPIOA_AHBCR GPIO Commit 0x524 read-only n 0x0 0x0 GPIOA_AHBDATA GPIO Data 0x3FC read-write n 0x0 0x0 GPIOA_AHBDEN GPIO Digital Enable 0x51C read-write n 0x0 0x0 GPIOA_AHBDIR GPIO Direction 0x400 read-write n 0x0 0x0 GPIOA_AHBDMACTL GPIO DMA Control 0x534 read-write n 0x0 0x0 GPIOA_AHBDR12R GPIO 12-mA Drive Select 0x53C read-write n 0x0 0x0 GPIO_DR12R_DRV12 Output Pad 12-mA Drive Enable 0 8 GPIO_DR12R_DRV12_12MA The corresponding GPIO pin has 12-mA drive. This encoding is only valid if the GPIOPP EDE bit is set and the appropriate GPIOPC EDM bit field is programmed to 0x3 0x1 GPIOA_AHBDR2R GPIO 2-mA Drive Select 0x500 read-write n 0x0 0x0 GPIOA_AHBDR4R GPIO 4-mA Drive Select 0x504 read-write n 0x0 0x0 GPIOA_AHBDR8R GPIO 8-mA Drive Select 0x508 read-write n 0x0 0x0 GPIOA_AHBIBE GPIO Interrupt Both Edges 0x408 read-write n 0x0 0x0 GPIOA_AHBICR GPIO Interrupt Clear 0x41C write-only n 0x0 0x0 GPIO_ICR_DMAIC GPIO uDMA Interrupt Clear 8 9 write-only GPIO_ICR_GPIO GPIO Interrupt Clear 0 8 write-only GPIOA_AHBIEV GPIO Interrupt Event 0x40C read-write n 0x0 0x0 GPIOA_AHBIM GPIO Interrupt Mask 0x410 read-write n 0x0 0x0 GPIO_IM_DMAIME GPIO uDMA Done Interrupt Mask Enable 8 9 GPIO_IM_GPIO GPIO Interrupt Mask Enable 0 8 GPIOA_AHBIS GPIO Interrupt Sense 0x404 read-write n 0x0 0x0 GPIOA_AHBLOCK GPIO Lock 0x520 read-write n 0x0 0x0 GPIO_LOCK GPIO Lock 0 32 GPIO_LOCK_UNLOCKED The GPIOCR register is unlocked and may be modified 0x0 GPIO_LOCK_LOCKED The GPIOCR register is locked and may not be modified 0x1 GPIO_LOCK_KEY Unlocks the GPIO_CR register 0x4c4f434b GPIOA_AHBMIS GPIO Masked Interrupt Status 0x418 read-write n 0x0 0x0 GPIO_MIS_DMAMIS GPIO uDMA Done Masked Interrupt Status 8 9 GPIO_MIS_GPIO GPIO Masked Interrupt Status 0 8 GPIOA_AHBODR GPIO Open Drain Select 0x50C read-write n 0x0 0x0 GPIOA_AHBPC GPIO Peripheral Configuration 0xFC4 read-write n 0x0 0x0 GPIO_PC_EDM0 Extended Drive Mode Bit 0 0 2 GPIO_PC_EDM0_DISABLE Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive Select (GPIODRnR) registers function as normal 0x0 GPIO_PC_EDM0_6MA An additional 6 mA option is provided 0x1 GPIO_PC_EDM0_PLUS2MA A 2 mA driver is always enabled; setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R of GPIODR12R register bit adds an additional 4 mA 0x3 GPIO_PC_EDM1 Extended Drive Mode Bit 1 2 4 GPIO_PC_EDM2 Extended Drive Mode Bit 2 4 6 GPIO_PC_EDM3 Extended Drive Mode Bit 3 6 8 GPIO_PC_EDM4 Extended Drive Mode Bit 4 8 10 GPIO_PC_EDM5 Extended Drive Mode Bit 5 10 12 GPIO_PC_EDM6 Extended Drive Mode Bit 6 12 14 GPIO_PC_EDM7 Extended Drive Mode Bit 7 14 16 GPIOA_AHBPCTL GPIO Port Control 0x52C read-write n 0x0 0x0 GPIOA_AHBPDR GPIO Pull-Down Select 0x514 read-write n 0x0 0x0 GPIOA_AHBPP GPIO Peripheral Property 0xFC0 read-write n 0x0 0x0 GPIO_PP_EDE Extended Drive Enable 0 1 GPIOA_AHBPUR GPIO Pull-Up Select 0x510 read-write n 0x0 0x0 GPIOA_AHBRIS GPIO Raw Interrupt Status 0x414 read-write n 0x0 0x0 GPIO_RIS_DMARIS GPIO uDMA Done Interrupt Raw Status 8 9 GPIO_RIS_GPIO GPIO Interrupt Raw Status 0 8 GPIOA_AHBSI GPIO Select Interrupt 0x538 read-write n 0x0 0x0 GPIO_SI_SUM Summary Interrupt 0 1 GPIOA_AHBSLR GPIO Slew Rate Control Select 0x518 read-write n 0x0 0x0 GPIOA_AHBWAKELVL GPIO Wake Level 0x544 read-write n 0x0 0x0 GPIO_WAKELVL_WAKELVL4 P[4] Wake Level 4 5 GPIOA_AHBWAKEPEN GPIO Wake Pin Enable 0x540 read-write n 0x0 0x0 GPIO_WAKEPEN_WAKEP4 P[4] Wake Enable 4 5 GPIOA_AHBWAKESTAT GPIO Wake Status 0x548 read-write n 0x0 0x0 GPIO_WAKESTAT_STAT4 P[4] Wake Status 4 5 IBE GPIO Interrupt Both Edges 0x408 -1 read-write n 0x0 0x0 ICR GPIO Interrupt Clear 0x41C -1 write-only n 0x0 0x0 GPIO_ICR_DMAIC GPIO uDMA Interrupt Clear 8 9 write-only GPIO_ICR_GPIO GPIO Interrupt Clear 0 8 write-only IEV GPIO Interrupt Event 0x40C -1 read-write n 0x0 0x0 IM GPIO Interrupt Mask 0x410 -1 read-write n 0x0 0x0 GPIO_IM_DMAIME GPIO uDMA Done Interrupt Mask Enable 8 9 GPIO_IM_GPIO GPIO Interrupt Mask Enable 0 8 IS GPIO Interrupt Sense 0x404 -1 read-write n 0x0 0x0 LOCK GPIO Lock 0x520 -1 read-write n 0x0 0x0 GPIO_LOCK GPIO Lock 0 32 GPIO_LOCK_UNLOCKED The GPIOCR register is unlocked and may be modified 0x0 GPIO_LOCK_LOCKED The GPIOCR register is locked and may not be modified 0x1 GPIO_LOCK_KEY Unlocks the GPIO_CR register 0x4c4f434b MIS GPIO Masked Interrupt Status 0x418 -1 read-write n 0x0 0x0 GPIO_MIS_DMAMIS GPIO uDMA Done Masked Interrupt Status 8 9 GPIO_MIS_GPIO GPIO Masked Interrupt Status 0 8 ODR GPIO Open Drain Select 0x50C -1 read-write n 0x0 0x0 PC GPIO Peripheral Configuration 0xFC4 -1 read-write n 0x0 0x0 GPIO_PC_EDM0 Extended Drive Mode Bit 0 0 2 GPIO_PC_EDM0_DISABLE Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive Select (GPIODRnR) registers function as normal 0x0 GPIO_PC_EDM0_6MA An additional 6 mA option is provided 0x1 GPIO_PC_EDM0_PLUS2MA A 2 mA driver is always enabled setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R of GPIODR12R register bit adds an additional 4 mA 0x3 GPIO_PC_EDM1 Extended Drive Mode Bit 1 2 4 GPIO_PC_EDM2 Extended Drive Mode Bit 2 4 6 GPIO_PC_EDM3 Extended Drive Mode Bit 3 6 8 GPIO_PC_EDM4 Extended Drive Mode Bit 4 8 10 GPIO_PC_EDM5 Extended Drive Mode Bit 5 10 12 GPIO_PC_EDM6 Extended Drive Mode Bit 6 12 14 GPIO_PC_EDM7 Extended Drive Mode Bit 7 14 16 PCTL GPIO Port Control 0x52C -1 read-write n 0x0 0x0 PDR GPIO Pull-Down Select 0x514 -1 read-write n 0x0 0x0 PP GPIO Peripheral Property 0xFC0 -1 read-write n 0x0 0x0 GPIO_PP_EDE Extended Drive Enable 0 1 PUR GPIO Pull-Up Select 0x510 -1 read-write n 0x0 0x0 RIS GPIO Raw Interrupt Status 0x414 -1 read-write n 0x0 0x0 GPIO_RIS_DMARIS GPIO uDMA Done Interrupt Raw Status 8 9 GPIO_RIS_GPIO GPIO Interrupt Raw Status 0 8 SI GPIO Select Interrupt 0x538 -1 read-write n 0x0 0x0 GPIO_SI_SUM Summary Interrupt 0 1 SLR GPIO Slew Rate Control Select 0x518 -1 read-write n 0x0 0x0 WAKELVL GPIO Wake Level 0x544 -1 read-write n 0x0 0x0 GPIO_WAKELVL_WAKELVL4 P[4] Wake Level 4 5 WAKEPEN GPIO Wake Pin Enable 0x540 -1 read-write n 0x0 0x0 GPIO_WAKEPEN_WAKEP4 P[4] Wake Enable 4 5 WAKESTAT GPIO Wake Status 0x548 -1 read-write n 0x0 0x0 GPIO_WAKESTAT_STAT4 P[4] Wake Status 4 5 GPIOL Register map for GPIOA_AHB peripheral GPIO 0x0 0x0 0x1000 registers n GPIOL 53 ADCCTL GPIO ADC Control 0x530 -1 read-write n 0x0 0x0 AFSEL GPIO Alternate Function Select 0x420 -1 read-write n 0x0 0x0 AMSEL GPIO Analog Mode Select 0x528 -1 read-write n 0x0 0x0 CR GPIO Commit 0x524 -1 read-only n 0x0 0x0 DATA GPIO Data 0x3FC -1 read-write n 0x0 0x0 DEN GPIO Digital Enable 0x51C -1 read-write n 0x0 0x0 DIR GPIO Direction 0x400 -1 read-write n 0x0 0x0 DMACTL GPIO DMA Control 0x534 -1 read-write n 0x0 0x0 DR12R GPIO 12-mA Drive Select 0x53C -1 read-write n 0x0 0x0 GPIO_DR12R_DRV12 Output Pad 12-mA Drive Enable 0 8 GPIO_DR12R_DRV12_12MA The corresponding GPIO pin has 12-mA drive. This encoding is only valid if the GPIOPP EDE bit is set and the appropriate GPIOPC EDM bit field is programmed to 0x3 0x1 DR2R GPIO 2-mA Drive Select 0x500 -1 read-write n 0x0 0x0 DR4R GPIO 4-mA Drive Select 0x504 -1 read-write n 0x0 0x0 DR8R GPIO 8-mA Drive Select 0x508 -1 read-write n 0x0 0x0 GPIOA_AHBADCCTL GPIO ADC Control 0x530 read-write n 0x0 0x0 GPIOA_AHBAFSEL GPIO Alternate Function Select 0x420 read-write n 0x0 0x0 GPIOA_AHBAMSEL GPIO Analog Mode Select 0x528 read-write n 0x0 0x0 GPIOA_AHBCR GPIO Commit 0x524 read-only n 0x0 0x0 GPIOA_AHBDATA GPIO Data 0x3FC read-write n 0x0 0x0 GPIOA_AHBDEN GPIO Digital Enable 0x51C read-write n 0x0 0x0 GPIOA_AHBDIR GPIO Direction 0x400 read-write n 0x0 0x0 GPIOA_AHBDMACTL GPIO DMA Control 0x534 read-write n 0x0 0x0 GPIOA_AHBDR12R GPIO 12-mA Drive Select 0x53C read-write n 0x0 0x0 GPIO_DR12R_DRV12 Output Pad 12-mA Drive Enable 0 8 GPIO_DR12R_DRV12_12MA The corresponding GPIO pin has 12-mA drive. This encoding is only valid if the GPIOPP EDE bit is set and the appropriate GPIOPC EDM bit field is programmed to 0x3 0x1 GPIOA_AHBDR2R GPIO 2-mA Drive Select 0x500 read-write n 0x0 0x0 GPIOA_AHBDR4R GPIO 4-mA Drive Select 0x504 read-write n 0x0 0x0 GPIOA_AHBDR8R GPIO 8-mA Drive Select 0x508 read-write n 0x0 0x0 GPIOA_AHBIBE GPIO Interrupt Both Edges 0x408 read-write n 0x0 0x0 GPIOA_AHBICR GPIO Interrupt Clear 0x41C write-only n 0x0 0x0 GPIO_ICR_DMAIC GPIO uDMA Interrupt Clear 8 9 write-only GPIO_ICR_GPIO GPIO Interrupt Clear 0 8 write-only GPIOA_AHBIEV GPIO Interrupt Event 0x40C read-write n 0x0 0x0 GPIOA_AHBIM GPIO Interrupt Mask 0x410 read-write n 0x0 0x0 GPIO_IM_DMAIME GPIO uDMA Done Interrupt Mask Enable 8 9 GPIO_IM_GPIO GPIO Interrupt Mask Enable 0 8 GPIOA_AHBIS GPIO Interrupt Sense 0x404 read-write n 0x0 0x0 GPIOA_AHBLOCK GPIO Lock 0x520 read-write n 0x0 0x0 GPIO_LOCK GPIO Lock 0 32 GPIO_LOCK_UNLOCKED The GPIOCR register is unlocked and may be modified 0x0 GPIO_LOCK_LOCKED The GPIOCR register is locked and may not be modified 0x1 GPIO_LOCK_KEY Unlocks the GPIO_CR register 0x4c4f434b GPIOA_AHBMIS GPIO Masked Interrupt Status 0x418 read-write n 0x0 0x0 GPIO_MIS_DMAMIS GPIO uDMA Done Masked Interrupt Status 8 9 GPIO_MIS_GPIO GPIO Masked Interrupt Status 0 8 GPIOA_AHBODR GPIO Open Drain Select 0x50C read-write n 0x0 0x0 GPIOA_AHBPC GPIO Peripheral Configuration 0xFC4 read-write n 0x0 0x0 GPIO_PC_EDM0 Extended Drive Mode Bit 0 0 2 GPIO_PC_EDM0_DISABLE Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive Select (GPIODRnR) registers function as normal 0x0 GPIO_PC_EDM0_6MA An additional 6 mA option is provided 0x1 GPIO_PC_EDM0_PLUS2MA A 2 mA driver is always enabled; setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R of GPIODR12R register bit adds an additional 4 mA 0x3 GPIO_PC_EDM1 Extended Drive Mode Bit 1 2 4 GPIO_PC_EDM2 Extended Drive Mode Bit 2 4 6 GPIO_PC_EDM3 Extended Drive Mode Bit 3 6 8 GPIO_PC_EDM4 Extended Drive Mode Bit 4 8 10 GPIO_PC_EDM5 Extended Drive Mode Bit 5 10 12 GPIO_PC_EDM6 Extended Drive Mode Bit 6 12 14 GPIO_PC_EDM7 Extended Drive Mode Bit 7 14 16 GPIOA_AHBPCTL GPIO Port Control 0x52C read-write n 0x0 0x0 GPIOA_AHBPDR GPIO Pull-Down Select 0x514 read-write n 0x0 0x0 GPIOA_AHBPP GPIO Peripheral Property 0xFC0 read-write n 0x0 0x0 GPIO_PP_EDE Extended Drive Enable 0 1 GPIOA_AHBPUR GPIO Pull-Up Select 0x510 read-write n 0x0 0x0 GPIOA_AHBRIS GPIO Raw Interrupt Status 0x414 read-write n 0x0 0x0 GPIO_RIS_DMARIS GPIO uDMA Done Interrupt Raw Status 8 9 GPIO_RIS_GPIO GPIO Interrupt Raw Status 0 8 GPIOA_AHBSI GPIO Select Interrupt 0x538 read-write n 0x0 0x0 GPIO_SI_SUM Summary Interrupt 0 1 GPIOA_AHBSLR GPIO Slew Rate Control Select 0x518 read-write n 0x0 0x0 GPIOA_AHBWAKELVL GPIO Wake Level 0x544 read-write n 0x0 0x0 GPIO_WAKELVL_WAKELVL4 P[4] Wake Level 4 5 GPIOA_AHBWAKEPEN GPIO Wake Pin Enable 0x540 read-write n 0x0 0x0 GPIO_WAKEPEN_WAKEP4 P[4] Wake Enable 4 5 GPIOA_AHBWAKESTAT GPIO Wake Status 0x548 read-write n 0x0 0x0 GPIO_WAKESTAT_STAT4 P[4] Wake Status 4 5 IBE GPIO Interrupt Both Edges 0x408 -1 read-write n 0x0 0x0 ICR GPIO Interrupt Clear 0x41C -1 write-only n 0x0 0x0 GPIO_ICR_DMAIC GPIO uDMA Interrupt Clear 8 9 write-only GPIO_ICR_GPIO GPIO Interrupt Clear 0 8 write-only IEV GPIO Interrupt Event 0x40C -1 read-write n 0x0 0x0 IM GPIO Interrupt Mask 0x410 -1 read-write n 0x0 0x0 GPIO_IM_DMAIME GPIO uDMA Done Interrupt Mask Enable 8 9 GPIO_IM_GPIO GPIO Interrupt Mask Enable 0 8 IS GPIO Interrupt Sense 0x404 -1 read-write n 0x0 0x0 LOCK GPIO Lock 0x520 -1 read-write n 0x0 0x0 GPIO_LOCK GPIO Lock 0 32 GPIO_LOCK_UNLOCKED The GPIOCR register is unlocked and may be modified 0x0 GPIO_LOCK_LOCKED The GPIOCR register is locked and may not be modified 0x1 GPIO_LOCK_KEY Unlocks the GPIO_CR register 0x4c4f434b MIS GPIO Masked Interrupt Status 0x418 -1 read-write n 0x0 0x0 GPIO_MIS_DMAMIS GPIO uDMA Done Masked Interrupt Status 8 9 GPIO_MIS_GPIO GPIO Masked Interrupt Status 0 8 ODR GPIO Open Drain Select 0x50C -1 read-write n 0x0 0x0 PC GPIO Peripheral Configuration 0xFC4 -1 read-write n 0x0 0x0 GPIO_PC_EDM0 Extended Drive Mode Bit 0 0 2 GPIO_PC_EDM0_DISABLE Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive Select (GPIODRnR) registers function as normal 0x0 GPIO_PC_EDM0_6MA An additional 6 mA option is provided 0x1 GPIO_PC_EDM0_PLUS2MA A 2 mA driver is always enabled setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R of GPIODR12R register bit adds an additional 4 mA 0x3 GPIO_PC_EDM1 Extended Drive Mode Bit 1 2 4 GPIO_PC_EDM2 Extended Drive Mode Bit 2 4 6 GPIO_PC_EDM3 Extended Drive Mode Bit 3 6 8 GPIO_PC_EDM4 Extended Drive Mode Bit 4 8 10 GPIO_PC_EDM5 Extended Drive Mode Bit 5 10 12 GPIO_PC_EDM6 Extended Drive Mode Bit 6 12 14 GPIO_PC_EDM7 Extended Drive Mode Bit 7 14 16 PCTL GPIO Port Control 0x52C -1 read-write n 0x0 0x0 PDR GPIO Pull-Down Select 0x514 -1 read-write n 0x0 0x0 PP GPIO Peripheral Property 0xFC0 -1 read-write n 0x0 0x0 GPIO_PP_EDE Extended Drive Enable 0 1 PUR GPIO Pull-Up Select 0x510 -1 read-write n 0x0 0x0 RIS GPIO Raw Interrupt Status 0x414 -1 read-write n 0x0 0x0 GPIO_RIS_DMARIS GPIO uDMA Done Interrupt Raw Status 8 9 GPIO_RIS_GPIO GPIO Interrupt Raw Status 0 8 SI GPIO Select Interrupt 0x538 -1 read-write n 0x0 0x0 GPIO_SI_SUM Summary Interrupt 0 1 SLR GPIO Slew Rate Control Select 0x518 -1 read-write n 0x0 0x0 WAKELVL GPIO Wake Level 0x544 -1 read-write n 0x0 0x0 GPIO_WAKELVL_WAKELVL4 P[4] Wake Level 4 5 WAKEPEN GPIO Wake Pin Enable 0x540 -1 read-write n 0x0 0x0 GPIO_WAKEPEN_WAKEP4 P[4] Wake Enable 4 5 WAKESTAT GPIO Wake Status 0x548 -1 read-write n 0x0 0x0 GPIO_WAKESTAT_STAT4 P[4] Wake Status 4 5 GPIOM Register map for GPIOA_AHB peripheral GPIO 0x0 0x0 0x1000 registers n GPIOM 72 ADCCTL GPIO ADC Control 0x530 -1 read-write n 0x0 0x0 AFSEL GPIO Alternate Function Select 0x420 -1 read-write n 0x0 0x0 AMSEL GPIO Analog Mode Select 0x528 -1 read-write n 0x0 0x0 CR GPIO Commit 0x524 -1 read-only n 0x0 0x0 DATA GPIO Data 0x3FC -1 read-write n 0x0 0x0 DEN GPIO Digital Enable 0x51C -1 read-write n 0x0 0x0 DIR GPIO Direction 0x400 -1 read-write n 0x0 0x0 DMACTL GPIO DMA Control 0x534 -1 read-write n 0x0 0x0 DR12R GPIO 12-mA Drive Select 0x53C -1 read-write n 0x0 0x0 GPIO_DR12R_DRV12 Output Pad 12-mA Drive Enable 0 8 GPIO_DR12R_DRV12_12MA The corresponding GPIO pin has 12-mA drive. This encoding is only valid if the GPIOPP EDE bit is set and the appropriate GPIOPC EDM bit field is programmed to 0x3 0x1 DR2R GPIO 2-mA Drive Select 0x500 -1 read-write n 0x0 0x0 DR4R GPIO 4-mA Drive Select 0x504 -1 read-write n 0x0 0x0 DR8R GPIO 8-mA Drive Select 0x508 -1 read-write n 0x0 0x0 GPIOA_AHBADCCTL GPIO ADC Control 0x530 read-write n 0x0 0x0 GPIOA_AHBAFSEL GPIO Alternate Function Select 0x420 read-write n 0x0 0x0 GPIOA_AHBAMSEL GPIO Analog Mode Select 0x528 read-write n 0x0 0x0 GPIOA_AHBCR GPIO Commit 0x524 read-only n 0x0 0x0 GPIOA_AHBDATA GPIO Data 0x3FC read-write n 0x0 0x0 GPIOA_AHBDEN GPIO Digital Enable 0x51C read-write n 0x0 0x0 GPIOA_AHBDIR GPIO Direction 0x400 read-write n 0x0 0x0 GPIOA_AHBDMACTL GPIO DMA Control 0x534 read-write n 0x0 0x0 GPIOA_AHBDR12R GPIO 12-mA Drive Select 0x53C read-write n 0x0 0x0 GPIO_DR12R_DRV12 Output Pad 12-mA Drive Enable 0 8 GPIO_DR12R_DRV12_12MA The corresponding GPIO pin has 12-mA drive. This encoding is only valid if the GPIOPP EDE bit is set and the appropriate GPIOPC EDM bit field is programmed to 0x3 0x1 GPIOA_AHBDR2R GPIO 2-mA Drive Select 0x500 read-write n 0x0 0x0 GPIOA_AHBDR4R GPIO 4-mA Drive Select 0x504 read-write n 0x0 0x0 GPIOA_AHBDR8R GPIO 8-mA Drive Select 0x508 read-write n 0x0 0x0 GPIOA_AHBIBE GPIO Interrupt Both Edges 0x408 read-write n 0x0 0x0 GPIOA_AHBICR GPIO Interrupt Clear 0x41C write-only n 0x0 0x0 GPIO_ICR_DMAIC GPIO uDMA Interrupt Clear 8 9 write-only GPIO_ICR_GPIO GPIO Interrupt Clear 0 8 write-only GPIOA_AHBIEV GPIO Interrupt Event 0x40C read-write n 0x0 0x0 GPIOA_AHBIM GPIO Interrupt Mask 0x410 read-write n 0x0 0x0 GPIO_IM_DMAIME GPIO uDMA Done Interrupt Mask Enable 8 9 GPIO_IM_GPIO GPIO Interrupt Mask Enable 0 8 GPIOA_AHBIS GPIO Interrupt Sense 0x404 read-write n 0x0 0x0 GPIOA_AHBLOCK GPIO Lock 0x520 read-write n 0x0 0x0 GPIO_LOCK GPIO Lock 0 32 GPIO_LOCK_UNLOCKED The GPIOCR register is unlocked and may be modified 0x0 GPIO_LOCK_LOCKED The GPIOCR register is locked and may not be modified 0x1 GPIO_LOCK_KEY Unlocks the GPIO_CR register 0x4c4f434b GPIOA_AHBMIS GPIO Masked Interrupt Status 0x418 read-write n 0x0 0x0 GPIO_MIS_DMAMIS GPIO uDMA Done Masked Interrupt Status 8 9 GPIO_MIS_GPIO GPIO Masked Interrupt Status 0 8 GPIOA_AHBODR GPIO Open Drain Select 0x50C read-write n 0x0 0x0 GPIOA_AHBPC GPIO Peripheral Configuration 0xFC4 read-write n 0x0 0x0 GPIO_PC_EDM0 Extended Drive Mode Bit 0 0 2 GPIO_PC_EDM0_DISABLE Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive Select (GPIODRnR) registers function as normal 0x0 GPIO_PC_EDM0_6MA An additional 6 mA option is provided 0x1 GPIO_PC_EDM0_PLUS2MA A 2 mA driver is always enabled; setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R of GPIODR12R register bit adds an additional 4 mA 0x3 GPIO_PC_EDM1 Extended Drive Mode Bit 1 2 4 GPIO_PC_EDM2 Extended Drive Mode Bit 2 4 6 GPIO_PC_EDM3 Extended Drive Mode Bit 3 6 8 GPIO_PC_EDM4 Extended Drive Mode Bit 4 8 10 GPIO_PC_EDM5 Extended Drive Mode Bit 5 10 12 GPIO_PC_EDM6 Extended Drive Mode Bit 6 12 14 GPIO_PC_EDM7 Extended Drive Mode Bit 7 14 16 GPIOA_AHBPCTL GPIO Port Control 0x52C read-write n 0x0 0x0 GPIOA_AHBPDR GPIO Pull-Down Select 0x514 read-write n 0x0 0x0 GPIOA_AHBPP GPIO Peripheral Property 0xFC0 read-write n 0x0 0x0 GPIO_PP_EDE Extended Drive Enable 0 1 GPIOA_AHBPUR GPIO Pull-Up Select 0x510 read-write n 0x0 0x0 GPIOA_AHBRIS GPIO Raw Interrupt Status 0x414 read-write n 0x0 0x0 GPIO_RIS_DMARIS GPIO uDMA Done Interrupt Raw Status 8 9 GPIO_RIS_GPIO GPIO Interrupt Raw Status 0 8 GPIOA_AHBSI GPIO Select Interrupt 0x538 read-write n 0x0 0x0 GPIO_SI_SUM Summary Interrupt 0 1 GPIOA_AHBSLR GPIO Slew Rate Control Select 0x518 read-write n 0x0 0x0 GPIOA_AHBWAKELVL GPIO Wake Level 0x544 read-write n 0x0 0x0 GPIO_WAKELVL_WAKELVL4 P[4] Wake Level 4 5 GPIOA_AHBWAKEPEN GPIO Wake Pin Enable 0x540 read-write n 0x0 0x0 GPIO_WAKEPEN_WAKEP4 P[4] Wake Enable 4 5 GPIOA_AHBWAKESTAT GPIO Wake Status 0x548 read-write n 0x0 0x0 GPIO_WAKESTAT_STAT4 P[4] Wake Status 4 5 IBE GPIO Interrupt Both Edges 0x408 -1 read-write n 0x0 0x0 ICR GPIO Interrupt Clear 0x41C -1 write-only n 0x0 0x0 GPIO_ICR_DMAIC GPIO uDMA Interrupt Clear 8 9 write-only GPIO_ICR_GPIO GPIO Interrupt Clear 0 8 write-only IEV GPIO Interrupt Event 0x40C -1 read-write n 0x0 0x0 IM GPIO Interrupt Mask 0x410 -1 read-write n 0x0 0x0 GPIO_IM_DMAIME GPIO uDMA Done Interrupt Mask Enable 8 9 GPIO_IM_GPIO GPIO Interrupt Mask Enable 0 8 IS GPIO Interrupt Sense 0x404 -1 read-write n 0x0 0x0 LOCK GPIO Lock 0x520 -1 read-write n 0x0 0x0 GPIO_LOCK GPIO Lock 0 32 GPIO_LOCK_UNLOCKED The GPIOCR register is unlocked and may be modified 0x0 GPIO_LOCK_LOCKED The GPIOCR register is locked and may not be modified 0x1 GPIO_LOCK_KEY Unlocks the GPIO_CR register 0x4c4f434b MIS GPIO Masked Interrupt Status 0x418 -1 read-write n 0x0 0x0 GPIO_MIS_DMAMIS GPIO uDMA Done Masked Interrupt Status 8 9 GPIO_MIS_GPIO GPIO Masked Interrupt Status 0 8 ODR GPIO Open Drain Select 0x50C -1 read-write n 0x0 0x0 PC GPIO Peripheral Configuration 0xFC4 -1 read-write n 0x0 0x0 GPIO_PC_EDM0 Extended Drive Mode Bit 0 0 2 GPIO_PC_EDM0_DISABLE Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive Select (GPIODRnR) registers function as normal 0x0 GPIO_PC_EDM0_6MA An additional 6 mA option is provided 0x1 GPIO_PC_EDM0_PLUS2MA A 2 mA driver is always enabled setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R of GPIODR12R register bit adds an additional 4 mA 0x3 GPIO_PC_EDM1 Extended Drive Mode Bit 1 2 4 GPIO_PC_EDM2 Extended Drive Mode Bit 2 4 6 GPIO_PC_EDM3 Extended Drive Mode Bit 3 6 8 GPIO_PC_EDM4 Extended Drive Mode Bit 4 8 10 GPIO_PC_EDM5 Extended Drive Mode Bit 5 10 12 GPIO_PC_EDM6 Extended Drive Mode Bit 6 12 14 GPIO_PC_EDM7 Extended Drive Mode Bit 7 14 16 PCTL GPIO Port Control 0x52C -1 read-write n 0x0 0x0 PDR GPIO Pull-Down Select 0x514 -1 read-write n 0x0 0x0 PP GPIO Peripheral Property 0xFC0 -1 read-write n 0x0 0x0 GPIO_PP_EDE Extended Drive Enable 0 1 PUR GPIO Pull-Up Select 0x510 -1 read-write n 0x0 0x0 RIS GPIO Raw Interrupt Status 0x414 -1 read-write n 0x0 0x0 GPIO_RIS_DMARIS GPIO uDMA Done Interrupt Raw Status 8 9 GPIO_RIS_GPIO GPIO Interrupt Raw Status 0 8 SI GPIO Select Interrupt 0x538 -1 read-write n 0x0 0x0 GPIO_SI_SUM Summary Interrupt 0 1 SLR GPIO Slew Rate Control Select 0x518 -1 read-write n 0x0 0x0 WAKELVL GPIO Wake Level 0x544 -1 read-write n 0x0 0x0 GPIO_WAKELVL_WAKELVL4 P[4] Wake Level 4 5 WAKEPEN GPIO Wake Pin Enable 0x540 -1 read-write n 0x0 0x0 GPIO_WAKEPEN_WAKEP4 P[4] Wake Enable 4 5 WAKESTAT GPIO Wake Status 0x548 -1 read-write n 0x0 0x0 GPIO_WAKESTAT_STAT4 P[4] Wake Status 4 5 GPION Register map for GPIOA_AHB peripheral GPIO 0x0 0x0 0x1000 registers n GPION 73 ADCCTL GPIO ADC Control 0x530 -1 read-write n 0x0 0x0 AFSEL GPIO Alternate Function Select 0x420 -1 read-write n 0x0 0x0 AMSEL GPIO Analog Mode Select 0x528 -1 read-write n 0x0 0x0 CR GPIO Commit 0x524 -1 read-only n 0x0 0x0 DATA GPIO Data 0x3FC -1 read-write n 0x0 0x0 DEN GPIO Digital Enable 0x51C -1 read-write n 0x0 0x0 DIR GPIO Direction 0x400 -1 read-write n 0x0 0x0 DMACTL GPIO DMA Control 0x534 -1 read-write n 0x0 0x0 DR12R GPIO 12-mA Drive Select 0x53C -1 read-write n 0x0 0x0 GPIO_DR12R_DRV12 Output Pad 12-mA Drive Enable 0 8 GPIO_DR12R_DRV12_12MA The corresponding GPIO pin has 12-mA drive. This encoding is only valid if the GPIOPP EDE bit is set and the appropriate GPIOPC EDM bit field is programmed to 0x3 0x1 DR2R GPIO 2-mA Drive Select 0x500 -1 read-write n 0x0 0x0 DR4R GPIO 4-mA Drive Select 0x504 -1 read-write n 0x0 0x0 DR8R GPIO 8-mA Drive Select 0x508 -1 read-write n 0x0 0x0 GPIOA_AHBADCCTL GPIO ADC Control 0x530 read-write n 0x0 0x0 GPIOA_AHBAFSEL GPIO Alternate Function Select 0x420 read-write n 0x0 0x0 GPIOA_AHBAMSEL GPIO Analog Mode Select 0x528 read-write n 0x0 0x0 GPIOA_AHBCR GPIO Commit 0x524 read-only n 0x0 0x0 GPIOA_AHBDATA GPIO Data 0x3FC read-write n 0x0 0x0 GPIOA_AHBDEN GPIO Digital Enable 0x51C read-write n 0x0 0x0 GPIOA_AHBDIR GPIO Direction 0x400 read-write n 0x0 0x0 GPIOA_AHBDMACTL GPIO DMA Control 0x534 read-write n 0x0 0x0 GPIOA_AHBDR12R GPIO 12-mA Drive Select 0x53C read-write n 0x0 0x0 GPIO_DR12R_DRV12 Output Pad 12-mA Drive Enable 0 8 GPIO_DR12R_DRV12_12MA The corresponding GPIO pin has 12-mA drive. This encoding is only valid if the GPIOPP EDE bit is set and the appropriate GPIOPC EDM bit field is programmed to 0x3 0x1 GPIOA_AHBDR2R GPIO 2-mA Drive Select 0x500 read-write n 0x0 0x0 GPIOA_AHBDR4R GPIO 4-mA Drive Select 0x504 read-write n 0x0 0x0 GPIOA_AHBDR8R GPIO 8-mA Drive Select 0x508 read-write n 0x0 0x0 GPIOA_AHBIBE GPIO Interrupt Both Edges 0x408 read-write n 0x0 0x0 GPIOA_AHBICR GPIO Interrupt Clear 0x41C write-only n 0x0 0x0 GPIO_ICR_DMAIC GPIO uDMA Interrupt Clear 8 9 write-only GPIO_ICR_GPIO GPIO Interrupt Clear 0 8 write-only GPIOA_AHBIEV GPIO Interrupt Event 0x40C read-write n 0x0 0x0 GPIOA_AHBIM GPIO Interrupt Mask 0x410 read-write n 0x0 0x0 GPIO_IM_DMAIME GPIO uDMA Done Interrupt Mask Enable 8 9 GPIO_IM_GPIO GPIO Interrupt Mask Enable 0 8 GPIOA_AHBIS GPIO Interrupt Sense 0x404 read-write n 0x0 0x0 GPIOA_AHBLOCK GPIO Lock 0x520 read-write n 0x0 0x0 GPIO_LOCK GPIO Lock 0 32 GPIO_LOCK_UNLOCKED The GPIOCR register is unlocked and may be modified 0x0 GPIO_LOCK_LOCKED The GPIOCR register is locked and may not be modified 0x1 GPIO_LOCK_KEY Unlocks the GPIO_CR register 0x4c4f434b GPIOA_AHBMIS GPIO Masked Interrupt Status 0x418 read-write n 0x0 0x0 GPIO_MIS_DMAMIS GPIO uDMA Done Masked Interrupt Status 8 9 GPIO_MIS_GPIO GPIO Masked Interrupt Status 0 8 GPIOA_AHBODR GPIO Open Drain Select 0x50C read-write n 0x0 0x0 GPIOA_AHBPC GPIO Peripheral Configuration 0xFC4 read-write n 0x0 0x0 GPIO_PC_EDM0 Extended Drive Mode Bit 0 0 2 GPIO_PC_EDM0_DISABLE Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive Select (GPIODRnR) registers function as normal 0x0 GPIO_PC_EDM0_6MA An additional 6 mA option is provided 0x1 GPIO_PC_EDM0_PLUS2MA A 2 mA driver is always enabled; setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R of GPIODR12R register bit adds an additional 4 mA 0x3 GPIO_PC_EDM1 Extended Drive Mode Bit 1 2 4 GPIO_PC_EDM2 Extended Drive Mode Bit 2 4 6 GPIO_PC_EDM3 Extended Drive Mode Bit 3 6 8 GPIO_PC_EDM4 Extended Drive Mode Bit 4 8 10 GPIO_PC_EDM5 Extended Drive Mode Bit 5 10 12 GPIO_PC_EDM6 Extended Drive Mode Bit 6 12 14 GPIO_PC_EDM7 Extended Drive Mode Bit 7 14 16 GPIOA_AHBPCTL GPIO Port Control 0x52C read-write n 0x0 0x0 GPIOA_AHBPDR GPIO Pull-Down Select 0x514 read-write n 0x0 0x0 GPIOA_AHBPP GPIO Peripheral Property 0xFC0 read-write n 0x0 0x0 GPIO_PP_EDE Extended Drive Enable 0 1 GPIOA_AHBPUR GPIO Pull-Up Select 0x510 read-write n 0x0 0x0 GPIOA_AHBRIS GPIO Raw Interrupt Status 0x414 read-write n 0x0 0x0 GPIO_RIS_DMARIS GPIO uDMA Done Interrupt Raw Status 8 9 GPIO_RIS_GPIO GPIO Interrupt Raw Status 0 8 GPIOA_AHBSI GPIO Select Interrupt 0x538 read-write n 0x0 0x0 GPIO_SI_SUM Summary Interrupt 0 1 GPIOA_AHBSLR GPIO Slew Rate Control Select 0x518 read-write n 0x0 0x0 GPIOA_AHBWAKELVL GPIO Wake Level 0x544 read-write n 0x0 0x0 GPIO_WAKELVL_WAKELVL4 P[4] Wake Level 4 5 GPIOA_AHBWAKEPEN GPIO Wake Pin Enable 0x540 read-write n 0x0 0x0 GPIO_WAKEPEN_WAKEP4 P[4] Wake Enable 4 5 GPIOA_AHBWAKESTAT GPIO Wake Status 0x548 read-write n 0x0 0x0 GPIO_WAKESTAT_STAT4 P[4] Wake Status 4 5 IBE GPIO Interrupt Both Edges 0x408 -1 read-write n 0x0 0x0 ICR GPIO Interrupt Clear 0x41C -1 write-only n 0x0 0x0 GPIO_ICR_DMAIC GPIO uDMA Interrupt Clear 8 9 write-only GPIO_ICR_GPIO GPIO Interrupt Clear 0 8 write-only IEV GPIO Interrupt Event 0x40C -1 read-write n 0x0 0x0 IM GPIO Interrupt Mask 0x410 -1 read-write n 0x0 0x0 GPIO_IM_DMAIME GPIO uDMA Done Interrupt Mask Enable 8 9 GPIO_IM_GPIO GPIO Interrupt Mask Enable 0 8 IS GPIO Interrupt Sense 0x404 -1 read-write n 0x0 0x0 LOCK GPIO Lock 0x520 -1 read-write n 0x0 0x0 GPIO_LOCK GPIO Lock 0 32 GPIO_LOCK_UNLOCKED The GPIOCR register is unlocked and may be modified 0x0 GPIO_LOCK_LOCKED The GPIOCR register is locked and may not be modified 0x1 GPIO_LOCK_KEY Unlocks the GPIO_CR register 0x4c4f434b MIS GPIO Masked Interrupt Status 0x418 -1 read-write n 0x0 0x0 GPIO_MIS_DMAMIS GPIO uDMA Done Masked Interrupt Status 8 9 GPIO_MIS_GPIO GPIO Masked Interrupt Status 0 8 ODR GPIO Open Drain Select 0x50C -1 read-write n 0x0 0x0 PC GPIO Peripheral Configuration 0xFC4 -1 read-write n 0x0 0x0 GPIO_PC_EDM0 Extended Drive Mode Bit 0 0 2 GPIO_PC_EDM0_DISABLE Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive Select (GPIODRnR) registers function as normal 0x0 GPIO_PC_EDM0_6MA An additional 6 mA option is provided 0x1 GPIO_PC_EDM0_PLUS2MA A 2 mA driver is always enabled setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R of GPIODR12R register bit adds an additional 4 mA 0x3 GPIO_PC_EDM1 Extended Drive Mode Bit 1 2 4 GPIO_PC_EDM2 Extended Drive Mode Bit 2 4 6 GPIO_PC_EDM3 Extended Drive Mode Bit 3 6 8 GPIO_PC_EDM4 Extended Drive Mode Bit 4 8 10 GPIO_PC_EDM5 Extended Drive Mode Bit 5 10 12 GPIO_PC_EDM6 Extended Drive Mode Bit 6 12 14 GPIO_PC_EDM7 Extended Drive Mode Bit 7 14 16 PCTL GPIO Port Control 0x52C -1 read-write n 0x0 0x0 PDR GPIO Pull-Down Select 0x514 -1 read-write n 0x0 0x0 PP GPIO Peripheral Property 0xFC0 -1 read-write n 0x0 0x0 GPIO_PP_EDE Extended Drive Enable 0 1 PUR GPIO Pull-Up Select 0x510 -1 read-write n 0x0 0x0 RIS GPIO Raw Interrupt Status 0x414 -1 read-write n 0x0 0x0 GPIO_RIS_DMARIS GPIO uDMA Done Interrupt Raw Status 8 9 GPIO_RIS_GPIO GPIO Interrupt Raw Status 0 8 SI GPIO Select Interrupt 0x538 -1 read-write n 0x0 0x0 GPIO_SI_SUM Summary Interrupt 0 1 SLR GPIO Slew Rate Control Select 0x518 -1 read-write n 0x0 0x0 WAKELVL GPIO Wake Level 0x544 -1 read-write n 0x0 0x0 GPIO_WAKELVL_WAKELVL4 P[4] Wake Level 4 5 WAKEPEN GPIO Wake Pin Enable 0x540 -1 read-write n 0x0 0x0 GPIO_WAKEPEN_WAKEP4 P[4] Wake Enable 4 5 WAKESTAT GPIO Wake Status 0x548 -1 read-write n 0x0 0x0 GPIO_WAKESTAT_STAT4 P[4] Wake Status 4 5 GPIOP Register map for GPIOA_AHB peripheral GPIO 0x0 0x0 0x1000 registers n GPIOP0 76 GPIOP1 77 GPIOP2 78 GPIOP3 79 GPIOP4 80 GPIOP5 81 GPIOP6 82 GPIOP7 83 ADCCTL GPIO ADC Control 0x530 -1 read-write n 0x0 0x0 AFSEL GPIO Alternate Function Select 0x420 -1 read-write n 0x0 0x0 AMSEL GPIO Analog Mode Select 0x528 -1 read-write n 0x0 0x0 CR GPIO Commit 0x524 -1 read-only n 0x0 0x0 DATA GPIO Data 0x3FC -1 read-write n 0x0 0x0 DEN GPIO Digital Enable 0x51C -1 read-write n 0x0 0x0 DIR GPIO Direction 0x400 -1 read-write n 0x0 0x0 DMACTL GPIO DMA Control 0x534 -1 read-write n 0x0 0x0 DR12R GPIO 12-mA Drive Select 0x53C -1 read-write n 0x0 0x0 GPIO_DR12R_DRV12 Output Pad 12-mA Drive Enable 0 8 GPIO_DR12R_DRV12_12MA The corresponding GPIO pin has 12-mA drive. This encoding is only valid if the GPIOPP EDE bit is set and the appropriate GPIOPC EDM bit field is programmed to 0x3 0x1 DR2R GPIO 2-mA Drive Select 0x500 -1 read-write n 0x0 0x0 DR4R GPIO 4-mA Drive Select 0x504 -1 read-write n 0x0 0x0 DR8R GPIO 8-mA Drive Select 0x508 -1 read-write n 0x0 0x0 GPIOA_AHBADCCTL GPIO ADC Control 0x530 read-write n 0x0 0x0 GPIOA_AHBAFSEL GPIO Alternate Function Select 0x420 read-write n 0x0 0x0 GPIOA_AHBAMSEL GPIO Analog Mode Select 0x528 read-write n 0x0 0x0 GPIOA_AHBCR GPIO Commit 0x524 read-only n 0x0 0x0 GPIOA_AHBDATA GPIO Data 0x3FC read-write n 0x0 0x0 GPIOA_AHBDEN GPIO Digital Enable 0x51C read-write n 0x0 0x0 GPIOA_AHBDIR GPIO Direction 0x400 read-write n 0x0 0x0 GPIOA_AHBDMACTL GPIO DMA Control 0x534 read-write n 0x0 0x0 GPIOA_AHBDR12R GPIO 12-mA Drive Select 0x53C read-write n 0x0 0x0 GPIO_DR12R_DRV12 Output Pad 12-mA Drive Enable 0 8 GPIO_DR12R_DRV12_12MA The corresponding GPIO pin has 12-mA drive. This encoding is only valid if the GPIOPP EDE bit is set and the appropriate GPIOPC EDM bit field is programmed to 0x3 0x1 GPIOA_AHBDR2R GPIO 2-mA Drive Select 0x500 read-write n 0x0 0x0 GPIOA_AHBDR4R GPIO 4-mA Drive Select 0x504 read-write n 0x0 0x0 GPIOA_AHBDR8R GPIO 8-mA Drive Select 0x508 read-write n 0x0 0x0 GPIOA_AHBIBE GPIO Interrupt Both Edges 0x408 read-write n 0x0 0x0 GPIOA_AHBICR GPIO Interrupt Clear 0x41C write-only n 0x0 0x0 GPIO_ICR_DMAIC GPIO uDMA Interrupt Clear 8 9 write-only GPIO_ICR_GPIO GPIO Interrupt Clear 0 8 write-only GPIOA_AHBIEV GPIO Interrupt Event 0x40C read-write n 0x0 0x0 GPIOA_AHBIM GPIO Interrupt Mask 0x410 read-write n 0x0 0x0 GPIO_IM_DMAIME GPIO uDMA Done Interrupt Mask Enable 8 9 GPIO_IM_GPIO GPIO Interrupt Mask Enable 0 8 GPIOA_AHBIS GPIO Interrupt Sense 0x404 read-write n 0x0 0x0 GPIOA_AHBLOCK GPIO Lock 0x520 read-write n 0x0 0x0 GPIO_LOCK GPIO Lock 0 32 GPIO_LOCK_UNLOCKED The GPIOCR register is unlocked and may be modified 0x0 GPIO_LOCK_LOCKED The GPIOCR register is locked and may not be modified 0x1 GPIO_LOCK_KEY Unlocks the GPIO_CR register 0x4c4f434b GPIOA_AHBMIS GPIO Masked Interrupt Status 0x418 read-write n 0x0 0x0 GPIO_MIS_DMAMIS GPIO uDMA Done Masked Interrupt Status 8 9 GPIO_MIS_GPIO GPIO Masked Interrupt Status 0 8 GPIOA_AHBODR GPIO Open Drain Select 0x50C read-write n 0x0 0x0 GPIOA_AHBPC GPIO Peripheral Configuration 0xFC4 read-write n 0x0 0x0 GPIO_PC_EDM0 Extended Drive Mode Bit 0 0 2 GPIO_PC_EDM0_DISABLE Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive Select (GPIODRnR) registers function as normal 0x0 GPIO_PC_EDM0_6MA An additional 6 mA option is provided 0x1 GPIO_PC_EDM0_PLUS2MA A 2 mA driver is always enabled; setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R of GPIODR12R register bit adds an additional 4 mA 0x3 GPIO_PC_EDM1 Extended Drive Mode Bit 1 2 4 GPIO_PC_EDM2 Extended Drive Mode Bit 2 4 6 GPIO_PC_EDM3 Extended Drive Mode Bit 3 6 8 GPIO_PC_EDM4 Extended Drive Mode Bit 4 8 10 GPIO_PC_EDM5 Extended Drive Mode Bit 5 10 12 GPIO_PC_EDM6 Extended Drive Mode Bit 6 12 14 GPIO_PC_EDM7 Extended Drive Mode Bit 7 14 16 GPIOA_AHBPCTL GPIO Port Control 0x52C read-write n 0x0 0x0 GPIOA_AHBPDR GPIO Pull-Down Select 0x514 read-write n 0x0 0x0 GPIOA_AHBPP GPIO Peripheral Property 0xFC0 read-write n 0x0 0x0 GPIO_PP_EDE Extended Drive Enable 0 1 GPIOA_AHBPUR GPIO Pull-Up Select 0x510 read-write n 0x0 0x0 GPIOA_AHBRIS GPIO Raw Interrupt Status 0x414 read-write n 0x0 0x0 GPIO_RIS_DMARIS GPIO uDMA Done Interrupt Raw Status 8 9 GPIO_RIS_GPIO GPIO Interrupt Raw Status 0 8 GPIOA_AHBSI GPIO Select Interrupt 0x538 read-write n 0x0 0x0 GPIO_SI_SUM Summary Interrupt 0 1 GPIOA_AHBSLR GPIO Slew Rate Control Select 0x518 read-write n 0x0 0x0 GPIOA_AHBWAKELVL GPIO Wake Level 0x544 read-write n 0x0 0x0 GPIO_WAKELVL_WAKELVL4 P[4] Wake Level 4 5 GPIOA_AHBWAKEPEN GPIO Wake Pin Enable 0x540 read-write n 0x0 0x0 GPIO_WAKEPEN_WAKEP4 P[4] Wake Enable 4 5 GPIOA_AHBWAKESTAT GPIO Wake Status 0x548 read-write n 0x0 0x0 GPIO_WAKESTAT_STAT4 P[4] Wake Status 4 5 IBE GPIO Interrupt Both Edges 0x408 -1 read-write n 0x0 0x0 ICR GPIO Interrupt Clear 0x41C -1 write-only n 0x0 0x0 GPIO_ICR_DMAIC GPIO uDMA Interrupt Clear 8 9 write-only GPIO_ICR_GPIO GPIO Interrupt Clear 0 8 write-only IEV GPIO Interrupt Event 0x40C -1 read-write n 0x0 0x0 IM GPIO Interrupt Mask 0x410 -1 read-write n 0x0 0x0 GPIO_IM_DMAIME GPIO uDMA Done Interrupt Mask Enable 8 9 GPIO_IM_GPIO GPIO Interrupt Mask Enable 0 8 IS GPIO Interrupt Sense 0x404 -1 read-write n 0x0 0x0 LOCK GPIO Lock 0x520 -1 read-write n 0x0 0x0 GPIO_LOCK GPIO Lock 0 32 GPIO_LOCK_UNLOCKED The GPIOCR register is unlocked and may be modified 0x0 GPIO_LOCK_LOCKED The GPIOCR register is locked and may not be modified 0x1 GPIO_LOCK_KEY Unlocks the GPIO_CR register 0x4c4f434b MIS GPIO Masked Interrupt Status 0x418 -1 read-write n 0x0 0x0 GPIO_MIS_DMAMIS GPIO uDMA Done Masked Interrupt Status 8 9 GPIO_MIS_GPIO GPIO Masked Interrupt Status 0 8 ODR GPIO Open Drain Select 0x50C -1 read-write n 0x0 0x0 PC GPIO Peripheral Configuration 0xFC4 -1 read-write n 0x0 0x0 GPIO_PC_EDM0 Extended Drive Mode Bit 0 0 2 GPIO_PC_EDM0_DISABLE Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive Select (GPIODRnR) registers function as normal 0x0 GPIO_PC_EDM0_6MA An additional 6 mA option is provided 0x1 GPIO_PC_EDM0_PLUS2MA A 2 mA driver is always enabled setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R of GPIODR12R register bit adds an additional 4 mA 0x3 GPIO_PC_EDM1 Extended Drive Mode Bit 1 2 4 GPIO_PC_EDM2 Extended Drive Mode Bit 2 4 6 GPIO_PC_EDM3 Extended Drive Mode Bit 3 6 8 GPIO_PC_EDM4 Extended Drive Mode Bit 4 8 10 GPIO_PC_EDM5 Extended Drive Mode Bit 5 10 12 GPIO_PC_EDM6 Extended Drive Mode Bit 6 12 14 GPIO_PC_EDM7 Extended Drive Mode Bit 7 14 16 PCTL GPIO Port Control 0x52C -1 read-write n 0x0 0x0 PDR GPIO Pull-Down Select 0x514 -1 read-write n 0x0 0x0 PP GPIO Peripheral Property 0xFC0 -1 read-write n 0x0 0x0 GPIO_PP_EDE Extended Drive Enable 0 1 PUR GPIO Pull-Up Select 0x510 -1 read-write n 0x0 0x0 RIS GPIO Raw Interrupt Status 0x414 -1 read-write n 0x0 0x0 GPIO_RIS_DMARIS GPIO uDMA Done Interrupt Raw Status 8 9 GPIO_RIS_GPIO GPIO Interrupt Raw Status 0 8 SI GPIO Select Interrupt 0x538 -1 read-write n 0x0 0x0 GPIO_SI_SUM Summary Interrupt 0 1 SLR GPIO Slew Rate Control Select 0x518 -1 read-write n 0x0 0x0 WAKELVL GPIO Wake Level 0x544 -1 read-write n 0x0 0x0 GPIO_WAKELVL_WAKELVL4 P[4] Wake Level 4 5 WAKEPEN GPIO Wake Pin Enable 0x540 -1 read-write n 0x0 0x0 GPIO_WAKEPEN_WAKEP4 P[4] Wake Enable 4 5 WAKESTAT GPIO Wake Status 0x548 -1 read-write n 0x0 0x0 GPIO_WAKESTAT_STAT4 P[4] Wake Status 4 5 GPIOQ Register map for GPIOA_AHB peripheral GPIO 0x0 0x0 0x1000 registers n GPIOQ0 84 GPIOQ1 85 GPIOQ2 86 GPIOQ3 87 GPIOQ4 88 GPIOQ5 89 GPIOQ6 90 GPIOQ7 91 ADCCTL GPIO ADC Control 0x530 -1 read-write n 0x0 0x0 AFSEL GPIO Alternate Function Select 0x420 -1 read-write n 0x0 0x0 AMSEL GPIO Analog Mode Select 0x528 -1 read-write n 0x0 0x0 CR GPIO Commit 0x524 -1 read-only n 0x0 0x0 DATA GPIO Data 0x3FC -1 read-write n 0x0 0x0 DEN GPIO Digital Enable 0x51C -1 read-write n 0x0 0x0 DIR GPIO Direction 0x400 -1 read-write n 0x0 0x0 DMACTL GPIO DMA Control 0x534 -1 read-write n 0x0 0x0 DR12R GPIO 12-mA Drive Select 0x53C -1 read-write n 0x0 0x0 GPIO_DR12R_DRV12 Output Pad 12-mA Drive Enable 0 8 GPIO_DR12R_DRV12_12MA The corresponding GPIO pin has 12-mA drive. This encoding is only valid if the GPIOPP EDE bit is set and the appropriate GPIOPC EDM bit field is programmed to 0x3 0x1 DR2R GPIO 2-mA Drive Select 0x500 -1 read-write n 0x0 0x0 DR4R GPIO 4-mA Drive Select 0x504 -1 read-write n 0x0 0x0 DR8R GPIO 8-mA Drive Select 0x508 -1 read-write n 0x0 0x0 GPIOA_AHBADCCTL GPIO ADC Control 0x530 read-write n 0x0 0x0 GPIOA_AHBAFSEL GPIO Alternate Function Select 0x420 read-write n 0x0 0x0 GPIOA_AHBAMSEL GPIO Analog Mode Select 0x528 read-write n 0x0 0x0 GPIOA_AHBCR GPIO Commit 0x524 read-only n 0x0 0x0 GPIOA_AHBDATA GPIO Data 0x3FC read-write n 0x0 0x0 GPIOA_AHBDEN GPIO Digital Enable 0x51C read-write n 0x0 0x0 GPIOA_AHBDIR GPIO Direction 0x400 read-write n 0x0 0x0 GPIOA_AHBDMACTL GPIO DMA Control 0x534 read-write n 0x0 0x0 GPIOA_AHBDR12R GPIO 12-mA Drive Select 0x53C read-write n 0x0 0x0 GPIO_DR12R_DRV12 Output Pad 12-mA Drive Enable 0 8 GPIO_DR12R_DRV12_12MA The corresponding GPIO pin has 12-mA drive. This encoding is only valid if the GPIOPP EDE bit is set and the appropriate GPIOPC EDM bit field is programmed to 0x3 0x1 GPIOA_AHBDR2R GPIO 2-mA Drive Select 0x500 read-write n 0x0 0x0 GPIOA_AHBDR4R GPIO 4-mA Drive Select 0x504 read-write n 0x0 0x0 GPIOA_AHBDR8R GPIO 8-mA Drive Select 0x508 read-write n 0x0 0x0 GPIOA_AHBIBE GPIO Interrupt Both Edges 0x408 read-write n 0x0 0x0 GPIOA_AHBICR GPIO Interrupt Clear 0x41C write-only n 0x0 0x0 GPIO_ICR_DMAIC GPIO uDMA Interrupt Clear 8 9 write-only GPIO_ICR_GPIO GPIO Interrupt Clear 0 8 write-only GPIOA_AHBIEV GPIO Interrupt Event 0x40C read-write n 0x0 0x0 GPIOA_AHBIM GPIO Interrupt Mask 0x410 read-write n 0x0 0x0 GPIO_IM_DMAIME GPIO uDMA Done Interrupt Mask Enable 8 9 GPIO_IM_GPIO GPIO Interrupt Mask Enable 0 8 GPIOA_AHBIS GPIO Interrupt Sense 0x404 read-write n 0x0 0x0 GPIOA_AHBLOCK GPIO Lock 0x520 read-write n 0x0 0x0 GPIO_LOCK GPIO Lock 0 32 GPIO_LOCK_UNLOCKED The GPIOCR register is unlocked and may be modified 0x0 GPIO_LOCK_LOCKED The GPIOCR register is locked and may not be modified 0x1 GPIO_LOCK_KEY Unlocks the GPIO_CR register 0x4c4f434b GPIOA_AHBMIS GPIO Masked Interrupt Status 0x418 read-write n 0x0 0x0 GPIO_MIS_DMAMIS GPIO uDMA Done Masked Interrupt Status 8 9 GPIO_MIS_GPIO GPIO Masked Interrupt Status 0 8 GPIOA_AHBODR GPIO Open Drain Select 0x50C read-write n 0x0 0x0 GPIOA_AHBPC GPIO Peripheral Configuration 0xFC4 read-write n 0x0 0x0 GPIO_PC_EDM0 Extended Drive Mode Bit 0 0 2 GPIO_PC_EDM0_DISABLE Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive Select (GPIODRnR) registers function as normal 0x0 GPIO_PC_EDM0_6MA An additional 6 mA option is provided 0x1 GPIO_PC_EDM0_PLUS2MA A 2 mA driver is always enabled; setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R of GPIODR12R register bit adds an additional 4 mA 0x3 GPIO_PC_EDM1 Extended Drive Mode Bit 1 2 4 GPIO_PC_EDM2 Extended Drive Mode Bit 2 4 6 GPIO_PC_EDM3 Extended Drive Mode Bit 3 6 8 GPIO_PC_EDM4 Extended Drive Mode Bit 4 8 10 GPIO_PC_EDM5 Extended Drive Mode Bit 5 10 12 GPIO_PC_EDM6 Extended Drive Mode Bit 6 12 14 GPIO_PC_EDM7 Extended Drive Mode Bit 7 14 16 GPIOA_AHBPCTL GPIO Port Control 0x52C read-write n 0x0 0x0 GPIOA_AHBPDR GPIO Pull-Down Select 0x514 read-write n 0x0 0x0 GPIOA_AHBPP GPIO Peripheral Property 0xFC0 read-write n 0x0 0x0 GPIO_PP_EDE Extended Drive Enable 0 1 GPIOA_AHBPUR GPIO Pull-Up Select 0x510 read-write n 0x0 0x0 GPIOA_AHBRIS GPIO Raw Interrupt Status 0x414 read-write n 0x0 0x0 GPIO_RIS_DMARIS GPIO uDMA Done Interrupt Raw Status 8 9 GPIO_RIS_GPIO GPIO Interrupt Raw Status 0 8 GPIOA_AHBSI GPIO Select Interrupt 0x538 read-write n 0x0 0x0 GPIO_SI_SUM Summary Interrupt 0 1 GPIOA_AHBSLR GPIO Slew Rate Control Select 0x518 read-write n 0x0 0x0 GPIOA_AHBWAKELVL GPIO Wake Level 0x544 read-write n 0x0 0x0 GPIO_WAKELVL_WAKELVL4 P[4] Wake Level 4 5 GPIOA_AHBWAKEPEN GPIO Wake Pin Enable 0x540 read-write n 0x0 0x0 GPIO_WAKEPEN_WAKEP4 P[4] Wake Enable 4 5 GPIOA_AHBWAKESTAT GPIO Wake Status 0x548 read-write n 0x0 0x0 GPIO_WAKESTAT_STAT4 P[4] Wake Status 4 5 IBE GPIO Interrupt Both Edges 0x408 -1 read-write n 0x0 0x0 ICR GPIO Interrupt Clear 0x41C -1 write-only n 0x0 0x0 GPIO_ICR_DMAIC GPIO uDMA Interrupt Clear 8 9 write-only GPIO_ICR_GPIO GPIO Interrupt Clear 0 8 write-only IEV GPIO Interrupt Event 0x40C -1 read-write n 0x0 0x0 IM GPIO Interrupt Mask 0x410 -1 read-write n 0x0 0x0 GPIO_IM_DMAIME GPIO uDMA Done Interrupt Mask Enable 8 9 GPIO_IM_GPIO GPIO Interrupt Mask Enable 0 8 IS GPIO Interrupt Sense 0x404 -1 read-write n 0x0 0x0 LOCK GPIO Lock 0x520 -1 read-write n 0x0 0x0 GPIO_LOCK GPIO Lock 0 32 GPIO_LOCK_UNLOCKED The GPIOCR register is unlocked and may be modified 0x0 GPIO_LOCK_LOCKED The GPIOCR register is locked and may not be modified 0x1 GPIO_LOCK_KEY Unlocks the GPIO_CR register 0x4c4f434b MIS GPIO Masked Interrupt Status 0x418 -1 read-write n 0x0 0x0 GPIO_MIS_DMAMIS GPIO uDMA Done Masked Interrupt Status 8 9 GPIO_MIS_GPIO GPIO Masked Interrupt Status 0 8 ODR GPIO Open Drain Select 0x50C -1 read-write n 0x0 0x0 PC GPIO Peripheral Configuration 0xFC4 -1 read-write n 0x0 0x0 GPIO_PC_EDM0 Extended Drive Mode Bit 0 0 2 GPIO_PC_EDM0_DISABLE Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive Select (GPIODRnR) registers function as normal 0x0 GPIO_PC_EDM0_6MA An additional 6 mA option is provided 0x1 GPIO_PC_EDM0_PLUS2MA A 2 mA driver is always enabled setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R of GPIODR12R register bit adds an additional 4 mA 0x3 GPIO_PC_EDM1 Extended Drive Mode Bit 1 2 4 GPIO_PC_EDM2 Extended Drive Mode Bit 2 4 6 GPIO_PC_EDM3 Extended Drive Mode Bit 3 6 8 GPIO_PC_EDM4 Extended Drive Mode Bit 4 8 10 GPIO_PC_EDM5 Extended Drive Mode Bit 5 10 12 GPIO_PC_EDM6 Extended Drive Mode Bit 6 12 14 GPIO_PC_EDM7 Extended Drive Mode Bit 7 14 16 PCTL GPIO Port Control 0x52C -1 read-write n 0x0 0x0 PDR GPIO Pull-Down Select 0x514 -1 read-write n 0x0 0x0 PP GPIO Peripheral Property 0xFC0 -1 read-write n 0x0 0x0 GPIO_PP_EDE Extended Drive Enable 0 1 PUR GPIO Pull-Up Select 0x510 -1 read-write n 0x0 0x0 RIS GPIO Raw Interrupt Status 0x414 -1 read-write n 0x0 0x0 GPIO_RIS_DMARIS GPIO uDMA Done Interrupt Raw Status 8 9 GPIO_RIS_GPIO GPIO Interrupt Raw Status 0 8 SI GPIO Select Interrupt 0x538 -1 read-write n 0x0 0x0 GPIO_SI_SUM Summary Interrupt 0 1 SLR GPIO Slew Rate Control Select 0x518 -1 read-write n 0x0 0x0 WAKELVL GPIO Wake Level 0x544 -1 read-write n 0x0 0x0 GPIO_WAKELVL_WAKELVL4 P[4] Wake Level 4 5 WAKEPEN GPIO Wake Pin Enable 0x540 -1 read-write n 0x0 0x0 GPIO_WAKEPEN_WAKEP4 P[4] Wake Enable 4 5 WAKESTAT GPIO Wake Status 0x548 -1 read-write n 0x0 0x0 GPIO_WAKESTAT_STAT4 P[4] Wake Status 4 5 GPIOR Register map for GPIOA_AHB peripheral GPIO 0x0 0x0 0x1000 registers n GPIOR 92 ADCCTL GPIO ADC Control 0x530 -1 read-write n 0x0 0x0 AFSEL GPIO Alternate Function Select 0x420 -1 read-write n 0x0 0x0 AMSEL GPIO Analog Mode Select 0x528 -1 read-write n 0x0 0x0 CR GPIO Commit 0x524 -1 read-only n 0x0 0x0 DATA GPIO Data 0x3FC -1 read-write n 0x0 0x0 DEN GPIO Digital Enable 0x51C -1 read-write n 0x0 0x0 DIR GPIO Direction 0x400 -1 read-write n 0x0 0x0 DMACTL GPIO DMA Control 0x534 -1 read-write n 0x0 0x0 DR12R GPIO 12-mA Drive Select 0x53C -1 read-write n 0x0 0x0 GPIO_DR12R_DRV12 Output Pad 12-mA Drive Enable 0 8 GPIO_DR12R_DRV12_12MA The corresponding GPIO pin has 12-mA drive. This encoding is only valid if the GPIOPP EDE bit is set and the appropriate GPIOPC EDM bit field is programmed to 0x3 0x1 DR2R GPIO 2-mA Drive Select 0x500 -1 read-write n 0x0 0x0 DR4R GPIO 4-mA Drive Select 0x504 -1 read-write n 0x0 0x0 DR8R GPIO 8-mA Drive Select 0x508 -1 read-write n 0x0 0x0 GPIOA_AHBADCCTL GPIO ADC Control 0x530 read-write n 0x0 0x0 GPIOA_AHBAFSEL GPIO Alternate Function Select 0x420 read-write n 0x0 0x0 GPIOA_AHBAMSEL GPIO Analog Mode Select 0x528 read-write n 0x0 0x0 GPIOA_AHBCR GPIO Commit 0x524 read-only n 0x0 0x0 GPIOA_AHBDATA GPIO Data 0x3FC read-write n 0x0 0x0 GPIOA_AHBDEN GPIO Digital Enable 0x51C read-write n 0x0 0x0 GPIOA_AHBDIR GPIO Direction 0x400 read-write n 0x0 0x0 GPIOA_AHBDMACTL GPIO DMA Control 0x534 read-write n 0x0 0x0 GPIOA_AHBDR12R GPIO 12-mA Drive Select 0x53C read-write n 0x0 0x0 GPIO_DR12R_DRV12 Output Pad 12-mA Drive Enable 0 8 GPIO_DR12R_DRV12_12MA The corresponding GPIO pin has 12-mA drive. This encoding is only valid if the GPIOPP EDE bit is set and the appropriate GPIOPC EDM bit field is programmed to 0x3 0x1 GPIOA_AHBDR2R GPIO 2-mA Drive Select 0x500 read-write n 0x0 0x0 GPIOA_AHBDR4R GPIO 4-mA Drive Select 0x504 read-write n 0x0 0x0 GPIOA_AHBDR8R GPIO 8-mA Drive Select 0x508 read-write n 0x0 0x0 GPIOA_AHBIBE GPIO Interrupt Both Edges 0x408 read-write n 0x0 0x0 GPIOA_AHBICR GPIO Interrupt Clear 0x41C write-only n 0x0 0x0 GPIO_ICR_DMAIC GPIO uDMA Interrupt Clear 8 9 write-only GPIO_ICR_GPIO GPIO Interrupt Clear 0 8 write-only GPIOA_AHBIEV GPIO Interrupt Event 0x40C read-write n 0x0 0x0 GPIOA_AHBIM GPIO Interrupt Mask 0x410 read-write n 0x0 0x0 GPIO_IM_DMAIME GPIO uDMA Done Interrupt Mask Enable 8 9 GPIO_IM_GPIO GPIO Interrupt Mask Enable 0 8 GPIOA_AHBIS GPIO Interrupt Sense 0x404 read-write n 0x0 0x0 GPIOA_AHBLOCK GPIO Lock 0x520 read-write n 0x0 0x0 GPIO_LOCK GPIO Lock 0 32 GPIO_LOCK_UNLOCKED The GPIOCR register is unlocked and may be modified 0x0 GPIO_LOCK_LOCKED The GPIOCR register is locked and may not be modified 0x1 GPIO_LOCK_KEY Unlocks the GPIO_CR register 0x4c4f434b GPIOA_AHBMIS GPIO Masked Interrupt Status 0x418 read-write n 0x0 0x0 GPIO_MIS_DMAMIS GPIO uDMA Done Masked Interrupt Status 8 9 GPIO_MIS_GPIO GPIO Masked Interrupt Status 0 8 GPIOA_AHBODR GPIO Open Drain Select 0x50C read-write n 0x0 0x0 GPIOA_AHBPC GPIO Peripheral Configuration 0xFC4 read-write n 0x0 0x0 GPIO_PC_EDM0 Extended Drive Mode Bit 0 0 2 GPIO_PC_EDM0_DISABLE Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive Select (GPIODRnR) registers function as normal 0x0 GPIO_PC_EDM0_6MA An additional 6 mA option is provided 0x1 GPIO_PC_EDM0_PLUS2MA A 2 mA driver is always enabled; setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R of GPIODR12R register bit adds an additional 4 mA 0x3 GPIO_PC_EDM1 Extended Drive Mode Bit 1 2 4 GPIO_PC_EDM2 Extended Drive Mode Bit 2 4 6 GPIO_PC_EDM3 Extended Drive Mode Bit 3 6 8 GPIO_PC_EDM4 Extended Drive Mode Bit 4 8 10 GPIO_PC_EDM5 Extended Drive Mode Bit 5 10 12 GPIO_PC_EDM6 Extended Drive Mode Bit 6 12 14 GPIO_PC_EDM7 Extended Drive Mode Bit 7 14 16 GPIOA_AHBPCTL GPIO Port Control 0x52C read-write n 0x0 0x0 GPIOA_AHBPDR GPIO Pull-Down Select 0x514 read-write n 0x0 0x0 GPIOA_AHBPP GPIO Peripheral Property 0xFC0 read-write n 0x0 0x0 GPIO_PP_EDE Extended Drive Enable 0 1 GPIOA_AHBPUR GPIO Pull-Up Select 0x510 read-write n 0x0 0x0 GPIOA_AHBRIS GPIO Raw Interrupt Status 0x414 read-write n 0x0 0x0 GPIO_RIS_DMARIS GPIO uDMA Done Interrupt Raw Status 8 9 GPIO_RIS_GPIO GPIO Interrupt Raw Status 0 8 GPIOA_AHBSI GPIO Select Interrupt 0x538 read-write n 0x0 0x0 GPIO_SI_SUM Summary Interrupt 0 1 GPIOA_AHBSLR GPIO Slew Rate Control Select 0x518 read-write n 0x0 0x0 GPIOA_AHBWAKELVL GPIO Wake Level 0x544 read-write n 0x0 0x0 GPIO_WAKELVL_WAKELVL4 P[4] Wake Level 4 5 GPIOA_AHBWAKEPEN GPIO Wake Pin Enable 0x540 read-write n 0x0 0x0 GPIO_WAKEPEN_WAKEP4 P[4] Wake Enable 4 5 GPIOA_AHBWAKESTAT GPIO Wake Status 0x548 read-write n 0x0 0x0 GPIO_WAKESTAT_STAT4 P[4] Wake Status 4 5 IBE GPIO Interrupt Both Edges 0x408 -1 read-write n 0x0 0x0 ICR GPIO Interrupt Clear 0x41C -1 write-only n 0x0 0x0 GPIO_ICR_DMAIC GPIO uDMA Interrupt Clear 8 9 write-only GPIO_ICR_GPIO GPIO Interrupt Clear 0 8 write-only IEV GPIO Interrupt Event 0x40C -1 read-write n 0x0 0x0 IM GPIO Interrupt Mask 0x410 -1 read-write n 0x0 0x0 GPIO_IM_DMAIME GPIO uDMA Done Interrupt Mask Enable 8 9 GPIO_IM_GPIO GPIO Interrupt Mask Enable 0 8 IS GPIO Interrupt Sense 0x404 -1 read-write n 0x0 0x0 LOCK GPIO Lock 0x520 -1 read-write n 0x0 0x0 GPIO_LOCK GPIO Lock 0 32 GPIO_LOCK_UNLOCKED The GPIOCR register is unlocked and may be modified 0x0 GPIO_LOCK_LOCKED The GPIOCR register is locked and may not be modified 0x1 GPIO_LOCK_KEY Unlocks the GPIO_CR register 0x4c4f434b MIS GPIO Masked Interrupt Status 0x418 -1 read-write n 0x0 0x0 GPIO_MIS_DMAMIS GPIO uDMA Done Masked Interrupt Status 8 9 GPIO_MIS_GPIO GPIO Masked Interrupt Status 0 8 ODR GPIO Open Drain Select 0x50C -1 read-write n 0x0 0x0 PC GPIO Peripheral Configuration 0xFC4 -1 read-write n 0x0 0x0 GPIO_PC_EDM0 Extended Drive Mode Bit 0 0 2 GPIO_PC_EDM0_DISABLE Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive Select (GPIODRnR) registers function as normal 0x0 GPIO_PC_EDM0_6MA An additional 6 mA option is provided 0x1 GPIO_PC_EDM0_PLUS2MA A 2 mA driver is always enabled setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R of GPIODR12R register bit adds an additional 4 mA 0x3 GPIO_PC_EDM1 Extended Drive Mode Bit 1 2 4 GPIO_PC_EDM2 Extended Drive Mode Bit 2 4 6 GPIO_PC_EDM3 Extended Drive Mode Bit 3 6 8 GPIO_PC_EDM4 Extended Drive Mode Bit 4 8 10 GPIO_PC_EDM5 Extended Drive Mode Bit 5 10 12 GPIO_PC_EDM6 Extended Drive Mode Bit 6 12 14 GPIO_PC_EDM7 Extended Drive Mode Bit 7 14 16 PCTL GPIO Port Control 0x52C -1 read-write n 0x0 0x0 PDR GPIO Pull-Down Select 0x514 -1 read-write n 0x0 0x0 PP GPIO Peripheral Property 0xFC0 -1 read-write n 0x0 0x0 GPIO_PP_EDE Extended Drive Enable 0 1 PUR GPIO Pull-Up Select 0x510 -1 read-write n 0x0 0x0 RIS GPIO Raw Interrupt Status 0x414 -1 read-write n 0x0 0x0 GPIO_RIS_DMARIS GPIO uDMA Done Interrupt Raw Status 8 9 GPIO_RIS_GPIO GPIO Interrupt Raw Status 0 8 SI GPIO Select Interrupt 0x538 -1 read-write n 0x0 0x0 GPIO_SI_SUM Summary Interrupt 0 1 SLR GPIO Slew Rate Control Select 0x518 -1 read-write n 0x0 0x0 WAKELVL GPIO Wake Level 0x544 -1 read-write n 0x0 0x0 GPIO_WAKELVL_WAKELVL4 P[4] Wake Level 4 5 WAKEPEN GPIO Wake Pin Enable 0x540 -1 read-write n 0x0 0x0 GPIO_WAKEPEN_WAKEP4 P[4] Wake Enable 4 5 WAKESTAT GPIO Wake Status 0x548 -1 read-write n 0x0 0x0 GPIO_WAKESTAT_STAT4 P[4] Wake Status 4 5 GPIOS Register map for GPIOA_AHB peripheral GPIO 0x0 0x0 0x1000 registers n GPIOS 93 ADCCTL GPIO ADC Control 0x530 -1 read-write n 0x0 0x0 AFSEL GPIO Alternate Function Select 0x420 -1 read-write n 0x0 0x0 AMSEL GPIO Analog Mode Select 0x528 -1 read-write n 0x0 0x0 CR GPIO Commit 0x524 -1 read-only n 0x0 0x0 DATA GPIO Data 0x3FC -1 read-write n 0x0 0x0 DEN GPIO Digital Enable 0x51C -1 read-write n 0x0 0x0 DIR GPIO Direction 0x400 -1 read-write n 0x0 0x0 DMACTL GPIO DMA Control 0x534 -1 read-write n 0x0 0x0 DR12R GPIO 12-mA Drive Select 0x53C -1 read-write n 0x0 0x0 GPIO_DR12R_DRV12 Output Pad 12-mA Drive Enable 0 8 GPIO_DR12R_DRV12_12MA The corresponding GPIO pin has 12-mA drive. This encoding is only valid if the GPIOPP EDE bit is set and the appropriate GPIOPC EDM bit field is programmed to 0x3 0x1 DR2R GPIO 2-mA Drive Select 0x500 -1 read-write n 0x0 0x0 DR4R GPIO 4-mA Drive Select 0x504 -1 read-write n 0x0 0x0 DR8R GPIO 8-mA Drive Select 0x508 -1 read-write n 0x0 0x0 GPIOA_AHBADCCTL GPIO ADC Control 0x530 read-write n 0x0 0x0 GPIOA_AHBAFSEL GPIO Alternate Function Select 0x420 read-write n 0x0 0x0 GPIOA_AHBAMSEL GPIO Analog Mode Select 0x528 read-write n 0x0 0x0 GPIOA_AHBCR GPIO Commit 0x524 read-only n 0x0 0x0 GPIOA_AHBDATA GPIO Data 0x3FC read-write n 0x0 0x0 GPIOA_AHBDEN GPIO Digital Enable 0x51C read-write n 0x0 0x0 GPIOA_AHBDIR GPIO Direction 0x400 read-write n 0x0 0x0 GPIOA_AHBDMACTL GPIO DMA Control 0x534 read-write n 0x0 0x0 GPIOA_AHBDR12R GPIO 12-mA Drive Select 0x53C read-write n 0x0 0x0 GPIO_DR12R_DRV12 Output Pad 12-mA Drive Enable 0 8 GPIO_DR12R_DRV12_12MA The corresponding GPIO pin has 12-mA drive. This encoding is only valid if the GPIOPP EDE bit is set and the appropriate GPIOPC EDM bit field is programmed to 0x3 0x1 GPIOA_AHBDR2R GPIO 2-mA Drive Select 0x500 read-write n 0x0 0x0 GPIOA_AHBDR4R GPIO 4-mA Drive Select 0x504 read-write n 0x0 0x0 GPIOA_AHBDR8R GPIO 8-mA Drive Select 0x508 read-write n 0x0 0x0 GPIOA_AHBIBE GPIO Interrupt Both Edges 0x408 read-write n 0x0 0x0 GPIOA_AHBICR GPIO Interrupt Clear 0x41C write-only n 0x0 0x0 GPIO_ICR_DMAIC GPIO uDMA Interrupt Clear 8 9 write-only GPIO_ICR_GPIO GPIO Interrupt Clear 0 8 write-only GPIOA_AHBIEV GPIO Interrupt Event 0x40C read-write n 0x0 0x0 GPIOA_AHBIM GPIO Interrupt Mask 0x410 read-write n 0x0 0x0 GPIO_IM_DMAIME GPIO uDMA Done Interrupt Mask Enable 8 9 GPIO_IM_GPIO GPIO Interrupt Mask Enable 0 8 GPIOA_AHBIS GPIO Interrupt Sense 0x404 read-write n 0x0 0x0 GPIOA_AHBLOCK GPIO Lock 0x520 read-write n 0x0 0x0 GPIO_LOCK GPIO Lock 0 32 GPIO_LOCK_UNLOCKED The GPIOCR register is unlocked and may be modified 0x0 GPIO_LOCK_LOCKED The GPIOCR register is locked and may not be modified 0x1 GPIO_LOCK_KEY Unlocks the GPIO_CR register 0x4c4f434b GPIOA_AHBMIS GPIO Masked Interrupt Status 0x418 read-write n 0x0 0x0 GPIO_MIS_DMAMIS GPIO uDMA Done Masked Interrupt Status 8 9 GPIO_MIS_GPIO GPIO Masked Interrupt Status 0 8 GPIOA_AHBODR GPIO Open Drain Select 0x50C read-write n 0x0 0x0 GPIOA_AHBPC GPIO Peripheral Configuration 0xFC4 read-write n 0x0 0x0 GPIO_PC_EDM0 Extended Drive Mode Bit 0 0 2 GPIO_PC_EDM0_DISABLE Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive Select (GPIODRnR) registers function as normal 0x0 GPIO_PC_EDM0_6MA An additional 6 mA option is provided 0x1 GPIO_PC_EDM0_PLUS2MA A 2 mA driver is always enabled; setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R of GPIODR12R register bit adds an additional 4 mA 0x3 GPIO_PC_EDM1 Extended Drive Mode Bit 1 2 4 GPIO_PC_EDM2 Extended Drive Mode Bit 2 4 6 GPIO_PC_EDM3 Extended Drive Mode Bit 3 6 8 GPIO_PC_EDM4 Extended Drive Mode Bit 4 8 10 GPIO_PC_EDM5 Extended Drive Mode Bit 5 10 12 GPIO_PC_EDM6 Extended Drive Mode Bit 6 12 14 GPIO_PC_EDM7 Extended Drive Mode Bit 7 14 16 GPIOA_AHBPCTL GPIO Port Control 0x52C read-write n 0x0 0x0 GPIOA_AHBPDR GPIO Pull-Down Select 0x514 read-write n 0x0 0x0 GPIOA_AHBPP GPIO Peripheral Property 0xFC0 read-write n 0x0 0x0 GPIO_PP_EDE Extended Drive Enable 0 1 GPIOA_AHBPUR GPIO Pull-Up Select 0x510 read-write n 0x0 0x0 GPIOA_AHBRIS GPIO Raw Interrupt Status 0x414 read-write n 0x0 0x0 GPIO_RIS_DMARIS GPIO uDMA Done Interrupt Raw Status 8 9 GPIO_RIS_GPIO GPIO Interrupt Raw Status 0 8 GPIOA_AHBSI GPIO Select Interrupt 0x538 read-write n 0x0 0x0 GPIO_SI_SUM Summary Interrupt 0 1 GPIOA_AHBSLR GPIO Slew Rate Control Select 0x518 read-write n 0x0 0x0 GPIOA_AHBWAKELVL GPIO Wake Level 0x544 read-write n 0x0 0x0 GPIO_WAKELVL_WAKELVL4 P[4] Wake Level 4 5 GPIOA_AHBWAKEPEN GPIO Wake Pin Enable 0x540 read-write n 0x0 0x0 GPIO_WAKEPEN_WAKEP4 P[4] Wake Enable 4 5 GPIOA_AHBWAKESTAT GPIO Wake Status 0x548 read-write n 0x0 0x0 GPIO_WAKESTAT_STAT4 P[4] Wake Status 4 5 IBE GPIO Interrupt Both Edges 0x408 -1 read-write n 0x0 0x0 ICR GPIO Interrupt Clear 0x41C -1 write-only n 0x0 0x0 GPIO_ICR_DMAIC GPIO uDMA Interrupt Clear 8 9 write-only GPIO_ICR_GPIO GPIO Interrupt Clear 0 8 write-only IEV GPIO Interrupt Event 0x40C -1 read-write n 0x0 0x0 IM GPIO Interrupt Mask 0x410 -1 read-write n 0x0 0x0 GPIO_IM_DMAIME GPIO uDMA Done Interrupt Mask Enable 8 9 GPIO_IM_GPIO GPIO Interrupt Mask Enable 0 8 IS GPIO Interrupt Sense 0x404 -1 read-write n 0x0 0x0 LOCK GPIO Lock 0x520 -1 read-write n 0x0 0x0 GPIO_LOCK GPIO Lock 0 32 GPIO_LOCK_UNLOCKED The GPIOCR register is unlocked and may be modified 0x0 GPIO_LOCK_LOCKED The GPIOCR register is locked and may not be modified 0x1 GPIO_LOCK_KEY Unlocks the GPIO_CR register 0x4c4f434b MIS GPIO Masked Interrupt Status 0x418 -1 read-write n 0x0 0x0 GPIO_MIS_DMAMIS GPIO uDMA Done Masked Interrupt Status 8 9 GPIO_MIS_GPIO GPIO Masked Interrupt Status 0 8 ODR GPIO Open Drain Select 0x50C -1 read-write n 0x0 0x0 PC GPIO Peripheral Configuration 0xFC4 -1 read-write n 0x0 0x0 GPIO_PC_EDM0 Extended Drive Mode Bit 0 0 2 GPIO_PC_EDM0_DISABLE Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive Select (GPIODRnR) registers function as normal 0x0 GPIO_PC_EDM0_6MA An additional 6 mA option is provided 0x1 GPIO_PC_EDM0_PLUS2MA A 2 mA driver is always enabled setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R of GPIODR12R register bit adds an additional 4 mA 0x3 GPIO_PC_EDM1 Extended Drive Mode Bit 1 2 4 GPIO_PC_EDM2 Extended Drive Mode Bit 2 4 6 GPIO_PC_EDM3 Extended Drive Mode Bit 3 6 8 GPIO_PC_EDM4 Extended Drive Mode Bit 4 8 10 GPIO_PC_EDM5 Extended Drive Mode Bit 5 10 12 GPIO_PC_EDM6 Extended Drive Mode Bit 6 12 14 GPIO_PC_EDM7 Extended Drive Mode Bit 7 14 16 PCTL GPIO Port Control 0x52C -1 read-write n 0x0 0x0 PDR GPIO Pull-Down Select 0x514 -1 read-write n 0x0 0x0 PP GPIO Peripheral Property 0xFC0 -1 read-write n 0x0 0x0 GPIO_PP_EDE Extended Drive Enable 0 1 PUR GPIO Pull-Up Select 0x510 -1 read-write n 0x0 0x0 RIS GPIO Raw Interrupt Status 0x414 -1 read-write n 0x0 0x0 GPIO_RIS_DMARIS GPIO uDMA Done Interrupt Raw Status 8 9 GPIO_RIS_GPIO GPIO Interrupt Raw Status 0 8 SI GPIO Select Interrupt 0x538 -1 read-write n 0x0 0x0 GPIO_SI_SUM Summary Interrupt 0 1 SLR GPIO Slew Rate Control Select 0x518 -1 read-write n 0x0 0x0 WAKELVL GPIO Wake Level 0x544 -1 read-write n 0x0 0x0 GPIO_WAKELVL_WAKELVL4 P[4] Wake Level 4 5 WAKEPEN GPIO Wake Pin Enable 0x540 -1 read-write n 0x0 0x0 GPIO_WAKEPEN_WAKEP4 P[4] Wake Enable 4 5 WAKESTAT GPIO Wake Status 0x548 -1 read-write n 0x0 0x0 GPIO_WAKESTAT_STAT4 P[4] Wake Status 4 5 GPIOT Register map for GPIOA_AHB peripheral GPIO 0x0 0x0 0x1000 registers n GPIOT 111 ADCCTL GPIO ADC Control 0x530 -1 read-write n 0x0 0x0 AFSEL GPIO Alternate Function Select 0x420 -1 read-write n 0x0 0x0 AMSEL GPIO Analog Mode Select 0x528 -1 read-write n 0x0 0x0 CR GPIO Commit 0x524 -1 read-only n 0x0 0x0 DATA GPIO Data 0x3FC -1 read-write n 0x0 0x0 DEN GPIO Digital Enable 0x51C -1 read-write n 0x0 0x0 DIR GPIO Direction 0x400 -1 read-write n 0x0 0x0 DMACTL GPIO DMA Control 0x534 -1 read-write n 0x0 0x0 DR12R GPIO 12-mA Drive Select 0x53C -1 read-write n 0x0 0x0 GPIO_DR12R_DRV12 Output Pad 12-mA Drive Enable 0 8 GPIO_DR12R_DRV12_12MA The corresponding GPIO pin has 12-mA drive. This encoding is only valid if the GPIOPP EDE bit is set and the appropriate GPIOPC EDM bit field is programmed to 0x3 0x1 DR2R GPIO 2-mA Drive Select 0x500 -1 read-write n 0x0 0x0 DR4R GPIO 4-mA Drive Select 0x504 -1 read-write n 0x0 0x0 DR8R GPIO 8-mA Drive Select 0x508 -1 read-write n 0x0 0x0 GPIOA_AHBADCCTL GPIO ADC Control 0x530 read-write n 0x0 0x0 GPIOA_AHBAFSEL GPIO Alternate Function Select 0x420 read-write n 0x0 0x0 GPIOA_AHBAMSEL GPIO Analog Mode Select 0x528 read-write n 0x0 0x0 GPIOA_AHBCR GPIO Commit 0x524 read-only n 0x0 0x0 GPIOA_AHBDATA GPIO Data 0x3FC read-write n 0x0 0x0 GPIOA_AHBDEN GPIO Digital Enable 0x51C read-write n 0x0 0x0 GPIOA_AHBDIR GPIO Direction 0x400 read-write n 0x0 0x0 GPIOA_AHBDMACTL GPIO DMA Control 0x534 read-write n 0x0 0x0 GPIOA_AHBDR12R GPIO 12-mA Drive Select 0x53C read-write n 0x0 0x0 GPIO_DR12R_DRV12 Output Pad 12-mA Drive Enable 0 8 GPIO_DR12R_DRV12_12MA The corresponding GPIO pin has 12-mA drive. This encoding is only valid if the GPIOPP EDE bit is set and the appropriate GPIOPC EDM bit field is programmed to 0x3 0x1 GPIOA_AHBDR2R GPIO 2-mA Drive Select 0x500 read-write n 0x0 0x0 GPIOA_AHBDR4R GPIO 4-mA Drive Select 0x504 read-write n 0x0 0x0 GPIOA_AHBDR8R GPIO 8-mA Drive Select 0x508 read-write n 0x0 0x0 GPIOA_AHBIBE GPIO Interrupt Both Edges 0x408 read-write n 0x0 0x0 GPIOA_AHBICR GPIO Interrupt Clear 0x41C write-only n 0x0 0x0 GPIO_ICR_DMAIC GPIO uDMA Interrupt Clear 8 9 write-only GPIO_ICR_GPIO GPIO Interrupt Clear 0 8 write-only GPIOA_AHBIEV GPIO Interrupt Event 0x40C read-write n 0x0 0x0 GPIOA_AHBIM GPIO Interrupt Mask 0x410 read-write n 0x0 0x0 GPIO_IM_DMAIME GPIO uDMA Done Interrupt Mask Enable 8 9 GPIO_IM_GPIO GPIO Interrupt Mask Enable 0 8 GPIOA_AHBIS GPIO Interrupt Sense 0x404 read-write n 0x0 0x0 GPIOA_AHBLOCK GPIO Lock 0x520 read-write n 0x0 0x0 GPIO_LOCK GPIO Lock 0 32 GPIO_LOCK_UNLOCKED The GPIOCR register is unlocked and may be modified 0x0 GPIO_LOCK_LOCKED The GPIOCR register is locked and may not be modified 0x1 GPIO_LOCK_KEY Unlocks the GPIO_CR register 0x4c4f434b GPIOA_AHBMIS GPIO Masked Interrupt Status 0x418 read-write n 0x0 0x0 GPIO_MIS_DMAMIS GPIO uDMA Done Masked Interrupt Status 8 9 GPIO_MIS_GPIO GPIO Masked Interrupt Status 0 8 GPIOA_AHBODR GPIO Open Drain Select 0x50C read-write n 0x0 0x0 GPIOA_AHBPC GPIO Peripheral Configuration 0xFC4 read-write n 0x0 0x0 GPIO_PC_EDM0 Extended Drive Mode Bit 0 0 2 GPIO_PC_EDM0_DISABLE Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive Select (GPIODRnR) registers function as normal 0x0 GPIO_PC_EDM0_6MA An additional 6 mA option is provided 0x1 GPIO_PC_EDM0_PLUS2MA A 2 mA driver is always enabled; setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R of GPIODR12R register bit adds an additional 4 mA 0x3 GPIO_PC_EDM1 Extended Drive Mode Bit 1 2 4 GPIO_PC_EDM2 Extended Drive Mode Bit 2 4 6 GPIO_PC_EDM3 Extended Drive Mode Bit 3 6 8 GPIO_PC_EDM4 Extended Drive Mode Bit 4 8 10 GPIO_PC_EDM5 Extended Drive Mode Bit 5 10 12 GPIO_PC_EDM6 Extended Drive Mode Bit 6 12 14 GPIO_PC_EDM7 Extended Drive Mode Bit 7 14 16 GPIOA_AHBPCTL GPIO Port Control 0x52C read-write n 0x0 0x0 GPIOA_AHBPDR GPIO Pull-Down Select 0x514 read-write n 0x0 0x0 GPIOA_AHBPP GPIO Peripheral Property 0xFC0 read-write n 0x0 0x0 GPIO_PP_EDE Extended Drive Enable 0 1 GPIOA_AHBPUR GPIO Pull-Up Select 0x510 read-write n 0x0 0x0 GPIOA_AHBRIS GPIO Raw Interrupt Status 0x414 read-write n 0x0 0x0 GPIO_RIS_DMARIS GPIO uDMA Done Interrupt Raw Status 8 9 GPIO_RIS_GPIO GPIO Interrupt Raw Status 0 8 GPIOA_AHBSI GPIO Select Interrupt 0x538 read-write n 0x0 0x0 GPIO_SI_SUM Summary Interrupt 0 1 GPIOA_AHBSLR GPIO Slew Rate Control Select 0x518 read-write n 0x0 0x0 GPIOA_AHBWAKELVL GPIO Wake Level 0x544 read-write n 0x0 0x0 GPIO_WAKELVL_WAKELVL4 P[4] Wake Level 4 5 GPIOA_AHBWAKEPEN GPIO Wake Pin Enable 0x540 read-write n 0x0 0x0 GPIO_WAKEPEN_WAKEP4 P[4] Wake Enable 4 5 GPIOA_AHBWAKESTAT GPIO Wake Status 0x548 read-write n 0x0 0x0 GPIO_WAKESTAT_STAT4 P[4] Wake Status 4 5 IBE GPIO Interrupt Both Edges 0x408 -1 read-write n 0x0 0x0 ICR GPIO Interrupt Clear 0x41C -1 write-only n 0x0 0x0 GPIO_ICR_DMAIC GPIO uDMA Interrupt Clear 8 9 write-only GPIO_ICR_GPIO GPIO Interrupt Clear 0 8 write-only IEV GPIO Interrupt Event 0x40C -1 read-write n 0x0 0x0 IM GPIO Interrupt Mask 0x410 -1 read-write n 0x0 0x0 GPIO_IM_DMAIME GPIO uDMA Done Interrupt Mask Enable 8 9 GPIO_IM_GPIO GPIO Interrupt Mask Enable 0 8 IS GPIO Interrupt Sense 0x404 -1 read-write n 0x0 0x0 LOCK GPIO Lock 0x520 -1 read-write n 0x0 0x0 GPIO_LOCK GPIO Lock 0 32 GPIO_LOCK_UNLOCKED The GPIOCR register is unlocked and may be modified 0x0 GPIO_LOCK_LOCKED The GPIOCR register is locked and may not be modified 0x1 GPIO_LOCK_KEY Unlocks the GPIO_CR register 0x4c4f434b MIS GPIO Masked Interrupt Status 0x418 -1 read-write n 0x0 0x0 GPIO_MIS_DMAMIS GPIO uDMA Done Masked Interrupt Status 8 9 GPIO_MIS_GPIO GPIO Masked Interrupt Status 0 8 ODR GPIO Open Drain Select 0x50C -1 read-write n 0x0 0x0 PC GPIO Peripheral Configuration 0xFC4 -1 read-write n 0x0 0x0 GPIO_PC_EDM0 Extended Drive Mode Bit 0 0 2 GPIO_PC_EDM0_DISABLE Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive Select (GPIODRnR) registers function as normal 0x0 GPIO_PC_EDM0_6MA An additional 6 mA option is provided 0x1 GPIO_PC_EDM0_PLUS2MA A 2 mA driver is always enabled setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R of GPIODR12R register bit adds an additional 4 mA 0x3 GPIO_PC_EDM1 Extended Drive Mode Bit 1 2 4 GPIO_PC_EDM2 Extended Drive Mode Bit 2 4 6 GPIO_PC_EDM3 Extended Drive Mode Bit 3 6 8 GPIO_PC_EDM4 Extended Drive Mode Bit 4 8 10 GPIO_PC_EDM5 Extended Drive Mode Bit 5 10 12 GPIO_PC_EDM6 Extended Drive Mode Bit 6 12 14 GPIO_PC_EDM7 Extended Drive Mode Bit 7 14 16 PCTL GPIO Port Control 0x52C -1 read-write n 0x0 0x0 PDR GPIO Pull-Down Select 0x514 -1 read-write n 0x0 0x0 PP GPIO Peripheral Property 0xFC0 -1 read-write n 0x0 0x0 GPIO_PP_EDE Extended Drive Enable 0 1 PUR GPIO Pull-Up Select 0x510 -1 read-write n 0x0 0x0 RIS GPIO Raw Interrupt Status 0x414 -1 read-write n 0x0 0x0 GPIO_RIS_DMARIS GPIO uDMA Done Interrupt Raw Status 8 9 GPIO_RIS_GPIO GPIO Interrupt Raw Status 0 8 SI GPIO Select Interrupt 0x538 -1 read-write n 0x0 0x0 GPIO_SI_SUM Summary Interrupt 0 1 SLR GPIO Slew Rate Control Select 0x518 -1 read-write n 0x0 0x0 WAKELVL GPIO Wake Level 0x544 -1 read-write n 0x0 0x0 GPIO_WAKELVL_WAKELVL4 P[4] Wake Level 4 5 WAKEPEN GPIO Wake Pin Enable 0x540 -1 read-write n 0x0 0x0 GPIO_WAKEPEN_WAKEP4 P[4] Wake Enable 4 5 WAKESTAT GPIO Wake Status 0x548 -1 read-write n 0x0 0x0 GPIO_WAKESTAT_STAT4 P[4] Wake Status 4 5 HIB Register map for HIB peripheral HIB 0x0 0x0 0x1000 registers n HIB 41 CAL0 Hibernation Calendar 0 0x310 -1 read-write n 0x0 0x0 HIB_CAL0_AMPM AM/PM Designation 22 23 HIB_CAL0_HR Hours 16 21 HIB_CAL0_MIN Minutes 8 14 HIB_CAL0_SEC Seconds 0 6 HIB_CAL0_VALID Valid Calendar Load 31 32 CAL1 Hibernation Calendar 1 0x314 -1 read-write n 0x0 0x0 HIB_CAL1_DOM Day of Month 0 5 HIB_CAL1_DOW Day of Week 24 27 HIB_CAL1_MON Month 8 12 HIB_CAL1_VALID Valid Calendar Load 31 32 HIB_CAL1_YEAR Year Value 16 23 CALCTL Hibernation Calendar Control 0x300 -1 read-write n 0x0 0x0 HIB_CALCTL_CAL24 Calendar Mode 2 3 HIB_CALCTL_CALEN RTC Calendar/Counter Mode Select 0 1 CALLD0 Hibernation Calendar Load 0 0x320 -1 write-only n 0x0 0x0 HIB_CALLD0_AMPM AM/PM Designation 22 23 write-only HIB_CALLD0_HR Hours 16 21 write-only HIB_CALLD0_MIN Minutes 8 14 write-only HIB_CALLD0_SEC Seconds 0 6 write-only CALLD1 Hibernation Calendar Load 0x324 -1 write-only n 0x0 0x0 HIB_CALLD1_DOM Day of Month 0 5 write-only HIB_CALLD1_DOW Day of Week 24 27 write-only HIB_CALLD1_MON Month 8 12 write-only HIB_CALLD1_YEAR Year Value 16 23 write-only CALM0 Hibernation Calendar Match 0 0x330 -1 read-write n 0x0 0x0 HIB_CALM0_AMPM AM/PM Designation 22 23 HIB_CALM0_HR Hours 16 21 HIB_CALM0_MIN Minutes 8 14 HIB_CALM0_SEC Seconds 0 6 CALM1 Hibernation Calendar Match 1 0x334 -1 read-write n 0x0 0x0 HIB_CALM1_DOM Day of Month 0 5 CC Hibernation Clock Control 0xFC8 -1 read-write n 0x0 0x0 HIB_CC_SYSCLKEN RTCOSC to System Clock Enable 0 1 CTL Hibernation Control 0x10 -1 read-write n 0x0 0x0 HIB_CTL_BATCHK Check Battery Status 10 11 HIB_CTL_BATWKEN Wake on Low Battery 9 10 HIB_CTL_CLK32EN Clocking Enable 6 7 HIB_CTL_HIBREQ Hibernation Request 1 2 HIB_CTL_OSCBYP Oscillator Bypass 16 17 HIB_CTL_OSCDRV Oscillator Drive Capability 17 18 HIB_CTL_OSCSEL Oscillator Select 19 20 HIB_CTL_PINWEN External Wake Pin Enable 4 5 HIB_CTL_RETCLR GPIO Retention/Clear 30 31 HIB_CTL_RTCEN RTC Timer Enable 0 1 HIB_CTL_RTCWEN RTC Wake-up Enable 3 4 HIB_CTL_VABORT Power Cut Abort Enable 7 8 HIB_CTL_VBATSEL Select for Low-Battery Comparator 13 15 HIB_CTL_VBATSEL_1_9V 1.9 Volts 0x0 HIB_CTL_VBATSEL_2_1V 2.1 Volts (default) 0x1 HIB_CTL_VBATSEL_2_3V 2.3 Volts 0x2 HIB_CTL_VBATSEL_2_5V 2.5 Volts 0x3 HIB_CTL_VDD3ON VDD Powered 8 9 HIB_CTL_WRC Write Complete/Capable 31 32 DATA Hibernation Data 0x30 -1 read-write n 0x0 0x0 HIB_DATA_RTD Hibernation Module NV Data 0 32 HIBCAL0 Hibernation Calendar 0 0x310 read-write n 0x0 0x0 HIB_CAL0_AMPM AM/PM Designation 22 23 HIB_CAL0_HR Hours 16 21 HIB_CAL0_MIN Minutes 8 14 HIB_CAL0_SEC Seconds 0 6 HIB_CAL0_VALID Valid Calendar Load 31 32 HIBCAL1 Hibernation Calendar 1 0x314 read-write n 0x0 0x0 HIB_CAL1_DOM Day of Month 0 5 HIB_CAL1_DOW Day of Week 24 27 HIB_CAL1_MON Month 8 12 HIB_CAL1_VALID Valid Calendar Load 31 32 HIB_CAL1_YEAR Year Value 16 23 HIBCALCTL Hibernation Calendar Control 0x300 read-write n 0x0 0x0 HIB_CALCTL_CAL24 Calendar Mode 2 3 HIB_CALCTL_CALEN RTC Calendar/Counter Mode Select 0 1 HIBCALLD0 Hibernation Calendar Load 0 0x320 write-only n 0x0 0x0 HIB_CALLD0_AMPM AM/PM Designation 22 23 write-only HIB_CALLD0_HR Hours 16 21 write-only HIB_CALLD0_MIN Minutes 8 14 write-only HIB_CALLD0_SEC Seconds 0 6 write-only HIBCALLD1 Hibernation Calendar Load 0x324 write-only n 0x0 0x0 HIB_CALLD1_DOM Day of Month 0 5 write-only HIB_CALLD1_DOW Day of Week 24 27 write-only HIB_CALLD1_MON Month 8 12 write-only HIB_CALLD1_YEAR Year Value 16 23 write-only HIBCALM0 Hibernation Calendar Match 0 0x330 read-write n 0x0 0x0 HIB_CALM0_AMPM AM/PM Designation 22 23 HIB_CALM0_HR Hours 16 21 HIB_CALM0_MIN Minutes 8 14 HIB_CALM0_SEC Seconds 0 6 HIBCALM1 Hibernation Calendar Match 1 0x334 read-write n 0x0 0x0 HIB_CALM1_DOM Day of Month 0 5 HIBCC Hibernation Clock Control 0xFC8 read-write n 0x0 0x0 HIB_CC_SYSCLKEN RTCOSC to System Clock Enable 0 1 HIBCTL Hibernation Control 0x10 read-write n 0x0 0x0 HIB_CTL_BATCHK Check Battery Status 10 11 HIB_CTL_BATWKEN Wake on Low Battery 9 10 HIB_CTL_CLK32EN Clocking Enable 6 7 HIB_CTL_HIBREQ Hibernation Request 1 2 HIB_CTL_OSCBYP Oscillator Bypass 16 17 HIB_CTL_OSCDRV Oscillator Drive Capability 17 18 HIB_CTL_OSCSEL Oscillator Select 19 20 HIB_CTL_PINWEN External Wake Pin Enable 4 5 HIB_CTL_RETCLR GPIO Retention/Clear 30 31 HIB_CTL_RTCEN RTC Timer Enable 0 1 HIB_CTL_RTCWEN RTC Wake-up Enable 3 4 HIB_CTL_VABORT Power Cut Abort Enable 7 8 HIB_CTL_VBATSEL Select for Low-Battery Comparator 13 15 HIB_CTL_VBATSEL_1_9V 1.9 Volts 0x0 HIB_CTL_VBATSEL_2_1V 2.1 Volts (default) 0x1 HIB_CTL_VBATSEL_2_3V 2.3 Volts 0x2 HIB_CTL_VBATSEL_2_5V 2.5 Volts 0x3 HIB_CTL_VDD3ON VDD Powered 8 9 HIB_CTL_WRC Write Complete/Capable 31 32 HIBDATA Hibernation Data 0x30 read-write n 0x0 0x0 HIB_DATA_RTD Hibernation Module NV Data 0 32 HIBIC Hibernation Interrupt Clear 0x20 read-write n 0x0 0x0 HIB_IC_EXTW External Wake-Up Interrupt Clear 3 4 HIB_IC_LOWBAT Low Battery Voltage Interrupt Clear 2 3 HIB_IC_PADIOWK Pad I/O Wake-Up Interrupt Clear 5 6 HIB_IC_RSTWK Reset Pad I/O Wake-Up Interrupt Clear 6 7 HIB_IC_RTCALT0 RTC Alert0 Masked Interrupt Clear 0 1 HIB_IC_VDDFAIL VDD Fail Interrupt Clear 7 8 HIB_IC_WC Write Complete/Capable Interrupt Clear 4 5 HIBIM Hibernation Interrupt Mask 0x14 read-write n 0x0 0x0 HIB_IM_EXTW External Wake-Up Interrupt Mask 3 4 HIB_IM_LOWBAT Low Battery Voltage Interrupt Mask 2 3 HIB_IM_PADIOWK Pad I/O Wake-Up Interrupt Mask 5 6 HIB_IM_RSTWK Reset Pad I/O Wake-Up Interrupt Mask 6 7 HIB_IM_RTCALT0 RTC Alert 0 Interrupt Mask 0 1 HIB_IM_VDDFAIL VDD Fail Interrupt Mask 7 8 HIB_IM_WC External Write Complete/Capable Interrupt Mask 4 5 HIBIO Hibernation IO Configuration 0x2C read-write n 0x0 0x0 HIB_IO_IOWRC I/O Write Complete 31 32 HIB_IO_WURSTEN Reset Wake Source Enable 4 5 HIB_IO_WUUNLK I/O Wake Pad Configuration Enable 0 1 HIBLOCK Hibernation Lock 0x360 read-write n 0x0 0x0 HIB_LOCK_HIBLOCK HIbernate Lock 0 32 HIBMIS Hibernation Masked Interrupt Status 0x1C read-write n 0x0 0x0 HIB_MIS_EXTW External Wake-Up Masked Interrupt Status 3 4 HIB_MIS_LOWBAT Low Battery Voltage Masked Interrupt Status 2 3 HIB_MIS_PADIOWK Pad I/O Wake-Up Interrupt Mask 5 6 HIB_MIS_RSTWK Reset Pad I/O Wake-Up Interrupt Mask 6 7 HIB_MIS_RTCALT0 RTC Alert 0 Masked Interrupt Status 0 1 HIB_MIS_VDDFAIL VDD Fail Interrupt Mask 7 8 HIB_MIS_WC Write Complete/Capable Masked Interrupt Status 4 5 HIBPP Hibernation Peripheral Properties 0xFC0 read-write n 0x0 0x0 HIB_PP_TAMPER Tamper Pin Presence 1 2 HIB_PP_WAKENC Wake Pin Presence 0 1 HIBRIS Hibernation Raw Interrupt Status 0x18 read-write n 0x0 0x0 HIB_RIS_EXTW External Wake-Up Raw Interrupt Status 3 4 HIB_RIS_LOWBAT Low Battery Voltage Raw Interrupt Status 2 3 HIB_RIS_PADIOWK Pad I/O Wake-Up Raw Interrupt Status 5 6 HIB_RIS_RSTWK Reset Pad I/O Wake-Up Raw Interrupt Status 6 7 HIB_RIS_RTCALT0 RTC Alert 0 Raw Interrupt Status 0 1 HIB_RIS_VDDFAIL VDD Fail Raw Interrupt Status 7 8 HIB_RIS_WC Write Complete/Capable Raw Interrupt Status 4 5 HIBRTCC Hibernation RTC Counter 0x0 read-write n 0x0 0x0 HIB_RTCC RTC Counter 0 32 HIBRTCLD Hibernation RTC Load 0xC read-write n 0x0 0x0 HIB_RTCLD RTC Load 0 32 HIBRTCM0 Hibernation RTC Match 0 0x4 read-write n 0x0 0x0 HIB_RTCM0 RTC Match 0 0 32 HIBRTCSS Hibernation RTC Sub Seconds 0x28 read-write n 0x0 0x0 HIB_RTCSS_RTCSSC RTC Sub Seconds Count 0 15 HIB_RTCSS_RTCSSM RTC Sub Seconds Match 16 31 HIBRTCT Hibernation RTC Trim 0x24 read-write n 0x0 0x0 HIB_RTCT_TRIM RTC Trim Value 0 16 HIBTPCTL HIB Tamper Control 0x400 read-write n 0x0 0x0 HIB_TPCTL_MEMCLR HIB Memory Clear on Tamper Event 8 10 HIB_TPCTL_MEMCLR_NONE Do not Clear HIB memory on tamper event 0x0 HIB_TPCTL_MEMCLR_LOW32 Clear Lower 32 Bytes of HIB memory on tamper event 0x1 HIB_TPCTL_MEMCLR_HIGH32 Clear upper 32 Bytes of HIB memory on tamper event 0x2 HIB_TPCTL_MEMCLR_ALL Clear all HIB memory on tamper event 0x3 HIB_TPCTL_TPCLR Tamper Event Clear 4 5 HIB_TPCTL_TPEN Tamper Module Enable 0 1 HIB_TPCTL_WAKE Wake from Hibernate on a Tamper Event 11 12 HIBTPIO HIB Tamper I/O Control 0x410 read-write n 0x0 0x0 HIB_TPIO_EN0 TMPR0 Enable 0 1 HIB_TPIO_EN1 TMPR1Enable 8 9 HIB_TPIO_EN2 TMPR2 Enable 16 17 HIB_TPIO_EN3 TMPR3 Enable 24 25 HIB_TPIO_GFLTR0 TMPR0 Glitch Filtering 3 4 HIB_TPIO_GFLTR1 TMPR1 Glitch Filtering 11 12 HIB_TPIO_GFLTR2 TMPR2 Glitch Filtering 19 20 HIB_TPIO_GFLTR3 TMPR3 Glitch Filtering 27 28 HIB_TPIO_LEV0 TMPR0 Trigger Level 1 2 HIB_TPIO_LEV1 TMPR1 Trigger Level 9 10 HIB_TPIO_LEV2 TMPR2 Trigger Level 17 18 HIB_TPIO_LEV3 TMPR3 Trigger Level 25 26 HIB_TPIO_PUEN0 TMPR0 Internal Weak Pull-up Enable 2 3 HIB_TPIO_PUEN1 TMPR1 Internal Weak Pull-up Enable 10 11 HIB_TPIO_PUEN2 TMPR2 Internal Weak Pull-up Enable 18 19 HIB_TPIO_PUEN3 TMPR3 Internal Weak Pull-up Enable 26 27 HIBTPLOG0 HIB Tamper Log 0 0x4E0 read-write n 0x0 0x0 HIB_TPLOG0_TIME Tamper Log Calendar Information 0 32 HIBTPLOG1 HIB Tamper Log 1 0x4E4 read-write n 0x0 0x0 HIB_TPLOG1_TRIG0 Status of TMPR[0] Trigger 0 1 HIB_TPLOG1_TRIG1 Status of TMPR[1] Trigger 1 2 HIB_TPLOG1_TRIG2 Status of TMPR[2] Trigger 2 3 HIB_TPLOG1_TRIG3 Status of TMPR[3] Trigger 3 4 HIB_TPLOG1_XOSC Status of external 32 16 17 HIBTPLOG2 HIB Tamper Log 2 0x4E8 read-write n 0x0 0x0 HIB_TPLOG2_TIME Tamper Log Calendar Information 0 32 HIBTPLOG3 HIB Tamper Log 3 0x4EC read-write n 0x0 0x0 HIB_TPLOG3_TRIG0 Status of TMPR[0] Trigger 0 1 HIB_TPLOG3_TRIG1 Status of TMPR[1] Trigger 1 2 HIB_TPLOG3_TRIG2 Status of TMPR[2] Trigger 2 3 HIB_TPLOG3_TRIG3 Status of TMPR[3] Trigger 3 4 HIB_TPLOG3_XOSC Status of external 32 16 17 HIBTPLOG4 HIB Tamper Log 4 0x4F0 read-write n 0x0 0x0 HIB_TPLOG4_TIME Tamper Log Calendar Information 0 32 HIBTPLOG5 HIB Tamper Log 5 0x4F4 read-write n 0x0 0x0 HIB_TPLOG5_TRIG0 Status of TMPR[0] Trigger 0 1 HIB_TPLOG5_TRIG1 Status of TMPR[1] Trigger 1 2 HIB_TPLOG5_TRIG2 Status of TMPR[2] Trigger 2 3 HIB_TPLOG5_TRIG3 Status of TMPR[3] Trigger 3 4 HIB_TPLOG5_XOSC Status of external 32 16 17 HIBTPLOG6 HIB Tamper Log 6 0x4F8 read-write n 0x0 0x0 HIB_TPLOG6_TIME Tamper Log Calendar Information 0 32 HIBTPLOG7 HIB Tamper Log 7 0x4FC read-write n 0x0 0x0 HIB_TPLOG7_TRIG0 Status of TMPR[0] Trigger 0 1 HIB_TPLOG7_TRIG1 Status of TMPR[1] Trigger 1 2 HIB_TPLOG7_TRIG2 Status of TMPR[2] Trigger 2 3 HIB_TPLOG7_TRIG3 Status of TMPR[3] Trigger 3 4 HIB_TPLOG7_XOSC Status of external 32 16 17 HIBTPSTAT HIB Tamper Status 0x404 read-write n 0x0 0x0 HIB_TPSTAT_STATE Tamper Module Status 2 4 HIB_TPSTAT_STATE_DISABLED Tamper disabled 0x0 HIB_TPSTAT_STATE_CONFIGED Tamper configured 0x1 HIB_TPSTAT_STATE_ERROR Tamper pin event occurred 0x2 HIB_TPSTAT_XOSCFAIL External Oscillator Failure 0 1 HIB_TPSTAT_XOSCST External Oscillator Status 1 2 IC Hibernation Interrupt Clear 0x20 -1 read-write n 0x0 0x0 HIB_IC_EXTW External Wake-Up Interrupt Clear 3 4 HIB_IC_LOWBAT Low Battery Voltage Interrupt Clear 2 3 HIB_IC_PADIOWK Pad I/O Wake-Up Interrupt Clear 5 6 HIB_IC_RSTWK Reset Pad I/O Wake-Up Interrupt Clear 6 7 HIB_IC_RTCALT0 RTC Alert0 Masked Interrupt Clear 0 1 HIB_IC_VDDFAIL VDD Fail Interrupt Clear 7 8 HIB_IC_WC Write Complete/Capable Interrupt Clear 4 5 IM Hibernation Interrupt Mask 0x14 -1 read-write n 0x0 0x0 HIB_IM_EXTW External Wake-Up Interrupt Mask 3 4 HIB_IM_LOWBAT Low Battery Voltage Interrupt Mask 2 3 HIB_IM_PADIOWK Pad I/O Wake-Up Interrupt Mask 5 6 HIB_IM_RSTWK Reset Pad I/O Wake-Up Interrupt Mask 6 7 HIB_IM_RTCALT0 RTC Alert 0 Interrupt Mask 0 1 HIB_IM_VDDFAIL VDD Fail Interrupt Mask 7 8 HIB_IM_WC External Write Complete/Capable Interrupt Mask 4 5 IO Hibernation IO Configuration 0x2C -1 read-write n 0x0 0x0 HIB_IO_IOWRC I/O Write Complete 31 32 HIB_IO_WURSTEN Reset Wake Source Enable 4 5 HIB_IO_WUUNLK I/O Wake Pad Configuration Enable 0 1 LOCK Hibernation Lock 0x360 -1 read-write n 0x0 0x0 HIB_LOCK_HIBLOCK HIbernate Lock 0 32 MIS Hibernation Masked Interrupt Status 0x1C -1 read-write n 0x0 0x0 HIB_MIS_EXTW External Wake-Up Masked Interrupt Status 3 4 HIB_MIS_LOWBAT Low Battery Voltage Masked Interrupt Status 2 3 HIB_MIS_PADIOWK Pad I/O Wake-Up Interrupt Mask 5 6 HIB_MIS_RSTWK Reset Pad I/O Wake-Up Interrupt Mask 6 7 HIB_MIS_RTCALT0 RTC Alert 0 Masked Interrupt Status 0 1 HIB_MIS_VDDFAIL VDD Fail Interrupt Mask 7 8 HIB_MIS_WC Write Complete/Capable Masked Interrupt Status 4 5 PP Hibernation Peripheral Properties 0xFC0 -1 read-write n 0x0 0x0 HIB_PP_TAMPER Tamper Pin Presence 1 2 HIB_PP_WAKENC Wake Pin Presence 0 1 RIS Hibernation Raw Interrupt Status 0x18 -1 read-write n 0x0 0x0 HIB_RIS_EXTW External Wake-Up Raw Interrupt Status 3 4 HIB_RIS_LOWBAT Low Battery Voltage Raw Interrupt Status 2 3 HIB_RIS_PADIOWK Pad I/O Wake-Up Raw Interrupt Status 5 6 HIB_RIS_RSTWK Reset Pad I/O Wake-Up Raw Interrupt Status 6 7 HIB_RIS_RTCALT0 RTC Alert 0 Raw Interrupt Status 0 1 HIB_RIS_VDDFAIL VDD Fail Raw Interrupt Status 7 8 HIB_RIS_WC Write Complete/Capable Raw Interrupt Status 4 5 RTCC Hibernation RTC Counter 0x0 -1 read-write n 0x0 0x0 HIB_RTCC RTC Counter 0 32 RTCLD Hibernation RTC Load 0xC -1 read-write n 0x0 0x0 HIB_RTCLD RTC Load 0 32 RTCM0 Hibernation RTC Match 0 0x4 -1 read-write n 0x0 0x0 HIB_RTCM0 RTC Match 0 0 32 RTCSS Hibernation RTC Sub Seconds 0x28 -1 read-write n 0x0 0x0 HIB_RTCSS_RTCSSC RTC Sub Seconds Count 0 15 HIB_RTCSS_RTCSSM RTC Sub Seconds Match 16 31 RTCT Hibernation RTC Trim 0x24 -1 read-write n 0x0 0x0 HIB_RTCT_TRIM RTC Trim Value 0 16 TPCTL HIB Tamper Control 0x400 -1 read-write n 0x0 0x0 HIB_TPCTL_MEMCLR HIB Memory Clear on Tamper Event 8 10 HIB_TPCTL_MEMCLR_NONE Do not Clear HIB memory on tamper event 0x0 HIB_TPCTL_MEMCLR_LOW32 Clear Lower 32 Bytes of HIB memory on tamper event 0x1 HIB_TPCTL_MEMCLR_HIGH32 Clear upper 32 Bytes of HIB memory on tamper event 0x2 HIB_TPCTL_MEMCLR_ALL Clear all HIB memory on tamper event 0x3 HIB_TPCTL_TPCLR Tamper Event Clear 4 5 HIB_TPCTL_TPEN Tamper Module Enable 0 1 HIB_TPCTL_WAKE Wake from Hibernate on a Tamper Event 11 12 TPIO HIB Tamper I/O Control 0x410 -1 read-write n 0x0 0x0 HIB_TPIO_EN0 TMPR0 Enable 0 1 HIB_TPIO_EN1 TMPR1Enable 8 9 HIB_TPIO_EN2 TMPR2 Enable 16 17 HIB_TPIO_EN3 TMPR3 Enable 24 25 HIB_TPIO_GFLTR0 TMPR0 Glitch Filtering 3 4 HIB_TPIO_GFLTR1 TMPR1 Glitch Filtering 11 12 HIB_TPIO_GFLTR2 TMPR2 Glitch Filtering 19 20 HIB_TPIO_GFLTR3 TMPR3 Glitch Filtering 27 28 HIB_TPIO_LEV0 TMPR0 Trigger Level 1 2 HIB_TPIO_LEV1 TMPR1 Trigger Level 9 10 HIB_TPIO_LEV2 TMPR2 Trigger Level 17 18 HIB_TPIO_LEV3 TMPR3 Trigger Level 25 26 HIB_TPIO_PUEN0 TMPR0 Internal Weak Pull-up Enable 2 3 HIB_TPIO_PUEN1 TMPR1 Internal Weak Pull-up Enable 10 11 HIB_TPIO_PUEN2 TMPR2 Internal Weak Pull-up Enable 18 19 HIB_TPIO_PUEN3 TMPR3 Internal Weak Pull-up Enable 26 27 TPLOG0 HIB Tamper Log 0 0x4E0 -1 read-write n 0x0 0x0 HIB_TPLOG0_TIME Tamper Log Calendar Information 0 32 TPLOG1 HIB Tamper Log 1 0x4E4 -1 read-write n 0x0 0x0 HIB_TPLOG1_TRIG0 Status of TMPR[0] Trigger 0 1 HIB_TPLOG1_TRIG1 Status of TMPR[1] Trigger 1 2 HIB_TPLOG1_TRIG2 Status of TMPR[2] Trigger 2 3 HIB_TPLOG1_TRIG3 Status of TMPR[3] Trigger 3 4 HIB_TPLOG1_XOSC Status of external 32 16 17 TPLOG2 HIB Tamper Log 2 0x4E8 -1 read-write n 0x0 0x0 HIB_TPLOG2_TIME Tamper Log Calendar Information 0 32 TPLOG3 HIB Tamper Log 3 0x4EC -1 read-write n 0x0 0x0 HIB_TPLOG3_TRIG0 Status of TMPR[0] Trigger 0 1 HIB_TPLOG3_TRIG1 Status of TMPR[1] Trigger 1 2 HIB_TPLOG3_TRIG2 Status of TMPR[2] Trigger 2 3 HIB_TPLOG3_TRIG3 Status of TMPR[3] Trigger 3 4 HIB_TPLOG3_XOSC Status of external 32 16 17 TPLOG4 HIB Tamper Log 4 0x4F0 -1 read-write n 0x0 0x0 HIB_TPLOG4_TIME Tamper Log Calendar Information 0 32 TPLOG5 HIB Tamper Log 5 0x4F4 -1 read-write n 0x0 0x0 HIB_TPLOG5_TRIG0 Status of TMPR[0] Trigger 0 1 HIB_TPLOG5_TRIG1 Status of TMPR[1] Trigger 1 2 HIB_TPLOG5_TRIG2 Status of TMPR[2] Trigger 2 3 HIB_TPLOG5_TRIG3 Status of TMPR[3] Trigger 3 4 HIB_TPLOG5_XOSC Status of external 32 16 17 TPLOG6 HIB Tamper Log 6 0x4F8 -1 read-write n 0x0 0x0 HIB_TPLOG6_TIME Tamper Log Calendar Information 0 32 TPLOG7 HIB Tamper Log 7 0x4FC -1 read-write n 0x0 0x0 HIB_TPLOG7_TRIG0 Status of TMPR[0] Trigger 0 1 HIB_TPLOG7_TRIG1 Status of TMPR[1] Trigger 1 2 HIB_TPLOG7_TRIG2 Status of TMPR[2] Trigger 2 3 HIB_TPLOG7_TRIG3 Status of TMPR[3] Trigger 3 4 HIB_TPLOG7_XOSC Status of external 32 16 17 TPSTAT HIB Tamper Status 0x404 -1 read-write n 0x0 0x0 HIB_TPSTAT_STATE Tamper Module Status 2 4 HIB_TPSTAT_STATE_DISABLED Tamper disabled 0x0 HIB_TPSTAT_STATE_CONFIGED Tamper configured 0x1 HIB_TPSTAT_STATE_ERROR Tamper pin event occurred 0x2 HIB_TPSTAT_XOSCFAIL External Oscillator Failure 0 1 HIB_TPSTAT_XOSCST External Oscillator Status 1 2 I2C0 Register map for I2C0 peripheral I2C 0x0 0x0 0x1000 registers n I2C0 8 FIFOCTL I2C FIFO Control 0xF04 -1 read-write n 0x0 0x0 I2C_FIFOCTL_DMARXENA DMA RX Channel Enable 29 30 I2C_FIFOCTL_DMATXENA DMA TX Channel Enable 13 14 I2C_FIFOCTL_RXASGNMT RX Control Assignment 31 32 I2C_FIFOCTL_RXFLUSH RX FIFO Flush 30 31 I2C_FIFOCTL_RXTRIG RX FIFO Trigger 16 19 I2C_FIFOCTL_TXASGNMT TX Control Assignment 15 16 I2C_FIFOCTL_TXFLUSH TX FIFO Flush 14 15 I2C_FIFOCTL_TXTRIG TX FIFO Trigger 0 3 FIFODATA I2C FIFO Data 0xF00 -1 read-write n 0x0 0x0 I2C_FIFODATA_DATA I2C TX FIFO Write Data Byte 0 8 FIFOSTATUS I2C FIFO Status 0xF08 -1 read-write n 0x0 0x0 I2C_FIFOSTATUS_RXABVTRIG RX FIFO Above Trigger Level 18 19 I2C_FIFOSTATUS_RXFE RX FIFO Empty 16 17 I2C_FIFOSTATUS_RXFF RX FIFO Full 17 18 I2C_FIFOSTATUS_TXBLWTRIG TX FIFO Below Trigger Level 2 3 I2C_FIFOSTATUS_TXFE TX FIFO Empty 0 1 I2C_FIFOSTATUS_TXFF TX FIFO Full 1 2 I2C0FIFOCTL I2C FIFO Control 0xF04 read-write n 0x0 0x0 I2C_FIFOCTL_DMARXENA DMA RX Channel Enable 29 30 I2C_FIFOCTL_DMATXENA DMA TX Channel Enable 13 14 I2C_FIFOCTL_RXASGNMT RX Control Assignment 31 32 I2C_FIFOCTL_RXFLUSH RX FIFO Flush 30 31 I2C_FIFOCTL_RXTRIG RX FIFO Trigger 16 19 I2C_FIFOCTL_TXASGNMT TX Control Assignment 15 16 I2C_FIFOCTL_TXFLUSH TX FIFO Flush 14 15 I2C_FIFOCTL_TXTRIG TX FIFO Trigger 0 3 I2C0FIFODATA I2C FIFO Data 0xF00 read-write n 0x0 0x0 I2C_FIFODATA_DATA I2C TX FIFO Write Data Byte 0 8 I2C0FIFOSTATUS I2C FIFO Status 0xF08 read-write n 0x0 0x0 I2C_FIFOSTATUS_RXABVTRIG RX FIFO Above Trigger Level 18 19 I2C_FIFOSTATUS_RXFE RX FIFO Empty 16 17 I2C_FIFOSTATUS_RXFF RX FIFO Full 17 18 I2C_FIFOSTATUS_TXBLWTRIG TX FIFO Below Trigger Level 2 3 I2C_FIFOSTATUS_TXFE TX FIFO Empty 0 1 I2C_FIFOSTATUS_TXFF TX FIFO Full 1 2 I2C0MBCNT I2C Master Burst Count 0x34 read-write n 0x0 0x0 I2C_MBCNT_CNTL I2C Master Burst Count 0 8 I2C0MBLEN I2C Master Burst Length 0x30 read-write n 0x0 0x0 I2C_MBLEN_CNTL I2C Burst Length 0 8 I2C0MBMON I2C Master Bus Monitor 0x2C read-write n 0x0 0x0 I2C_MBMON_SCL I2C SCL Status 0 1 I2C_MBMON_SDA I2C SDA Status 1 2 I2C0MCLKOCNT I2C Master Clock Low Timeout Count 0x24 read-write n 0x0 0x0 I2C_MCLKOCNT_CNTL I2C Master Count 0 8 I2C0MCR I2C Master Configuration 0x20 read-write n 0x0 0x0 I2C_MCR_LPBK I2C Loopback 0 1 I2C_MCR_MFE I2C Master Function Enable 4 5 I2C_MCR_SFE I2C Slave Function Enable 5 6 I2C0MCS I2C Master Control/Status 0x4 read-write n 0x0 0x0 I2C_MCS_ACK Data Acknowledge Enable 3 4 I2C_MCS_ACTDMARX DMA RX Active Status 31 32 I2C_MCS_ACTDMATX DMA TX Active Status 30 31 I2C_MCS_ADRACK Acknowledge Address 2 3 I2C_MCS_ARBLST Arbitration Lost 4 5 I2C_MCS_BURST Burst Enable 6 7 I2C_MCS_CLKTO Clock Timeout Error 7 8 I2C_MCS_IDLE I2C Idle 5 6 I2C_MCS_RUN I2C Master Enable 0 1 I2C_MCS_START Generate START 1 2 I2C0MDR I2C Master Data 0x8 read-write n 0x0 0x0 I2C_MDR_DATA This byte contains the data transferred during a transaction 0 8 I2C0MICR I2C Master Interrupt Clear 0x1C write-only n 0x0 0x0 I2C_MICR_ARBLOSTIC Arbitration Lost Interrupt Clear 7 8 write-only I2C_MICR_CLKIC Clock Timeout Interrupt Clear 1 2 write-only I2C_MICR_DMARXIC Receive DMA Interrupt Clear 2 3 write-only I2C_MICR_DMATXIC Transmit DMA Interrupt Clear 3 4 write-only I2C_MICR_IC Master Interrupt Clear 0 1 write-only I2C_MICR_NACKIC Address/Data NACK Interrupt Clear 4 5 write-only I2C_MICR_RXFFIC Receive FIFO Full Interrupt Clear 11 12 write-only I2C_MICR_RXIC Receive FIFO Request Interrupt Clear 9 10 write-only I2C_MICR_STARTIC START Detection Interrupt Clear 5 6 write-only I2C_MICR_STOPIC STOP Detection Interrupt Clear 6 7 write-only I2C_MICR_TXFEIC Transmit FIFO Empty Interrupt Clear 10 11 write-only I2C_MICR_TXIC Transmit FIFO Request Interrupt Clear 8 9 write-only I2C0MIMR I2C Master Interrupt Mask 0x10 read-write n 0x0 0x0 I2C_MIMR_ARBLOSTIM Arbitration Lost Interrupt Mask 7 8 I2C_MIMR_CLKIM Clock Timeout Interrupt Mask 1 2 I2C_MIMR_DMARXIM Receive DMA Interrupt Mask 2 3 I2C_MIMR_DMATXIM Transmit DMA Interrupt Mask 3 4 I2C_MIMR_IM Master Interrupt Mask 0 1 I2C_MIMR_NACKIM Address/Data NACK Interrupt Mask 4 5 I2C_MIMR_RXFFIM Receive FIFO Full Interrupt Mask 11 12 I2C_MIMR_RXIM Receive FIFO Request Interrupt Mask 9 10 I2C_MIMR_STARTIM START Detection Interrupt Mask 5 6 I2C_MIMR_STOPIM STOP Detection Interrupt Mask 6 7 I2C_MIMR_TXFEIM Transmit FIFO Empty Interrupt Mask 10 11 I2C_MIMR_TXIM Transmit FIFO Request Interrupt Mask 8 9 I2C0MMIS I2C Master Masked Interrupt Status 0x18 read-write n 0x0 0x0 I2C_MMIS_ARBLOSTMIS Arbitration Lost Interrupt Mask 7 8 I2C_MMIS_CLKMIS Clock Timeout Masked Interrupt Status 1 2 I2C_MMIS_DMARXMIS Receive DMA Interrupt Status 2 3 I2C_MMIS_DMATXMIS Transmit DMA Interrupt Status 3 4 I2C_MMIS_MIS Masked Interrupt Status 0 1 I2C_MMIS_NACKMIS Address/Data NACK Interrupt Mask 4 5 I2C_MMIS_RXFFMIS Receive FIFO Full Interrupt Mask 11 12 I2C_MMIS_RXMIS Receive FIFO Request Interrupt Mask 9 10 I2C_MMIS_STARTMIS START Detection Interrupt Mask 5 6 I2C_MMIS_STOPMIS STOP Detection Interrupt Mask 6 7 I2C_MMIS_TXFEMIS Transmit FIFO Empty Interrupt Mask 10 11 I2C_MMIS_TXMIS Transmit Request Interrupt Mask 8 9 I2C0MRIS I2C Master Raw Interrupt Status 0x14 read-write n 0x0 0x0 I2C_MRIS_ARBLOSTRIS Arbitration Lost Raw Interrupt Status 7 8 I2C_MRIS_CLKRIS Clock Timeout Raw Interrupt Status 1 2 I2C_MRIS_DMARXRIS Receive DMA Raw Interrupt Status 2 3 I2C_MRIS_DMATXRIS Transmit DMA Raw Interrupt Status 3 4 I2C_MRIS_NACKRIS Address/Data NACK Raw Interrupt Status 4 5 I2C_MRIS_RIS Master Raw Interrupt Status 0 1 I2C_MRIS_RXFFRIS Receive FIFO Full Raw Interrupt Status 11 12 I2C_MRIS_RXRIS Receive FIFO Request Raw Interrupt Status 9 10 I2C_MRIS_STARTRIS START Detection Raw Interrupt Status 5 6 I2C_MRIS_STOPRIS STOP Detection Raw Interrupt Status 6 7 I2C_MRIS_TXFERIS Transmit FIFO Empty Raw Interrupt Status 10 11 I2C_MRIS_TXRIS Transmit Request Raw Interrupt Status 8 9 I2C0MSA I2C Master Slave Address 0x0 read-write n 0x0 0x0 I2C_MSA_RS Receive not send 0 1 I2C_MSA_SA I2C Slave Address 1 8 I2C0MTPR I2C Master Timer Period 0xC read-write n 0x0 0x0 I2C_MTPR_HS High-Speed Enable 7 8 I2C_MTPR_PULSEL Glitch Suppression Pulse Width 16 19 I2C_MTPR_PULSEL_BYPASS Bypass 0x0 I2C_MTPR_PULSEL_1 1 clock 0x1 I2C_MTPR_PULSEL_2 2 clocks 0x2 I2C_MTPR_PULSEL_3 3 clocks 0x3 I2C_MTPR_PULSEL_4 4 clocks 0x4 I2C_MTPR_PULSEL_8 8 clocks 0x5 I2C_MTPR_PULSEL_16 16 clocks 0x6 I2C_MTPR_PULSEL_31 31 clocks 0x7 I2C_MTPR_TPR Timer Period 0 7 I2C0PC I2C Peripheral Configuration 0xFC4 read-write n 0x0 0x0 I2C_PC_HS High-Speed Capable 0 1 I2C0PP I2C Peripheral Properties 0xFC0 read-write n 0x0 0x0 I2C_PP_HS High-Speed Capable 0 1 I2C0SACKCTL I2C Slave ACK Control 0x820 read-write n 0x0 0x0 I2C_SACKCTL_ACKOEN I2C Slave ACK Override Enable 0 1 I2C_SACKCTL_ACKOVAL I2C Slave ACK Override Value 1 2 I2C0SCSR I2C Slave Control/Status 0x804 read-write n 0x0 0x0 I2C_SCSR_ACTDMARX DMA RX Active Status 31 32 I2C_SCSR_ACTDMATX DMA TX Active Status 30 31 I2C_SCSR_FBR First Byte Received 2 3 I2C_SCSR_OAR2SEL OAR2 Address Matched 3 4 I2C_SCSR_QCMDRW Quick Command Read / Write 5 6 I2C_SCSR_QCMDST Quick Command Status 4 5 I2C_SCSR_RREQ Receive Request 0 1 I2C_SCSR_TXFIFO TX FIFO Enable 1 2 I2C0SDR I2C Slave Data 0x808 read-write n 0x0 0x0 I2C_SDR_DATA Data for Transfer 0 8 I2C0SICR I2C Slave Interrupt Clear 0x818 write-only n 0x0 0x0 I2C_SICR_DATAIC Data Interrupt Clear 0 1 write-only I2C_SICR_DMARXIC Receive DMA Interrupt Clear 3 4 write-only I2C_SICR_DMATXIC Transmit DMA Interrupt Clear 4 5 write-only I2C_SICR_RXFFIC Receive FIFO Full Interrupt Mask 8 9 write-only I2C_SICR_RXIC Receive Request Interrupt Mask 6 7 write-only I2C_SICR_STARTIC Start Condition Interrupt Clear 1 2 write-only I2C_SICR_STOPIC Stop Condition Interrupt Clear 2 3 write-only I2C_SICR_TXFEIC Transmit FIFO Empty Interrupt Mask 7 8 write-only I2C_SICR_TXIC Transmit Request Interrupt Mask 5 6 write-only I2C0SIMR I2C Slave Interrupt Mask 0x80C read-write n 0x0 0x0 I2C_SIMR_DATAIM Data Interrupt Mask 0 1 I2C_SIMR_DMARXIM Receive DMA Interrupt Mask 3 4 I2C_SIMR_DMATXIM Transmit DMA Interrupt Mask 4 5 I2C_SIMR_RXFFIM Receive FIFO Full Interrupt Mask 8 9 I2C_SIMR_RXIM Receive FIFO Request Interrupt Mask 6 7 I2C_SIMR_STARTIM Start Condition Interrupt Mask 1 2 I2C_SIMR_STOPIM Stop Condition Interrupt Mask 2 3 I2C_SIMR_TXFEIM Transmit FIFO Empty Interrupt Mask 7 8 I2C_SIMR_TXIM Transmit FIFO Request Interrupt Mask 5 6 I2C0SMIS I2C Slave Masked Interrupt Status 0x814 read-write n 0x0 0x0 I2C_SMIS_DATAMIS Data Masked Interrupt Status 0 1 I2C_SMIS_DMARXMIS Receive DMA Masked Interrupt Status 3 4 I2C_SMIS_DMATXMIS Transmit DMA Masked Interrupt Status 4 5 I2C_SMIS_RXFFMIS Receive FIFO Full Interrupt Mask 8 9 I2C_SMIS_RXMIS Receive FIFO Request Interrupt Mask 6 7 I2C_SMIS_STARTMIS Start Condition Masked Interrupt Status 1 2 I2C_SMIS_STOPMIS Stop Condition Masked Interrupt Status 2 3 I2C_SMIS_TXFEMIS Transmit FIFO Empty Interrupt Mask 7 8 I2C_SMIS_TXMIS Transmit FIFO Request Interrupt Mask 5 6 I2C0SOAR I2C Slave Own Address 0x800 read-write n 0x0 0x0 I2C_SOAR_OAR I2C Slave Own Address 0 7 I2C0SOAR2 I2C Slave Own Address 2 0x81C read-write n 0x0 0x0 I2C_SOAR2_OAR2 I2C Slave Own Address 2 0 7 I2C_SOAR2_OAR2EN I2C Slave Own Address 2 Enable 7 8 I2C0SRIS I2C Slave Raw Interrupt Status 0x810 read-write n 0x0 0x0 I2C_SRIS_DATARIS Data Raw Interrupt Status 0 1 I2C_SRIS_DMARXRIS Receive DMA Raw Interrupt Status 3 4 I2C_SRIS_DMATXRIS Transmit DMA Raw Interrupt Status 4 5 I2C_SRIS_RXFFRIS Receive FIFO Full Raw Interrupt Status 8 9 I2C_SRIS_RXRIS Receive FIFO Request Raw Interrupt Status 6 7 I2C_SRIS_STARTRIS Start Condition Raw Interrupt Status 1 2 I2C_SRIS_STOPRIS Stop Condition Raw Interrupt Status 2 3 I2C_SRIS_TXFERIS Transmit FIFO Empty Raw Interrupt Status 7 8 I2C_SRIS_TXRIS Transmit Request Raw Interrupt Status 5 6 MBCNT I2C Master Burst Count 0x34 -1 read-write n 0x0 0x0 I2C_MBCNT_CNTL I2C Master Burst Count 0 8 MBLEN I2C Master Burst Length 0x30 -1 read-write n 0x0 0x0 I2C_MBLEN_CNTL I2C Burst Length 0 8 MBMON I2C Master Bus Monitor 0x2C -1 read-write n 0x0 0x0 I2C_MBMON_SCL I2C SCL Status 0 1 I2C_MBMON_SDA I2C SDA Status 1 2 MCLKOCNT I2C Master Clock Low Timeout Count 0x24 -1 read-write n 0x0 0x0 I2C_MCLKOCNT_CNTL I2C Master Count 0 8 MCR I2C Master Configuration 0x20 -1 read-write n 0x0 0x0 I2C_MCR_LPBK I2C Loopback 0 1 I2C_MCR_MFE I2C Master Function Enable 4 5 I2C_MCR_SFE I2C Slave Function Enable 5 6 MCS I2C Master Control/Status 0x4 -1 read-write n 0x0 0x0 I2C_MCS_ACK Data Acknowledge Enable 3 4 I2C_MCS_ACTDMARX DMA RX Active Status 31 32 I2C_MCS_ACTDMATX DMA TX Active Status 30 31 I2C_MCS_ADRACK Acknowledge Address 2 3 I2C_MCS_ARBLST Arbitration Lost 4 5 I2C_MCS_BURST Burst Enable 6 7 I2C_MCS_BUSBSY Bus Busy 6 7 I2C_MCS_BUSY I2C Busy 0 1 I2C_MCS_CLKTO Clock Timeout Error 7 8 I2C_MCS_DATACK Acknowledge Data 3 4 I2C_MCS_ERROR Error 1 2 I2C_MCS_HS High-Speed Enable 4 5 I2C_MCS_IDLE I2C Idle 5 6 I2C_MCS_QCMD Quick Command 5 6 I2C_MCS_RUN I2C Master Enable 0 1 I2C_MCS_START Generate START 1 2 I2C_MCS_STOP Generate STOP 2 3 MDR I2C Master Data 0x8 -1 read-write n 0x0 0x0 I2C_MDR_DATA This byte contains the data transferred during a transaction 0 8 MICR I2C Master Interrupt Clear 0x1C -1 write-only n 0x0 0x0 I2C_MICR_ARBLOSTIC Arbitration Lost Interrupt Clear 7 8 write-only I2C_MICR_CLKIC Clock Timeout Interrupt Clear 1 2 write-only I2C_MICR_DMARXIC Receive DMA Interrupt Clear 2 3 write-only I2C_MICR_DMATXIC Transmit DMA Interrupt Clear 3 4 write-only I2C_MICR_IC Master Interrupt Clear 0 1 write-only I2C_MICR_NACKIC Address/Data NACK Interrupt Clear 4 5 write-only I2C_MICR_RXFFIC Receive FIFO Full Interrupt Clear 11 12 write-only I2C_MICR_RXIC Receive FIFO Request Interrupt Clear 9 10 write-only I2C_MICR_STARTIC START Detection Interrupt Clear 5 6 write-only I2C_MICR_STOPIC STOP Detection Interrupt Clear 6 7 write-only I2C_MICR_TXFEIC Transmit FIFO Empty Interrupt Clear 10 11 write-only I2C_MICR_TXIC Transmit FIFO Request Interrupt Clear 8 9 write-only MIMR I2C Master Interrupt Mask 0x10 -1 read-write n 0x0 0x0 I2C_MIMR_ARBLOSTIM Arbitration Lost Interrupt Mask 7 8 I2C_MIMR_CLKIM Clock Timeout Interrupt Mask 1 2 I2C_MIMR_DMARXIM Receive DMA Interrupt Mask 2 3 I2C_MIMR_DMATXIM Transmit DMA Interrupt Mask 3 4 I2C_MIMR_IM Master Interrupt Mask 0 1 I2C_MIMR_NACKIM Address/Data NACK Interrupt Mask 4 5 I2C_MIMR_RXFFIM Receive FIFO Full Interrupt Mask 11 12 I2C_MIMR_RXIM Receive FIFO Request Interrupt Mask 9 10 I2C_MIMR_STARTIM START Detection Interrupt Mask 5 6 I2C_MIMR_STOPIM STOP Detection Interrupt Mask 6 7 I2C_MIMR_TXFEIM Transmit FIFO Empty Interrupt Mask 10 11 I2C_MIMR_TXIM Transmit FIFO Request Interrupt Mask 8 9 MMIS I2C Master Masked Interrupt Status 0x18 -1 read-write n 0x0 0x0 I2C_MMIS_ARBLOSTMIS Arbitration Lost Interrupt Mask 7 8 I2C_MMIS_CLKMIS Clock Timeout Masked Interrupt Status 1 2 I2C_MMIS_DMARXMIS Receive DMA Interrupt Status 2 3 I2C_MMIS_DMATXMIS Transmit DMA Interrupt Status 3 4 I2C_MMIS_MIS Masked Interrupt Status 0 1 I2C_MMIS_NACKMIS Address/Data NACK Interrupt Mask 4 5 I2C_MMIS_RXFFMIS Receive FIFO Full Interrupt Mask 11 12 I2C_MMIS_RXMIS Receive FIFO Request Interrupt Mask 9 10 I2C_MMIS_STARTMIS START Detection Interrupt Mask 5 6 I2C_MMIS_STOPMIS STOP Detection Interrupt Mask 6 7 I2C_MMIS_TXFEMIS Transmit FIFO Empty Interrupt Mask 10 11 I2C_MMIS_TXMIS Transmit Request Interrupt Mask 8 9 MRIS I2C Master Raw Interrupt Status 0x14 -1 read-write n 0x0 0x0 I2C_MRIS_ARBLOSTRIS Arbitration Lost Raw Interrupt Status 7 8 I2C_MRIS_CLKRIS Clock Timeout Raw Interrupt Status 1 2 I2C_MRIS_DMARXRIS Receive DMA Raw Interrupt Status 2 3 I2C_MRIS_DMATXRIS Transmit DMA Raw Interrupt Status 3 4 I2C_MRIS_NACKRIS Address/Data NACK Raw Interrupt Status 4 5 I2C_MRIS_RIS Master Raw Interrupt Status 0 1 I2C_MRIS_RXFFRIS Receive FIFO Full Raw Interrupt Status 11 12 I2C_MRIS_RXRIS Receive FIFO Request Raw Interrupt Status 9 10 I2C_MRIS_STARTRIS START Detection Raw Interrupt Status 5 6 I2C_MRIS_STOPRIS STOP Detection Raw Interrupt Status 6 7 I2C_MRIS_TXFERIS Transmit FIFO Empty Raw Interrupt Status 10 11 I2C_MRIS_TXRIS Transmit Request Raw Interrupt Status 8 9 MSA I2C Master Slave Address 0x0 -1 read-write n 0x0 0x0 I2C_MSA_RS Receive not send 0 1 I2C_MSA_SA I2C Slave Address 1 8 MTPR I2C Master Timer Period 0xC -1 read-write n 0x0 0x0 I2C_MTPR_HS High-Speed Enable 7 8 I2C_MTPR_PULSEL Glitch Suppression Pulse Width 16 19 I2C_MTPR_PULSEL_BYPASS Bypass 0x0 I2C_MTPR_PULSEL_1 1 clock 0x1 I2C_MTPR_PULSEL_2 2 clocks 0x2 I2C_MTPR_PULSEL_3 3 clocks 0x3 I2C_MTPR_PULSEL_4 4 clocks 0x4 I2C_MTPR_PULSEL_8 8 clocks 0x5 I2C_MTPR_PULSEL_16 16 clocks 0x6 I2C_MTPR_PULSEL_31 31 clocks 0x7 I2C_MTPR_TPR Timer Period 0 7 PC I2C Peripheral Configuration 0xFC4 -1 read-write n 0x0 0x0 I2C_PC_HS High-Speed Capable 0 1 PP I2C Peripheral Properties 0xFC0 -1 read-write n 0x0 0x0 I2C_PP_HS High-Speed Capable 0 1 SACKCTL I2C Slave ACK Control 0x820 -1 read-write n 0x0 0x0 I2C_SACKCTL_ACKOEN I2C Slave ACK Override Enable 0 1 I2C_SACKCTL_ACKOVAL I2C Slave ACK Override Value 1 2 SCSR I2C Slave Control/Status 0x804 -1 read-write n 0x0 0x0 I2C_SCSR_ACTDMARX DMA RX Active Status 31 32 I2C_SCSR_ACTDMATX DMA TX Active Status 30 31 I2C_SCSR_DA Device Active 0 1 I2C_SCSR_FBR First Byte Received 2 3 I2C_SCSR_OAR2SEL OAR2 Address Matched 3 4 I2C_SCSR_QCMDRW Quick Command Read / Write 5 6 I2C_SCSR_QCMDST Quick Command Status 4 5 I2C_SCSR_RREQ Receive Request 0 1 I2C_SCSR_RXFIFO RX FIFO Enable 2 3 I2C_SCSR_TREQ Transmit Request 1 2 I2C_SCSR_TXFIFO TX FIFO Enable 1 2 SDR I2C Slave Data 0x808 -1 read-write n 0x0 0x0 I2C_SDR_DATA Data for Transfer 0 8 SICR I2C Slave Interrupt Clear 0x818 -1 write-only n 0x0 0x0 I2C_SICR_DATAIC Data Interrupt Clear 0 1 write-only I2C_SICR_DMARXIC Receive DMA Interrupt Clear 3 4 write-only I2C_SICR_DMATXIC Transmit DMA Interrupt Clear 4 5 write-only I2C_SICR_RXFFIC Receive FIFO Full Interrupt Mask 8 9 write-only I2C_SICR_RXIC Receive Request Interrupt Mask 6 7 write-only I2C_SICR_STARTIC Start Condition Interrupt Clear 1 2 write-only I2C_SICR_STOPIC Stop Condition Interrupt Clear 2 3 write-only I2C_SICR_TXFEIC Transmit FIFO Empty Interrupt Mask 7 8 write-only I2C_SICR_TXIC Transmit Request Interrupt Mask 5 6 write-only SIMR I2C Slave Interrupt Mask 0x80C -1 read-write n 0x0 0x0 I2C_SIMR_DATAIM Data Interrupt Mask 0 1 I2C_SIMR_DMARXIM Receive DMA Interrupt Mask 3 4 I2C_SIMR_DMATXIM Transmit DMA Interrupt Mask 4 5 I2C_SIMR_RXFFIM Receive FIFO Full Interrupt Mask 8 9 I2C_SIMR_RXIM Receive FIFO Request Interrupt Mask 6 7 I2C_SIMR_STARTIM Start Condition Interrupt Mask 1 2 I2C_SIMR_STOPIM Stop Condition Interrupt Mask 2 3 I2C_SIMR_TXFEIM Transmit FIFO Empty Interrupt Mask 7 8 I2C_SIMR_TXIM Transmit FIFO Request Interrupt Mask 5 6 SMIS I2C Slave Masked Interrupt Status 0x814 -1 read-write n 0x0 0x0 I2C_SMIS_DATAMIS Data Masked Interrupt Status 0 1 I2C_SMIS_DMARXMIS Receive DMA Masked Interrupt Status 3 4 I2C_SMIS_DMATXMIS Transmit DMA Masked Interrupt Status 4 5 I2C_SMIS_RXFFMIS Receive FIFO Full Interrupt Mask 8 9 I2C_SMIS_RXMIS Receive FIFO Request Interrupt Mask 6 7 I2C_SMIS_STARTMIS Start Condition Masked Interrupt Status 1 2 I2C_SMIS_STOPMIS Stop Condition Masked Interrupt Status 2 3 I2C_SMIS_TXFEMIS Transmit FIFO Empty Interrupt Mask 7 8 I2C_SMIS_TXMIS Transmit FIFO Request Interrupt Mask 5 6 SOAR I2C Slave Own Address 0x800 -1 read-write n 0x0 0x0 I2C_SOAR_OAR I2C Slave Own Address 0 7 SOAR2 I2C Slave Own Address 2 0x81C -1 read-write n 0x0 0x0 I2C_SOAR2_OAR2 I2C Slave Own Address 2 0 7 I2C_SOAR2_OAR2EN I2C Slave Own Address 2 Enable 7 8 SRIS I2C Slave Raw Interrupt Status 0x810 -1 read-write n 0x0 0x0 I2C_SRIS_DATARIS Data Raw Interrupt Status 0 1 I2C_SRIS_DMARXRIS Receive DMA Raw Interrupt Status 3 4 I2C_SRIS_DMATXRIS Transmit DMA Raw Interrupt Status 4 5 I2C_SRIS_RXFFRIS Receive FIFO Full Raw Interrupt Status 8 9 I2C_SRIS_RXRIS Receive FIFO Request Raw Interrupt Status 6 7 I2C_SRIS_STARTRIS Start Condition Raw Interrupt Status 1 2 I2C_SRIS_STOPRIS Stop Condition Raw Interrupt Status 2 3 I2C_SRIS_TXFERIS Transmit FIFO Empty Raw Interrupt Status 7 8 I2C_SRIS_TXRIS Transmit Request Raw Interrupt Status 5 6 I2C1 Register map for I2C0 peripheral I2C 0x0 0x0 0x1000 registers n I2C1 37 FIFOCTL I2C FIFO Control 0xF04 -1 read-write n 0x0 0x0 I2C_FIFOCTL_DMARXENA DMA RX Channel Enable 29 30 I2C_FIFOCTL_DMATXENA DMA TX Channel Enable 13 14 I2C_FIFOCTL_RXASGNMT RX Control Assignment 31 32 I2C_FIFOCTL_RXFLUSH RX FIFO Flush 30 31 I2C_FIFOCTL_RXTRIG RX FIFO Trigger 16 19 I2C_FIFOCTL_TXASGNMT TX Control Assignment 15 16 I2C_FIFOCTL_TXFLUSH TX FIFO Flush 14 15 I2C_FIFOCTL_TXTRIG TX FIFO Trigger 0 3 FIFODATA I2C FIFO Data 0xF00 -1 read-write n 0x0 0x0 I2C_FIFODATA_DATA I2C TX FIFO Write Data Byte 0 8 FIFOSTATUS I2C FIFO Status 0xF08 -1 read-write n 0x0 0x0 I2C_FIFOSTATUS_RXABVTRIG RX FIFO Above Trigger Level 18 19 I2C_FIFOSTATUS_RXFE RX FIFO Empty 16 17 I2C_FIFOSTATUS_RXFF RX FIFO Full 17 18 I2C_FIFOSTATUS_TXBLWTRIG TX FIFO Below Trigger Level 2 3 I2C_FIFOSTATUS_TXFE TX FIFO Empty 0 1 I2C_FIFOSTATUS_TXFF TX FIFO Full 1 2 I2C0FIFOCTL I2C FIFO Control 0xF04 read-write n 0x0 0x0 I2C_FIFOCTL_DMARXENA DMA RX Channel Enable 29 30 I2C_FIFOCTL_DMATXENA DMA TX Channel Enable 13 14 I2C_FIFOCTL_RXASGNMT RX Control Assignment 31 32 I2C_FIFOCTL_RXFLUSH RX FIFO Flush 30 31 I2C_FIFOCTL_RXTRIG RX FIFO Trigger 16 19 I2C_FIFOCTL_TXASGNMT TX Control Assignment 15 16 I2C_FIFOCTL_TXFLUSH TX FIFO Flush 14 15 I2C_FIFOCTL_TXTRIG TX FIFO Trigger 0 3 I2C0FIFODATA I2C FIFO Data 0xF00 read-write n 0x0 0x0 I2C_FIFODATA_DATA I2C TX FIFO Write Data Byte 0 8 I2C0FIFOSTATUS I2C FIFO Status 0xF08 read-write n 0x0 0x0 I2C_FIFOSTATUS_RXABVTRIG RX FIFO Above Trigger Level 18 19 I2C_FIFOSTATUS_RXFE RX FIFO Empty 16 17 I2C_FIFOSTATUS_RXFF RX FIFO Full 17 18 I2C_FIFOSTATUS_TXBLWTRIG TX FIFO Below Trigger Level 2 3 I2C_FIFOSTATUS_TXFE TX FIFO Empty 0 1 I2C_FIFOSTATUS_TXFF TX FIFO Full 1 2 I2C0MBCNT I2C Master Burst Count 0x34 read-write n 0x0 0x0 I2C_MBCNT_CNTL I2C Master Burst Count 0 8 I2C0MBLEN I2C Master Burst Length 0x30 read-write n 0x0 0x0 I2C_MBLEN_CNTL I2C Burst Length 0 8 I2C0MBMON I2C Master Bus Monitor 0x2C read-write n 0x0 0x0 I2C_MBMON_SCL I2C SCL Status 0 1 I2C_MBMON_SDA I2C SDA Status 1 2 I2C0MCLKOCNT I2C Master Clock Low Timeout Count 0x24 read-write n 0x0 0x0 I2C_MCLKOCNT_CNTL I2C Master Count 0 8 I2C0MCR I2C Master Configuration 0x20 read-write n 0x0 0x0 I2C_MCR_LPBK I2C Loopback 0 1 I2C_MCR_MFE I2C Master Function Enable 4 5 I2C_MCR_SFE I2C Slave Function Enable 5 6 I2C0MCS I2C Master Control/Status 0x4 read-write n 0x0 0x0 I2C_MCS_ACK Data Acknowledge Enable 3 4 I2C_MCS_ACTDMARX DMA RX Active Status 31 32 I2C_MCS_ACTDMATX DMA TX Active Status 30 31 I2C_MCS_ADRACK Acknowledge Address 2 3 I2C_MCS_ARBLST Arbitration Lost 4 5 I2C_MCS_BURST Burst Enable 6 7 I2C_MCS_CLKTO Clock Timeout Error 7 8 I2C_MCS_IDLE I2C Idle 5 6 I2C_MCS_RUN I2C Master Enable 0 1 I2C_MCS_START Generate START 1 2 I2C0MDR I2C Master Data 0x8 read-write n 0x0 0x0 I2C_MDR_DATA This byte contains the data transferred during a transaction 0 8 I2C0MICR I2C Master Interrupt Clear 0x1C write-only n 0x0 0x0 I2C_MICR_ARBLOSTIC Arbitration Lost Interrupt Clear 7 8 write-only I2C_MICR_CLKIC Clock Timeout Interrupt Clear 1 2 write-only I2C_MICR_DMARXIC Receive DMA Interrupt Clear 2 3 write-only I2C_MICR_DMATXIC Transmit DMA Interrupt Clear 3 4 write-only I2C_MICR_IC Master Interrupt Clear 0 1 write-only I2C_MICR_NACKIC Address/Data NACK Interrupt Clear 4 5 write-only I2C_MICR_RXFFIC Receive FIFO Full Interrupt Clear 11 12 write-only I2C_MICR_RXIC Receive FIFO Request Interrupt Clear 9 10 write-only I2C_MICR_STARTIC START Detection Interrupt Clear 5 6 write-only I2C_MICR_STOPIC STOP Detection Interrupt Clear 6 7 write-only I2C_MICR_TXFEIC Transmit FIFO Empty Interrupt Clear 10 11 write-only I2C_MICR_TXIC Transmit FIFO Request Interrupt Clear 8 9 write-only I2C0MIMR I2C Master Interrupt Mask 0x10 read-write n 0x0 0x0 I2C_MIMR_ARBLOSTIM Arbitration Lost Interrupt Mask 7 8 I2C_MIMR_CLKIM Clock Timeout Interrupt Mask 1 2 I2C_MIMR_DMARXIM Receive DMA Interrupt Mask 2 3 I2C_MIMR_DMATXIM Transmit DMA Interrupt Mask 3 4 I2C_MIMR_IM Master Interrupt Mask 0 1 I2C_MIMR_NACKIM Address/Data NACK Interrupt Mask 4 5 I2C_MIMR_RXFFIM Receive FIFO Full Interrupt Mask 11 12 I2C_MIMR_RXIM Receive FIFO Request Interrupt Mask 9 10 I2C_MIMR_STARTIM START Detection Interrupt Mask 5 6 I2C_MIMR_STOPIM STOP Detection Interrupt Mask 6 7 I2C_MIMR_TXFEIM Transmit FIFO Empty Interrupt Mask 10 11 I2C_MIMR_TXIM Transmit FIFO Request Interrupt Mask 8 9 I2C0MMIS I2C Master Masked Interrupt Status 0x18 read-write n 0x0 0x0 I2C_MMIS_ARBLOSTMIS Arbitration Lost Interrupt Mask 7 8 I2C_MMIS_CLKMIS Clock Timeout Masked Interrupt Status 1 2 I2C_MMIS_DMARXMIS Receive DMA Interrupt Status 2 3 I2C_MMIS_DMATXMIS Transmit DMA Interrupt Status 3 4 I2C_MMIS_MIS Masked Interrupt Status 0 1 I2C_MMIS_NACKMIS Address/Data NACK Interrupt Mask 4 5 I2C_MMIS_RXFFMIS Receive FIFO Full Interrupt Mask 11 12 I2C_MMIS_RXMIS Receive FIFO Request Interrupt Mask 9 10 I2C_MMIS_STARTMIS START Detection Interrupt Mask 5 6 I2C_MMIS_STOPMIS STOP Detection Interrupt Mask 6 7 I2C_MMIS_TXFEMIS Transmit FIFO Empty Interrupt Mask 10 11 I2C_MMIS_TXMIS Transmit Request Interrupt Mask 8 9 I2C0MRIS I2C Master Raw Interrupt Status 0x14 read-write n 0x0 0x0 I2C_MRIS_ARBLOSTRIS Arbitration Lost Raw Interrupt Status 7 8 I2C_MRIS_CLKRIS Clock Timeout Raw Interrupt Status 1 2 I2C_MRIS_DMARXRIS Receive DMA Raw Interrupt Status 2 3 I2C_MRIS_DMATXRIS Transmit DMA Raw Interrupt Status 3 4 I2C_MRIS_NACKRIS Address/Data NACK Raw Interrupt Status 4 5 I2C_MRIS_RIS Master Raw Interrupt Status 0 1 I2C_MRIS_RXFFRIS Receive FIFO Full Raw Interrupt Status 11 12 I2C_MRIS_RXRIS Receive FIFO Request Raw Interrupt Status 9 10 I2C_MRIS_STARTRIS START Detection Raw Interrupt Status 5 6 I2C_MRIS_STOPRIS STOP Detection Raw Interrupt Status 6 7 I2C_MRIS_TXFERIS Transmit FIFO Empty Raw Interrupt Status 10 11 I2C_MRIS_TXRIS Transmit Request Raw Interrupt Status 8 9 I2C0MSA I2C Master Slave Address 0x0 read-write n 0x0 0x0 I2C_MSA_RS Receive not send 0 1 I2C_MSA_SA I2C Slave Address 1 8 I2C0MTPR I2C Master Timer Period 0xC read-write n 0x0 0x0 I2C_MTPR_HS High-Speed Enable 7 8 I2C_MTPR_PULSEL Glitch Suppression Pulse Width 16 19 I2C_MTPR_PULSEL_BYPASS Bypass 0x0 I2C_MTPR_PULSEL_1 1 clock 0x1 I2C_MTPR_PULSEL_2 2 clocks 0x2 I2C_MTPR_PULSEL_3 3 clocks 0x3 I2C_MTPR_PULSEL_4 4 clocks 0x4 I2C_MTPR_PULSEL_8 8 clocks 0x5 I2C_MTPR_PULSEL_16 16 clocks 0x6 I2C_MTPR_PULSEL_31 31 clocks 0x7 I2C_MTPR_TPR Timer Period 0 7 I2C0PC I2C Peripheral Configuration 0xFC4 read-write n 0x0 0x0 I2C_PC_HS High-Speed Capable 0 1 I2C0PP I2C Peripheral Properties 0xFC0 read-write n 0x0 0x0 I2C_PP_HS High-Speed Capable 0 1 I2C0SACKCTL I2C Slave ACK Control 0x820 read-write n 0x0 0x0 I2C_SACKCTL_ACKOEN I2C Slave ACK Override Enable 0 1 I2C_SACKCTL_ACKOVAL I2C Slave ACK Override Value 1 2 I2C0SCSR I2C Slave Control/Status 0x804 read-write n 0x0 0x0 I2C_SCSR_ACTDMARX DMA RX Active Status 31 32 I2C_SCSR_ACTDMATX DMA TX Active Status 30 31 I2C_SCSR_FBR First Byte Received 2 3 I2C_SCSR_OAR2SEL OAR2 Address Matched 3 4 I2C_SCSR_QCMDRW Quick Command Read / Write 5 6 I2C_SCSR_QCMDST Quick Command Status 4 5 I2C_SCSR_RREQ Receive Request 0 1 I2C_SCSR_TXFIFO TX FIFO Enable 1 2 I2C0SDR I2C Slave Data 0x808 read-write n 0x0 0x0 I2C_SDR_DATA Data for Transfer 0 8 I2C0SICR I2C Slave Interrupt Clear 0x818 write-only n 0x0 0x0 I2C_SICR_DATAIC Data Interrupt Clear 0 1 write-only I2C_SICR_DMARXIC Receive DMA Interrupt Clear 3 4 write-only I2C_SICR_DMATXIC Transmit DMA Interrupt Clear 4 5 write-only I2C_SICR_RXFFIC Receive FIFO Full Interrupt Mask 8 9 write-only I2C_SICR_RXIC Receive Request Interrupt Mask 6 7 write-only I2C_SICR_STARTIC Start Condition Interrupt Clear 1 2 write-only I2C_SICR_STOPIC Stop Condition Interrupt Clear 2 3 write-only I2C_SICR_TXFEIC Transmit FIFO Empty Interrupt Mask 7 8 write-only I2C_SICR_TXIC Transmit Request Interrupt Mask 5 6 write-only I2C0SIMR I2C Slave Interrupt Mask 0x80C read-write n 0x0 0x0 I2C_SIMR_DATAIM Data Interrupt Mask 0 1 I2C_SIMR_DMARXIM Receive DMA Interrupt Mask 3 4 I2C_SIMR_DMATXIM Transmit DMA Interrupt Mask 4 5 I2C_SIMR_RXFFIM Receive FIFO Full Interrupt Mask 8 9 I2C_SIMR_RXIM Receive FIFO Request Interrupt Mask 6 7 I2C_SIMR_STARTIM Start Condition Interrupt Mask 1 2 I2C_SIMR_STOPIM Stop Condition Interrupt Mask 2 3 I2C_SIMR_TXFEIM Transmit FIFO Empty Interrupt Mask 7 8 I2C_SIMR_TXIM Transmit FIFO Request Interrupt Mask 5 6 I2C0SMIS I2C Slave Masked Interrupt Status 0x814 read-write n 0x0 0x0 I2C_SMIS_DATAMIS Data Masked Interrupt Status 0 1 I2C_SMIS_DMARXMIS Receive DMA Masked Interrupt Status 3 4 I2C_SMIS_DMATXMIS Transmit DMA Masked Interrupt Status 4 5 I2C_SMIS_RXFFMIS Receive FIFO Full Interrupt Mask 8 9 I2C_SMIS_RXMIS Receive FIFO Request Interrupt Mask 6 7 I2C_SMIS_STARTMIS Start Condition Masked Interrupt Status 1 2 I2C_SMIS_STOPMIS Stop Condition Masked Interrupt Status 2 3 I2C_SMIS_TXFEMIS Transmit FIFO Empty Interrupt Mask 7 8 I2C_SMIS_TXMIS Transmit FIFO Request Interrupt Mask 5 6 I2C0SOAR I2C Slave Own Address 0x800 read-write n 0x0 0x0 I2C_SOAR_OAR I2C Slave Own Address 0 7 I2C0SOAR2 I2C Slave Own Address 2 0x81C read-write n 0x0 0x0 I2C_SOAR2_OAR2 I2C Slave Own Address 2 0 7 I2C_SOAR2_OAR2EN I2C Slave Own Address 2 Enable 7 8 I2C0SRIS I2C Slave Raw Interrupt Status 0x810 read-write n 0x0 0x0 I2C_SRIS_DATARIS Data Raw Interrupt Status 0 1 I2C_SRIS_DMARXRIS Receive DMA Raw Interrupt Status 3 4 I2C_SRIS_DMATXRIS Transmit DMA Raw Interrupt Status 4 5 I2C_SRIS_RXFFRIS Receive FIFO Full Raw Interrupt Status 8 9 I2C_SRIS_RXRIS Receive FIFO Request Raw Interrupt Status 6 7 I2C_SRIS_STARTRIS Start Condition Raw Interrupt Status 1 2 I2C_SRIS_STOPRIS Stop Condition Raw Interrupt Status 2 3 I2C_SRIS_TXFERIS Transmit FIFO Empty Raw Interrupt Status 7 8 I2C_SRIS_TXRIS Transmit Request Raw Interrupt Status 5 6 MBCNT I2C Master Burst Count 0x34 -1 read-write n 0x0 0x0 I2C_MBCNT_CNTL I2C Master Burst Count 0 8 MBLEN I2C Master Burst Length 0x30 -1 read-write n 0x0 0x0 I2C_MBLEN_CNTL I2C Burst Length 0 8 MBMON I2C Master Bus Monitor 0x2C -1 read-write n 0x0 0x0 I2C_MBMON_SCL I2C SCL Status 0 1 I2C_MBMON_SDA I2C SDA Status 1 2 MCLKOCNT I2C Master Clock Low Timeout Count 0x24 -1 read-write n 0x0 0x0 I2C_MCLKOCNT_CNTL I2C Master Count 0 8 MCR I2C Master Configuration 0x20 -1 read-write n 0x0 0x0 I2C_MCR_LPBK I2C Loopback 0 1 I2C_MCR_MFE I2C Master Function Enable 4 5 I2C_MCR_SFE I2C Slave Function Enable 5 6 MCS I2C Master Control/Status 0x4 -1 read-write n 0x0 0x0 I2C_MCS_ACK Data Acknowledge Enable 3 4 I2C_MCS_ACTDMARX DMA RX Active Status 31 32 I2C_MCS_ACTDMATX DMA TX Active Status 30 31 I2C_MCS_ADRACK Acknowledge Address 2 3 I2C_MCS_ARBLST Arbitration Lost 4 5 I2C_MCS_BURST Burst Enable 6 7 I2C_MCS_BUSBSY Bus Busy 6 7 I2C_MCS_BUSY I2C Busy 0 1 I2C_MCS_CLKTO Clock Timeout Error 7 8 I2C_MCS_DATACK Acknowledge Data 3 4 I2C_MCS_ERROR Error 1 2 I2C_MCS_HS High-Speed Enable 4 5 I2C_MCS_IDLE I2C Idle 5 6 I2C_MCS_QCMD Quick Command 5 6 I2C_MCS_RUN I2C Master Enable 0 1 I2C_MCS_START Generate START 1 2 I2C_MCS_STOP Generate STOP 2 3 MDR I2C Master Data 0x8 -1 read-write n 0x0 0x0 I2C_MDR_DATA This byte contains the data transferred during a transaction 0 8 MICR I2C Master Interrupt Clear 0x1C -1 write-only n 0x0 0x0 I2C_MICR_ARBLOSTIC Arbitration Lost Interrupt Clear 7 8 write-only I2C_MICR_CLKIC Clock Timeout Interrupt Clear 1 2 write-only I2C_MICR_DMARXIC Receive DMA Interrupt Clear 2 3 write-only I2C_MICR_DMATXIC Transmit DMA Interrupt Clear 3 4 write-only I2C_MICR_IC Master Interrupt Clear 0 1 write-only I2C_MICR_NACKIC Address/Data NACK Interrupt Clear 4 5 write-only I2C_MICR_RXFFIC Receive FIFO Full Interrupt Clear 11 12 write-only I2C_MICR_RXIC Receive FIFO Request Interrupt Clear 9 10 write-only I2C_MICR_STARTIC START Detection Interrupt Clear 5 6 write-only I2C_MICR_STOPIC STOP Detection Interrupt Clear 6 7 write-only I2C_MICR_TXFEIC Transmit FIFO Empty Interrupt Clear 10 11 write-only I2C_MICR_TXIC Transmit FIFO Request Interrupt Clear 8 9 write-only MIMR I2C Master Interrupt Mask 0x10 -1 read-write n 0x0 0x0 I2C_MIMR_ARBLOSTIM Arbitration Lost Interrupt Mask 7 8 I2C_MIMR_CLKIM Clock Timeout Interrupt Mask 1 2 I2C_MIMR_DMARXIM Receive DMA Interrupt Mask 2 3 I2C_MIMR_DMATXIM Transmit DMA Interrupt Mask 3 4 I2C_MIMR_IM Master Interrupt Mask 0 1 I2C_MIMR_NACKIM Address/Data NACK Interrupt Mask 4 5 I2C_MIMR_RXFFIM Receive FIFO Full Interrupt Mask 11 12 I2C_MIMR_RXIM Receive FIFO Request Interrupt Mask 9 10 I2C_MIMR_STARTIM START Detection Interrupt Mask 5 6 I2C_MIMR_STOPIM STOP Detection Interrupt Mask 6 7 I2C_MIMR_TXFEIM Transmit FIFO Empty Interrupt Mask 10 11 I2C_MIMR_TXIM Transmit FIFO Request Interrupt Mask 8 9 MMIS I2C Master Masked Interrupt Status 0x18 -1 read-write n 0x0 0x0 I2C_MMIS_ARBLOSTMIS Arbitration Lost Interrupt Mask 7 8 I2C_MMIS_CLKMIS Clock Timeout Masked Interrupt Status 1 2 I2C_MMIS_DMARXMIS Receive DMA Interrupt Status 2 3 I2C_MMIS_DMATXMIS Transmit DMA Interrupt Status 3 4 I2C_MMIS_MIS Masked Interrupt Status 0 1 I2C_MMIS_NACKMIS Address/Data NACK Interrupt Mask 4 5 I2C_MMIS_RXFFMIS Receive FIFO Full Interrupt Mask 11 12 I2C_MMIS_RXMIS Receive FIFO Request Interrupt Mask 9 10 I2C_MMIS_STARTMIS START Detection Interrupt Mask 5 6 I2C_MMIS_STOPMIS STOP Detection Interrupt Mask 6 7 I2C_MMIS_TXFEMIS Transmit FIFO Empty Interrupt Mask 10 11 I2C_MMIS_TXMIS Transmit Request Interrupt Mask 8 9 MRIS I2C Master Raw Interrupt Status 0x14 -1 read-write n 0x0 0x0 I2C_MRIS_ARBLOSTRIS Arbitration Lost Raw Interrupt Status 7 8 I2C_MRIS_CLKRIS Clock Timeout Raw Interrupt Status 1 2 I2C_MRIS_DMARXRIS Receive DMA Raw Interrupt Status 2 3 I2C_MRIS_DMATXRIS Transmit DMA Raw Interrupt Status 3 4 I2C_MRIS_NACKRIS Address/Data NACK Raw Interrupt Status 4 5 I2C_MRIS_RIS Master Raw Interrupt Status 0 1 I2C_MRIS_RXFFRIS Receive FIFO Full Raw Interrupt Status 11 12 I2C_MRIS_RXRIS Receive FIFO Request Raw Interrupt Status 9 10 I2C_MRIS_STARTRIS START Detection Raw Interrupt Status 5 6 I2C_MRIS_STOPRIS STOP Detection Raw Interrupt Status 6 7 I2C_MRIS_TXFERIS Transmit FIFO Empty Raw Interrupt Status 10 11 I2C_MRIS_TXRIS Transmit Request Raw Interrupt Status 8 9 MSA I2C Master Slave Address 0x0 -1 read-write n 0x0 0x0 I2C_MSA_RS Receive not send 0 1 I2C_MSA_SA I2C Slave Address 1 8 MTPR I2C Master Timer Period 0xC -1 read-write n 0x0 0x0 I2C_MTPR_HS High-Speed Enable 7 8 I2C_MTPR_PULSEL Glitch Suppression Pulse Width 16 19 I2C_MTPR_PULSEL_BYPASS Bypass 0x0 I2C_MTPR_PULSEL_1 1 clock 0x1 I2C_MTPR_PULSEL_2 2 clocks 0x2 I2C_MTPR_PULSEL_3 3 clocks 0x3 I2C_MTPR_PULSEL_4 4 clocks 0x4 I2C_MTPR_PULSEL_8 8 clocks 0x5 I2C_MTPR_PULSEL_16 16 clocks 0x6 I2C_MTPR_PULSEL_31 31 clocks 0x7 I2C_MTPR_TPR Timer Period 0 7 PC I2C Peripheral Configuration 0xFC4 -1 read-write n 0x0 0x0 I2C_PC_HS High-Speed Capable 0 1 PP I2C Peripheral Properties 0xFC0 -1 read-write n 0x0 0x0 I2C_PP_HS High-Speed Capable 0 1 SACKCTL I2C Slave ACK Control 0x820 -1 read-write n 0x0 0x0 I2C_SACKCTL_ACKOEN I2C Slave ACK Override Enable 0 1 I2C_SACKCTL_ACKOVAL I2C Slave ACK Override Value 1 2 SCSR I2C Slave Control/Status 0x804 -1 read-write n 0x0 0x0 I2C_SCSR_ACTDMARX DMA RX Active Status 31 32 I2C_SCSR_ACTDMATX DMA TX Active Status 30 31 I2C_SCSR_DA Device Active 0 1 I2C_SCSR_FBR First Byte Received 2 3 I2C_SCSR_OAR2SEL OAR2 Address Matched 3 4 I2C_SCSR_QCMDRW Quick Command Read / Write 5 6 I2C_SCSR_QCMDST Quick Command Status 4 5 I2C_SCSR_RREQ Receive Request 0 1 I2C_SCSR_RXFIFO RX FIFO Enable 2 3 I2C_SCSR_TREQ Transmit Request 1 2 I2C_SCSR_TXFIFO TX FIFO Enable 1 2 SDR I2C Slave Data 0x808 -1 read-write n 0x0 0x0 I2C_SDR_DATA Data for Transfer 0 8 SICR I2C Slave Interrupt Clear 0x818 -1 write-only n 0x0 0x0 I2C_SICR_DATAIC Data Interrupt Clear 0 1 write-only I2C_SICR_DMARXIC Receive DMA Interrupt Clear 3 4 write-only I2C_SICR_DMATXIC Transmit DMA Interrupt Clear 4 5 write-only I2C_SICR_RXFFIC Receive FIFO Full Interrupt Mask 8 9 write-only I2C_SICR_RXIC Receive Request Interrupt Mask 6 7 write-only I2C_SICR_STARTIC Start Condition Interrupt Clear 1 2 write-only I2C_SICR_STOPIC Stop Condition Interrupt Clear 2 3 write-only I2C_SICR_TXFEIC Transmit FIFO Empty Interrupt Mask 7 8 write-only I2C_SICR_TXIC Transmit Request Interrupt Mask 5 6 write-only SIMR I2C Slave Interrupt Mask 0x80C -1 read-write n 0x0 0x0 I2C_SIMR_DATAIM Data Interrupt Mask 0 1 I2C_SIMR_DMARXIM Receive DMA Interrupt Mask 3 4 I2C_SIMR_DMATXIM Transmit DMA Interrupt Mask 4 5 I2C_SIMR_RXFFIM Receive FIFO Full Interrupt Mask 8 9 I2C_SIMR_RXIM Receive FIFO Request Interrupt Mask 6 7 I2C_SIMR_STARTIM Start Condition Interrupt Mask 1 2 I2C_SIMR_STOPIM Stop Condition Interrupt Mask 2 3 I2C_SIMR_TXFEIM Transmit FIFO Empty Interrupt Mask 7 8 I2C_SIMR_TXIM Transmit FIFO Request Interrupt Mask 5 6 SMIS I2C Slave Masked Interrupt Status 0x814 -1 read-write n 0x0 0x0 I2C_SMIS_DATAMIS Data Masked Interrupt Status 0 1 I2C_SMIS_DMARXMIS Receive DMA Masked Interrupt Status 3 4 I2C_SMIS_DMATXMIS Transmit DMA Masked Interrupt Status 4 5 I2C_SMIS_RXFFMIS Receive FIFO Full Interrupt Mask 8 9 I2C_SMIS_RXMIS Receive FIFO Request Interrupt Mask 6 7 I2C_SMIS_STARTMIS Start Condition Masked Interrupt Status 1 2 I2C_SMIS_STOPMIS Stop Condition Masked Interrupt Status 2 3 I2C_SMIS_TXFEMIS Transmit FIFO Empty Interrupt Mask 7 8 I2C_SMIS_TXMIS Transmit FIFO Request Interrupt Mask 5 6 SOAR I2C Slave Own Address 0x800 -1 read-write n 0x0 0x0 I2C_SOAR_OAR I2C Slave Own Address 0 7 SOAR2 I2C Slave Own Address 2 0x81C -1 read-write n 0x0 0x0 I2C_SOAR2_OAR2 I2C Slave Own Address 2 0 7 I2C_SOAR2_OAR2EN I2C Slave Own Address 2 Enable 7 8 SRIS I2C Slave Raw Interrupt Status 0x810 -1 read-write n 0x0 0x0 I2C_SRIS_DATARIS Data Raw Interrupt Status 0 1 I2C_SRIS_DMARXRIS Receive DMA Raw Interrupt Status 3 4 I2C_SRIS_DMATXRIS Transmit DMA Raw Interrupt Status 4 5 I2C_SRIS_RXFFRIS Receive FIFO Full Raw Interrupt Status 8 9 I2C_SRIS_RXRIS Receive FIFO Request Raw Interrupt Status 6 7 I2C_SRIS_STARTRIS Start Condition Raw Interrupt Status 1 2 I2C_SRIS_STOPRIS Stop Condition Raw Interrupt Status 2 3 I2C_SRIS_TXFERIS Transmit FIFO Empty Raw Interrupt Status 7 8 I2C_SRIS_TXRIS Transmit Request Raw Interrupt Status 5 6 I2C2 Register map for I2C0 peripheral I2C 0x0 0x0 0x1000 registers n I2C2 61 FIFOCTL I2C FIFO Control 0xF04 -1 read-write n 0x0 0x0 I2C_FIFOCTL_DMARXENA DMA RX Channel Enable 29 30 I2C_FIFOCTL_DMATXENA DMA TX Channel Enable 13 14 I2C_FIFOCTL_RXASGNMT RX Control Assignment 31 32 I2C_FIFOCTL_RXFLUSH RX FIFO Flush 30 31 I2C_FIFOCTL_RXTRIG RX FIFO Trigger 16 19 I2C_FIFOCTL_TXASGNMT TX Control Assignment 15 16 I2C_FIFOCTL_TXFLUSH TX FIFO Flush 14 15 I2C_FIFOCTL_TXTRIG TX FIFO Trigger 0 3 FIFODATA I2C FIFO Data 0xF00 -1 read-write n 0x0 0x0 I2C_FIFODATA_DATA I2C TX FIFO Write Data Byte 0 8 FIFOSTATUS I2C FIFO Status 0xF08 -1 read-write n 0x0 0x0 I2C_FIFOSTATUS_RXABVTRIG RX FIFO Above Trigger Level 18 19 I2C_FIFOSTATUS_RXFE RX FIFO Empty 16 17 I2C_FIFOSTATUS_RXFF RX FIFO Full 17 18 I2C_FIFOSTATUS_TXBLWTRIG TX FIFO Below Trigger Level 2 3 I2C_FIFOSTATUS_TXFE TX FIFO Empty 0 1 I2C_FIFOSTATUS_TXFF TX FIFO Full 1 2 I2C0FIFOCTL I2C FIFO Control 0xF04 read-write n 0x0 0x0 I2C_FIFOCTL_DMARXENA DMA RX Channel Enable 29 30 I2C_FIFOCTL_DMATXENA DMA TX Channel Enable 13 14 I2C_FIFOCTL_RXASGNMT RX Control Assignment 31 32 I2C_FIFOCTL_RXFLUSH RX FIFO Flush 30 31 I2C_FIFOCTL_RXTRIG RX FIFO Trigger 16 19 I2C_FIFOCTL_TXASGNMT TX Control Assignment 15 16 I2C_FIFOCTL_TXFLUSH TX FIFO Flush 14 15 I2C_FIFOCTL_TXTRIG TX FIFO Trigger 0 3 I2C0FIFODATA I2C FIFO Data 0xF00 read-write n 0x0 0x0 I2C_FIFODATA_DATA I2C TX FIFO Write Data Byte 0 8 I2C0FIFOSTATUS I2C FIFO Status 0xF08 read-write n 0x0 0x0 I2C_FIFOSTATUS_RXABVTRIG RX FIFO Above Trigger Level 18 19 I2C_FIFOSTATUS_RXFE RX FIFO Empty 16 17 I2C_FIFOSTATUS_RXFF RX FIFO Full 17 18 I2C_FIFOSTATUS_TXBLWTRIG TX FIFO Below Trigger Level 2 3 I2C_FIFOSTATUS_TXFE TX FIFO Empty 0 1 I2C_FIFOSTATUS_TXFF TX FIFO Full 1 2 I2C0MBCNT I2C Master Burst Count 0x34 read-write n 0x0 0x0 I2C_MBCNT_CNTL I2C Master Burst Count 0 8 I2C0MBLEN I2C Master Burst Length 0x30 read-write n 0x0 0x0 I2C_MBLEN_CNTL I2C Burst Length 0 8 I2C0MBMON I2C Master Bus Monitor 0x2C read-write n 0x0 0x0 I2C_MBMON_SCL I2C SCL Status 0 1 I2C_MBMON_SDA I2C SDA Status 1 2 I2C0MCLKOCNT I2C Master Clock Low Timeout Count 0x24 read-write n 0x0 0x0 I2C_MCLKOCNT_CNTL I2C Master Count 0 8 I2C0MCR I2C Master Configuration 0x20 read-write n 0x0 0x0 I2C_MCR_LPBK I2C Loopback 0 1 I2C_MCR_MFE I2C Master Function Enable 4 5 I2C_MCR_SFE I2C Slave Function Enable 5 6 I2C0MCS I2C Master Control/Status 0x4 read-write n 0x0 0x0 I2C_MCS_ACK Data Acknowledge Enable 3 4 I2C_MCS_ACTDMARX DMA RX Active Status 31 32 I2C_MCS_ACTDMATX DMA TX Active Status 30 31 I2C_MCS_ADRACK Acknowledge Address 2 3 I2C_MCS_ARBLST Arbitration Lost 4 5 I2C_MCS_BURST Burst Enable 6 7 I2C_MCS_CLKTO Clock Timeout Error 7 8 I2C_MCS_IDLE I2C Idle 5 6 I2C_MCS_RUN I2C Master Enable 0 1 I2C_MCS_START Generate START 1 2 I2C0MDR I2C Master Data 0x8 read-write n 0x0 0x0 I2C_MDR_DATA This byte contains the data transferred during a transaction 0 8 I2C0MICR I2C Master Interrupt Clear 0x1C write-only n 0x0 0x0 I2C_MICR_ARBLOSTIC Arbitration Lost Interrupt Clear 7 8 write-only I2C_MICR_CLKIC Clock Timeout Interrupt Clear 1 2 write-only I2C_MICR_DMARXIC Receive DMA Interrupt Clear 2 3 write-only I2C_MICR_DMATXIC Transmit DMA Interrupt Clear 3 4 write-only I2C_MICR_IC Master Interrupt Clear 0 1 write-only I2C_MICR_NACKIC Address/Data NACK Interrupt Clear 4 5 write-only I2C_MICR_RXFFIC Receive FIFO Full Interrupt Clear 11 12 write-only I2C_MICR_RXIC Receive FIFO Request Interrupt Clear 9 10 write-only I2C_MICR_STARTIC START Detection Interrupt Clear 5 6 write-only I2C_MICR_STOPIC STOP Detection Interrupt Clear 6 7 write-only I2C_MICR_TXFEIC Transmit FIFO Empty Interrupt Clear 10 11 write-only I2C_MICR_TXIC Transmit FIFO Request Interrupt Clear 8 9 write-only I2C0MIMR I2C Master Interrupt Mask 0x10 read-write n 0x0 0x0 I2C_MIMR_ARBLOSTIM Arbitration Lost Interrupt Mask 7 8 I2C_MIMR_CLKIM Clock Timeout Interrupt Mask 1 2 I2C_MIMR_DMARXIM Receive DMA Interrupt Mask 2 3 I2C_MIMR_DMATXIM Transmit DMA Interrupt Mask 3 4 I2C_MIMR_IM Master Interrupt Mask 0 1 I2C_MIMR_NACKIM Address/Data NACK Interrupt Mask 4 5 I2C_MIMR_RXFFIM Receive FIFO Full Interrupt Mask 11 12 I2C_MIMR_RXIM Receive FIFO Request Interrupt Mask 9 10 I2C_MIMR_STARTIM START Detection Interrupt Mask 5 6 I2C_MIMR_STOPIM STOP Detection Interrupt Mask 6 7 I2C_MIMR_TXFEIM Transmit FIFO Empty Interrupt Mask 10 11 I2C_MIMR_TXIM Transmit FIFO Request Interrupt Mask 8 9 I2C0MMIS I2C Master Masked Interrupt Status 0x18 read-write n 0x0 0x0 I2C_MMIS_ARBLOSTMIS Arbitration Lost Interrupt Mask 7 8 I2C_MMIS_CLKMIS Clock Timeout Masked Interrupt Status 1 2 I2C_MMIS_DMARXMIS Receive DMA Interrupt Status 2 3 I2C_MMIS_DMATXMIS Transmit DMA Interrupt Status 3 4 I2C_MMIS_MIS Masked Interrupt Status 0 1 I2C_MMIS_NACKMIS Address/Data NACK Interrupt Mask 4 5 I2C_MMIS_RXFFMIS Receive FIFO Full Interrupt Mask 11 12 I2C_MMIS_RXMIS Receive FIFO Request Interrupt Mask 9 10 I2C_MMIS_STARTMIS START Detection Interrupt Mask 5 6 I2C_MMIS_STOPMIS STOP Detection Interrupt Mask 6 7 I2C_MMIS_TXFEMIS Transmit FIFO Empty Interrupt Mask 10 11 I2C_MMIS_TXMIS Transmit Request Interrupt Mask 8 9 I2C0MRIS I2C Master Raw Interrupt Status 0x14 read-write n 0x0 0x0 I2C_MRIS_ARBLOSTRIS Arbitration Lost Raw Interrupt Status 7 8 I2C_MRIS_CLKRIS Clock Timeout Raw Interrupt Status 1 2 I2C_MRIS_DMARXRIS Receive DMA Raw Interrupt Status 2 3 I2C_MRIS_DMATXRIS Transmit DMA Raw Interrupt Status 3 4 I2C_MRIS_NACKRIS Address/Data NACK Raw Interrupt Status 4 5 I2C_MRIS_RIS Master Raw Interrupt Status 0 1 I2C_MRIS_RXFFRIS Receive FIFO Full Raw Interrupt Status 11 12 I2C_MRIS_RXRIS Receive FIFO Request Raw Interrupt Status 9 10 I2C_MRIS_STARTRIS START Detection Raw Interrupt Status 5 6 I2C_MRIS_STOPRIS STOP Detection Raw Interrupt Status 6 7 I2C_MRIS_TXFERIS Transmit FIFO Empty Raw Interrupt Status 10 11 I2C_MRIS_TXRIS Transmit Request Raw Interrupt Status 8 9 I2C0MSA I2C Master Slave Address 0x0 read-write n 0x0 0x0 I2C_MSA_RS Receive not send 0 1 I2C_MSA_SA I2C Slave Address 1 8 I2C0MTPR I2C Master Timer Period 0xC read-write n 0x0 0x0 I2C_MTPR_HS High-Speed Enable 7 8 I2C_MTPR_PULSEL Glitch Suppression Pulse Width 16 19 I2C_MTPR_PULSEL_BYPASS Bypass 0x0 I2C_MTPR_PULSEL_1 1 clock 0x1 I2C_MTPR_PULSEL_2 2 clocks 0x2 I2C_MTPR_PULSEL_3 3 clocks 0x3 I2C_MTPR_PULSEL_4 4 clocks 0x4 I2C_MTPR_PULSEL_8 8 clocks 0x5 I2C_MTPR_PULSEL_16 16 clocks 0x6 I2C_MTPR_PULSEL_31 31 clocks 0x7 I2C_MTPR_TPR Timer Period 0 7 I2C0PC I2C Peripheral Configuration 0xFC4 read-write n 0x0 0x0 I2C_PC_HS High-Speed Capable 0 1 I2C0PP I2C Peripheral Properties 0xFC0 read-write n 0x0 0x0 I2C_PP_HS High-Speed Capable 0 1 I2C0SACKCTL I2C Slave ACK Control 0x820 read-write n 0x0 0x0 I2C_SACKCTL_ACKOEN I2C Slave ACK Override Enable 0 1 I2C_SACKCTL_ACKOVAL I2C Slave ACK Override Value 1 2 I2C0SCSR I2C Slave Control/Status 0x804 read-write n 0x0 0x0 I2C_SCSR_ACTDMARX DMA RX Active Status 31 32 I2C_SCSR_ACTDMATX DMA TX Active Status 30 31 I2C_SCSR_FBR First Byte Received 2 3 I2C_SCSR_OAR2SEL OAR2 Address Matched 3 4 I2C_SCSR_QCMDRW Quick Command Read / Write 5 6 I2C_SCSR_QCMDST Quick Command Status 4 5 I2C_SCSR_RREQ Receive Request 0 1 I2C_SCSR_TXFIFO TX FIFO Enable 1 2 I2C0SDR I2C Slave Data 0x808 read-write n 0x0 0x0 I2C_SDR_DATA Data for Transfer 0 8 I2C0SICR I2C Slave Interrupt Clear 0x818 write-only n 0x0 0x0 I2C_SICR_DATAIC Data Interrupt Clear 0 1 write-only I2C_SICR_DMARXIC Receive DMA Interrupt Clear 3 4 write-only I2C_SICR_DMATXIC Transmit DMA Interrupt Clear 4 5 write-only I2C_SICR_RXFFIC Receive FIFO Full Interrupt Mask 8 9 write-only I2C_SICR_RXIC Receive Request Interrupt Mask 6 7 write-only I2C_SICR_STARTIC Start Condition Interrupt Clear 1 2 write-only I2C_SICR_STOPIC Stop Condition Interrupt Clear 2 3 write-only I2C_SICR_TXFEIC Transmit FIFO Empty Interrupt Mask 7 8 write-only I2C_SICR_TXIC Transmit Request Interrupt Mask 5 6 write-only I2C0SIMR I2C Slave Interrupt Mask 0x80C read-write n 0x0 0x0 I2C_SIMR_DATAIM Data Interrupt Mask 0 1 I2C_SIMR_DMARXIM Receive DMA Interrupt Mask 3 4 I2C_SIMR_DMATXIM Transmit DMA Interrupt Mask 4 5 I2C_SIMR_RXFFIM Receive FIFO Full Interrupt Mask 8 9 I2C_SIMR_RXIM Receive FIFO Request Interrupt Mask 6 7 I2C_SIMR_STARTIM Start Condition Interrupt Mask 1 2 I2C_SIMR_STOPIM Stop Condition Interrupt Mask 2 3 I2C_SIMR_TXFEIM Transmit FIFO Empty Interrupt Mask 7 8 I2C_SIMR_TXIM Transmit FIFO Request Interrupt Mask 5 6 I2C0SMIS I2C Slave Masked Interrupt Status 0x814 read-write n 0x0 0x0 I2C_SMIS_DATAMIS Data Masked Interrupt Status 0 1 I2C_SMIS_DMARXMIS Receive DMA Masked Interrupt Status 3 4 I2C_SMIS_DMATXMIS Transmit DMA Masked Interrupt Status 4 5 I2C_SMIS_RXFFMIS Receive FIFO Full Interrupt Mask 8 9 I2C_SMIS_RXMIS Receive FIFO Request Interrupt Mask 6 7 I2C_SMIS_STARTMIS Start Condition Masked Interrupt Status 1 2 I2C_SMIS_STOPMIS Stop Condition Masked Interrupt Status 2 3 I2C_SMIS_TXFEMIS Transmit FIFO Empty Interrupt Mask 7 8 I2C_SMIS_TXMIS Transmit FIFO Request Interrupt Mask 5 6 I2C0SOAR I2C Slave Own Address 0x800 read-write n 0x0 0x0 I2C_SOAR_OAR I2C Slave Own Address 0 7 I2C0SOAR2 I2C Slave Own Address 2 0x81C read-write n 0x0 0x0 I2C_SOAR2_OAR2 I2C Slave Own Address 2 0 7 I2C_SOAR2_OAR2EN I2C Slave Own Address 2 Enable 7 8 I2C0SRIS I2C Slave Raw Interrupt Status 0x810 read-write n 0x0 0x0 I2C_SRIS_DATARIS Data Raw Interrupt Status 0 1 I2C_SRIS_DMARXRIS Receive DMA Raw Interrupt Status 3 4 I2C_SRIS_DMATXRIS Transmit DMA Raw Interrupt Status 4 5 I2C_SRIS_RXFFRIS Receive FIFO Full Raw Interrupt Status 8 9 I2C_SRIS_RXRIS Receive FIFO Request Raw Interrupt Status 6 7 I2C_SRIS_STARTRIS Start Condition Raw Interrupt Status 1 2 I2C_SRIS_STOPRIS Stop Condition Raw Interrupt Status 2 3 I2C_SRIS_TXFERIS Transmit FIFO Empty Raw Interrupt Status 7 8 I2C_SRIS_TXRIS Transmit Request Raw Interrupt Status 5 6 MBCNT I2C Master Burst Count 0x34 -1 read-write n 0x0 0x0 I2C_MBCNT_CNTL I2C Master Burst Count 0 8 MBLEN I2C Master Burst Length 0x30 -1 read-write n 0x0 0x0 I2C_MBLEN_CNTL I2C Burst Length 0 8 MBMON I2C Master Bus Monitor 0x2C -1 read-write n 0x0 0x0 I2C_MBMON_SCL I2C SCL Status 0 1 I2C_MBMON_SDA I2C SDA Status 1 2 MCLKOCNT I2C Master Clock Low Timeout Count 0x24 -1 read-write n 0x0 0x0 I2C_MCLKOCNT_CNTL I2C Master Count 0 8 MCR I2C Master Configuration 0x20 -1 read-write n 0x0 0x0 I2C_MCR_LPBK I2C Loopback 0 1 I2C_MCR_MFE I2C Master Function Enable 4 5 I2C_MCR_SFE I2C Slave Function Enable 5 6 MCS I2C Master Control/Status 0x4 -1 read-write n 0x0 0x0 I2C_MCS_ACK Data Acknowledge Enable 3 4 I2C_MCS_ACTDMARX DMA RX Active Status 31 32 I2C_MCS_ACTDMATX DMA TX Active Status 30 31 I2C_MCS_ADRACK Acknowledge Address 2 3 I2C_MCS_ARBLST Arbitration Lost 4 5 I2C_MCS_BURST Burst Enable 6 7 I2C_MCS_BUSBSY Bus Busy 6 7 I2C_MCS_BUSY I2C Busy 0 1 I2C_MCS_CLKTO Clock Timeout Error 7 8 I2C_MCS_DATACK Acknowledge Data 3 4 I2C_MCS_ERROR Error 1 2 I2C_MCS_HS High-Speed Enable 4 5 I2C_MCS_IDLE I2C Idle 5 6 I2C_MCS_QCMD Quick Command 5 6 I2C_MCS_RUN I2C Master Enable 0 1 I2C_MCS_START Generate START 1 2 I2C_MCS_STOP Generate STOP 2 3 MDR I2C Master Data 0x8 -1 read-write n 0x0 0x0 I2C_MDR_DATA This byte contains the data transferred during a transaction 0 8 MICR I2C Master Interrupt Clear 0x1C -1 write-only n 0x0 0x0 I2C_MICR_ARBLOSTIC Arbitration Lost Interrupt Clear 7 8 write-only I2C_MICR_CLKIC Clock Timeout Interrupt Clear 1 2 write-only I2C_MICR_DMARXIC Receive DMA Interrupt Clear 2 3 write-only I2C_MICR_DMATXIC Transmit DMA Interrupt Clear 3 4 write-only I2C_MICR_IC Master Interrupt Clear 0 1 write-only I2C_MICR_NACKIC Address/Data NACK Interrupt Clear 4 5 write-only I2C_MICR_RXFFIC Receive FIFO Full Interrupt Clear 11 12 write-only I2C_MICR_RXIC Receive FIFO Request Interrupt Clear 9 10 write-only I2C_MICR_STARTIC START Detection Interrupt Clear 5 6 write-only I2C_MICR_STOPIC STOP Detection Interrupt Clear 6 7 write-only I2C_MICR_TXFEIC Transmit FIFO Empty Interrupt Clear 10 11 write-only I2C_MICR_TXIC Transmit FIFO Request Interrupt Clear 8 9 write-only MIMR I2C Master Interrupt Mask 0x10 -1 read-write n 0x0 0x0 I2C_MIMR_ARBLOSTIM Arbitration Lost Interrupt Mask 7 8 I2C_MIMR_CLKIM Clock Timeout Interrupt Mask 1 2 I2C_MIMR_DMARXIM Receive DMA Interrupt Mask 2 3 I2C_MIMR_DMATXIM Transmit DMA Interrupt Mask 3 4 I2C_MIMR_IM Master Interrupt Mask 0 1 I2C_MIMR_NACKIM Address/Data NACK Interrupt Mask 4 5 I2C_MIMR_RXFFIM Receive FIFO Full Interrupt Mask 11 12 I2C_MIMR_RXIM Receive FIFO Request Interrupt Mask 9 10 I2C_MIMR_STARTIM START Detection Interrupt Mask 5 6 I2C_MIMR_STOPIM STOP Detection Interrupt Mask 6 7 I2C_MIMR_TXFEIM Transmit FIFO Empty Interrupt Mask 10 11 I2C_MIMR_TXIM Transmit FIFO Request Interrupt Mask 8 9 MMIS I2C Master Masked Interrupt Status 0x18 -1 read-write n 0x0 0x0 I2C_MMIS_ARBLOSTMIS Arbitration Lost Interrupt Mask 7 8 I2C_MMIS_CLKMIS Clock Timeout Masked Interrupt Status 1 2 I2C_MMIS_DMARXMIS Receive DMA Interrupt Status 2 3 I2C_MMIS_DMATXMIS Transmit DMA Interrupt Status 3 4 I2C_MMIS_MIS Masked Interrupt Status 0 1 I2C_MMIS_NACKMIS Address/Data NACK Interrupt Mask 4 5 I2C_MMIS_RXFFMIS Receive FIFO Full Interrupt Mask 11 12 I2C_MMIS_RXMIS Receive FIFO Request Interrupt Mask 9 10 I2C_MMIS_STARTMIS START Detection Interrupt Mask 5 6 I2C_MMIS_STOPMIS STOP Detection Interrupt Mask 6 7 I2C_MMIS_TXFEMIS Transmit FIFO Empty Interrupt Mask 10 11 I2C_MMIS_TXMIS Transmit Request Interrupt Mask 8 9 MRIS I2C Master Raw Interrupt Status 0x14 -1 read-write n 0x0 0x0 I2C_MRIS_ARBLOSTRIS Arbitration Lost Raw Interrupt Status 7 8 I2C_MRIS_CLKRIS Clock Timeout Raw Interrupt Status 1 2 I2C_MRIS_DMARXRIS Receive DMA Raw Interrupt Status 2 3 I2C_MRIS_DMATXRIS Transmit DMA Raw Interrupt Status 3 4 I2C_MRIS_NACKRIS Address/Data NACK Raw Interrupt Status 4 5 I2C_MRIS_RIS Master Raw Interrupt Status 0 1 I2C_MRIS_RXFFRIS Receive FIFO Full Raw Interrupt Status 11 12 I2C_MRIS_RXRIS Receive FIFO Request Raw Interrupt Status 9 10 I2C_MRIS_STARTRIS START Detection Raw Interrupt Status 5 6 I2C_MRIS_STOPRIS STOP Detection Raw Interrupt Status 6 7 I2C_MRIS_TXFERIS Transmit FIFO Empty Raw Interrupt Status 10 11 I2C_MRIS_TXRIS Transmit Request Raw Interrupt Status 8 9 MSA I2C Master Slave Address 0x0 -1 read-write n 0x0 0x0 I2C_MSA_RS Receive not send 0 1 I2C_MSA_SA I2C Slave Address 1 8 MTPR I2C Master Timer Period 0xC -1 read-write n 0x0 0x0 I2C_MTPR_HS High-Speed Enable 7 8 I2C_MTPR_PULSEL Glitch Suppression Pulse Width 16 19 I2C_MTPR_PULSEL_BYPASS Bypass 0x0 I2C_MTPR_PULSEL_1 1 clock 0x1 I2C_MTPR_PULSEL_2 2 clocks 0x2 I2C_MTPR_PULSEL_3 3 clocks 0x3 I2C_MTPR_PULSEL_4 4 clocks 0x4 I2C_MTPR_PULSEL_8 8 clocks 0x5 I2C_MTPR_PULSEL_16 16 clocks 0x6 I2C_MTPR_PULSEL_31 31 clocks 0x7 I2C_MTPR_TPR Timer Period 0 7 PC I2C Peripheral Configuration 0xFC4 -1 read-write n 0x0 0x0 I2C_PC_HS High-Speed Capable 0 1 PP I2C Peripheral Properties 0xFC0 -1 read-write n 0x0 0x0 I2C_PP_HS High-Speed Capable 0 1 SACKCTL I2C Slave ACK Control 0x820 -1 read-write n 0x0 0x0 I2C_SACKCTL_ACKOEN I2C Slave ACK Override Enable 0 1 I2C_SACKCTL_ACKOVAL I2C Slave ACK Override Value 1 2 SCSR I2C Slave Control/Status 0x804 -1 read-write n 0x0 0x0 I2C_SCSR_ACTDMARX DMA RX Active Status 31 32 I2C_SCSR_ACTDMATX DMA TX Active Status 30 31 I2C_SCSR_DA Device Active 0 1 I2C_SCSR_FBR First Byte Received 2 3 I2C_SCSR_OAR2SEL OAR2 Address Matched 3 4 I2C_SCSR_QCMDRW Quick Command Read / Write 5 6 I2C_SCSR_QCMDST Quick Command Status 4 5 I2C_SCSR_RREQ Receive Request 0 1 I2C_SCSR_RXFIFO RX FIFO Enable 2 3 I2C_SCSR_TREQ Transmit Request 1 2 I2C_SCSR_TXFIFO TX FIFO Enable 1 2 SDR I2C Slave Data 0x808 -1 read-write n 0x0 0x0 I2C_SDR_DATA Data for Transfer 0 8 SICR I2C Slave Interrupt Clear 0x818 -1 write-only n 0x0 0x0 I2C_SICR_DATAIC Data Interrupt Clear 0 1 write-only I2C_SICR_DMARXIC Receive DMA Interrupt Clear 3 4 write-only I2C_SICR_DMATXIC Transmit DMA Interrupt Clear 4 5 write-only I2C_SICR_RXFFIC Receive FIFO Full Interrupt Mask 8 9 write-only I2C_SICR_RXIC Receive Request Interrupt Mask 6 7 write-only I2C_SICR_STARTIC Start Condition Interrupt Clear 1 2 write-only I2C_SICR_STOPIC Stop Condition Interrupt Clear 2 3 write-only I2C_SICR_TXFEIC Transmit FIFO Empty Interrupt Mask 7 8 write-only I2C_SICR_TXIC Transmit Request Interrupt Mask 5 6 write-only SIMR I2C Slave Interrupt Mask 0x80C -1 read-write n 0x0 0x0 I2C_SIMR_DATAIM Data Interrupt Mask 0 1 I2C_SIMR_DMARXIM Receive DMA Interrupt Mask 3 4 I2C_SIMR_DMATXIM Transmit DMA Interrupt Mask 4 5 I2C_SIMR_RXFFIM Receive FIFO Full Interrupt Mask 8 9 I2C_SIMR_RXIM Receive FIFO Request Interrupt Mask 6 7 I2C_SIMR_STARTIM Start Condition Interrupt Mask 1 2 I2C_SIMR_STOPIM Stop Condition Interrupt Mask 2 3 I2C_SIMR_TXFEIM Transmit FIFO Empty Interrupt Mask 7 8 I2C_SIMR_TXIM Transmit FIFO Request Interrupt Mask 5 6 SMIS I2C Slave Masked Interrupt Status 0x814 -1 read-write n 0x0 0x0 I2C_SMIS_DATAMIS Data Masked Interrupt Status 0 1 I2C_SMIS_DMARXMIS Receive DMA Masked Interrupt Status 3 4 I2C_SMIS_DMATXMIS Transmit DMA Masked Interrupt Status 4 5 I2C_SMIS_RXFFMIS Receive FIFO Full Interrupt Mask 8 9 I2C_SMIS_RXMIS Receive FIFO Request Interrupt Mask 6 7 I2C_SMIS_STARTMIS Start Condition Masked Interrupt Status 1 2 I2C_SMIS_STOPMIS Stop Condition Masked Interrupt Status 2 3 I2C_SMIS_TXFEMIS Transmit FIFO Empty Interrupt Mask 7 8 I2C_SMIS_TXMIS Transmit FIFO Request Interrupt Mask 5 6 SOAR I2C Slave Own Address 0x800 -1 read-write n 0x0 0x0 I2C_SOAR_OAR I2C Slave Own Address 0 7 SOAR2 I2C Slave Own Address 2 0x81C -1 read-write n 0x0 0x0 I2C_SOAR2_OAR2 I2C Slave Own Address 2 0 7 I2C_SOAR2_OAR2EN I2C Slave Own Address 2 Enable 7 8 SRIS I2C Slave Raw Interrupt Status 0x810 -1 read-write n 0x0 0x0 I2C_SRIS_DATARIS Data Raw Interrupt Status 0 1 I2C_SRIS_DMARXRIS Receive DMA Raw Interrupt Status 3 4 I2C_SRIS_DMATXRIS Transmit DMA Raw Interrupt Status 4 5 I2C_SRIS_RXFFRIS Receive FIFO Full Raw Interrupt Status 8 9 I2C_SRIS_RXRIS Receive FIFO Request Raw Interrupt Status 6 7 I2C_SRIS_STARTRIS Start Condition Raw Interrupt Status 1 2 I2C_SRIS_STOPRIS Stop Condition Raw Interrupt Status 2 3 I2C_SRIS_TXFERIS Transmit FIFO Empty Raw Interrupt Status 7 8 I2C_SRIS_TXRIS Transmit Request Raw Interrupt Status 5 6 I2C3 Register map for I2C0 peripheral I2C 0x0 0x0 0x1000 registers n I2C3 62 FIFOCTL I2C FIFO Control 0xF04 -1 read-write n 0x0 0x0 I2C_FIFOCTL_DMARXENA DMA RX Channel Enable 29 30 I2C_FIFOCTL_DMATXENA DMA TX Channel Enable 13 14 I2C_FIFOCTL_RXASGNMT RX Control Assignment 31 32 I2C_FIFOCTL_RXFLUSH RX FIFO Flush 30 31 I2C_FIFOCTL_RXTRIG RX FIFO Trigger 16 19 I2C_FIFOCTL_TXASGNMT TX Control Assignment 15 16 I2C_FIFOCTL_TXFLUSH TX FIFO Flush 14 15 I2C_FIFOCTL_TXTRIG TX FIFO Trigger 0 3 FIFODATA I2C FIFO Data 0xF00 -1 read-write n 0x0 0x0 I2C_FIFODATA_DATA I2C TX FIFO Write Data Byte 0 8 FIFOSTATUS I2C FIFO Status 0xF08 -1 read-write n 0x0 0x0 I2C_FIFOSTATUS_RXABVTRIG RX FIFO Above Trigger Level 18 19 I2C_FIFOSTATUS_RXFE RX FIFO Empty 16 17 I2C_FIFOSTATUS_RXFF RX FIFO Full 17 18 I2C_FIFOSTATUS_TXBLWTRIG TX FIFO Below Trigger Level 2 3 I2C_FIFOSTATUS_TXFE TX FIFO Empty 0 1 I2C_FIFOSTATUS_TXFF TX FIFO Full 1 2 I2C0FIFOCTL I2C FIFO Control 0xF04 read-write n 0x0 0x0 I2C_FIFOCTL_DMARXENA DMA RX Channel Enable 29 30 I2C_FIFOCTL_DMATXENA DMA TX Channel Enable 13 14 I2C_FIFOCTL_RXASGNMT RX Control Assignment 31 32 I2C_FIFOCTL_RXFLUSH RX FIFO Flush 30 31 I2C_FIFOCTL_RXTRIG RX FIFO Trigger 16 19 I2C_FIFOCTL_TXASGNMT TX Control Assignment 15 16 I2C_FIFOCTL_TXFLUSH TX FIFO Flush 14 15 I2C_FIFOCTL_TXTRIG TX FIFO Trigger 0 3 I2C0FIFODATA I2C FIFO Data 0xF00 read-write n 0x0 0x0 I2C_FIFODATA_DATA I2C TX FIFO Write Data Byte 0 8 I2C0FIFOSTATUS I2C FIFO Status 0xF08 read-write n 0x0 0x0 I2C_FIFOSTATUS_RXABVTRIG RX FIFO Above Trigger Level 18 19 I2C_FIFOSTATUS_RXFE RX FIFO Empty 16 17 I2C_FIFOSTATUS_RXFF RX FIFO Full 17 18 I2C_FIFOSTATUS_TXBLWTRIG TX FIFO Below Trigger Level 2 3 I2C_FIFOSTATUS_TXFE TX FIFO Empty 0 1 I2C_FIFOSTATUS_TXFF TX FIFO Full 1 2 I2C0MBCNT I2C Master Burst Count 0x34 read-write n 0x0 0x0 I2C_MBCNT_CNTL I2C Master Burst Count 0 8 I2C0MBLEN I2C Master Burst Length 0x30 read-write n 0x0 0x0 I2C_MBLEN_CNTL I2C Burst Length 0 8 I2C0MBMON I2C Master Bus Monitor 0x2C read-write n 0x0 0x0 I2C_MBMON_SCL I2C SCL Status 0 1 I2C_MBMON_SDA I2C SDA Status 1 2 I2C0MCLKOCNT I2C Master Clock Low Timeout Count 0x24 read-write n 0x0 0x0 I2C_MCLKOCNT_CNTL I2C Master Count 0 8 I2C0MCR I2C Master Configuration 0x20 read-write n 0x0 0x0 I2C_MCR_LPBK I2C Loopback 0 1 I2C_MCR_MFE I2C Master Function Enable 4 5 I2C_MCR_SFE I2C Slave Function Enable 5 6 I2C0MCS I2C Master Control/Status 0x4 read-write n 0x0 0x0 I2C_MCS_ACK Data Acknowledge Enable 3 4 I2C_MCS_ACTDMARX DMA RX Active Status 31 32 I2C_MCS_ACTDMATX DMA TX Active Status 30 31 I2C_MCS_ADRACK Acknowledge Address 2 3 I2C_MCS_ARBLST Arbitration Lost 4 5 I2C_MCS_BURST Burst Enable 6 7 I2C_MCS_CLKTO Clock Timeout Error 7 8 I2C_MCS_IDLE I2C Idle 5 6 I2C_MCS_RUN I2C Master Enable 0 1 I2C_MCS_START Generate START 1 2 I2C0MDR I2C Master Data 0x8 read-write n 0x0 0x0 I2C_MDR_DATA This byte contains the data transferred during a transaction 0 8 I2C0MICR I2C Master Interrupt Clear 0x1C write-only n 0x0 0x0 I2C_MICR_ARBLOSTIC Arbitration Lost Interrupt Clear 7 8 write-only I2C_MICR_CLKIC Clock Timeout Interrupt Clear 1 2 write-only I2C_MICR_DMARXIC Receive DMA Interrupt Clear 2 3 write-only I2C_MICR_DMATXIC Transmit DMA Interrupt Clear 3 4 write-only I2C_MICR_IC Master Interrupt Clear 0 1 write-only I2C_MICR_NACKIC Address/Data NACK Interrupt Clear 4 5 write-only I2C_MICR_RXFFIC Receive FIFO Full Interrupt Clear 11 12 write-only I2C_MICR_RXIC Receive FIFO Request Interrupt Clear 9 10 write-only I2C_MICR_STARTIC START Detection Interrupt Clear 5 6 write-only I2C_MICR_STOPIC STOP Detection Interrupt Clear 6 7 write-only I2C_MICR_TXFEIC Transmit FIFO Empty Interrupt Clear 10 11 write-only I2C_MICR_TXIC Transmit FIFO Request Interrupt Clear 8 9 write-only I2C0MIMR I2C Master Interrupt Mask 0x10 read-write n 0x0 0x0 I2C_MIMR_ARBLOSTIM Arbitration Lost Interrupt Mask 7 8 I2C_MIMR_CLKIM Clock Timeout Interrupt Mask 1 2 I2C_MIMR_DMARXIM Receive DMA Interrupt Mask 2 3 I2C_MIMR_DMATXIM Transmit DMA Interrupt Mask 3 4 I2C_MIMR_IM Master Interrupt Mask 0 1 I2C_MIMR_NACKIM Address/Data NACK Interrupt Mask 4 5 I2C_MIMR_RXFFIM Receive FIFO Full Interrupt Mask 11 12 I2C_MIMR_RXIM Receive FIFO Request Interrupt Mask 9 10 I2C_MIMR_STARTIM START Detection Interrupt Mask 5 6 I2C_MIMR_STOPIM STOP Detection Interrupt Mask 6 7 I2C_MIMR_TXFEIM Transmit FIFO Empty Interrupt Mask 10 11 I2C_MIMR_TXIM Transmit FIFO Request Interrupt Mask 8 9 I2C0MMIS I2C Master Masked Interrupt Status 0x18 read-write n 0x0 0x0 I2C_MMIS_ARBLOSTMIS Arbitration Lost Interrupt Mask 7 8 I2C_MMIS_CLKMIS Clock Timeout Masked Interrupt Status 1 2 I2C_MMIS_DMARXMIS Receive DMA Interrupt Status 2 3 I2C_MMIS_DMATXMIS Transmit DMA Interrupt Status 3 4 I2C_MMIS_MIS Masked Interrupt Status 0 1 I2C_MMIS_NACKMIS Address/Data NACK Interrupt Mask 4 5 I2C_MMIS_RXFFMIS Receive FIFO Full Interrupt Mask 11 12 I2C_MMIS_RXMIS Receive FIFO Request Interrupt Mask 9 10 I2C_MMIS_STARTMIS START Detection Interrupt Mask 5 6 I2C_MMIS_STOPMIS STOP Detection Interrupt Mask 6 7 I2C_MMIS_TXFEMIS Transmit FIFO Empty Interrupt Mask 10 11 I2C_MMIS_TXMIS Transmit Request Interrupt Mask 8 9 I2C0MRIS I2C Master Raw Interrupt Status 0x14 read-write n 0x0 0x0 I2C_MRIS_ARBLOSTRIS Arbitration Lost Raw Interrupt Status 7 8 I2C_MRIS_CLKRIS Clock Timeout Raw Interrupt Status 1 2 I2C_MRIS_DMARXRIS Receive DMA Raw Interrupt Status 2 3 I2C_MRIS_DMATXRIS Transmit DMA Raw Interrupt Status 3 4 I2C_MRIS_NACKRIS Address/Data NACK Raw Interrupt Status 4 5 I2C_MRIS_RIS Master Raw Interrupt Status 0 1 I2C_MRIS_RXFFRIS Receive FIFO Full Raw Interrupt Status 11 12 I2C_MRIS_RXRIS Receive FIFO Request Raw Interrupt Status 9 10 I2C_MRIS_STARTRIS START Detection Raw Interrupt Status 5 6 I2C_MRIS_STOPRIS STOP Detection Raw Interrupt Status 6 7 I2C_MRIS_TXFERIS Transmit FIFO Empty Raw Interrupt Status 10 11 I2C_MRIS_TXRIS Transmit Request Raw Interrupt Status 8 9 I2C0MSA I2C Master Slave Address 0x0 read-write n 0x0 0x0 I2C_MSA_RS Receive not send 0 1 I2C_MSA_SA I2C Slave Address 1 8 I2C0MTPR I2C Master Timer Period 0xC read-write n 0x0 0x0 I2C_MTPR_HS High-Speed Enable 7 8 I2C_MTPR_PULSEL Glitch Suppression Pulse Width 16 19 I2C_MTPR_PULSEL_BYPASS Bypass 0x0 I2C_MTPR_PULSEL_1 1 clock 0x1 I2C_MTPR_PULSEL_2 2 clocks 0x2 I2C_MTPR_PULSEL_3 3 clocks 0x3 I2C_MTPR_PULSEL_4 4 clocks 0x4 I2C_MTPR_PULSEL_8 8 clocks 0x5 I2C_MTPR_PULSEL_16 16 clocks 0x6 I2C_MTPR_PULSEL_31 31 clocks 0x7 I2C_MTPR_TPR Timer Period 0 7 I2C0PC I2C Peripheral Configuration 0xFC4 read-write n 0x0 0x0 I2C_PC_HS High-Speed Capable 0 1 I2C0PP I2C Peripheral Properties 0xFC0 read-write n 0x0 0x0 I2C_PP_HS High-Speed Capable 0 1 I2C0SACKCTL I2C Slave ACK Control 0x820 read-write n 0x0 0x0 I2C_SACKCTL_ACKOEN I2C Slave ACK Override Enable 0 1 I2C_SACKCTL_ACKOVAL I2C Slave ACK Override Value 1 2 I2C0SCSR I2C Slave Control/Status 0x804 read-write n 0x0 0x0 I2C_SCSR_ACTDMARX DMA RX Active Status 31 32 I2C_SCSR_ACTDMATX DMA TX Active Status 30 31 I2C_SCSR_FBR First Byte Received 2 3 I2C_SCSR_OAR2SEL OAR2 Address Matched 3 4 I2C_SCSR_QCMDRW Quick Command Read / Write 5 6 I2C_SCSR_QCMDST Quick Command Status 4 5 I2C_SCSR_RREQ Receive Request 0 1 I2C_SCSR_TXFIFO TX FIFO Enable 1 2 I2C0SDR I2C Slave Data 0x808 read-write n 0x0 0x0 I2C_SDR_DATA Data for Transfer 0 8 I2C0SICR I2C Slave Interrupt Clear 0x818 write-only n 0x0 0x0 I2C_SICR_DATAIC Data Interrupt Clear 0 1 write-only I2C_SICR_DMARXIC Receive DMA Interrupt Clear 3 4 write-only I2C_SICR_DMATXIC Transmit DMA Interrupt Clear 4 5 write-only I2C_SICR_RXFFIC Receive FIFO Full Interrupt Mask 8 9 write-only I2C_SICR_RXIC Receive Request Interrupt Mask 6 7 write-only I2C_SICR_STARTIC Start Condition Interrupt Clear 1 2 write-only I2C_SICR_STOPIC Stop Condition Interrupt Clear 2 3 write-only I2C_SICR_TXFEIC Transmit FIFO Empty Interrupt Mask 7 8 write-only I2C_SICR_TXIC Transmit Request Interrupt Mask 5 6 write-only I2C0SIMR I2C Slave Interrupt Mask 0x80C read-write n 0x0 0x0 I2C_SIMR_DATAIM Data Interrupt Mask 0 1 I2C_SIMR_DMARXIM Receive DMA Interrupt Mask 3 4 I2C_SIMR_DMATXIM Transmit DMA Interrupt Mask 4 5 I2C_SIMR_RXFFIM Receive FIFO Full Interrupt Mask 8 9 I2C_SIMR_RXIM Receive FIFO Request Interrupt Mask 6 7 I2C_SIMR_STARTIM Start Condition Interrupt Mask 1 2 I2C_SIMR_STOPIM Stop Condition Interrupt Mask 2 3 I2C_SIMR_TXFEIM Transmit FIFO Empty Interrupt Mask 7 8 I2C_SIMR_TXIM Transmit FIFO Request Interrupt Mask 5 6 I2C0SMIS I2C Slave Masked Interrupt Status 0x814 read-write n 0x0 0x0 I2C_SMIS_DATAMIS Data Masked Interrupt Status 0 1 I2C_SMIS_DMARXMIS Receive DMA Masked Interrupt Status 3 4 I2C_SMIS_DMATXMIS Transmit DMA Masked Interrupt Status 4 5 I2C_SMIS_RXFFMIS Receive FIFO Full Interrupt Mask 8 9 I2C_SMIS_RXMIS Receive FIFO Request Interrupt Mask 6 7 I2C_SMIS_STARTMIS Start Condition Masked Interrupt Status 1 2 I2C_SMIS_STOPMIS Stop Condition Masked Interrupt Status 2 3 I2C_SMIS_TXFEMIS Transmit FIFO Empty Interrupt Mask 7 8 I2C_SMIS_TXMIS Transmit FIFO Request Interrupt Mask 5 6 I2C0SOAR I2C Slave Own Address 0x800 read-write n 0x0 0x0 I2C_SOAR_OAR I2C Slave Own Address 0 7 I2C0SOAR2 I2C Slave Own Address 2 0x81C read-write n 0x0 0x0 I2C_SOAR2_OAR2 I2C Slave Own Address 2 0 7 I2C_SOAR2_OAR2EN I2C Slave Own Address 2 Enable 7 8 I2C0SRIS I2C Slave Raw Interrupt Status 0x810 read-write n 0x0 0x0 I2C_SRIS_DATARIS Data Raw Interrupt Status 0 1 I2C_SRIS_DMARXRIS Receive DMA Raw Interrupt Status 3 4 I2C_SRIS_DMATXRIS Transmit DMA Raw Interrupt Status 4 5 I2C_SRIS_RXFFRIS Receive FIFO Full Raw Interrupt Status 8 9 I2C_SRIS_RXRIS Receive FIFO Request Raw Interrupt Status 6 7 I2C_SRIS_STARTRIS Start Condition Raw Interrupt Status 1 2 I2C_SRIS_STOPRIS Stop Condition Raw Interrupt Status 2 3 I2C_SRIS_TXFERIS Transmit FIFO Empty Raw Interrupt Status 7 8 I2C_SRIS_TXRIS Transmit Request Raw Interrupt Status 5 6 MBCNT I2C Master Burst Count 0x34 -1 read-write n 0x0 0x0 I2C_MBCNT_CNTL I2C Master Burst Count 0 8 MBLEN I2C Master Burst Length 0x30 -1 read-write n 0x0 0x0 I2C_MBLEN_CNTL I2C Burst Length 0 8 MBMON I2C Master Bus Monitor 0x2C -1 read-write n 0x0 0x0 I2C_MBMON_SCL I2C SCL Status 0 1 I2C_MBMON_SDA I2C SDA Status 1 2 MCLKOCNT I2C Master Clock Low Timeout Count 0x24 -1 read-write n 0x0 0x0 I2C_MCLKOCNT_CNTL I2C Master Count 0 8 MCR I2C Master Configuration 0x20 -1 read-write n 0x0 0x0 I2C_MCR_LPBK I2C Loopback 0 1 I2C_MCR_MFE I2C Master Function Enable 4 5 I2C_MCR_SFE I2C Slave Function Enable 5 6 MCS I2C Master Control/Status 0x4 -1 read-write n 0x0 0x0 I2C_MCS_ACK Data Acknowledge Enable 3 4 I2C_MCS_ACTDMARX DMA RX Active Status 31 32 I2C_MCS_ACTDMATX DMA TX Active Status 30 31 I2C_MCS_ADRACK Acknowledge Address 2 3 I2C_MCS_ARBLST Arbitration Lost 4 5 I2C_MCS_BURST Burst Enable 6 7 I2C_MCS_BUSBSY Bus Busy 6 7 I2C_MCS_BUSY I2C Busy 0 1 I2C_MCS_CLKTO Clock Timeout Error 7 8 I2C_MCS_DATACK Acknowledge Data 3 4 I2C_MCS_ERROR Error 1 2 I2C_MCS_HS High-Speed Enable 4 5 I2C_MCS_IDLE I2C Idle 5 6 I2C_MCS_QCMD Quick Command 5 6 I2C_MCS_RUN I2C Master Enable 0 1 I2C_MCS_START Generate START 1 2 I2C_MCS_STOP Generate STOP 2 3 MDR I2C Master Data 0x8 -1 read-write n 0x0 0x0 I2C_MDR_DATA This byte contains the data transferred during a transaction 0 8 MICR I2C Master Interrupt Clear 0x1C -1 write-only n 0x0 0x0 I2C_MICR_ARBLOSTIC Arbitration Lost Interrupt Clear 7 8 write-only I2C_MICR_CLKIC Clock Timeout Interrupt Clear 1 2 write-only I2C_MICR_DMARXIC Receive DMA Interrupt Clear 2 3 write-only I2C_MICR_DMATXIC Transmit DMA Interrupt Clear 3 4 write-only I2C_MICR_IC Master Interrupt Clear 0 1 write-only I2C_MICR_NACKIC Address/Data NACK Interrupt Clear 4 5 write-only I2C_MICR_RXFFIC Receive FIFO Full Interrupt Clear 11 12 write-only I2C_MICR_RXIC Receive FIFO Request Interrupt Clear 9 10 write-only I2C_MICR_STARTIC START Detection Interrupt Clear 5 6 write-only I2C_MICR_STOPIC STOP Detection Interrupt Clear 6 7 write-only I2C_MICR_TXFEIC Transmit FIFO Empty Interrupt Clear 10 11 write-only I2C_MICR_TXIC Transmit FIFO Request Interrupt Clear 8 9 write-only MIMR I2C Master Interrupt Mask 0x10 -1 read-write n 0x0 0x0 I2C_MIMR_ARBLOSTIM Arbitration Lost Interrupt Mask 7 8 I2C_MIMR_CLKIM Clock Timeout Interrupt Mask 1 2 I2C_MIMR_DMARXIM Receive DMA Interrupt Mask 2 3 I2C_MIMR_DMATXIM Transmit DMA Interrupt Mask 3 4 I2C_MIMR_IM Master Interrupt Mask 0 1 I2C_MIMR_NACKIM Address/Data NACK Interrupt Mask 4 5 I2C_MIMR_RXFFIM Receive FIFO Full Interrupt Mask 11 12 I2C_MIMR_RXIM Receive FIFO Request Interrupt Mask 9 10 I2C_MIMR_STARTIM START Detection Interrupt Mask 5 6 I2C_MIMR_STOPIM STOP Detection Interrupt Mask 6 7 I2C_MIMR_TXFEIM Transmit FIFO Empty Interrupt Mask 10 11 I2C_MIMR_TXIM Transmit FIFO Request Interrupt Mask 8 9 MMIS I2C Master Masked Interrupt Status 0x18 -1 read-write n 0x0 0x0 I2C_MMIS_ARBLOSTMIS Arbitration Lost Interrupt Mask 7 8 I2C_MMIS_CLKMIS Clock Timeout Masked Interrupt Status 1 2 I2C_MMIS_DMARXMIS Receive DMA Interrupt Status 2 3 I2C_MMIS_DMATXMIS Transmit DMA Interrupt Status 3 4 I2C_MMIS_MIS Masked Interrupt Status 0 1 I2C_MMIS_NACKMIS Address/Data NACK Interrupt Mask 4 5 I2C_MMIS_RXFFMIS Receive FIFO Full Interrupt Mask 11 12 I2C_MMIS_RXMIS Receive FIFO Request Interrupt Mask 9 10 I2C_MMIS_STARTMIS START Detection Interrupt Mask 5 6 I2C_MMIS_STOPMIS STOP Detection Interrupt Mask 6 7 I2C_MMIS_TXFEMIS Transmit FIFO Empty Interrupt Mask 10 11 I2C_MMIS_TXMIS Transmit Request Interrupt Mask 8 9 MRIS I2C Master Raw Interrupt Status 0x14 -1 read-write n 0x0 0x0 I2C_MRIS_ARBLOSTRIS Arbitration Lost Raw Interrupt Status 7 8 I2C_MRIS_CLKRIS Clock Timeout Raw Interrupt Status 1 2 I2C_MRIS_DMARXRIS Receive DMA Raw Interrupt Status 2 3 I2C_MRIS_DMATXRIS Transmit DMA Raw Interrupt Status 3 4 I2C_MRIS_NACKRIS Address/Data NACK Raw Interrupt Status 4 5 I2C_MRIS_RIS Master Raw Interrupt Status 0 1 I2C_MRIS_RXFFRIS Receive FIFO Full Raw Interrupt Status 11 12 I2C_MRIS_RXRIS Receive FIFO Request Raw Interrupt Status 9 10 I2C_MRIS_STARTRIS START Detection Raw Interrupt Status 5 6 I2C_MRIS_STOPRIS STOP Detection Raw Interrupt Status 6 7 I2C_MRIS_TXFERIS Transmit FIFO Empty Raw Interrupt Status 10 11 I2C_MRIS_TXRIS Transmit Request Raw Interrupt Status 8 9 MSA I2C Master Slave Address 0x0 -1 read-write n 0x0 0x0 I2C_MSA_RS Receive not send 0 1 I2C_MSA_SA I2C Slave Address 1 8 MTPR I2C Master Timer Period 0xC -1 read-write n 0x0 0x0 I2C_MTPR_HS High-Speed Enable 7 8 I2C_MTPR_PULSEL Glitch Suppression Pulse Width 16 19 I2C_MTPR_PULSEL_BYPASS Bypass 0x0 I2C_MTPR_PULSEL_1 1 clock 0x1 I2C_MTPR_PULSEL_2 2 clocks 0x2 I2C_MTPR_PULSEL_3 3 clocks 0x3 I2C_MTPR_PULSEL_4 4 clocks 0x4 I2C_MTPR_PULSEL_8 8 clocks 0x5 I2C_MTPR_PULSEL_16 16 clocks 0x6 I2C_MTPR_PULSEL_31 31 clocks 0x7 I2C_MTPR_TPR Timer Period 0 7 PC I2C Peripheral Configuration 0xFC4 -1 read-write n 0x0 0x0 I2C_PC_HS High-Speed Capable 0 1 PP I2C Peripheral Properties 0xFC0 -1 read-write n 0x0 0x0 I2C_PP_HS High-Speed Capable 0 1 SACKCTL I2C Slave ACK Control 0x820 -1 read-write n 0x0 0x0 I2C_SACKCTL_ACKOEN I2C Slave ACK Override Enable 0 1 I2C_SACKCTL_ACKOVAL I2C Slave ACK Override Value 1 2 SCSR I2C Slave Control/Status 0x804 -1 read-write n 0x0 0x0 I2C_SCSR_ACTDMARX DMA RX Active Status 31 32 I2C_SCSR_ACTDMATX DMA TX Active Status 30 31 I2C_SCSR_DA Device Active 0 1 I2C_SCSR_FBR First Byte Received 2 3 I2C_SCSR_OAR2SEL OAR2 Address Matched 3 4 I2C_SCSR_QCMDRW Quick Command Read / Write 5 6 I2C_SCSR_QCMDST Quick Command Status 4 5 I2C_SCSR_RREQ Receive Request 0 1 I2C_SCSR_RXFIFO RX FIFO Enable 2 3 I2C_SCSR_TREQ Transmit Request 1 2 I2C_SCSR_TXFIFO TX FIFO Enable 1 2 SDR I2C Slave Data 0x808 -1 read-write n 0x0 0x0 I2C_SDR_DATA Data for Transfer 0 8 SICR I2C Slave Interrupt Clear 0x818 -1 write-only n 0x0 0x0 I2C_SICR_DATAIC Data Interrupt Clear 0 1 write-only I2C_SICR_DMARXIC Receive DMA Interrupt Clear 3 4 write-only I2C_SICR_DMATXIC Transmit DMA Interrupt Clear 4 5 write-only I2C_SICR_RXFFIC Receive FIFO Full Interrupt Mask 8 9 write-only I2C_SICR_RXIC Receive Request Interrupt Mask 6 7 write-only I2C_SICR_STARTIC Start Condition Interrupt Clear 1 2 write-only I2C_SICR_STOPIC Stop Condition Interrupt Clear 2 3 write-only I2C_SICR_TXFEIC Transmit FIFO Empty Interrupt Mask 7 8 write-only I2C_SICR_TXIC Transmit Request Interrupt Mask 5 6 write-only SIMR I2C Slave Interrupt Mask 0x80C -1 read-write n 0x0 0x0 I2C_SIMR_DATAIM Data Interrupt Mask 0 1 I2C_SIMR_DMARXIM Receive DMA Interrupt Mask 3 4 I2C_SIMR_DMATXIM Transmit DMA Interrupt Mask 4 5 I2C_SIMR_RXFFIM Receive FIFO Full Interrupt Mask 8 9 I2C_SIMR_RXIM Receive FIFO Request Interrupt Mask 6 7 I2C_SIMR_STARTIM Start Condition Interrupt Mask 1 2 I2C_SIMR_STOPIM Stop Condition Interrupt Mask 2 3 I2C_SIMR_TXFEIM Transmit FIFO Empty Interrupt Mask 7 8 I2C_SIMR_TXIM Transmit FIFO Request Interrupt Mask 5 6 SMIS I2C Slave Masked Interrupt Status 0x814 -1 read-write n 0x0 0x0 I2C_SMIS_DATAMIS Data Masked Interrupt Status 0 1 I2C_SMIS_DMARXMIS Receive DMA Masked Interrupt Status 3 4 I2C_SMIS_DMATXMIS Transmit DMA Masked Interrupt Status 4 5 I2C_SMIS_RXFFMIS Receive FIFO Full Interrupt Mask 8 9 I2C_SMIS_RXMIS Receive FIFO Request Interrupt Mask 6 7 I2C_SMIS_STARTMIS Start Condition Masked Interrupt Status 1 2 I2C_SMIS_STOPMIS Stop Condition Masked Interrupt Status 2 3 I2C_SMIS_TXFEMIS Transmit FIFO Empty Interrupt Mask 7 8 I2C_SMIS_TXMIS Transmit FIFO Request Interrupt Mask 5 6 SOAR I2C Slave Own Address 0x800 -1 read-write n 0x0 0x0 I2C_SOAR_OAR I2C Slave Own Address 0 7 SOAR2 I2C Slave Own Address 2 0x81C -1 read-write n 0x0 0x0 I2C_SOAR2_OAR2 I2C Slave Own Address 2 0 7 I2C_SOAR2_OAR2EN I2C Slave Own Address 2 Enable 7 8 SRIS I2C Slave Raw Interrupt Status 0x810 -1 read-write n 0x0 0x0 I2C_SRIS_DATARIS Data Raw Interrupt Status 0 1 I2C_SRIS_DMARXRIS Receive DMA Raw Interrupt Status 3 4 I2C_SRIS_DMATXRIS Transmit DMA Raw Interrupt Status 4 5 I2C_SRIS_RXFFRIS Receive FIFO Full Raw Interrupt Status 8 9 I2C_SRIS_RXRIS Receive FIFO Request Raw Interrupt Status 6 7 I2C_SRIS_STARTRIS Start Condition Raw Interrupt Status 1 2 I2C_SRIS_STOPRIS Stop Condition Raw Interrupt Status 2 3 I2C_SRIS_TXFERIS Transmit FIFO Empty Raw Interrupt Status 7 8 I2C_SRIS_TXRIS Transmit Request Raw Interrupt Status 5 6 I2C4 Register map for I2C0 peripheral I2C 0x0 0x0 0x1000 registers n I2C4 70 FIFOCTL I2C FIFO Control 0xF04 -1 read-write n 0x0 0x0 I2C_FIFOCTL_DMARXENA DMA RX Channel Enable 29 30 I2C_FIFOCTL_DMATXENA DMA TX Channel Enable 13 14 I2C_FIFOCTL_RXASGNMT RX Control Assignment 31 32 I2C_FIFOCTL_RXFLUSH RX FIFO Flush 30 31 I2C_FIFOCTL_RXTRIG RX FIFO Trigger 16 19 I2C_FIFOCTL_TXASGNMT TX Control Assignment 15 16 I2C_FIFOCTL_TXFLUSH TX FIFO Flush 14 15 I2C_FIFOCTL_TXTRIG TX FIFO Trigger 0 3 FIFODATA I2C FIFO Data 0xF00 -1 read-write n 0x0 0x0 I2C_FIFODATA_DATA I2C TX FIFO Write Data Byte 0 8 FIFOSTATUS I2C FIFO Status 0xF08 -1 read-write n 0x0 0x0 I2C_FIFOSTATUS_RXABVTRIG RX FIFO Above Trigger Level 18 19 I2C_FIFOSTATUS_RXFE RX FIFO Empty 16 17 I2C_FIFOSTATUS_RXFF RX FIFO Full 17 18 I2C_FIFOSTATUS_TXBLWTRIG TX FIFO Below Trigger Level 2 3 I2C_FIFOSTATUS_TXFE TX FIFO Empty 0 1 I2C_FIFOSTATUS_TXFF TX FIFO Full 1 2 I2C0FIFOCTL I2C FIFO Control 0xF04 read-write n 0x0 0x0 I2C_FIFOCTL_DMARXENA DMA RX Channel Enable 29 30 I2C_FIFOCTL_DMATXENA DMA TX Channel Enable 13 14 I2C_FIFOCTL_RXASGNMT RX Control Assignment 31 32 I2C_FIFOCTL_RXFLUSH RX FIFO Flush 30 31 I2C_FIFOCTL_RXTRIG RX FIFO Trigger 16 19 I2C_FIFOCTL_TXASGNMT TX Control Assignment 15 16 I2C_FIFOCTL_TXFLUSH TX FIFO Flush 14 15 I2C_FIFOCTL_TXTRIG TX FIFO Trigger 0 3 I2C0FIFODATA I2C FIFO Data 0xF00 read-write n 0x0 0x0 I2C_FIFODATA_DATA I2C TX FIFO Write Data Byte 0 8 I2C0FIFOSTATUS I2C FIFO Status 0xF08 read-write n 0x0 0x0 I2C_FIFOSTATUS_RXABVTRIG RX FIFO Above Trigger Level 18 19 I2C_FIFOSTATUS_RXFE RX FIFO Empty 16 17 I2C_FIFOSTATUS_RXFF RX FIFO Full 17 18 I2C_FIFOSTATUS_TXBLWTRIG TX FIFO Below Trigger Level 2 3 I2C_FIFOSTATUS_TXFE TX FIFO Empty 0 1 I2C_FIFOSTATUS_TXFF TX FIFO Full 1 2 I2C0MBCNT I2C Master Burst Count 0x34 read-write n 0x0 0x0 I2C_MBCNT_CNTL I2C Master Burst Count 0 8 I2C0MBLEN I2C Master Burst Length 0x30 read-write n 0x0 0x0 I2C_MBLEN_CNTL I2C Burst Length 0 8 I2C0MBMON I2C Master Bus Monitor 0x2C read-write n 0x0 0x0 I2C_MBMON_SCL I2C SCL Status 0 1 I2C_MBMON_SDA I2C SDA Status 1 2 I2C0MCLKOCNT I2C Master Clock Low Timeout Count 0x24 read-write n 0x0 0x0 I2C_MCLKOCNT_CNTL I2C Master Count 0 8 I2C0MCR I2C Master Configuration 0x20 read-write n 0x0 0x0 I2C_MCR_LPBK I2C Loopback 0 1 I2C_MCR_MFE I2C Master Function Enable 4 5 I2C_MCR_SFE I2C Slave Function Enable 5 6 I2C0MCS I2C Master Control/Status 0x4 read-write n 0x0 0x0 I2C_MCS_ACK Data Acknowledge Enable 3 4 I2C_MCS_ACTDMARX DMA RX Active Status 31 32 I2C_MCS_ACTDMATX DMA TX Active Status 30 31 I2C_MCS_ADRACK Acknowledge Address 2 3 I2C_MCS_ARBLST Arbitration Lost 4 5 I2C_MCS_BURST Burst Enable 6 7 I2C_MCS_CLKTO Clock Timeout Error 7 8 I2C_MCS_IDLE I2C Idle 5 6 I2C_MCS_RUN I2C Master Enable 0 1 I2C_MCS_START Generate START 1 2 I2C0MDR I2C Master Data 0x8 read-write n 0x0 0x0 I2C_MDR_DATA This byte contains the data transferred during a transaction 0 8 I2C0MICR I2C Master Interrupt Clear 0x1C write-only n 0x0 0x0 I2C_MICR_ARBLOSTIC Arbitration Lost Interrupt Clear 7 8 write-only I2C_MICR_CLKIC Clock Timeout Interrupt Clear 1 2 write-only I2C_MICR_DMARXIC Receive DMA Interrupt Clear 2 3 write-only I2C_MICR_DMATXIC Transmit DMA Interrupt Clear 3 4 write-only I2C_MICR_IC Master Interrupt Clear 0 1 write-only I2C_MICR_NACKIC Address/Data NACK Interrupt Clear 4 5 write-only I2C_MICR_RXFFIC Receive FIFO Full Interrupt Clear 11 12 write-only I2C_MICR_RXIC Receive FIFO Request Interrupt Clear 9 10 write-only I2C_MICR_STARTIC START Detection Interrupt Clear 5 6 write-only I2C_MICR_STOPIC STOP Detection Interrupt Clear 6 7 write-only I2C_MICR_TXFEIC Transmit FIFO Empty Interrupt Clear 10 11 write-only I2C_MICR_TXIC Transmit FIFO Request Interrupt Clear 8 9 write-only I2C0MIMR I2C Master Interrupt Mask 0x10 read-write n 0x0 0x0 I2C_MIMR_ARBLOSTIM Arbitration Lost Interrupt Mask 7 8 I2C_MIMR_CLKIM Clock Timeout Interrupt Mask 1 2 I2C_MIMR_DMARXIM Receive DMA Interrupt Mask 2 3 I2C_MIMR_DMATXIM Transmit DMA Interrupt Mask 3 4 I2C_MIMR_IM Master Interrupt Mask 0 1 I2C_MIMR_NACKIM Address/Data NACK Interrupt Mask 4 5 I2C_MIMR_RXFFIM Receive FIFO Full Interrupt Mask 11 12 I2C_MIMR_RXIM Receive FIFO Request Interrupt Mask 9 10 I2C_MIMR_STARTIM START Detection Interrupt Mask 5 6 I2C_MIMR_STOPIM STOP Detection Interrupt Mask 6 7 I2C_MIMR_TXFEIM Transmit FIFO Empty Interrupt Mask 10 11 I2C_MIMR_TXIM Transmit FIFO Request Interrupt Mask 8 9 I2C0MMIS I2C Master Masked Interrupt Status 0x18 read-write n 0x0 0x0 I2C_MMIS_ARBLOSTMIS Arbitration Lost Interrupt Mask 7 8 I2C_MMIS_CLKMIS Clock Timeout Masked Interrupt Status 1 2 I2C_MMIS_DMARXMIS Receive DMA Interrupt Status 2 3 I2C_MMIS_DMATXMIS Transmit DMA Interrupt Status 3 4 I2C_MMIS_MIS Masked Interrupt Status 0 1 I2C_MMIS_NACKMIS Address/Data NACK Interrupt Mask 4 5 I2C_MMIS_RXFFMIS Receive FIFO Full Interrupt Mask 11 12 I2C_MMIS_RXMIS Receive FIFO Request Interrupt Mask 9 10 I2C_MMIS_STARTMIS START Detection Interrupt Mask 5 6 I2C_MMIS_STOPMIS STOP Detection Interrupt Mask 6 7 I2C_MMIS_TXFEMIS Transmit FIFO Empty Interrupt Mask 10 11 I2C_MMIS_TXMIS Transmit Request Interrupt Mask 8 9 I2C0MRIS I2C Master Raw Interrupt Status 0x14 read-write n 0x0 0x0 I2C_MRIS_ARBLOSTRIS Arbitration Lost Raw Interrupt Status 7 8 I2C_MRIS_CLKRIS Clock Timeout Raw Interrupt Status 1 2 I2C_MRIS_DMARXRIS Receive DMA Raw Interrupt Status 2 3 I2C_MRIS_DMATXRIS Transmit DMA Raw Interrupt Status 3 4 I2C_MRIS_NACKRIS Address/Data NACK Raw Interrupt Status 4 5 I2C_MRIS_RIS Master Raw Interrupt Status 0 1 I2C_MRIS_RXFFRIS Receive FIFO Full Raw Interrupt Status 11 12 I2C_MRIS_RXRIS Receive FIFO Request Raw Interrupt Status 9 10 I2C_MRIS_STARTRIS START Detection Raw Interrupt Status 5 6 I2C_MRIS_STOPRIS STOP Detection Raw Interrupt Status 6 7 I2C_MRIS_TXFERIS Transmit FIFO Empty Raw Interrupt Status 10 11 I2C_MRIS_TXRIS Transmit Request Raw Interrupt Status 8 9 I2C0MSA I2C Master Slave Address 0x0 read-write n 0x0 0x0 I2C_MSA_RS Receive not send 0 1 I2C_MSA_SA I2C Slave Address 1 8 I2C0MTPR I2C Master Timer Period 0xC read-write n 0x0 0x0 I2C_MTPR_HS High-Speed Enable 7 8 I2C_MTPR_PULSEL Glitch Suppression Pulse Width 16 19 I2C_MTPR_PULSEL_BYPASS Bypass 0x0 I2C_MTPR_PULSEL_1 1 clock 0x1 I2C_MTPR_PULSEL_2 2 clocks 0x2 I2C_MTPR_PULSEL_3 3 clocks 0x3 I2C_MTPR_PULSEL_4 4 clocks 0x4 I2C_MTPR_PULSEL_8 8 clocks 0x5 I2C_MTPR_PULSEL_16 16 clocks 0x6 I2C_MTPR_PULSEL_31 31 clocks 0x7 I2C_MTPR_TPR Timer Period 0 7 I2C0PC I2C Peripheral Configuration 0xFC4 read-write n 0x0 0x0 I2C_PC_HS High-Speed Capable 0 1 I2C0PP I2C Peripheral Properties 0xFC0 read-write n 0x0 0x0 I2C_PP_HS High-Speed Capable 0 1 I2C0SACKCTL I2C Slave ACK Control 0x820 read-write n 0x0 0x0 I2C_SACKCTL_ACKOEN I2C Slave ACK Override Enable 0 1 I2C_SACKCTL_ACKOVAL I2C Slave ACK Override Value 1 2 I2C0SCSR I2C Slave Control/Status 0x804 read-write n 0x0 0x0 I2C_SCSR_ACTDMARX DMA RX Active Status 31 32 I2C_SCSR_ACTDMATX DMA TX Active Status 30 31 I2C_SCSR_FBR First Byte Received 2 3 I2C_SCSR_OAR2SEL OAR2 Address Matched 3 4 I2C_SCSR_QCMDRW Quick Command Read / Write 5 6 I2C_SCSR_QCMDST Quick Command Status 4 5 I2C_SCSR_RREQ Receive Request 0 1 I2C_SCSR_TXFIFO TX FIFO Enable 1 2 I2C0SDR I2C Slave Data 0x808 read-write n 0x0 0x0 I2C_SDR_DATA Data for Transfer 0 8 I2C0SICR I2C Slave Interrupt Clear 0x818 write-only n 0x0 0x0 I2C_SICR_DATAIC Data Interrupt Clear 0 1 write-only I2C_SICR_DMARXIC Receive DMA Interrupt Clear 3 4 write-only I2C_SICR_DMATXIC Transmit DMA Interrupt Clear 4 5 write-only I2C_SICR_RXFFIC Receive FIFO Full Interrupt Mask 8 9 write-only I2C_SICR_RXIC Receive Request Interrupt Mask 6 7 write-only I2C_SICR_STARTIC Start Condition Interrupt Clear 1 2 write-only I2C_SICR_STOPIC Stop Condition Interrupt Clear 2 3 write-only I2C_SICR_TXFEIC Transmit FIFO Empty Interrupt Mask 7 8 write-only I2C_SICR_TXIC Transmit Request Interrupt Mask 5 6 write-only I2C0SIMR I2C Slave Interrupt Mask 0x80C read-write n 0x0 0x0 I2C_SIMR_DATAIM Data Interrupt Mask 0 1 I2C_SIMR_DMARXIM Receive DMA Interrupt Mask 3 4 I2C_SIMR_DMATXIM Transmit DMA Interrupt Mask 4 5 I2C_SIMR_RXFFIM Receive FIFO Full Interrupt Mask 8 9 I2C_SIMR_RXIM Receive FIFO Request Interrupt Mask 6 7 I2C_SIMR_STARTIM Start Condition Interrupt Mask 1 2 I2C_SIMR_STOPIM Stop Condition Interrupt Mask 2 3 I2C_SIMR_TXFEIM Transmit FIFO Empty Interrupt Mask 7 8 I2C_SIMR_TXIM Transmit FIFO Request Interrupt Mask 5 6 I2C0SMIS I2C Slave Masked Interrupt Status 0x814 read-write n 0x0 0x0 I2C_SMIS_DATAMIS Data Masked Interrupt Status 0 1 I2C_SMIS_DMARXMIS Receive DMA Masked Interrupt Status 3 4 I2C_SMIS_DMATXMIS Transmit DMA Masked Interrupt Status 4 5 I2C_SMIS_RXFFMIS Receive FIFO Full Interrupt Mask 8 9 I2C_SMIS_RXMIS Receive FIFO Request Interrupt Mask 6 7 I2C_SMIS_STARTMIS Start Condition Masked Interrupt Status 1 2 I2C_SMIS_STOPMIS Stop Condition Masked Interrupt Status 2 3 I2C_SMIS_TXFEMIS Transmit FIFO Empty Interrupt Mask 7 8 I2C_SMIS_TXMIS Transmit FIFO Request Interrupt Mask 5 6 I2C0SOAR I2C Slave Own Address 0x800 read-write n 0x0 0x0 I2C_SOAR_OAR I2C Slave Own Address 0 7 I2C0SOAR2 I2C Slave Own Address 2 0x81C read-write n 0x0 0x0 I2C_SOAR2_OAR2 I2C Slave Own Address 2 0 7 I2C_SOAR2_OAR2EN I2C Slave Own Address 2 Enable 7 8 I2C0SRIS I2C Slave Raw Interrupt Status 0x810 read-write n 0x0 0x0 I2C_SRIS_DATARIS Data Raw Interrupt Status 0 1 I2C_SRIS_DMARXRIS Receive DMA Raw Interrupt Status 3 4 I2C_SRIS_DMATXRIS Transmit DMA Raw Interrupt Status 4 5 I2C_SRIS_RXFFRIS Receive FIFO Full Raw Interrupt Status 8 9 I2C_SRIS_RXRIS Receive FIFO Request Raw Interrupt Status 6 7 I2C_SRIS_STARTRIS Start Condition Raw Interrupt Status 1 2 I2C_SRIS_STOPRIS Stop Condition Raw Interrupt Status 2 3 I2C_SRIS_TXFERIS Transmit FIFO Empty Raw Interrupt Status 7 8 I2C_SRIS_TXRIS Transmit Request Raw Interrupt Status 5 6 MBCNT I2C Master Burst Count 0x34 -1 read-write n 0x0 0x0 I2C_MBCNT_CNTL I2C Master Burst Count 0 8 MBLEN I2C Master Burst Length 0x30 -1 read-write n 0x0 0x0 I2C_MBLEN_CNTL I2C Burst Length 0 8 MBMON I2C Master Bus Monitor 0x2C -1 read-write n 0x0 0x0 I2C_MBMON_SCL I2C SCL Status 0 1 I2C_MBMON_SDA I2C SDA Status 1 2 MCLKOCNT I2C Master Clock Low Timeout Count 0x24 -1 read-write n 0x0 0x0 I2C_MCLKOCNT_CNTL I2C Master Count 0 8 MCR I2C Master Configuration 0x20 -1 read-write n 0x0 0x0 I2C_MCR_LPBK I2C Loopback 0 1 I2C_MCR_MFE I2C Master Function Enable 4 5 I2C_MCR_SFE I2C Slave Function Enable 5 6 MCS I2C Master Control/Status 0x4 -1 read-write n 0x0 0x0 I2C_MCS_ACK Data Acknowledge Enable 3 4 I2C_MCS_ACTDMARX DMA RX Active Status 31 32 I2C_MCS_ACTDMATX DMA TX Active Status 30 31 I2C_MCS_ADRACK Acknowledge Address 2 3 I2C_MCS_ARBLST Arbitration Lost 4 5 I2C_MCS_BURST Burst Enable 6 7 I2C_MCS_BUSBSY Bus Busy 6 7 I2C_MCS_BUSY I2C Busy 0 1 I2C_MCS_CLKTO Clock Timeout Error 7 8 I2C_MCS_DATACK Acknowledge Data 3 4 I2C_MCS_ERROR Error 1 2 I2C_MCS_HS High-Speed Enable 4 5 I2C_MCS_IDLE I2C Idle 5 6 I2C_MCS_QCMD Quick Command 5 6 I2C_MCS_RUN I2C Master Enable 0 1 I2C_MCS_START Generate START 1 2 I2C_MCS_STOP Generate STOP 2 3 MDR I2C Master Data 0x8 -1 read-write n 0x0 0x0 I2C_MDR_DATA This byte contains the data transferred during a transaction 0 8 MICR I2C Master Interrupt Clear 0x1C -1 write-only n 0x0 0x0 I2C_MICR_ARBLOSTIC Arbitration Lost Interrupt Clear 7 8 write-only I2C_MICR_CLKIC Clock Timeout Interrupt Clear 1 2 write-only I2C_MICR_DMARXIC Receive DMA Interrupt Clear 2 3 write-only I2C_MICR_DMATXIC Transmit DMA Interrupt Clear 3 4 write-only I2C_MICR_IC Master Interrupt Clear 0 1 write-only I2C_MICR_NACKIC Address/Data NACK Interrupt Clear 4 5 write-only I2C_MICR_RXFFIC Receive FIFO Full Interrupt Clear 11 12 write-only I2C_MICR_RXIC Receive FIFO Request Interrupt Clear 9 10 write-only I2C_MICR_STARTIC START Detection Interrupt Clear 5 6 write-only I2C_MICR_STOPIC STOP Detection Interrupt Clear 6 7 write-only I2C_MICR_TXFEIC Transmit FIFO Empty Interrupt Clear 10 11 write-only I2C_MICR_TXIC Transmit FIFO Request Interrupt Clear 8 9 write-only MIMR I2C Master Interrupt Mask 0x10 -1 read-write n 0x0 0x0 I2C_MIMR_ARBLOSTIM Arbitration Lost Interrupt Mask 7 8 I2C_MIMR_CLKIM Clock Timeout Interrupt Mask 1 2 I2C_MIMR_DMARXIM Receive DMA Interrupt Mask 2 3 I2C_MIMR_DMATXIM Transmit DMA Interrupt Mask 3 4 I2C_MIMR_IM Master Interrupt Mask 0 1 I2C_MIMR_NACKIM Address/Data NACK Interrupt Mask 4 5 I2C_MIMR_RXFFIM Receive FIFO Full Interrupt Mask 11 12 I2C_MIMR_RXIM Receive FIFO Request Interrupt Mask 9 10 I2C_MIMR_STARTIM START Detection Interrupt Mask 5 6 I2C_MIMR_STOPIM STOP Detection Interrupt Mask 6 7 I2C_MIMR_TXFEIM Transmit FIFO Empty Interrupt Mask 10 11 I2C_MIMR_TXIM Transmit FIFO Request Interrupt Mask 8 9 MMIS I2C Master Masked Interrupt Status 0x18 -1 read-write n 0x0 0x0 I2C_MMIS_ARBLOSTMIS Arbitration Lost Interrupt Mask 7 8 I2C_MMIS_CLKMIS Clock Timeout Masked Interrupt Status 1 2 I2C_MMIS_DMARXMIS Receive DMA Interrupt Status 2 3 I2C_MMIS_DMATXMIS Transmit DMA Interrupt Status 3 4 I2C_MMIS_MIS Masked Interrupt Status 0 1 I2C_MMIS_NACKMIS Address/Data NACK Interrupt Mask 4 5 I2C_MMIS_RXFFMIS Receive FIFO Full Interrupt Mask 11 12 I2C_MMIS_RXMIS Receive FIFO Request Interrupt Mask 9 10 I2C_MMIS_STARTMIS START Detection Interrupt Mask 5 6 I2C_MMIS_STOPMIS STOP Detection Interrupt Mask 6 7 I2C_MMIS_TXFEMIS Transmit FIFO Empty Interrupt Mask 10 11 I2C_MMIS_TXMIS Transmit Request Interrupt Mask 8 9 MRIS I2C Master Raw Interrupt Status 0x14 -1 read-write n 0x0 0x0 I2C_MRIS_ARBLOSTRIS Arbitration Lost Raw Interrupt Status 7 8 I2C_MRIS_CLKRIS Clock Timeout Raw Interrupt Status 1 2 I2C_MRIS_DMARXRIS Receive DMA Raw Interrupt Status 2 3 I2C_MRIS_DMATXRIS Transmit DMA Raw Interrupt Status 3 4 I2C_MRIS_NACKRIS Address/Data NACK Raw Interrupt Status 4 5 I2C_MRIS_RIS Master Raw Interrupt Status 0 1 I2C_MRIS_RXFFRIS Receive FIFO Full Raw Interrupt Status 11 12 I2C_MRIS_RXRIS Receive FIFO Request Raw Interrupt Status 9 10 I2C_MRIS_STARTRIS START Detection Raw Interrupt Status 5 6 I2C_MRIS_STOPRIS STOP Detection Raw Interrupt Status 6 7 I2C_MRIS_TXFERIS Transmit FIFO Empty Raw Interrupt Status 10 11 I2C_MRIS_TXRIS Transmit Request Raw Interrupt Status 8 9 MSA I2C Master Slave Address 0x0 -1 read-write n 0x0 0x0 I2C_MSA_RS Receive not send 0 1 I2C_MSA_SA I2C Slave Address 1 8 MTPR I2C Master Timer Period 0xC -1 read-write n 0x0 0x0 I2C_MTPR_HS High-Speed Enable 7 8 I2C_MTPR_PULSEL Glitch Suppression Pulse Width 16 19 I2C_MTPR_PULSEL_BYPASS Bypass 0x0 I2C_MTPR_PULSEL_1 1 clock 0x1 I2C_MTPR_PULSEL_2 2 clocks 0x2 I2C_MTPR_PULSEL_3 3 clocks 0x3 I2C_MTPR_PULSEL_4 4 clocks 0x4 I2C_MTPR_PULSEL_8 8 clocks 0x5 I2C_MTPR_PULSEL_16 16 clocks 0x6 I2C_MTPR_PULSEL_31 31 clocks 0x7 I2C_MTPR_TPR Timer Period 0 7 PC I2C Peripheral Configuration 0xFC4 -1 read-write n 0x0 0x0 I2C_PC_HS High-Speed Capable 0 1 PP I2C Peripheral Properties 0xFC0 -1 read-write n 0x0 0x0 I2C_PP_HS High-Speed Capable 0 1 SACKCTL I2C Slave ACK Control 0x820 -1 read-write n 0x0 0x0 I2C_SACKCTL_ACKOEN I2C Slave ACK Override Enable 0 1 I2C_SACKCTL_ACKOVAL I2C Slave ACK Override Value 1 2 SCSR I2C Slave Control/Status 0x804 -1 read-write n 0x0 0x0 I2C_SCSR_ACTDMARX DMA RX Active Status 31 32 I2C_SCSR_ACTDMATX DMA TX Active Status 30 31 I2C_SCSR_DA Device Active 0 1 I2C_SCSR_FBR First Byte Received 2 3 I2C_SCSR_OAR2SEL OAR2 Address Matched 3 4 I2C_SCSR_QCMDRW Quick Command Read / Write 5 6 I2C_SCSR_QCMDST Quick Command Status 4 5 I2C_SCSR_RREQ Receive Request 0 1 I2C_SCSR_RXFIFO RX FIFO Enable 2 3 I2C_SCSR_TREQ Transmit Request 1 2 I2C_SCSR_TXFIFO TX FIFO Enable 1 2 SDR I2C Slave Data 0x808 -1 read-write n 0x0 0x0 I2C_SDR_DATA Data for Transfer 0 8 SICR I2C Slave Interrupt Clear 0x818 -1 write-only n 0x0 0x0 I2C_SICR_DATAIC Data Interrupt Clear 0 1 write-only I2C_SICR_DMARXIC Receive DMA Interrupt Clear 3 4 write-only I2C_SICR_DMATXIC Transmit DMA Interrupt Clear 4 5 write-only I2C_SICR_RXFFIC Receive FIFO Full Interrupt Mask 8 9 write-only I2C_SICR_RXIC Receive Request Interrupt Mask 6 7 write-only I2C_SICR_STARTIC Start Condition Interrupt Clear 1 2 write-only I2C_SICR_STOPIC Stop Condition Interrupt Clear 2 3 write-only I2C_SICR_TXFEIC Transmit FIFO Empty Interrupt Mask 7 8 write-only I2C_SICR_TXIC Transmit Request Interrupt Mask 5 6 write-only SIMR I2C Slave Interrupt Mask 0x80C -1 read-write n 0x0 0x0 I2C_SIMR_DATAIM Data Interrupt Mask 0 1 I2C_SIMR_DMARXIM Receive DMA Interrupt Mask 3 4 I2C_SIMR_DMATXIM Transmit DMA Interrupt Mask 4 5 I2C_SIMR_RXFFIM Receive FIFO Full Interrupt Mask 8 9 I2C_SIMR_RXIM Receive FIFO Request Interrupt Mask 6 7 I2C_SIMR_STARTIM Start Condition Interrupt Mask 1 2 I2C_SIMR_STOPIM Stop Condition Interrupt Mask 2 3 I2C_SIMR_TXFEIM Transmit FIFO Empty Interrupt Mask 7 8 I2C_SIMR_TXIM Transmit FIFO Request Interrupt Mask 5 6 SMIS I2C Slave Masked Interrupt Status 0x814 -1 read-write n 0x0 0x0 I2C_SMIS_DATAMIS Data Masked Interrupt Status 0 1 I2C_SMIS_DMARXMIS Receive DMA Masked Interrupt Status 3 4 I2C_SMIS_DMATXMIS Transmit DMA Masked Interrupt Status 4 5 I2C_SMIS_RXFFMIS Receive FIFO Full Interrupt Mask 8 9 I2C_SMIS_RXMIS Receive FIFO Request Interrupt Mask 6 7 I2C_SMIS_STARTMIS Start Condition Masked Interrupt Status 1 2 I2C_SMIS_STOPMIS Stop Condition Masked Interrupt Status 2 3 I2C_SMIS_TXFEMIS Transmit FIFO Empty Interrupt Mask 7 8 I2C_SMIS_TXMIS Transmit FIFO Request Interrupt Mask 5 6 SOAR I2C Slave Own Address 0x800 -1 read-write n 0x0 0x0 I2C_SOAR_OAR I2C Slave Own Address 0 7 SOAR2 I2C Slave Own Address 2 0x81C -1 read-write n 0x0 0x0 I2C_SOAR2_OAR2 I2C Slave Own Address 2 0 7 I2C_SOAR2_OAR2EN I2C Slave Own Address 2 Enable 7 8 SRIS I2C Slave Raw Interrupt Status 0x810 -1 read-write n 0x0 0x0 I2C_SRIS_DATARIS Data Raw Interrupt Status 0 1 I2C_SRIS_DMARXRIS Receive DMA Raw Interrupt Status 3 4 I2C_SRIS_DMATXRIS Transmit DMA Raw Interrupt Status 4 5 I2C_SRIS_RXFFRIS Receive FIFO Full Raw Interrupt Status 8 9 I2C_SRIS_RXRIS Receive FIFO Request Raw Interrupt Status 6 7 I2C_SRIS_STARTRIS Start Condition Raw Interrupt Status 1 2 I2C_SRIS_STOPRIS Stop Condition Raw Interrupt Status 2 3 I2C_SRIS_TXFERIS Transmit FIFO Empty Raw Interrupt Status 7 8 I2C_SRIS_TXRIS Transmit Request Raw Interrupt Status 5 6 I2C5 Register map for I2C0 peripheral I2C 0x0 0x0 0x1000 registers n I2C5 71 FIFOCTL I2C FIFO Control 0xF04 -1 read-write n 0x0 0x0 I2C_FIFOCTL_DMARXENA DMA RX Channel Enable 29 30 I2C_FIFOCTL_DMATXENA DMA TX Channel Enable 13 14 I2C_FIFOCTL_RXASGNMT RX Control Assignment 31 32 I2C_FIFOCTL_RXFLUSH RX FIFO Flush 30 31 I2C_FIFOCTL_RXTRIG RX FIFO Trigger 16 19 I2C_FIFOCTL_TXASGNMT TX Control Assignment 15 16 I2C_FIFOCTL_TXFLUSH TX FIFO Flush 14 15 I2C_FIFOCTL_TXTRIG TX FIFO Trigger 0 3 FIFODATA I2C FIFO Data 0xF00 -1 read-write n 0x0 0x0 I2C_FIFODATA_DATA I2C TX FIFO Write Data Byte 0 8 FIFOSTATUS I2C FIFO Status 0xF08 -1 read-write n 0x0 0x0 I2C_FIFOSTATUS_RXABVTRIG RX FIFO Above Trigger Level 18 19 I2C_FIFOSTATUS_RXFE RX FIFO Empty 16 17 I2C_FIFOSTATUS_RXFF RX FIFO Full 17 18 I2C_FIFOSTATUS_TXBLWTRIG TX FIFO Below Trigger Level 2 3 I2C_FIFOSTATUS_TXFE TX FIFO Empty 0 1 I2C_FIFOSTATUS_TXFF TX FIFO Full 1 2 I2C0FIFOCTL I2C FIFO Control 0xF04 read-write n 0x0 0x0 I2C_FIFOCTL_DMARXENA DMA RX Channel Enable 29 30 I2C_FIFOCTL_DMATXENA DMA TX Channel Enable 13 14 I2C_FIFOCTL_RXASGNMT RX Control Assignment 31 32 I2C_FIFOCTL_RXFLUSH RX FIFO Flush 30 31 I2C_FIFOCTL_RXTRIG RX FIFO Trigger 16 19 I2C_FIFOCTL_TXASGNMT TX Control Assignment 15 16 I2C_FIFOCTL_TXFLUSH TX FIFO Flush 14 15 I2C_FIFOCTL_TXTRIG TX FIFO Trigger 0 3 I2C0FIFODATA I2C FIFO Data 0xF00 read-write n 0x0 0x0 I2C_FIFODATA_DATA I2C TX FIFO Write Data Byte 0 8 I2C0FIFOSTATUS I2C FIFO Status 0xF08 read-write n 0x0 0x0 I2C_FIFOSTATUS_RXABVTRIG RX FIFO Above Trigger Level 18 19 I2C_FIFOSTATUS_RXFE RX FIFO Empty 16 17 I2C_FIFOSTATUS_RXFF RX FIFO Full 17 18 I2C_FIFOSTATUS_TXBLWTRIG TX FIFO Below Trigger Level 2 3 I2C_FIFOSTATUS_TXFE TX FIFO Empty 0 1 I2C_FIFOSTATUS_TXFF TX FIFO Full 1 2 I2C0MBCNT I2C Master Burst Count 0x34 read-write n 0x0 0x0 I2C_MBCNT_CNTL I2C Master Burst Count 0 8 I2C0MBLEN I2C Master Burst Length 0x30 read-write n 0x0 0x0 I2C_MBLEN_CNTL I2C Burst Length 0 8 I2C0MBMON I2C Master Bus Monitor 0x2C read-write n 0x0 0x0 I2C_MBMON_SCL I2C SCL Status 0 1 I2C_MBMON_SDA I2C SDA Status 1 2 I2C0MCLKOCNT I2C Master Clock Low Timeout Count 0x24 read-write n 0x0 0x0 I2C_MCLKOCNT_CNTL I2C Master Count 0 8 I2C0MCR I2C Master Configuration 0x20 read-write n 0x0 0x0 I2C_MCR_LPBK I2C Loopback 0 1 I2C_MCR_MFE I2C Master Function Enable 4 5 I2C_MCR_SFE I2C Slave Function Enable 5 6 I2C0MCS I2C Master Control/Status 0x4 read-write n 0x0 0x0 I2C_MCS_ACK Data Acknowledge Enable 3 4 I2C_MCS_ACTDMARX DMA RX Active Status 31 32 I2C_MCS_ACTDMATX DMA TX Active Status 30 31 I2C_MCS_ADRACK Acknowledge Address 2 3 I2C_MCS_ARBLST Arbitration Lost 4 5 I2C_MCS_BURST Burst Enable 6 7 I2C_MCS_CLKTO Clock Timeout Error 7 8 I2C_MCS_IDLE I2C Idle 5 6 I2C_MCS_RUN I2C Master Enable 0 1 I2C_MCS_START Generate START 1 2 I2C0MDR I2C Master Data 0x8 read-write n 0x0 0x0 I2C_MDR_DATA This byte contains the data transferred during a transaction 0 8 I2C0MICR I2C Master Interrupt Clear 0x1C write-only n 0x0 0x0 I2C_MICR_ARBLOSTIC Arbitration Lost Interrupt Clear 7 8 write-only I2C_MICR_CLKIC Clock Timeout Interrupt Clear 1 2 write-only I2C_MICR_DMARXIC Receive DMA Interrupt Clear 2 3 write-only I2C_MICR_DMATXIC Transmit DMA Interrupt Clear 3 4 write-only I2C_MICR_IC Master Interrupt Clear 0 1 write-only I2C_MICR_NACKIC Address/Data NACK Interrupt Clear 4 5 write-only I2C_MICR_RXFFIC Receive FIFO Full Interrupt Clear 11 12 write-only I2C_MICR_RXIC Receive FIFO Request Interrupt Clear 9 10 write-only I2C_MICR_STARTIC START Detection Interrupt Clear 5 6 write-only I2C_MICR_STOPIC STOP Detection Interrupt Clear 6 7 write-only I2C_MICR_TXFEIC Transmit FIFO Empty Interrupt Clear 10 11 write-only I2C_MICR_TXIC Transmit FIFO Request Interrupt Clear 8 9 write-only I2C0MIMR I2C Master Interrupt Mask 0x10 read-write n 0x0 0x0 I2C_MIMR_ARBLOSTIM Arbitration Lost Interrupt Mask 7 8 I2C_MIMR_CLKIM Clock Timeout Interrupt Mask 1 2 I2C_MIMR_DMARXIM Receive DMA Interrupt Mask 2 3 I2C_MIMR_DMATXIM Transmit DMA Interrupt Mask 3 4 I2C_MIMR_IM Master Interrupt Mask 0 1 I2C_MIMR_NACKIM Address/Data NACK Interrupt Mask 4 5 I2C_MIMR_RXFFIM Receive FIFO Full Interrupt Mask 11 12 I2C_MIMR_RXIM Receive FIFO Request Interrupt Mask 9 10 I2C_MIMR_STARTIM START Detection Interrupt Mask 5 6 I2C_MIMR_STOPIM STOP Detection Interrupt Mask 6 7 I2C_MIMR_TXFEIM Transmit FIFO Empty Interrupt Mask 10 11 I2C_MIMR_TXIM Transmit FIFO Request Interrupt Mask 8 9 I2C0MMIS I2C Master Masked Interrupt Status 0x18 read-write n 0x0 0x0 I2C_MMIS_ARBLOSTMIS Arbitration Lost Interrupt Mask 7 8 I2C_MMIS_CLKMIS Clock Timeout Masked Interrupt Status 1 2 I2C_MMIS_DMARXMIS Receive DMA Interrupt Status 2 3 I2C_MMIS_DMATXMIS Transmit DMA Interrupt Status 3 4 I2C_MMIS_MIS Masked Interrupt Status 0 1 I2C_MMIS_NACKMIS Address/Data NACK Interrupt Mask 4 5 I2C_MMIS_RXFFMIS Receive FIFO Full Interrupt Mask 11 12 I2C_MMIS_RXMIS Receive FIFO Request Interrupt Mask 9 10 I2C_MMIS_STARTMIS START Detection Interrupt Mask 5 6 I2C_MMIS_STOPMIS STOP Detection Interrupt Mask 6 7 I2C_MMIS_TXFEMIS Transmit FIFO Empty Interrupt Mask 10 11 I2C_MMIS_TXMIS Transmit Request Interrupt Mask 8 9 I2C0MRIS I2C Master Raw Interrupt Status 0x14 read-write n 0x0 0x0 I2C_MRIS_ARBLOSTRIS Arbitration Lost Raw Interrupt Status 7 8 I2C_MRIS_CLKRIS Clock Timeout Raw Interrupt Status 1 2 I2C_MRIS_DMARXRIS Receive DMA Raw Interrupt Status 2 3 I2C_MRIS_DMATXRIS Transmit DMA Raw Interrupt Status 3 4 I2C_MRIS_NACKRIS Address/Data NACK Raw Interrupt Status 4 5 I2C_MRIS_RIS Master Raw Interrupt Status 0 1 I2C_MRIS_RXFFRIS Receive FIFO Full Raw Interrupt Status 11 12 I2C_MRIS_RXRIS Receive FIFO Request Raw Interrupt Status 9 10 I2C_MRIS_STARTRIS START Detection Raw Interrupt Status 5 6 I2C_MRIS_STOPRIS STOP Detection Raw Interrupt Status 6 7 I2C_MRIS_TXFERIS Transmit FIFO Empty Raw Interrupt Status 10 11 I2C_MRIS_TXRIS Transmit Request Raw Interrupt Status 8 9 I2C0MSA I2C Master Slave Address 0x0 read-write n 0x0 0x0 I2C_MSA_RS Receive not send 0 1 I2C_MSA_SA I2C Slave Address 1 8 I2C0MTPR I2C Master Timer Period 0xC read-write n 0x0 0x0 I2C_MTPR_HS High-Speed Enable 7 8 I2C_MTPR_PULSEL Glitch Suppression Pulse Width 16 19 I2C_MTPR_PULSEL_BYPASS Bypass 0x0 I2C_MTPR_PULSEL_1 1 clock 0x1 I2C_MTPR_PULSEL_2 2 clocks 0x2 I2C_MTPR_PULSEL_3 3 clocks 0x3 I2C_MTPR_PULSEL_4 4 clocks 0x4 I2C_MTPR_PULSEL_8 8 clocks 0x5 I2C_MTPR_PULSEL_16 16 clocks 0x6 I2C_MTPR_PULSEL_31 31 clocks 0x7 I2C_MTPR_TPR Timer Period 0 7 I2C0PC I2C Peripheral Configuration 0xFC4 read-write n 0x0 0x0 I2C_PC_HS High-Speed Capable 0 1 I2C0PP I2C Peripheral Properties 0xFC0 read-write n 0x0 0x0 I2C_PP_HS High-Speed Capable 0 1 I2C0SACKCTL I2C Slave ACK Control 0x820 read-write n 0x0 0x0 I2C_SACKCTL_ACKOEN I2C Slave ACK Override Enable 0 1 I2C_SACKCTL_ACKOVAL I2C Slave ACK Override Value 1 2 I2C0SCSR I2C Slave Control/Status 0x804 read-write n 0x0 0x0 I2C_SCSR_ACTDMARX DMA RX Active Status 31 32 I2C_SCSR_ACTDMATX DMA TX Active Status 30 31 I2C_SCSR_FBR First Byte Received 2 3 I2C_SCSR_OAR2SEL OAR2 Address Matched 3 4 I2C_SCSR_QCMDRW Quick Command Read / Write 5 6 I2C_SCSR_QCMDST Quick Command Status 4 5 I2C_SCSR_RREQ Receive Request 0 1 I2C_SCSR_TXFIFO TX FIFO Enable 1 2 I2C0SDR I2C Slave Data 0x808 read-write n 0x0 0x0 I2C_SDR_DATA Data for Transfer 0 8 I2C0SICR I2C Slave Interrupt Clear 0x818 write-only n 0x0 0x0 I2C_SICR_DATAIC Data Interrupt Clear 0 1 write-only I2C_SICR_DMARXIC Receive DMA Interrupt Clear 3 4 write-only I2C_SICR_DMATXIC Transmit DMA Interrupt Clear 4 5 write-only I2C_SICR_RXFFIC Receive FIFO Full Interrupt Mask 8 9 write-only I2C_SICR_RXIC Receive Request Interrupt Mask 6 7 write-only I2C_SICR_STARTIC Start Condition Interrupt Clear 1 2 write-only I2C_SICR_STOPIC Stop Condition Interrupt Clear 2 3 write-only I2C_SICR_TXFEIC Transmit FIFO Empty Interrupt Mask 7 8 write-only I2C_SICR_TXIC Transmit Request Interrupt Mask 5 6 write-only I2C0SIMR I2C Slave Interrupt Mask 0x80C read-write n 0x0 0x0 I2C_SIMR_DATAIM Data Interrupt Mask 0 1 I2C_SIMR_DMARXIM Receive DMA Interrupt Mask 3 4 I2C_SIMR_DMATXIM Transmit DMA Interrupt Mask 4 5 I2C_SIMR_RXFFIM Receive FIFO Full Interrupt Mask 8 9 I2C_SIMR_RXIM Receive FIFO Request Interrupt Mask 6 7 I2C_SIMR_STARTIM Start Condition Interrupt Mask 1 2 I2C_SIMR_STOPIM Stop Condition Interrupt Mask 2 3 I2C_SIMR_TXFEIM Transmit FIFO Empty Interrupt Mask 7 8 I2C_SIMR_TXIM Transmit FIFO Request Interrupt Mask 5 6 I2C0SMIS I2C Slave Masked Interrupt Status 0x814 read-write n 0x0 0x0 I2C_SMIS_DATAMIS Data Masked Interrupt Status 0 1 I2C_SMIS_DMARXMIS Receive DMA Masked Interrupt Status 3 4 I2C_SMIS_DMATXMIS Transmit DMA Masked Interrupt Status 4 5 I2C_SMIS_RXFFMIS Receive FIFO Full Interrupt Mask 8 9 I2C_SMIS_RXMIS Receive FIFO Request Interrupt Mask 6 7 I2C_SMIS_STARTMIS Start Condition Masked Interrupt Status 1 2 I2C_SMIS_STOPMIS Stop Condition Masked Interrupt Status 2 3 I2C_SMIS_TXFEMIS Transmit FIFO Empty Interrupt Mask 7 8 I2C_SMIS_TXMIS Transmit FIFO Request Interrupt Mask 5 6 I2C0SOAR I2C Slave Own Address 0x800 read-write n 0x0 0x0 I2C_SOAR_OAR I2C Slave Own Address 0 7 I2C0SOAR2 I2C Slave Own Address 2 0x81C read-write n 0x0 0x0 I2C_SOAR2_OAR2 I2C Slave Own Address 2 0 7 I2C_SOAR2_OAR2EN I2C Slave Own Address 2 Enable 7 8 I2C0SRIS I2C Slave Raw Interrupt Status 0x810 read-write n 0x0 0x0 I2C_SRIS_DATARIS Data Raw Interrupt Status 0 1 I2C_SRIS_DMARXRIS Receive DMA Raw Interrupt Status 3 4 I2C_SRIS_DMATXRIS Transmit DMA Raw Interrupt Status 4 5 I2C_SRIS_RXFFRIS Receive FIFO Full Raw Interrupt Status 8 9 I2C_SRIS_RXRIS Receive FIFO Request Raw Interrupt Status 6 7 I2C_SRIS_STARTRIS Start Condition Raw Interrupt Status 1 2 I2C_SRIS_STOPRIS Stop Condition Raw Interrupt Status 2 3 I2C_SRIS_TXFERIS Transmit FIFO Empty Raw Interrupt Status 7 8 I2C_SRIS_TXRIS Transmit Request Raw Interrupt Status 5 6 MBCNT I2C Master Burst Count 0x34 -1 read-write n 0x0 0x0 I2C_MBCNT_CNTL I2C Master Burst Count 0 8 MBLEN I2C Master Burst Length 0x30 -1 read-write n 0x0 0x0 I2C_MBLEN_CNTL I2C Burst Length 0 8 MBMON I2C Master Bus Monitor 0x2C -1 read-write n 0x0 0x0 I2C_MBMON_SCL I2C SCL Status 0 1 I2C_MBMON_SDA I2C SDA Status 1 2 MCLKOCNT I2C Master Clock Low Timeout Count 0x24 -1 read-write n 0x0 0x0 I2C_MCLKOCNT_CNTL I2C Master Count 0 8 MCR I2C Master Configuration 0x20 -1 read-write n 0x0 0x0 I2C_MCR_LPBK I2C Loopback 0 1 I2C_MCR_MFE I2C Master Function Enable 4 5 I2C_MCR_SFE I2C Slave Function Enable 5 6 MCS I2C Master Control/Status 0x4 -1 read-write n 0x0 0x0 I2C_MCS_ACK Data Acknowledge Enable 3 4 I2C_MCS_ACTDMARX DMA RX Active Status 31 32 I2C_MCS_ACTDMATX DMA TX Active Status 30 31 I2C_MCS_ADRACK Acknowledge Address 2 3 I2C_MCS_ARBLST Arbitration Lost 4 5 I2C_MCS_BURST Burst Enable 6 7 I2C_MCS_BUSBSY Bus Busy 6 7 I2C_MCS_BUSY I2C Busy 0 1 I2C_MCS_CLKTO Clock Timeout Error 7 8 I2C_MCS_DATACK Acknowledge Data 3 4 I2C_MCS_ERROR Error 1 2 I2C_MCS_HS High-Speed Enable 4 5 I2C_MCS_IDLE I2C Idle 5 6 I2C_MCS_QCMD Quick Command 5 6 I2C_MCS_RUN I2C Master Enable 0 1 I2C_MCS_START Generate START 1 2 I2C_MCS_STOP Generate STOP 2 3 MDR I2C Master Data 0x8 -1 read-write n 0x0 0x0 I2C_MDR_DATA This byte contains the data transferred during a transaction 0 8 MICR I2C Master Interrupt Clear 0x1C -1 write-only n 0x0 0x0 I2C_MICR_ARBLOSTIC Arbitration Lost Interrupt Clear 7 8 write-only I2C_MICR_CLKIC Clock Timeout Interrupt Clear 1 2 write-only I2C_MICR_DMARXIC Receive DMA Interrupt Clear 2 3 write-only I2C_MICR_DMATXIC Transmit DMA Interrupt Clear 3 4 write-only I2C_MICR_IC Master Interrupt Clear 0 1 write-only I2C_MICR_NACKIC Address/Data NACK Interrupt Clear 4 5 write-only I2C_MICR_RXFFIC Receive FIFO Full Interrupt Clear 11 12 write-only I2C_MICR_RXIC Receive FIFO Request Interrupt Clear 9 10 write-only I2C_MICR_STARTIC START Detection Interrupt Clear 5 6 write-only I2C_MICR_STOPIC STOP Detection Interrupt Clear 6 7 write-only I2C_MICR_TXFEIC Transmit FIFO Empty Interrupt Clear 10 11 write-only I2C_MICR_TXIC Transmit FIFO Request Interrupt Clear 8 9 write-only MIMR I2C Master Interrupt Mask 0x10 -1 read-write n 0x0 0x0 I2C_MIMR_ARBLOSTIM Arbitration Lost Interrupt Mask 7 8 I2C_MIMR_CLKIM Clock Timeout Interrupt Mask 1 2 I2C_MIMR_DMARXIM Receive DMA Interrupt Mask 2 3 I2C_MIMR_DMATXIM Transmit DMA Interrupt Mask 3 4 I2C_MIMR_IM Master Interrupt Mask 0 1 I2C_MIMR_NACKIM Address/Data NACK Interrupt Mask 4 5 I2C_MIMR_RXFFIM Receive FIFO Full Interrupt Mask 11 12 I2C_MIMR_RXIM Receive FIFO Request Interrupt Mask 9 10 I2C_MIMR_STARTIM START Detection Interrupt Mask 5 6 I2C_MIMR_STOPIM STOP Detection Interrupt Mask 6 7 I2C_MIMR_TXFEIM Transmit FIFO Empty Interrupt Mask 10 11 I2C_MIMR_TXIM Transmit FIFO Request Interrupt Mask 8 9 MMIS I2C Master Masked Interrupt Status 0x18 -1 read-write n 0x0 0x0 I2C_MMIS_ARBLOSTMIS Arbitration Lost Interrupt Mask 7 8 I2C_MMIS_CLKMIS Clock Timeout Masked Interrupt Status 1 2 I2C_MMIS_DMARXMIS Receive DMA Interrupt Status 2 3 I2C_MMIS_DMATXMIS Transmit DMA Interrupt Status 3 4 I2C_MMIS_MIS Masked Interrupt Status 0 1 I2C_MMIS_NACKMIS Address/Data NACK Interrupt Mask 4 5 I2C_MMIS_RXFFMIS Receive FIFO Full Interrupt Mask 11 12 I2C_MMIS_RXMIS Receive FIFO Request Interrupt Mask 9 10 I2C_MMIS_STARTMIS START Detection Interrupt Mask 5 6 I2C_MMIS_STOPMIS STOP Detection Interrupt Mask 6 7 I2C_MMIS_TXFEMIS Transmit FIFO Empty Interrupt Mask 10 11 I2C_MMIS_TXMIS Transmit Request Interrupt Mask 8 9 MRIS I2C Master Raw Interrupt Status 0x14 -1 read-write n 0x0 0x0 I2C_MRIS_ARBLOSTRIS Arbitration Lost Raw Interrupt Status 7 8 I2C_MRIS_CLKRIS Clock Timeout Raw Interrupt Status 1 2 I2C_MRIS_DMARXRIS Receive DMA Raw Interrupt Status 2 3 I2C_MRIS_DMATXRIS Transmit DMA Raw Interrupt Status 3 4 I2C_MRIS_NACKRIS Address/Data NACK Raw Interrupt Status 4 5 I2C_MRIS_RIS Master Raw Interrupt Status 0 1 I2C_MRIS_RXFFRIS Receive FIFO Full Raw Interrupt Status 11 12 I2C_MRIS_RXRIS Receive FIFO Request Raw Interrupt Status 9 10 I2C_MRIS_STARTRIS START Detection Raw Interrupt Status 5 6 I2C_MRIS_STOPRIS STOP Detection Raw Interrupt Status 6 7 I2C_MRIS_TXFERIS Transmit FIFO Empty Raw Interrupt Status 10 11 I2C_MRIS_TXRIS Transmit Request Raw Interrupt Status 8 9 MSA I2C Master Slave Address 0x0 -1 read-write n 0x0 0x0 I2C_MSA_RS Receive not send 0 1 I2C_MSA_SA I2C Slave Address 1 8 MTPR I2C Master Timer Period 0xC -1 read-write n 0x0 0x0 I2C_MTPR_HS High-Speed Enable 7 8 I2C_MTPR_PULSEL Glitch Suppression Pulse Width 16 19 I2C_MTPR_PULSEL_BYPASS Bypass 0x0 I2C_MTPR_PULSEL_1 1 clock 0x1 I2C_MTPR_PULSEL_2 2 clocks 0x2 I2C_MTPR_PULSEL_3 3 clocks 0x3 I2C_MTPR_PULSEL_4 4 clocks 0x4 I2C_MTPR_PULSEL_8 8 clocks 0x5 I2C_MTPR_PULSEL_16 16 clocks 0x6 I2C_MTPR_PULSEL_31 31 clocks 0x7 I2C_MTPR_TPR Timer Period 0 7 PC I2C Peripheral Configuration 0xFC4 -1 read-write n 0x0 0x0 I2C_PC_HS High-Speed Capable 0 1 PP I2C Peripheral Properties 0xFC0 -1 read-write n 0x0 0x0 I2C_PP_HS High-Speed Capable 0 1 SACKCTL I2C Slave ACK Control 0x820 -1 read-write n 0x0 0x0 I2C_SACKCTL_ACKOEN I2C Slave ACK Override Enable 0 1 I2C_SACKCTL_ACKOVAL I2C Slave ACK Override Value 1 2 SCSR I2C Slave Control/Status 0x804 -1 read-write n 0x0 0x0 I2C_SCSR_ACTDMARX DMA RX Active Status 31 32 I2C_SCSR_ACTDMATX DMA TX Active Status 30 31 I2C_SCSR_DA Device Active 0 1 I2C_SCSR_FBR First Byte Received 2 3 I2C_SCSR_OAR2SEL OAR2 Address Matched 3 4 I2C_SCSR_QCMDRW Quick Command Read / Write 5 6 I2C_SCSR_QCMDST Quick Command Status 4 5 I2C_SCSR_RREQ Receive Request 0 1 I2C_SCSR_RXFIFO RX FIFO Enable 2 3 I2C_SCSR_TREQ Transmit Request 1 2 I2C_SCSR_TXFIFO TX FIFO Enable 1 2 SDR I2C Slave Data 0x808 -1 read-write n 0x0 0x0 I2C_SDR_DATA Data for Transfer 0 8 SICR I2C Slave Interrupt Clear 0x818 -1 write-only n 0x0 0x0 I2C_SICR_DATAIC Data Interrupt Clear 0 1 write-only I2C_SICR_DMARXIC Receive DMA Interrupt Clear 3 4 write-only I2C_SICR_DMATXIC Transmit DMA Interrupt Clear 4 5 write-only I2C_SICR_RXFFIC Receive FIFO Full Interrupt Mask 8 9 write-only I2C_SICR_RXIC Receive Request Interrupt Mask 6 7 write-only I2C_SICR_STARTIC Start Condition Interrupt Clear 1 2 write-only I2C_SICR_STOPIC Stop Condition Interrupt Clear 2 3 write-only I2C_SICR_TXFEIC Transmit FIFO Empty Interrupt Mask 7 8 write-only I2C_SICR_TXIC Transmit Request Interrupt Mask 5 6 write-only SIMR I2C Slave Interrupt Mask 0x80C -1 read-write n 0x0 0x0 I2C_SIMR_DATAIM Data Interrupt Mask 0 1 I2C_SIMR_DMARXIM Receive DMA Interrupt Mask 3 4 I2C_SIMR_DMATXIM Transmit DMA Interrupt Mask 4 5 I2C_SIMR_RXFFIM Receive FIFO Full Interrupt Mask 8 9 I2C_SIMR_RXIM Receive FIFO Request Interrupt Mask 6 7 I2C_SIMR_STARTIM Start Condition Interrupt Mask 1 2 I2C_SIMR_STOPIM Stop Condition Interrupt Mask 2 3 I2C_SIMR_TXFEIM Transmit FIFO Empty Interrupt Mask 7 8 I2C_SIMR_TXIM Transmit FIFO Request Interrupt Mask 5 6 SMIS I2C Slave Masked Interrupt Status 0x814 -1 read-write n 0x0 0x0 I2C_SMIS_DATAMIS Data Masked Interrupt Status 0 1 I2C_SMIS_DMARXMIS Receive DMA Masked Interrupt Status 3 4 I2C_SMIS_DMATXMIS Transmit DMA Masked Interrupt Status 4 5 I2C_SMIS_RXFFMIS Receive FIFO Full Interrupt Mask 8 9 I2C_SMIS_RXMIS Receive FIFO Request Interrupt Mask 6 7 I2C_SMIS_STARTMIS Start Condition Masked Interrupt Status 1 2 I2C_SMIS_STOPMIS Stop Condition Masked Interrupt Status 2 3 I2C_SMIS_TXFEMIS Transmit FIFO Empty Interrupt Mask 7 8 I2C_SMIS_TXMIS Transmit FIFO Request Interrupt Mask 5 6 SOAR I2C Slave Own Address 0x800 -1 read-write n 0x0 0x0 I2C_SOAR_OAR I2C Slave Own Address 0 7 SOAR2 I2C Slave Own Address 2 0x81C -1 read-write n 0x0 0x0 I2C_SOAR2_OAR2 I2C Slave Own Address 2 0 7 I2C_SOAR2_OAR2EN I2C Slave Own Address 2 Enable 7 8 SRIS I2C Slave Raw Interrupt Status 0x810 -1 read-write n 0x0 0x0 I2C_SRIS_DATARIS Data Raw Interrupt Status 0 1 I2C_SRIS_DMARXRIS Receive DMA Raw Interrupt Status 3 4 I2C_SRIS_DMATXRIS Transmit DMA Raw Interrupt Status 4 5 I2C_SRIS_RXFFRIS Receive FIFO Full Raw Interrupt Status 8 9 I2C_SRIS_RXRIS Receive FIFO Request Raw Interrupt Status 6 7 I2C_SRIS_STARTRIS Start Condition Raw Interrupt Status 1 2 I2C_SRIS_STOPRIS Stop Condition Raw Interrupt Status 2 3 I2C_SRIS_TXFERIS Transmit FIFO Empty Raw Interrupt Status 7 8 I2C_SRIS_TXRIS Transmit Request Raw Interrupt Status 5 6 I2C6 Register map for I2C0 peripheral I2C 0x0 0x0 0x1000 registers n I2C6 102 FIFOCTL I2C FIFO Control 0xF04 -1 read-write n 0x0 0x0 I2C_FIFOCTL_DMARXENA DMA RX Channel Enable 29 30 I2C_FIFOCTL_DMATXENA DMA TX Channel Enable 13 14 I2C_FIFOCTL_RXASGNMT RX Control Assignment 31 32 I2C_FIFOCTL_RXFLUSH RX FIFO Flush 30 31 I2C_FIFOCTL_RXTRIG RX FIFO Trigger 16 19 I2C_FIFOCTL_TXASGNMT TX Control Assignment 15 16 I2C_FIFOCTL_TXFLUSH TX FIFO Flush 14 15 I2C_FIFOCTL_TXTRIG TX FIFO Trigger 0 3 FIFODATA I2C FIFO Data 0xF00 -1 read-write n 0x0 0x0 I2C_FIFODATA_DATA I2C TX FIFO Write Data Byte 0 8 FIFOSTATUS I2C FIFO Status 0xF08 -1 read-write n 0x0 0x0 I2C_FIFOSTATUS_RXABVTRIG RX FIFO Above Trigger Level 18 19 I2C_FIFOSTATUS_RXFE RX FIFO Empty 16 17 I2C_FIFOSTATUS_RXFF RX FIFO Full 17 18 I2C_FIFOSTATUS_TXBLWTRIG TX FIFO Below Trigger Level 2 3 I2C_FIFOSTATUS_TXFE TX FIFO Empty 0 1 I2C_FIFOSTATUS_TXFF TX FIFO Full 1 2 I2C0FIFOCTL I2C FIFO Control 0xF04 read-write n 0x0 0x0 I2C_FIFOCTL_DMARXENA DMA RX Channel Enable 29 30 I2C_FIFOCTL_DMATXENA DMA TX Channel Enable 13 14 I2C_FIFOCTL_RXASGNMT RX Control Assignment 31 32 I2C_FIFOCTL_RXFLUSH RX FIFO Flush 30 31 I2C_FIFOCTL_RXTRIG RX FIFO Trigger 16 19 I2C_FIFOCTL_TXASGNMT TX Control Assignment 15 16 I2C_FIFOCTL_TXFLUSH TX FIFO Flush 14 15 I2C_FIFOCTL_TXTRIG TX FIFO Trigger 0 3 I2C0FIFODATA I2C FIFO Data 0xF00 read-write n 0x0 0x0 I2C_FIFODATA_DATA I2C TX FIFO Write Data Byte 0 8 I2C0FIFOSTATUS I2C FIFO Status 0xF08 read-write n 0x0 0x0 I2C_FIFOSTATUS_RXABVTRIG RX FIFO Above Trigger Level 18 19 I2C_FIFOSTATUS_RXFE RX FIFO Empty 16 17 I2C_FIFOSTATUS_RXFF RX FIFO Full 17 18 I2C_FIFOSTATUS_TXBLWTRIG TX FIFO Below Trigger Level 2 3 I2C_FIFOSTATUS_TXFE TX FIFO Empty 0 1 I2C_FIFOSTATUS_TXFF TX FIFO Full 1 2 I2C0MBCNT I2C Master Burst Count 0x34 read-write n 0x0 0x0 I2C_MBCNT_CNTL I2C Master Burst Count 0 8 I2C0MBLEN I2C Master Burst Length 0x30 read-write n 0x0 0x0 I2C_MBLEN_CNTL I2C Burst Length 0 8 I2C0MBMON I2C Master Bus Monitor 0x2C read-write n 0x0 0x0 I2C_MBMON_SCL I2C SCL Status 0 1 I2C_MBMON_SDA I2C SDA Status 1 2 I2C0MCLKOCNT I2C Master Clock Low Timeout Count 0x24 read-write n 0x0 0x0 I2C_MCLKOCNT_CNTL I2C Master Count 0 8 I2C0MCR I2C Master Configuration 0x20 read-write n 0x0 0x0 I2C_MCR_LPBK I2C Loopback 0 1 I2C_MCR_MFE I2C Master Function Enable 4 5 I2C_MCR_SFE I2C Slave Function Enable 5 6 I2C0MCS I2C Master Control/Status 0x4 read-write n 0x0 0x0 I2C_MCS_ACK Data Acknowledge Enable 3 4 I2C_MCS_ACTDMARX DMA RX Active Status 31 32 I2C_MCS_ACTDMATX DMA TX Active Status 30 31 I2C_MCS_ADRACK Acknowledge Address 2 3 I2C_MCS_ARBLST Arbitration Lost 4 5 I2C_MCS_BURST Burst Enable 6 7 I2C_MCS_CLKTO Clock Timeout Error 7 8 I2C_MCS_IDLE I2C Idle 5 6 I2C_MCS_RUN I2C Master Enable 0 1 I2C_MCS_START Generate START 1 2 I2C0MDR I2C Master Data 0x8 read-write n 0x0 0x0 I2C_MDR_DATA This byte contains the data transferred during a transaction 0 8 I2C0MICR I2C Master Interrupt Clear 0x1C write-only n 0x0 0x0 I2C_MICR_ARBLOSTIC Arbitration Lost Interrupt Clear 7 8 write-only I2C_MICR_CLKIC Clock Timeout Interrupt Clear 1 2 write-only I2C_MICR_DMARXIC Receive DMA Interrupt Clear 2 3 write-only I2C_MICR_DMATXIC Transmit DMA Interrupt Clear 3 4 write-only I2C_MICR_IC Master Interrupt Clear 0 1 write-only I2C_MICR_NACKIC Address/Data NACK Interrupt Clear 4 5 write-only I2C_MICR_RXFFIC Receive FIFO Full Interrupt Clear 11 12 write-only I2C_MICR_RXIC Receive FIFO Request Interrupt Clear 9 10 write-only I2C_MICR_STARTIC START Detection Interrupt Clear 5 6 write-only I2C_MICR_STOPIC STOP Detection Interrupt Clear 6 7 write-only I2C_MICR_TXFEIC Transmit FIFO Empty Interrupt Clear 10 11 write-only I2C_MICR_TXIC Transmit FIFO Request Interrupt Clear 8 9 write-only I2C0MIMR I2C Master Interrupt Mask 0x10 read-write n 0x0 0x0 I2C_MIMR_ARBLOSTIM Arbitration Lost Interrupt Mask 7 8 I2C_MIMR_CLKIM Clock Timeout Interrupt Mask 1 2 I2C_MIMR_DMARXIM Receive DMA Interrupt Mask 2 3 I2C_MIMR_DMATXIM Transmit DMA Interrupt Mask 3 4 I2C_MIMR_IM Master Interrupt Mask 0 1 I2C_MIMR_NACKIM Address/Data NACK Interrupt Mask 4 5 I2C_MIMR_RXFFIM Receive FIFO Full Interrupt Mask 11 12 I2C_MIMR_RXIM Receive FIFO Request Interrupt Mask 9 10 I2C_MIMR_STARTIM START Detection Interrupt Mask 5 6 I2C_MIMR_STOPIM STOP Detection Interrupt Mask 6 7 I2C_MIMR_TXFEIM Transmit FIFO Empty Interrupt Mask 10 11 I2C_MIMR_TXIM Transmit FIFO Request Interrupt Mask 8 9 I2C0MMIS I2C Master Masked Interrupt Status 0x18 read-write n 0x0 0x0 I2C_MMIS_ARBLOSTMIS Arbitration Lost Interrupt Mask 7 8 I2C_MMIS_CLKMIS Clock Timeout Masked Interrupt Status 1 2 I2C_MMIS_DMARXMIS Receive DMA Interrupt Status 2 3 I2C_MMIS_DMATXMIS Transmit DMA Interrupt Status 3 4 I2C_MMIS_MIS Masked Interrupt Status 0 1 I2C_MMIS_NACKMIS Address/Data NACK Interrupt Mask 4 5 I2C_MMIS_RXFFMIS Receive FIFO Full Interrupt Mask 11 12 I2C_MMIS_RXMIS Receive FIFO Request Interrupt Mask 9 10 I2C_MMIS_STARTMIS START Detection Interrupt Mask 5 6 I2C_MMIS_STOPMIS STOP Detection Interrupt Mask 6 7 I2C_MMIS_TXFEMIS Transmit FIFO Empty Interrupt Mask 10 11 I2C_MMIS_TXMIS Transmit Request Interrupt Mask 8 9 I2C0MRIS I2C Master Raw Interrupt Status 0x14 read-write n 0x0 0x0 I2C_MRIS_ARBLOSTRIS Arbitration Lost Raw Interrupt Status 7 8 I2C_MRIS_CLKRIS Clock Timeout Raw Interrupt Status 1 2 I2C_MRIS_DMARXRIS Receive DMA Raw Interrupt Status 2 3 I2C_MRIS_DMATXRIS Transmit DMA Raw Interrupt Status 3 4 I2C_MRIS_NACKRIS Address/Data NACK Raw Interrupt Status 4 5 I2C_MRIS_RIS Master Raw Interrupt Status 0 1 I2C_MRIS_RXFFRIS Receive FIFO Full Raw Interrupt Status 11 12 I2C_MRIS_RXRIS Receive FIFO Request Raw Interrupt Status 9 10 I2C_MRIS_STARTRIS START Detection Raw Interrupt Status 5 6 I2C_MRIS_STOPRIS STOP Detection Raw Interrupt Status 6 7 I2C_MRIS_TXFERIS Transmit FIFO Empty Raw Interrupt Status 10 11 I2C_MRIS_TXRIS Transmit Request Raw Interrupt Status 8 9 I2C0MSA I2C Master Slave Address 0x0 read-write n 0x0 0x0 I2C_MSA_RS Receive not send 0 1 I2C_MSA_SA I2C Slave Address 1 8 I2C0MTPR I2C Master Timer Period 0xC read-write n 0x0 0x0 I2C_MTPR_HS High-Speed Enable 7 8 I2C_MTPR_PULSEL Glitch Suppression Pulse Width 16 19 I2C_MTPR_PULSEL_BYPASS Bypass 0x0 I2C_MTPR_PULSEL_1 1 clock 0x1 I2C_MTPR_PULSEL_2 2 clocks 0x2 I2C_MTPR_PULSEL_3 3 clocks 0x3 I2C_MTPR_PULSEL_4 4 clocks 0x4 I2C_MTPR_PULSEL_8 8 clocks 0x5 I2C_MTPR_PULSEL_16 16 clocks 0x6 I2C_MTPR_PULSEL_31 31 clocks 0x7 I2C_MTPR_TPR Timer Period 0 7 I2C0PC I2C Peripheral Configuration 0xFC4 read-write n 0x0 0x0 I2C_PC_HS High-Speed Capable 0 1 I2C0PP I2C Peripheral Properties 0xFC0 read-write n 0x0 0x0 I2C_PP_HS High-Speed Capable 0 1 I2C0SACKCTL I2C Slave ACK Control 0x820 read-write n 0x0 0x0 I2C_SACKCTL_ACKOEN I2C Slave ACK Override Enable 0 1 I2C_SACKCTL_ACKOVAL I2C Slave ACK Override Value 1 2 I2C0SCSR I2C Slave Control/Status 0x804 read-write n 0x0 0x0 I2C_SCSR_ACTDMARX DMA RX Active Status 31 32 I2C_SCSR_ACTDMATX DMA TX Active Status 30 31 I2C_SCSR_FBR First Byte Received 2 3 I2C_SCSR_OAR2SEL OAR2 Address Matched 3 4 I2C_SCSR_QCMDRW Quick Command Read / Write 5 6 I2C_SCSR_QCMDST Quick Command Status 4 5 I2C_SCSR_RREQ Receive Request 0 1 I2C_SCSR_TXFIFO TX FIFO Enable 1 2 I2C0SDR I2C Slave Data 0x808 read-write n 0x0 0x0 I2C_SDR_DATA Data for Transfer 0 8 I2C0SICR I2C Slave Interrupt Clear 0x818 write-only n 0x0 0x0 I2C_SICR_DATAIC Data Interrupt Clear 0 1 write-only I2C_SICR_DMARXIC Receive DMA Interrupt Clear 3 4 write-only I2C_SICR_DMATXIC Transmit DMA Interrupt Clear 4 5 write-only I2C_SICR_RXFFIC Receive FIFO Full Interrupt Mask 8 9 write-only I2C_SICR_RXIC Receive Request Interrupt Mask 6 7 write-only I2C_SICR_STARTIC Start Condition Interrupt Clear 1 2 write-only I2C_SICR_STOPIC Stop Condition Interrupt Clear 2 3 write-only I2C_SICR_TXFEIC Transmit FIFO Empty Interrupt Mask 7 8 write-only I2C_SICR_TXIC Transmit Request Interrupt Mask 5 6 write-only I2C0SIMR I2C Slave Interrupt Mask 0x80C read-write n 0x0 0x0 I2C_SIMR_DATAIM Data Interrupt Mask 0 1 I2C_SIMR_DMARXIM Receive DMA Interrupt Mask 3 4 I2C_SIMR_DMATXIM Transmit DMA Interrupt Mask 4 5 I2C_SIMR_RXFFIM Receive FIFO Full Interrupt Mask 8 9 I2C_SIMR_RXIM Receive FIFO Request Interrupt Mask 6 7 I2C_SIMR_STARTIM Start Condition Interrupt Mask 1 2 I2C_SIMR_STOPIM Stop Condition Interrupt Mask 2 3 I2C_SIMR_TXFEIM Transmit FIFO Empty Interrupt Mask 7 8 I2C_SIMR_TXIM Transmit FIFO Request Interrupt Mask 5 6 I2C0SMIS I2C Slave Masked Interrupt Status 0x814 read-write n 0x0 0x0 I2C_SMIS_DATAMIS Data Masked Interrupt Status 0 1 I2C_SMIS_DMARXMIS Receive DMA Masked Interrupt Status 3 4 I2C_SMIS_DMATXMIS Transmit DMA Masked Interrupt Status 4 5 I2C_SMIS_RXFFMIS Receive FIFO Full Interrupt Mask 8 9 I2C_SMIS_RXMIS Receive FIFO Request Interrupt Mask 6 7 I2C_SMIS_STARTMIS Start Condition Masked Interrupt Status 1 2 I2C_SMIS_STOPMIS Stop Condition Masked Interrupt Status 2 3 I2C_SMIS_TXFEMIS Transmit FIFO Empty Interrupt Mask 7 8 I2C_SMIS_TXMIS Transmit FIFO Request Interrupt Mask 5 6 I2C0SOAR I2C Slave Own Address 0x800 read-write n 0x0 0x0 I2C_SOAR_OAR I2C Slave Own Address 0 7 I2C0SOAR2 I2C Slave Own Address 2 0x81C read-write n 0x0 0x0 I2C_SOAR2_OAR2 I2C Slave Own Address 2 0 7 I2C_SOAR2_OAR2EN I2C Slave Own Address 2 Enable 7 8 I2C0SRIS I2C Slave Raw Interrupt Status 0x810 read-write n 0x0 0x0 I2C_SRIS_DATARIS Data Raw Interrupt Status 0 1 I2C_SRIS_DMARXRIS Receive DMA Raw Interrupt Status 3 4 I2C_SRIS_DMATXRIS Transmit DMA Raw Interrupt Status 4 5 I2C_SRIS_RXFFRIS Receive FIFO Full Raw Interrupt Status 8 9 I2C_SRIS_RXRIS Receive FIFO Request Raw Interrupt Status 6 7 I2C_SRIS_STARTRIS Start Condition Raw Interrupt Status 1 2 I2C_SRIS_STOPRIS Stop Condition Raw Interrupt Status 2 3 I2C_SRIS_TXFERIS Transmit FIFO Empty Raw Interrupt Status 7 8 I2C_SRIS_TXRIS Transmit Request Raw Interrupt Status 5 6 MBCNT I2C Master Burst Count 0x34 -1 read-write n 0x0 0x0 I2C_MBCNT_CNTL I2C Master Burst Count 0 8 MBLEN I2C Master Burst Length 0x30 -1 read-write n 0x0 0x0 I2C_MBLEN_CNTL I2C Burst Length 0 8 MBMON I2C Master Bus Monitor 0x2C -1 read-write n 0x0 0x0 I2C_MBMON_SCL I2C SCL Status 0 1 I2C_MBMON_SDA I2C SDA Status 1 2 MCLKOCNT I2C Master Clock Low Timeout Count 0x24 -1 read-write n 0x0 0x0 I2C_MCLKOCNT_CNTL I2C Master Count 0 8 MCR I2C Master Configuration 0x20 -1 read-write n 0x0 0x0 I2C_MCR_LPBK I2C Loopback 0 1 I2C_MCR_MFE I2C Master Function Enable 4 5 I2C_MCR_SFE I2C Slave Function Enable 5 6 MCS I2C Master Control/Status 0x4 -1 read-write n 0x0 0x0 I2C_MCS_ACK Data Acknowledge Enable 3 4 I2C_MCS_ACTDMARX DMA RX Active Status 31 32 I2C_MCS_ACTDMATX DMA TX Active Status 30 31 I2C_MCS_ADRACK Acknowledge Address 2 3 I2C_MCS_ARBLST Arbitration Lost 4 5 I2C_MCS_BURST Burst Enable 6 7 I2C_MCS_BUSBSY Bus Busy 6 7 I2C_MCS_BUSY I2C Busy 0 1 I2C_MCS_CLKTO Clock Timeout Error 7 8 I2C_MCS_DATACK Acknowledge Data 3 4 I2C_MCS_ERROR Error 1 2 I2C_MCS_HS High-Speed Enable 4 5 I2C_MCS_IDLE I2C Idle 5 6 I2C_MCS_QCMD Quick Command 5 6 I2C_MCS_RUN I2C Master Enable 0 1 I2C_MCS_START Generate START 1 2 I2C_MCS_STOP Generate STOP 2 3 MDR I2C Master Data 0x8 -1 read-write n 0x0 0x0 I2C_MDR_DATA This byte contains the data transferred during a transaction 0 8 MICR I2C Master Interrupt Clear 0x1C -1 write-only n 0x0 0x0 I2C_MICR_ARBLOSTIC Arbitration Lost Interrupt Clear 7 8 write-only I2C_MICR_CLKIC Clock Timeout Interrupt Clear 1 2 write-only I2C_MICR_DMARXIC Receive DMA Interrupt Clear 2 3 write-only I2C_MICR_DMATXIC Transmit DMA Interrupt Clear 3 4 write-only I2C_MICR_IC Master Interrupt Clear 0 1 write-only I2C_MICR_NACKIC Address/Data NACK Interrupt Clear 4 5 write-only I2C_MICR_RXFFIC Receive FIFO Full Interrupt Clear 11 12 write-only I2C_MICR_RXIC Receive FIFO Request Interrupt Clear 9 10 write-only I2C_MICR_STARTIC START Detection Interrupt Clear 5 6 write-only I2C_MICR_STOPIC STOP Detection Interrupt Clear 6 7 write-only I2C_MICR_TXFEIC Transmit FIFO Empty Interrupt Clear 10 11 write-only I2C_MICR_TXIC Transmit FIFO Request Interrupt Clear 8 9 write-only MIMR I2C Master Interrupt Mask 0x10 -1 read-write n 0x0 0x0 I2C_MIMR_ARBLOSTIM Arbitration Lost Interrupt Mask 7 8 I2C_MIMR_CLKIM Clock Timeout Interrupt Mask 1 2 I2C_MIMR_DMARXIM Receive DMA Interrupt Mask 2 3 I2C_MIMR_DMATXIM Transmit DMA Interrupt Mask 3 4 I2C_MIMR_IM Master Interrupt Mask 0 1 I2C_MIMR_NACKIM Address/Data NACK Interrupt Mask 4 5 I2C_MIMR_RXFFIM Receive FIFO Full Interrupt Mask 11 12 I2C_MIMR_RXIM Receive FIFO Request Interrupt Mask 9 10 I2C_MIMR_STARTIM START Detection Interrupt Mask 5 6 I2C_MIMR_STOPIM STOP Detection Interrupt Mask 6 7 I2C_MIMR_TXFEIM Transmit FIFO Empty Interrupt Mask 10 11 I2C_MIMR_TXIM Transmit FIFO Request Interrupt Mask 8 9 MMIS I2C Master Masked Interrupt Status 0x18 -1 read-write n 0x0 0x0 I2C_MMIS_ARBLOSTMIS Arbitration Lost Interrupt Mask 7 8 I2C_MMIS_CLKMIS Clock Timeout Masked Interrupt Status 1 2 I2C_MMIS_DMARXMIS Receive DMA Interrupt Status 2 3 I2C_MMIS_DMATXMIS Transmit DMA Interrupt Status 3 4 I2C_MMIS_MIS Masked Interrupt Status 0 1 I2C_MMIS_NACKMIS Address/Data NACK Interrupt Mask 4 5 I2C_MMIS_RXFFMIS Receive FIFO Full Interrupt Mask 11 12 I2C_MMIS_RXMIS Receive FIFO Request Interrupt Mask 9 10 I2C_MMIS_STARTMIS START Detection Interrupt Mask 5 6 I2C_MMIS_STOPMIS STOP Detection Interrupt Mask 6 7 I2C_MMIS_TXFEMIS Transmit FIFO Empty Interrupt Mask 10 11 I2C_MMIS_TXMIS Transmit Request Interrupt Mask 8 9 MRIS I2C Master Raw Interrupt Status 0x14 -1 read-write n 0x0 0x0 I2C_MRIS_ARBLOSTRIS Arbitration Lost Raw Interrupt Status 7 8 I2C_MRIS_CLKRIS Clock Timeout Raw Interrupt Status 1 2 I2C_MRIS_DMARXRIS Receive DMA Raw Interrupt Status 2 3 I2C_MRIS_DMATXRIS Transmit DMA Raw Interrupt Status 3 4 I2C_MRIS_NACKRIS Address/Data NACK Raw Interrupt Status 4 5 I2C_MRIS_RIS Master Raw Interrupt Status 0 1 I2C_MRIS_RXFFRIS Receive FIFO Full Raw Interrupt Status 11 12 I2C_MRIS_RXRIS Receive FIFO Request Raw Interrupt Status 9 10 I2C_MRIS_STARTRIS START Detection Raw Interrupt Status 5 6 I2C_MRIS_STOPRIS STOP Detection Raw Interrupt Status 6 7 I2C_MRIS_TXFERIS Transmit FIFO Empty Raw Interrupt Status 10 11 I2C_MRIS_TXRIS Transmit Request Raw Interrupt Status 8 9 MSA I2C Master Slave Address 0x0 -1 read-write n 0x0 0x0 I2C_MSA_RS Receive not send 0 1 I2C_MSA_SA I2C Slave Address 1 8 MTPR I2C Master Timer Period 0xC -1 read-write n 0x0 0x0 I2C_MTPR_HS High-Speed Enable 7 8 I2C_MTPR_PULSEL Glitch Suppression Pulse Width 16 19 I2C_MTPR_PULSEL_BYPASS Bypass 0x0 I2C_MTPR_PULSEL_1 1 clock 0x1 I2C_MTPR_PULSEL_2 2 clocks 0x2 I2C_MTPR_PULSEL_3 3 clocks 0x3 I2C_MTPR_PULSEL_4 4 clocks 0x4 I2C_MTPR_PULSEL_8 8 clocks 0x5 I2C_MTPR_PULSEL_16 16 clocks 0x6 I2C_MTPR_PULSEL_31 31 clocks 0x7 I2C_MTPR_TPR Timer Period 0 7 PC I2C Peripheral Configuration 0xFC4 -1 read-write n 0x0 0x0 I2C_PC_HS High-Speed Capable 0 1 PP I2C Peripheral Properties 0xFC0 -1 read-write n 0x0 0x0 I2C_PP_HS High-Speed Capable 0 1 SACKCTL I2C Slave ACK Control 0x820 -1 read-write n 0x0 0x0 I2C_SACKCTL_ACKOEN I2C Slave ACK Override Enable 0 1 I2C_SACKCTL_ACKOVAL I2C Slave ACK Override Value 1 2 SCSR I2C Slave Control/Status 0x804 -1 read-write n 0x0 0x0 I2C_SCSR_ACTDMARX DMA RX Active Status 31 32 I2C_SCSR_ACTDMATX DMA TX Active Status 30 31 I2C_SCSR_DA Device Active 0 1 I2C_SCSR_FBR First Byte Received 2 3 I2C_SCSR_OAR2SEL OAR2 Address Matched 3 4 I2C_SCSR_QCMDRW Quick Command Read / Write 5 6 I2C_SCSR_QCMDST Quick Command Status 4 5 I2C_SCSR_RREQ Receive Request 0 1 I2C_SCSR_RXFIFO RX FIFO Enable 2 3 I2C_SCSR_TREQ Transmit Request 1 2 I2C_SCSR_TXFIFO TX FIFO Enable 1 2 SDR I2C Slave Data 0x808 -1 read-write n 0x0 0x0 I2C_SDR_DATA Data for Transfer 0 8 SICR I2C Slave Interrupt Clear 0x818 -1 write-only n 0x0 0x0 I2C_SICR_DATAIC Data Interrupt Clear 0 1 write-only I2C_SICR_DMARXIC Receive DMA Interrupt Clear 3 4 write-only I2C_SICR_DMATXIC Transmit DMA Interrupt Clear 4 5 write-only I2C_SICR_RXFFIC Receive FIFO Full Interrupt Mask 8 9 write-only I2C_SICR_RXIC Receive Request Interrupt Mask 6 7 write-only I2C_SICR_STARTIC Start Condition Interrupt Clear 1 2 write-only I2C_SICR_STOPIC Stop Condition Interrupt Clear 2 3 write-only I2C_SICR_TXFEIC Transmit FIFO Empty Interrupt Mask 7 8 write-only I2C_SICR_TXIC Transmit Request Interrupt Mask 5 6 write-only SIMR I2C Slave Interrupt Mask 0x80C -1 read-write n 0x0 0x0 I2C_SIMR_DATAIM Data Interrupt Mask 0 1 I2C_SIMR_DMARXIM Receive DMA Interrupt Mask 3 4 I2C_SIMR_DMATXIM Transmit DMA Interrupt Mask 4 5 I2C_SIMR_RXFFIM Receive FIFO Full Interrupt Mask 8 9 I2C_SIMR_RXIM Receive FIFO Request Interrupt Mask 6 7 I2C_SIMR_STARTIM Start Condition Interrupt Mask 1 2 I2C_SIMR_STOPIM Stop Condition Interrupt Mask 2 3 I2C_SIMR_TXFEIM Transmit FIFO Empty Interrupt Mask 7 8 I2C_SIMR_TXIM Transmit FIFO Request Interrupt Mask 5 6 SMIS I2C Slave Masked Interrupt Status 0x814 -1 read-write n 0x0 0x0 I2C_SMIS_DATAMIS Data Masked Interrupt Status 0 1 I2C_SMIS_DMARXMIS Receive DMA Masked Interrupt Status 3 4 I2C_SMIS_DMATXMIS Transmit DMA Masked Interrupt Status 4 5 I2C_SMIS_RXFFMIS Receive FIFO Full Interrupt Mask 8 9 I2C_SMIS_RXMIS Receive FIFO Request Interrupt Mask 6 7 I2C_SMIS_STARTMIS Start Condition Masked Interrupt Status 1 2 I2C_SMIS_STOPMIS Stop Condition Masked Interrupt Status 2 3 I2C_SMIS_TXFEMIS Transmit FIFO Empty Interrupt Mask 7 8 I2C_SMIS_TXMIS Transmit FIFO Request Interrupt Mask 5 6 SOAR I2C Slave Own Address 0x800 -1 read-write n 0x0 0x0 I2C_SOAR_OAR I2C Slave Own Address 0 7 SOAR2 I2C Slave Own Address 2 0x81C -1 read-write n 0x0 0x0 I2C_SOAR2_OAR2 I2C Slave Own Address 2 0 7 I2C_SOAR2_OAR2EN I2C Slave Own Address 2 Enable 7 8 SRIS I2C Slave Raw Interrupt Status 0x810 -1 read-write n 0x0 0x0 I2C_SRIS_DATARIS Data Raw Interrupt Status 0 1 I2C_SRIS_DMARXRIS Receive DMA Raw Interrupt Status 3 4 I2C_SRIS_DMATXRIS Transmit DMA Raw Interrupt Status 4 5 I2C_SRIS_RXFFRIS Receive FIFO Full Raw Interrupt Status 8 9 I2C_SRIS_RXRIS Receive FIFO Request Raw Interrupt Status 6 7 I2C_SRIS_STARTRIS Start Condition Raw Interrupt Status 1 2 I2C_SRIS_STOPRIS Stop Condition Raw Interrupt Status 2 3 I2C_SRIS_TXFERIS Transmit FIFO Empty Raw Interrupt Status 7 8 I2C_SRIS_TXRIS Transmit Request Raw Interrupt Status 5 6 I2C7 Register map for I2C0 peripheral I2C 0x0 0x0 0x1000 registers n I2C7 103 FIFOCTL I2C FIFO Control 0xF04 -1 read-write n 0x0 0x0 I2C_FIFOCTL_DMARXENA DMA RX Channel Enable 29 30 I2C_FIFOCTL_DMATXENA DMA TX Channel Enable 13 14 I2C_FIFOCTL_RXASGNMT RX Control Assignment 31 32 I2C_FIFOCTL_RXFLUSH RX FIFO Flush 30 31 I2C_FIFOCTL_RXTRIG RX FIFO Trigger 16 19 I2C_FIFOCTL_TXASGNMT TX Control Assignment 15 16 I2C_FIFOCTL_TXFLUSH TX FIFO Flush 14 15 I2C_FIFOCTL_TXTRIG TX FIFO Trigger 0 3 FIFODATA I2C FIFO Data 0xF00 -1 read-write n 0x0 0x0 I2C_FIFODATA_DATA I2C TX FIFO Write Data Byte 0 8 FIFOSTATUS I2C FIFO Status 0xF08 -1 read-write n 0x0 0x0 I2C_FIFOSTATUS_RXABVTRIG RX FIFO Above Trigger Level 18 19 I2C_FIFOSTATUS_RXFE RX FIFO Empty 16 17 I2C_FIFOSTATUS_RXFF RX FIFO Full 17 18 I2C_FIFOSTATUS_TXBLWTRIG TX FIFO Below Trigger Level 2 3 I2C_FIFOSTATUS_TXFE TX FIFO Empty 0 1 I2C_FIFOSTATUS_TXFF TX FIFO Full 1 2 I2C0FIFOCTL I2C FIFO Control 0xF04 read-write n 0x0 0x0 I2C_FIFOCTL_DMARXENA DMA RX Channel Enable 29 30 I2C_FIFOCTL_DMATXENA DMA TX Channel Enable 13 14 I2C_FIFOCTL_RXASGNMT RX Control Assignment 31 32 I2C_FIFOCTL_RXFLUSH RX FIFO Flush 30 31 I2C_FIFOCTL_RXTRIG RX FIFO Trigger 16 19 I2C_FIFOCTL_TXASGNMT TX Control Assignment 15 16 I2C_FIFOCTL_TXFLUSH TX FIFO Flush 14 15 I2C_FIFOCTL_TXTRIG TX FIFO Trigger 0 3 I2C0FIFODATA I2C FIFO Data 0xF00 read-write n 0x0 0x0 I2C_FIFODATA_DATA I2C TX FIFO Write Data Byte 0 8 I2C0FIFOSTATUS I2C FIFO Status 0xF08 read-write n 0x0 0x0 I2C_FIFOSTATUS_RXABVTRIG RX FIFO Above Trigger Level 18 19 I2C_FIFOSTATUS_RXFE RX FIFO Empty 16 17 I2C_FIFOSTATUS_RXFF RX FIFO Full 17 18 I2C_FIFOSTATUS_TXBLWTRIG TX FIFO Below Trigger Level 2 3 I2C_FIFOSTATUS_TXFE TX FIFO Empty 0 1 I2C_FIFOSTATUS_TXFF TX FIFO Full 1 2 I2C0MBCNT I2C Master Burst Count 0x34 read-write n 0x0 0x0 I2C_MBCNT_CNTL I2C Master Burst Count 0 8 I2C0MBLEN I2C Master Burst Length 0x30 read-write n 0x0 0x0 I2C_MBLEN_CNTL I2C Burst Length 0 8 I2C0MBMON I2C Master Bus Monitor 0x2C read-write n 0x0 0x0 I2C_MBMON_SCL I2C SCL Status 0 1 I2C_MBMON_SDA I2C SDA Status 1 2 I2C0MCLKOCNT I2C Master Clock Low Timeout Count 0x24 read-write n 0x0 0x0 I2C_MCLKOCNT_CNTL I2C Master Count 0 8 I2C0MCR I2C Master Configuration 0x20 read-write n 0x0 0x0 I2C_MCR_LPBK I2C Loopback 0 1 I2C_MCR_MFE I2C Master Function Enable 4 5 I2C_MCR_SFE I2C Slave Function Enable 5 6 I2C0MCS I2C Master Control/Status 0x4 read-write n 0x0 0x0 I2C_MCS_ACK Data Acknowledge Enable 3 4 I2C_MCS_ACTDMARX DMA RX Active Status 31 32 I2C_MCS_ACTDMATX DMA TX Active Status 30 31 I2C_MCS_ADRACK Acknowledge Address 2 3 I2C_MCS_ARBLST Arbitration Lost 4 5 I2C_MCS_BURST Burst Enable 6 7 I2C_MCS_CLKTO Clock Timeout Error 7 8 I2C_MCS_IDLE I2C Idle 5 6 I2C_MCS_RUN I2C Master Enable 0 1 I2C_MCS_START Generate START 1 2 I2C0MDR I2C Master Data 0x8 read-write n 0x0 0x0 I2C_MDR_DATA This byte contains the data transferred during a transaction 0 8 I2C0MICR I2C Master Interrupt Clear 0x1C write-only n 0x0 0x0 I2C_MICR_ARBLOSTIC Arbitration Lost Interrupt Clear 7 8 write-only I2C_MICR_CLKIC Clock Timeout Interrupt Clear 1 2 write-only I2C_MICR_DMARXIC Receive DMA Interrupt Clear 2 3 write-only I2C_MICR_DMATXIC Transmit DMA Interrupt Clear 3 4 write-only I2C_MICR_IC Master Interrupt Clear 0 1 write-only I2C_MICR_NACKIC Address/Data NACK Interrupt Clear 4 5 write-only I2C_MICR_RXFFIC Receive FIFO Full Interrupt Clear 11 12 write-only I2C_MICR_RXIC Receive FIFO Request Interrupt Clear 9 10 write-only I2C_MICR_STARTIC START Detection Interrupt Clear 5 6 write-only I2C_MICR_STOPIC STOP Detection Interrupt Clear 6 7 write-only I2C_MICR_TXFEIC Transmit FIFO Empty Interrupt Clear 10 11 write-only I2C_MICR_TXIC Transmit FIFO Request Interrupt Clear 8 9 write-only I2C0MIMR I2C Master Interrupt Mask 0x10 read-write n 0x0 0x0 I2C_MIMR_ARBLOSTIM Arbitration Lost Interrupt Mask 7 8 I2C_MIMR_CLKIM Clock Timeout Interrupt Mask 1 2 I2C_MIMR_DMARXIM Receive DMA Interrupt Mask 2 3 I2C_MIMR_DMATXIM Transmit DMA Interrupt Mask 3 4 I2C_MIMR_IM Master Interrupt Mask 0 1 I2C_MIMR_NACKIM Address/Data NACK Interrupt Mask 4 5 I2C_MIMR_RXFFIM Receive FIFO Full Interrupt Mask 11 12 I2C_MIMR_RXIM Receive FIFO Request Interrupt Mask 9 10 I2C_MIMR_STARTIM START Detection Interrupt Mask 5 6 I2C_MIMR_STOPIM STOP Detection Interrupt Mask 6 7 I2C_MIMR_TXFEIM Transmit FIFO Empty Interrupt Mask 10 11 I2C_MIMR_TXIM Transmit FIFO Request Interrupt Mask 8 9 I2C0MMIS I2C Master Masked Interrupt Status 0x18 read-write n 0x0 0x0 I2C_MMIS_ARBLOSTMIS Arbitration Lost Interrupt Mask 7 8 I2C_MMIS_CLKMIS Clock Timeout Masked Interrupt Status 1 2 I2C_MMIS_DMARXMIS Receive DMA Interrupt Status 2 3 I2C_MMIS_DMATXMIS Transmit DMA Interrupt Status 3 4 I2C_MMIS_MIS Masked Interrupt Status 0 1 I2C_MMIS_NACKMIS Address/Data NACK Interrupt Mask 4 5 I2C_MMIS_RXFFMIS Receive FIFO Full Interrupt Mask 11 12 I2C_MMIS_RXMIS Receive FIFO Request Interrupt Mask 9 10 I2C_MMIS_STARTMIS START Detection Interrupt Mask 5 6 I2C_MMIS_STOPMIS STOP Detection Interrupt Mask 6 7 I2C_MMIS_TXFEMIS Transmit FIFO Empty Interrupt Mask 10 11 I2C_MMIS_TXMIS Transmit Request Interrupt Mask 8 9 I2C0MRIS I2C Master Raw Interrupt Status 0x14 read-write n 0x0 0x0 I2C_MRIS_ARBLOSTRIS Arbitration Lost Raw Interrupt Status 7 8 I2C_MRIS_CLKRIS Clock Timeout Raw Interrupt Status 1 2 I2C_MRIS_DMARXRIS Receive DMA Raw Interrupt Status 2 3 I2C_MRIS_DMATXRIS Transmit DMA Raw Interrupt Status 3 4 I2C_MRIS_NACKRIS Address/Data NACK Raw Interrupt Status 4 5 I2C_MRIS_RIS Master Raw Interrupt Status 0 1 I2C_MRIS_RXFFRIS Receive FIFO Full Raw Interrupt Status 11 12 I2C_MRIS_RXRIS Receive FIFO Request Raw Interrupt Status 9 10 I2C_MRIS_STARTRIS START Detection Raw Interrupt Status 5 6 I2C_MRIS_STOPRIS STOP Detection Raw Interrupt Status 6 7 I2C_MRIS_TXFERIS Transmit FIFO Empty Raw Interrupt Status 10 11 I2C_MRIS_TXRIS Transmit Request Raw Interrupt Status 8 9 I2C0MSA I2C Master Slave Address 0x0 read-write n 0x0 0x0 I2C_MSA_RS Receive not send 0 1 I2C_MSA_SA I2C Slave Address 1 8 I2C0MTPR I2C Master Timer Period 0xC read-write n 0x0 0x0 I2C_MTPR_HS High-Speed Enable 7 8 I2C_MTPR_PULSEL Glitch Suppression Pulse Width 16 19 I2C_MTPR_PULSEL_BYPASS Bypass 0x0 I2C_MTPR_PULSEL_1 1 clock 0x1 I2C_MTPR_PULSEL_2 2 clocks 0x2 I2C_MTPR_PULSEL_3 3 clocks 0x3 I2C_MTPR_PULSEL_4 4 clocks 0x4 I2C_MTPR_PULSEL_8 8 clocks 0x5 I2C_MTPR_PULSEL_16 16 clocks 0x6 I2C_MTPR_PULSEL_31 31 clocks 0x7 I2C_MTPR_TPR Timer Period 0 7 I2C0PC I2C Peripheral Configuration 0xFC4 read-write n 0x0 0x0 I2C_PC_HS High-Speed Capable 0 1 I2C0PP I2C Peripheral Properties 0xFC0 read-write n 0x0 0x0 I2C_PP_HS High-Speed Capable 0 1 I2C0SACKCTL I2C Slave ACK Control 0x820 read-write n 0x0 0x0 I2C_SACKCTL_ACKOEN I2C Slave ACK Override Enable 0 1 I2C_SACKCTL_ACKOVAL I2C Slave ACK Override Value 1 2 I2C0SCSR I2C Slave Control/Status 0x804 read-write n 0x0 0x0 I2C_SCSR_ACTDMARX DMA RX Active Status 31 32 I2C_SCSR_ACTDMATX DMA TX Active Status 30 31 I2C_SCSR_FBR First Byte Received 2 3 I2C_SCSR_OAR2SEL OAR2 Address Matched 3 4 I2C_SCSR_QCMDRW Quick Command Read / Write 5 6 I2C_SCSR_QCMDST Quick Command Status 4 5 I2C_SCSR_RREQ Receive Request 0 1 I2C_SCSR_TXFIFO TX FIFO Enable 1 2 I2C0SDR I2C Slave Data 0x808 read-write n 0x0 0x0 I2C_SDR_DATA Data for Transfer 0 8 I2C0SICR I2C Slave Interrupt Clear 0x818 write-only n 0x0 0x0 I2C_SICR_DATAIC Data Interrupt Clear 0 1 write-only I2C_SICR_DMARXIC Receive DMA Interrupt Clear 3 4 write-only I2C_SICR_DMATXIC Transmit DMA Interrupt Clear 4 5 write-only I2C_SICR_RXFFIC Receive FIFO Full Interrupt Mask 8 9 write-only I2C_SICR_RXIC Receive Request Interrupt Mask 6 7 write-only I2C_SICR_STARTIC Start Condition Interrupt Clear 1 2 write-only I2C_SICR_STOPIC Stop Condition Interrupt Clear 2 3 write-only I2C_SICR_TXFEIC Transmit FIFO Empty Interrupt Mask 7 8 write-only I2C_SICR_TXIC Transmit Request Interrupt Mask 5 6 write-only I2C0SIMR I2C Slave Interrupt Mask 0x80C read-write n 0x0 0x0 I2C_SIMR_DATAIM Data Interrupt Mask 0 1 I2C_SIMR_DMARXIM Receive DMA Interrupt Mask 3 4 I2C_SIMR_DMATXIM Transmit DMA Interrupt Mask 4 5 I2C_SIMR_RXFFIM Receive FIFO Full Interrupt Mask 8 9 I2C_SIMR_RXIM Receive FIFO Request Interrupt Mask 6 7 I2C_SIMR_STARTIM Start Condition Interrupt Mask 1 2 I2C_SIMR_STOPIM Stop Condition Interrupt Mask 2 3 I2C_SIMR_TXFEIM Transmit FIFO Empty Interrupt Mask 7 8 I2C_SIMR_TXIM Transmit FIFO Request Interrupt Mask 5 6 I2C0SMIS I2C Slave Masked Interrupt Status 0x814 read-write n 0x0 0x0 I2C_SMIS_DATAMIS Data Masked Interrupt Status 0 1 I2C_SMIS_DMARXMIS Receive DMA Masked Interrupt Status 3 4 I2C_SMIS_DMATXMIS Transmit DMA Masked Interrupt Status 4 5 I2C_SMIS_RXFFMIS Receive FIFO Full Interrupt Mask 8 9 I2C_SMIS_RXMIS Receive FIFO Request Interrupt Mask 6 7 I2C_SMIS_STARTMIS Start Condition Masked Interrupt Status 1 2 I2C_SMIS_STOPMIS Stop Condition Masked Interrupt Status 2 3 I2C_SMIS_TXFEMIS Transmit FIFO Empty Interrupt Mask 7 8 I2C_SMIS_TXMIS Transmit FIFO Request Interrupt Mask 5 6 I2C0SOAR I2C Slave Own Address 0x800 read-write n 0x0 0x0 I2C_SOAR_OAR I2C Slave Own Address 0 7 I2C0SOAR2 I2C Slave Own Address 2 0x81C read-write n 0x0 0x0 I2C_SOAR2_OAR2 I2C Slave Own Address 2 0 7 I2C_SOAR2_OAR2EN I2C Slave Own Address 2 Enable 7 8 I2C0SRIS I2C Slave Raw Interrupt Status 0x810 read-write n 0x0 0x0 I2C_SRIS_DATARIS Data Raw Interrupt Status 0 1 I2C_SRIS_DMARXRIS Receive DMA Raw Interrupt Status 3 4 I2C_SRIS_DMATXRIS Transmit DMA Raw Interrupt Status 4 5 I2C_SRIS_RXFFRIS Receive FIFO Full Raw Interrupt Status 8 9 I2C_SRIS_RXRIS Receive FIFO Request Raw Interrupt Status 6 7 I2C_SRIS_STARTRIS Start Condition Raw Interrupt Status 1 2 I2C_SRIS_STOPRIS Stop Condition Raw Interrupt Status 2 3 I2C_SRIS_TXFERIS Transmit FIFO Empty Raw Interrupt Status 7 8 I2C_SRIS_TXRIS Transmit Request Raw Interrupt Status 5 6 MBCNT I2C Master Burst Count 0x34 -1 read-write n 0x0 0x0 I2C_MBCNT_CNTL I2C Master Burst Count 0 8 MBLEN I2C Master Burst Length 0x30 -1 read-write n 0x0 0x0 I2C_MBLEN_CNTL I2C Burst Length 0 8 MBMON I2C Master Bus Monitor 0x2C -1 read-write n 0x0 0x0 I2C_MBMON_SCL I2C SCL Status 0 1 I2C_MBMON_SDA I2C SDA Status 1 2 MCLKOCNT I2C Master Clock Low Timeout Count 0x24 -1 read-write n 0x0 0x0 I2C_MCLKOCNT_CNTL I2C Master Count 0 8 MCR I2C Master Configuration 0x20 -1 read-write n 0x0 0x0 I2C_MCR_LPBK I2C Loopback 0 1 I2C_MCR_MFE I2C Master Function Enable 4 5 I2C_MCR_SFE I2C Slave Function Enable 5 6 MCS I2C Master Control/Status 0x4 -1 read-write n 0x0 0x0 I2C_MCS_ACK Data Acknowledge Enable 3 4 I2C_MCS_ACTDMARX DMA RX Active Status 31 32 I2C_MCS_ACTDMATX DMA TX Active Status 30 31 I2C_MCS_ADRACK Acknowledge Address 2 3 I2C_MCS_ARBLST Arbitration Lost 4 5 I2C_MCS_BURST Burst Enable 6 7 I2C_MCS_BUSBSY Bus Busy 6 7 I2C_MCS_BUSY I2C Busy 0 1 I2C_MCS_CLKTO Clock Timeout Error 7 8 I2C_MCS_DATACK Acknowledge Data 3 4 I2C_MCS_ERROR Error 1 2 I2C_MCS_HS High-Speed Enable 4 5 I2C_MCS_IDLE I2C Idle 5 6 I2C_MCS_QCMD Quick Command 5 6 I2C_MCS_RUN I2C Master Enable 0 1 I2C_MCS_START Generate START 1 2 I2C_MCS_STOP Generate STOP 2 3 MDR I2C Master Data 0x8 -1 read-write n 0x0 0x0 I2C_MDR_DATA This byte contains the data transferred during a transaction 0 8 MICR I2C Master Interrupt Clear 0x1C -1 write-only n 0x0 0x0 I2C_MICR_ARBLOSTIC Arbitration Lost Interrupt Clear 7 8 write-only I2C_MICR_CLKIC Clock Timeout Interrupt Clear 1 2 write-only I2C_MICR_DMARXIC Receive DMA Interrupt Clear 2 3 write-only I2C_MICR_DMATXIC Transmit DMA Interrupt Clear 3 4 write-only I2C_MICR_IC Master Interrupt Clear 0 1 write-only I2C_MICR_NACKIC Address/Data NACK Interrupt Clear 4 5 write-only I2C_MICR_RXFFIC Receive FIFO Full Interrupt Clear 11 12 write-only I2C_MICR_RXIC Receive FIFO Request Interrupt Clear 9 10 write-only I2C_MICR_STARTIC START Detection Interrupt Clear 5 6 write-only I2C_MICR_STOPIC STOP Detection Interrupt Clear 6 7 write-only I2C_MICR_TXFEIC Transmit FIFO Empty Interrupt Clear 10 11 write-only I2C_MICR_TXIC Transmit FIFO Request Interrupt Clear 8 9 write-only MIMR I2C Master Interrupt Mask 0x10 -1 read-write n 0x0 0x0 I2C_MIMR_ARBLOSTIM Arbitration Lost Interrupt Mask 7 8 I2C_MIMR_CLKIM Clock Timeout Interrupt Mask 1 2 I2C_MIMR_DMARXIM Receive DMA Interrupt Mask 2 3 I2C_MIMR_DMATXIM Transmit DMA Interrupt Mask 3 4 I2C_MIMR_IM Master Interrupt Mask 0 1 I2C_MIMR_NACKIM Address/Data NACK Interrupt Mask 4 5 I2C_MIMR_RXFFIM Receive FIFO Full Interrupt Mask 11 12 I2C_MIMR_RXIM Receive FIFO Request Interrupt Mask 9 10 I2C_MIMR_STARTIM START Detection Interrupt Mask 5 6 I2C_MIMR_STOPIM STOP Detection Interrupt Mask 6 7 I2C_MIMR_TXFEIM Transmit FIFO Empty Interrupt Mask 10 11 I2C_MIMR_TXIM Transmit FIFO Request Interrupt Mask 8 9 MMIS I2C Master Masked Interrupt Status 0x18 -1 read-write n 0x0 0x0 I2C_MMIS_ARBLOSTMIS Arbitration Lost Interrupt Mask 7 8 I2C_MMIS_CLKMIS Clock Timeout Masked Interrupt Status 1 2 I2C_MMIS_DMARXMIS Receive DMA Interrupt Status 2 3 I2C_MMIS_DMATXMIS Transmit DMA Interrupt Status 3 4 I2C_MMIS_MIS Masked Interrupt Status 0 1 I2C_MMIS_NACKMIS Address/Data NACK Interrupt Mask 4 5 I2C_MMIS_RXFFMIS Receive FIFO Full Interrupt Mask 11 12 I2C_MMIS_RXMIS Receive FIFO Request Interrupt Mask 9 10 I2C_MMIS_STARTMIS START Detection Interrupt Mask 5 6 I2C_MMIS_STOPMIS STOP Detection Interrupt Mask 6 7 I2C_MMIS_TXFEMIS Transmit FIFO Empty Interrupt Mask 10 11 I2C_MMIS_TXMIS Transmit Request Interrupt Mask 8 9 MRIS I2C Master Raw Interrupt Status 0x14 -1 read-write n 0x0 0x0 I2C_MRIS_ARBLOSTRIS Arbitration Lost Raw Interrupt Status 7 8 I2C_MRIS_CLKRIS Clock Timeout Raw Interrupt Status 1 2 I2C_MRIS_DMARXRIS Receive DMA Raw Interrupt Status 2 3 I2C_MRIS_DMATXRIS Transmit DMA Raw Interrupt Status 3 4 I2C_MRIS_NACKRIS Address/Data NACK Raw Interrupt Status 4 5 I2C_MRIS_RIS Master Raw Interrupt Status 0 1 I2C_MRIS_RXFFRIS Receive FIFO Full Raw Interrupt Status 11 12 I2C_MRIS_RXRIS Receive FIFO Request Raw Interrupt Status 9 10 I2C_MRIS_STARTRIS START Detection Raw Interrupt Status 5 6 I2C_MRIS_STOPRIS STOP Detection Raw Interrupt Status 6 7 I2C_MRIS_TXFERIS Transmit FIFO Empty Raw Interrupt Status 10 11 I2C_MRIS_TXRIS Transmit Request Raw Interrupt Status 8 9 MSA I2C Master Slave Address 0x0 -1 read-write n 0x0 0x0 I2C_MSA_RS Receive not send 0 1 I2C_MSA_SA I2C Slave Address 1 8 MTPR I2C Master Timer Period 0xC -1 read-write n 0x0 0x0 I2C_MTPR_HS High-Speed Enable 7 8 I2C_MTPR_PULSEL Glitch Suppression Pulse Width 16 19 I2C_MTPR_PULSEL_BYPASS Bypass 0x0 I2C_MTPR_PULSEL_1 1 clock 0x1 I2C_MTPR_PULSEL_2 2 clocks 0x2 I2C_MTPR_PULSEL_3 3 clocks 0x3 I2C_MTPR_PULSEL_4 4 clocks 0x4 I2C_MTPR_PULSEL_8 8 clocks 0x5 I2C_MTPR_PULSEL_16 16 clocks 0x6 I2C_MTPR_PULSEL_31 31 clocks 0x7 I2C_MTPR_TPR Timer Period 0 7 PC I2C Peripheral Configuration 0xFC4 -1 read-write n 0x0 0x0 I2C_PC_HS High-Speed Capable 0 1 PP I2C Peripheral Properties 0xFC0 -1 read-write n 0x0 0x0 I2C_PP_HS High-Speed Capable 0 1 SACKCTL I2C Slave ACK Control 0x820 -1 read-write n 0x0 0x0 I2C_SACKCTL_ACKOEN I2C Slave ACK Override Enable 0 1 I2C_SACKCTL_ACKOVAL I2C Slave ACK Override Value 1 2 SCSR I2C Slave Control/Status 0x804 -1 read-write n 0x0 0x0 I2C_SCSR_ACTDMARX DMA RX Active Status 31 32 I2C_SCSR_ACTDMATX DMA TX Active Status 30 31 I2C_SCSR_DA Device Active 0 1 I2C_SCSR_FBR First Byte Received 2 3 I2C_SCSR_OAR2SEL OAR2 Address Matched 3 4 I2C_SCSR_QCMDRW Quick Command Read / Write 5 6 I2C_SCSR_QCMDST Quick Command Status 4 5 I2C_SCSR_RREQ Receive Request 0 1 I2C_SCSR_RXFIFO RX FIFO Enable 2 3 I2C_SCSR_TREQ Transmit Request 1 2 I2C_SCSR_TXFIFO TX FIFO Enable 1 2 SDR I2C Slave Data 0x808 -1 read-write n 0x0 0x0 I2C_SDR_DATA Data for Transfer 0 8 SICR I2C Slave Interrupt Clear 0x818 -1 write-only n 0x0 0x0 I2C_SICR_DATAIC Data Interrupt Clear 0 1 write-only I2C_SICR_DMARXIC Receive DMA Interrupt Clear 3 4 write-only I2C_SICR_DMATXIC Transmit DMA Interrupt Clear 4 5 write-only I2C_SICR_RXFFIC Receive FIFO Full Interrupt Mask 8 9 write-only I2C_SICR_RXIC Receive Request Interrupt Mask 6 7 write-only I2C_SICR_STARTIC Start Condition Interrupt Clear 1 2 write-only I2C_SICR_STOPIC Stop Condition Interrupt Clear 2 3 write-only I2C_SICR_TXFEIC Transmit FIFO Empty Interrupt Mask 7 8 write-only I2C_SICR_TXIC Transmit Request Interrupt Mask 5 6 write-only SIMR I2C Slave Interrupt Mask 0x80C -1 read-write n 0x0 0x0 I2C_SIMR_DATAIM Data Interrupt Mask 0 1 I2C_SIMR_DMARXIM Receive DMA Interrupt Mask 3 4 I2C_SIMR_DMATXIM Transmit DMA Interrupt Mask 4 5 I2C_SIMR_RXFFIM Receive FIFO Full Interrupt Mask 8 9 I2C_SIMR_RXIM Receive FIFO Request Interrupt Mask 6 7 I2C_SIMR_STARTIM Start Condition Interrupt Mask 1 2 I2C_SIMR_STOPIM Stop Condition Interrupt Mask 2 3 I2C_SIMR_TXFEIM Transmit FIFO Empty Interrupt Mask 7 8 I2C_SIMR_TXIM Transmit FIFO Request Interrupt Mask 5 6 SMIS I2C Slave Masked Interrupt Status 0x814 -1 read-write n 0x0 0x0 I2C_SMIS_DATAMIS Data Masked Interrupt Status 0 1 I2C_SMIS_DMARXMIS Receive DMA Masked Interrupt Status 3 4 I2C_SMIS_DMATXMIS Transmit DMA Masked Interrupt Status 4 5 I2C_SMIS_RXFFMIS Receive FIFO Full Interrupt Mask 8 9 I2C_SMIS_RXMIS Receive FIFO Request Interrupt Mask 6 7 I2C_SMIS_STARTMIS Start Condition Masked Interrupt Status 1 2 I2C_SMIS_STOPMIS Stop Condition Masked Interrupt Status 2 3 I2C_SMIS_TXFEMIS Transmit FIFO Empty Interrupt Mask 7 8 I2C_SMIS_TXMIS Transmit FIFO Request Interrupt Mask 5 6 SOAR I2C Slave Own Address 0x800 -1 read-write n 0x0 0x0 I2C_SOAR_OAR I2C Slave Own Address 0 7 SOAR2 I2C Slave Own Address 2 0x81C -1 read-write n 0x0 0x0 I2C_SOAR2_OAR2 I2C Slave Own Address 2 0 7 I2C_SOAR2_OAR2EN I2C Slave Own Address 2 Enable 7 8 SRIS I2C Slave Raw Interrupt Status 0x810 -1 read-write n 0x0 0x0 I2C_SRIS_DATARIS Data Raw Interrupt Status 0 1 I2C_SRIS_DMARXRIS Receive DMA Raw Interrupt Status 3 4 I2C_SRIS_DMATXRIS Transmit DMA Raw Interrupt Status 4 5 I2C_SRIS_RXFFRIS Receive FIFO Full Raw Interrupt Status 8 9 I2C_SRIS_RXRIS Receive FIFO Request Raw Interrupt Status 6 7 I2C_SRIS_STARTRIS Start Condition Raw Interrupt Status 1 2 I2C_SRIS_STOPRIS Stop Condition Raw Interrupt Status 2 3 I2C_SRIS_TXFERIS Transmit FIFO Empty Raw Interrupt Status 7 8 I2C_SRIS_TXRIS Transmit Request Raw Interrupt Status 5 6 I2C8 Register map for I2C0 peripheral I2C 0x0 0x0 0x1000 registers n I2C8 109 FIFOCTL I2C FIFO Control 0xF04 -1 read-write n 0x0 0x0 I2C_FIFOCTL_DMARXENA DMA RX Channel Enable 29 30 I2C_FIFOCTL_DMATXENA DMA TX Channel Enable 13 14 I2C_FIFOCTL_RXASGNMT RX Control Assignment 31 32 I2C_FIFOCTL_RXFLUSH RX FIFO Flush 30 31 I2C_FIFOCTL_RXTRIG RX FIFO Trigger 16 19 I2C_FIFOCTL_TXASGNMT TX Control Assignment 15 16 I2C_FIFOCTL_TXFLUSH TX FIFO Flush 14 15 I2C_FIFOCTL_TXTRIG TX FIFO Trigger 0 3 FIFODATA I2C FIFO Data 0xF00 -1 read-write n 0x0 0x0 I2C_FIFODATA_DATA I2C TX FIFO Write Data Byte 0 8 FIFOSTATUS I2C FIFO Status 0xF08 -1 read-write n 0x0 0x0 I2C_FIFOSTATUS_RXABVTRIG RX FIFO Above Trigger Level 18 19 I2C_FIFOSTATUS_RXFE RX FIFO Empty 16 17 I2C_FIFOSTATUS_RXFF RX FIFO Full 17 18 I2C_FIFOSTATUS_TXBLWTRIG TX FIFO Below Trigger Level 2 3 I2C_FIFOSTATUS_TXFE TX FIFO Empty 0 1 I2C_FIFOSTATUS_TXFF TX FIFO Full 1 2 I2C0FIFOCTL I2C FIFO Control 0xF04 read-write n 0x0 0x0 I2C_FIFOCTL_DMARXENA DMA RX Channel Enable 29 30 I2C_FIFOCTL_DMATXENA DMA TX Channel Enable 13 14 I2C_FIFOCTL_RXASGNMT RX Control Assignment 31 32 I2C_FIFOCTL_RXFLUSH RX FIFO Flush 30 31 I2C_FIFOCTL_RXTRIG RX FIFO Trigger 16 19 I2C_FIFOCTL_TXASGNMT TX Control Assignment 15 16 I2C_FIFOCTL_TXFLUSH TX FIFO Flush 14 15 I2C_FIFOCTL_TXTRIG TX FIFO Trigger 0 3 I2C0FIFODATA I2C FIFO Data 0xF00 read-write n 0x0 0x0 I2C_FIFODATA_DATA I2C TX FIFO Write Data Byte 0 8 I2C0FIFOSTATUS I2C FIFO Status 0xF08 read-write n 0x0 0x0 I2C_FIFOSTATUS_RXABVTRIG RX FIFO Above Trigger Level 18 19 I2C_FIFOSTATUS_RXFE RX FIFO Empty 16 17 I2C_FIFOSTATUS_RXFF RX FIFO Full 17 18 I2C_FIFOSTATUS_TXBLWTRIG TX FIFO Below Trigger Level 2 3 I2C_FIFOSTATUS_TXFE TX FIFO Empty 0 1 I2C_FIFOSTATUS_TXFF TX FIFO Full 1 2 I2C0MBCNT I2C Master Burst Count 0x34 read-write n 0x0 0x0 I2C_MBCNT_CNTL I2C Master Burst Count 0 8 I2C0MBLEN I2C Master Burst Length 0x30 read-write n 0x0 0x0 I2C_MBLEN_CNTL I2C Burst Length 0 8 I2C0MBMON I2C Master Bus Monitor 0x2C read-write n 0x0 0x0 I2C_MBMON_SCL I2C SCL Status 0 1 I2C_MBMON_SDA I2C SDA Status 1 2 I2C0MCLKOCNT I2C Master Clock Low Timeout Count 0x24 read-write n 0x0 0x0 I2C_MCLKOCNT_CNTL I2C Master Count 0 8 I2C0MCR I2C Master Configuration 0x20 read-write n 0x0 0x0 I2C_MCR_LPBK I2C Loopback 0 1 I2C_MCR_MFE I2C Master Function Enable 4 5 I2C_MCR_SFE I2C Slave Function Enable 5 6 I2C0MCS I2C Master Control/Status 0x4 read-write n 0x0 0x0 I2C_MCS_ACK Data Acknowledge Enable 3 4 I2C_MCS_ACTDMARX DMA RX Active Status 31 32 I2C_MCS_ACTDMATX DMA TX Active Status 30 31 I2C_MCS_ADRACK Acknowledge Address 2 3 I2C_MCS_ARBLST Arbitration Lost 4 5 I2C_MCS_BURST Burst Enable 6 7 I2C_MCS_CLKTO Clock Timeout Error 7 8 I2C_MCS_IDLE I2C Idle 5 6 I2C_MCS_RUN I2C Master Enable 0 1 I2C_MCS_START Generate START 1 2 I2C0MDR I2C Master Data 0x8 read-write n 0x0 0x0 I2C_MDR_DATA This byte contains the data transferred during a transaction 0 8 I2C0MICR I2C Master Interrupt Clear 0x1C write-only n 0x0 0x0 I2C_MICR_ARBLOSTIC Arbitration Lost Interrupt Clear 7 8 write-only I2C_MICR_CLKIC Clock Timeout Interrupt Clear 1 2 write-only I2C_MICR_DMARXIC Receive DMA Interrupt Clear 2 3 write-only I2C_MICR_DMATXIC Transmit DMA Interrupt Clear 3 4 write-only I2C_MICR_IC Master Interrupt Clear 0 1 write-only I2C_MICR_NACKIC Address/Data NACK Interrupt Clear 4 5 write-only I2C_MICR_RXFFIC Receive FIFO Full Interrupt Clear 11 12 write-only I2C_MICR_RXIC Receive FIFO Request Interrupt Clear 9 10 write-only I2C_MICR_STARTIC START Detection Interrupt Clear 5 6 write-only I2C_MICR_STOPIC STOP Detection Interrupt Clear 6 7 write-only I2C_MICR_TXFEIC Transmit FIFO Empty Interrupt Clear 10 11 write-only I2C_MICR_TXIC Transmit FIFO Request Interrupt Clear 8 9 write-only I2C0MIMR I2C Master Interrupt Mask 0x10 read-write n 0x0 0x0 I2C_MIMR_ARBLOSTIM Arbitration Lost Interrupt Mask 7 8 I2C_MIMR_CLKIM Clock Timeout Interrupt Mask 1 2 I2C_MIMR_DMARXIM Receive DMA Interrupt Mask 2 3 I2C_MIMR_DMATXIM Transmit DMA Interrupt Mask 3 4 I2C_MIMR_IM Master Interrupt Mask 0 1 I2C_MIMR_NACKIM Address/Data NACK Interrupt Mask 4 5 I2C_MIMR_RXFFIM Receive FIFO Full Interrupt Mask 11 12 I2C_MIMR_RXIM Receive FIFO Request Interrupt Mask 9 10 I2C_MIMR_STARTIM START Detection Interrupt Mask 5 6 I2C_MIMR_STOPIM STOP Detection Interrupt Mask 6 7 I2C_MIMR_TXFEIM Transmit FIFO Empty Interrupt Mask 10 11 I2C_MIMR_TXIM Transmit FIFO Request Interrupt Mask 8 9 I2C0MMIS I2C Master Masked Interrupt Status 0x18 read-write n 0x0 0x0 I2C_MMIS_ARBLOSTMIS Arbitration Lost Interrupt Mask 7 8 I2C_MMIS_CLKMIS Clock Timeout Masked Interrupt Status 1 2 I2C_MMIS_DMARXMIS Receive DMA Interrupt Status 2 3 I2C_MMIS_DMATXMIS Transmit DMA Interrupt Status 3 4 I2C_MMIS_MIS Masked Interrupt Status 0 1 I2C_MMIS_NACKMIS Address/Data NACK Interrupt Mask 4 5 I2C_MMIS_RXFFMIS Receive FIFO Full Interrupt Mask 11 12 I2C_MMIS_RXMIS Receive FIFO Request Interrupt Mask 9 10 I2C_MMIS_STARTMIS START Detection Interrupt Mask 5 6 I2C_MMIS_STOPMIS STOP Detection Interrupt Mask 6 7 I2C_MMIS_TXFEMIS Transmit FIFO Empty Interrupt Mask 10 11 I2C_MMIS_TXMIS Transmit Request Interrupt Mask 8 9 I2C0MRIS I2C Master Raw Interrupt Status 0x14 read-write n 0x0 0x0 I2C_MRIS_ARBLOSTRIS Arbitration Lost Raw Interrupt Status 7 8 I2C_MRIS_CLKRIS Clock Timeout Raw Interrupt Status 1 2 I2C_MRIS_DMARXRIS Receive DMA Raw Interrupt Status 2 3 I2C_MRIS_DMATXRIS Transmit DMA Raw Interrupt Status 3 4 I2C_MRIS_NACKRIS Address/Data NACK Raw Interrupt Status 4 5 I2C_MRIS_RIS Master Raw Interrupt Status 0 1 I2C_MRIS_RXFFRIS Receive FIFO Full Raw Interrupt Status 11 12 I2C_MRIS_RXRIS Receive FIFO Request Raw Interrupt Status 9 10 I2C_MRIS_STARTRIS START Detection Raw Interrupt Status 5 6 I2C_MRIS_STOPRIS STOP Detection Raw Interrupt Status 6 7 I2C_MRIS_TXFERIS Transmit FIFO Empty Raw Interrupt Status 10 11 I2C_MRIS_TXRIS Transmit Request Raw Interrupt Status 8 9 I2C0MSA I2C Master Slave Address 0x0 read-write n 0x0 0x0 I2C_MSA_RS Receive not send 0 1 I2C_MSA_SA I2C Slave Address 1 8 I2C0MTPR I2C Master Timer Period 0xC read-write n 0x0 0x0 I2C_MTPR_HS High-Speed Enable 7 8 I2C_MTPR_PULSEL Glitch Suppression Pulse Width 16 19 I2C_MTPR_PULSEL_BYPASS Bypass 0x0 I2C_MTPR_PULSEL_1 1 clock 0x1 I2C_MTPR_PULSEL_2 2 clocks 0x2 I2C_MTPR_PULSEL_3 3 clocks 0x3 I2C_MTPR_PULSEL_4 4 clocks 0x4 I2C_MTPR_PULSEL_8 8 clocks 0x5 I2C_MTPR_PULSEL_16 16 clocks 0x6 I2C_MTPR_PULSEL_31 31 clocks 0x7 I2C_MTPR_TPR Timer Period 0 7 I2C0PC I2C Peripheral Configuration 0xFC4 read-write n 0x0 0x0 I2C_PC_HS High-Speed Capable 0 1 I2C0PP I2C Peripheral Properties 0xFC0 read-write n 0x0 0x0 I2C_PP_HS High-Speed Capable 0 1 I2C0SACKCTL I2C Slave ACK Control 0x820 read-write n 0x0 0x0 I2C_SACKCTL_ACKOEN I2C Slave ACK Override Enable 0 1 I2C_SACKCTL_ACKOVAL I2C Slave ACK Override Value 1 2 I2C0SCSR I2C Slave Control/Status 0x804 read-write n 0x0 0x0 I2C_SCSR_ACTDMARX DMA RX Active Status 31 32 I2C_SCSR_ACTDMATX DMA TX Active Status 30 31 I2C_SCSR_FBR First Byte Received 2 3 I2C_SCSR_OAR2SEL OAR2 Address Matched 3 4 I2C_SCSR_QCMDRW Quick Command Read / Write 5 6 I2C_SCSR_QCMDST Quick Command Status 4 5 I2C_SCSR_RREQ Receive Request 0 1 I2C_SCSR_TXFIFO TX FIFO Enable 1 2 I2C0SDR I2C Slave Data 0x808 read-write n 0x0 0x0 I2C_SDR_DATA Data for Transfer 0 8 I2C0SICR I2C Slave Interrupt Clear 0x818 write-only n 0x0 0x0 I2C_SICR_DATAIC Data Interrupt Clear 0 1 write-only I2C_SICR_DMARXIC Receive DMA Interrupt Clear 3 4 write-only I2C_SICR_DMATXIC Transmit DMA Interrupt Clear 4 5 write-only I2C_SICR_RXFFIC Receive FIFO Full Interrupt Mask 8 9 write-only I2C_SICR_RXIC Receive Request Interrupt Mask 6 7 write-only I2C_SICR_STARTIC Start Condition Interrupt Clear 1 2 write-only I2C_SICR_STOPIC Stop Condition Interrupt Clear 2 3 write-only I2C_SICR_TXFEIC Transmit FIFO Empty Interrupt Mask 7 8 write-only I2C_SICR_TXIC Transmit Request Interrupt Mask 5 6 write-only I2C0SIMR I2C Slave Interrupt Mask 0x80C read-write n 0x0 0x0 I2C_SIMR_DATAIM Data Interrupt Mask 0 1 I2C_SIMR_DMARXIM Receive DMA Interrupt Mask 3 4 I2C_SIMR_DMATXIM Transmit DMA Interrupt Mask 4 5 I2C_SIMR_RXFFIM Receive FIFO Full Interrupt Mask 8 9 I2C_SIMR_RXIM Receive FIFO Request Interrupt Mask 6 7 I2C_SIMR_STARTIM Start Condition Interrupt Mask 1 2 I2C_SIMR_STOPIM Stop Condition Interrupt Mask 2 3 I2C_SIMR_TXFEIM Transmit FIFO Empty Interrupt Mask 7 8 I2C_SIMR_TXIM Transmit FIFO Request Interrupt Mask 5 6 I2C0SMIS I2C Slave Masked Interrupt Status 0x814 read-write n 0x0 0x0 I2C_SMIS_DATAMIS Data Masked Interrupt Status 0 1 I2C_SMIS_DMARXMIS Receive DMA Masked Interrupt Status 3 4 I2C_SMIS_DMATXMIS Transmit DMA Masked Interrupt Status 4 5 I2C_SMIS_RXFFMIS Receive FIFO Full Interrupt Mask 8 9 I2C_SMIS_RXMIS Receive FIFO Request Interrupt Mask 6 7 I2C_SMIS_STARTMIS Start Condition Masked Interrupt Status 1 2 I2C_SMIS_STOPMIS Stop Condition Masked Interrupt Status 2 3 I2C_SMIS_TXFEMIS Transmit FIFO Empty Interrupt Mask 7 8 I2C_SMIS_TXMIS Transmit FIFO Request Interrupt Mask 5 6 I2C0SOAR I2C Slave Own Address 0x800 read-write n 0x0 0x0 I2C_SOAR_OAR I2C Slave Own Address 0 7 I2C0SOAR2 I2C Slave Own Address 2 0x81C read-write n 0x0 0x0 I2C_SOAR2_OAR2 I2C Slave Own Address 2 0 7 I2C_SOAR2_OAR2EN I2C Slave Own Address 2 Enable 7 8 I2C0SRIS I2C Slave Raw Interrupt Status 0x810 read-write n 0x0 0x0 I2C_SRIS_DATARIS Data Raw Interrupt Status 0 1 I2C_SRIS_DMARXRIS Receive DMA Raw Interrupt Status 3 4 I2C_SRIS_DMATXRIS Transmit DMA Raw Interrupt Status 4 5 I2C_SRIS_RXFFRIS Receive FIFO Full Raw Interrupt Status 8 9 I2C_SRIS_RXRIS Receive FIFO Request Raw Interrupt Status 6 7 I2C_SRIS_STARTRIS Start Condition Raw Interrupt Status 1 2 I2C_SRIS_STOPRIS Stop Condition Raw Interrupt Status 2 3 I2C_SRIS_TXFERIS Transmit FIFO Empty Raw Interrupt Status 7 8 I2C_SRIS_TXRIS Transmit Request Raw Interrupt Status 5 6 MBCNT I2C Master Burst Count 0x34 -1 read-write n 0x0 0x0 I2C_MBCNT_CNTL I2C Master Burst Count 0 8 MBLEN I2C Master Burst Length 0x30 -1 read-write n 0x0 0x0 I2C_MBLEN_CNTL I2C Burst Length 0 8 MBMON I2C Master Bus Monitor 0x2C -1 read-write n 0x0 0x0 I2C_MBMON_SCL I2C SCL Status 0 1 I2C_MBMON_SDA I2C SDA Status 1 2 MCLKOCNT I2C Master Clock Low Timeout Count 0x24 -1 read-write n 0x0 0x0 I2C_MCLKOCNT_CNTL I2C Master Count 0 8 MCR I2C Master Configuration 0x20 -1 read-write n 0x0 0x0 I2C_MCR_LPBK I2C Loopback 0 1 I2C_MCR_MFE I2C Master Function Enable 4 5 I2C_MCR_SFE I2C Slave Function Enable 5 6 MCS I2C Master Control/Status 0x4 -1 read-write n 0x0 0x0 I2C_MCS_ACK Data Acknowledge Enable 3 4 I2C_MCS_ACTDMARX DMA RX Active Status 31 32 I2C_MCS_ACTDMATX DMA TX Active Status 30 31 I2C_MCS_ADRACK Acknowledge Address 2 3 I2C_MCS_ARBLST Arbitration Lost 4 5 I2C_MCS_BURST Burst Enable 6 7 I2C_MCS_BUSBSY Bus Busy 6 7 I2C_MCS_BUSY I2C Busy 0 1 I2C_MCS_CLKTO Clock Timeout Error 7 8 I2C_MCS_DATACK Acknowledge Data 3 4 I2C_MCS_ERROR Error 1 2 I2C_MCS_HS High-Speed Enable 4 5 I2C_MCS_IDLE I2C Idle 5 6 I2C_MCS_QCMD Quick Command 5 6 I2C_MCS_RUN I2C Master Enable 0 1 I2C_MCS_START Generate START 1 2 I2C_MCS_STOP Generate STOP 2 3 MDR I2C Master Data 0x8 -1 read-write n 0x0 0x0 I2C_MDR_DATA This byte contains the data transferred during a transaction 0 8 MICR I2C Master Interrupt Clear 0x1C -1 write-only n 0x0 0x0 I2C_MICR_ARBLOSTIC Arbitration Lost Interrupt Clear 7 8 write-only I2C_MICR_CLKIC Clock Timeout Interrupt Clear 1 2 write-only I2C_MICR_DMARXIC Receive DMA Interrupt Clear 2 3 write-only I2C_MICR_DMATXIC Transmit DMA Interrupt Clear 3 4 write-only I2C_MICR_IC Master Interrupt Clear 0 1 write-only I2C_MICR_NACKIC Address/Data NACK Interrupt Clear 4 5 write-only I2C_MICR_RXFFIC Receive FIFO Full Interrupt Clear 11 12 write-only I2C_MICR_RXIC Receive FIFO Request Interrupt Clear 9 10 write-only I2C_MICR_STARTIC START Detection Interrupt Clear 5 6 write-only I2C_MICR_STOPIC STOP Detection Interrupt Clear 6 7 write-only I2C_MICR_TXFEIC Transmit FIFO Empty Interrupt Clear 10 11 write-only I2C_MICR_TXIC Transmit FIFO Request Interrupt Clear 8 9 write-only MIMR I2C Master Interrupt Mask 0x10 -1 read-write n 0x0 0x0 I2C_MIMR_ARBLOSTIM Arbitration Lost Interrupt Mask 7 8 I2C_MIMR_CLKIM Clock Timeout Interrupt Mask 1 2 I2C_MIMR_DMARXIM Receive DMA Interrupt Mask 2 3 I2C_MIMR_DMATXIM Transmit DMA Interrupt Mask 3 4 I2C_MIMR_IM Master Interrupt Mask 0 1 I2C_MIMR_NACKIM Address/Data NACK Interrupt Mask 4 5 I2C_MIMR_RXFFIM Receive FIFO Full Interrupt Mask 11 12 I2C_MIMR_RXIM Receive FIFO Request Interrupt Mask 9 10 I2C_MIMR_STARTIM START Detection Interrupt Mask 5 6 I2C_MIMR_STOPIM STOP Detection Interrupt Mask 6 7 I2C_MIMR_TXFEIM Transmit FIFO Empty Interrupt Mask 10 11 I2C_MIMR_TXIM Transmit FIFO Request Interrupt Mask 8 9 MMIS I2C Master Masked Interrupt Status 0x18 -1 read-write n 0x0 0x0 I2C_MMIS_ARBLOSTMIS Arbitration Lost Interrupt Mask 7 8 I2C_MMIS_CLKMIS Clock Timeout Masked Interrupt Status 1 2 I2C_MMIS_DMARXMIS Receive DMA Interrupt Status 2 3 I2C_MMIS_DMATXMIS Transmit DMA Interrupt Status 3 4 I2C_MMIS_MIS Masked Interrupt Status 0 1 I2C_MMIS_NACKMIS Address/Data NACK Interrupt Mask 4 5 I2C_MMIS_RXFFMIS Receive FIFO Full Interrupt Mask 11 12 I2C_MMIS_RXMIS Receive FIFO Request Interrupt Mask 9 10 I2C_MMIS_STARTMIS START Detection Interrupt Mask 5 6 I2C_MMIS_STOPMIS STOP Detection Interrupt Mask 6 7 I2C_MMIS_TXFEMIS Transmit FIFO Empty Interrupt Mask 10 11 I2C_MMIS_TXMIS Transmit Request Interrupt Mask 8 9 MRIS I2C Master Raw Interrupt Status 0x14 -1 read-write n 0x0 0x0 I2C_MRIS_ARBLOSTRIS Arbitration Lost Raw Interrupt Status 7 8 I2C_MRIS_CLKRIS Clock Timeout Raw Interrupt Status 1 2 I2C_MRIS_DMARXRIS Receive DMA Raw Interrupt Status 2 3 I2C_MRIS_DMATXRIS Transmit DMA Raw Interrupt Status 3 4 I2C_MRIS_NACKRIS Address/Data NACK Raw Interrupt Status 4 5 I2C_MRIS_RIS Master Raw Interrupt Status 0 1 I2C_MRIS_RXFFRIS Receive FIFO Full Raw Interrupt Status 11 12 I2C_MRIS_RXRIS Receive FIFO Request Raw Interrupt Status 9 10 I2C_MRIS_STARTRIS START Detection Raw Interrupt Status 5 6 I2C_MRIS_STOPRIS STOP Detection Raw Interrupt Status 6 7 I2C_MRIS_TXFERIS Transmit FIFO Empty Raw Interrupt Status 10 11 I2C_MRIS_TXRIS Transmit Request Raw Interrupt Status 8 9 MSA I2C Master Slave Address 0x0 -1 read-write n 0x0 0x0 I2C_MSA_RS Receive not send 0 1 I2C_MSA_SA I2C Slave Address 1 8 MTPR I2C Master Timer Period 0xC -1 read-write n 0x0 0x0 I2C_MTPR_HS High-Speed Enable 7 8 I2C_MTPR_PULSEL Glitch Suppression Pulse Width 16 19 I2C_MTPR_PULSEL_BYPASS Bypass 0x0 I2C_MTPR_PULSEL_1 1 clock 0x1 I2C_MTPR_PULSEL_2 2 clocks 0x2 I2C_MTPR_PULSEL_3 3 clocks 0x3 I2C_MTPR_PULSEL_4 4 clocks 0x4 I2C_MTPR_PULSEL_8 8 clocks 0x5 I2C_MTPR_PULSEL_16 16 clocks 0x6 I2C_MTPR_PULSEL_31 31 clocks 0x7 I2C_MTPR_TPR Timer Period 0 7 PC I2C Peripheral Configuration 0xFC4 -1 read-write n 0x0 0x0 I2C_PC_HS High-Speed Capable 0 1 PP I2C Peripheral Properties 0xFC0 -1 read-write n 0x0 0x0 I2C_PP_HS High-Speed Capable 0 1 SACKCTL I2C Slave ACK Control 0x820 -1 read-write n 0x0 0x0 I2C_SACKCTL_ACKOEN I2C Slave ACK Override Enable 0 1 I2C_SACKCTL_ACKOVAL I2C Slave ACK Override Value 1 2 SCSR I2C Slave Control/Status 0x804 -1 read-write n 0x0 0x0 I2C_SCSR_ACTDMARX DMA RX Active Status 31 32 I2C_SCSR_ACTDMATX DMA TX Active Status 30 31 I2C_SCSR_DA Device Active 0 1 I2C_SCSR_FBR First Byte Received 2 3 I2C_SCSR_OAR2SEL OAR2 Address Matched 3 4 I2C_SCSR_QCMDRW Quick Command Read / Write 5 6 I2C_SCSR_QCMDST Quick Command Status 4 5 I2C_SCSR_RREQ Receive Request 0 1 I2C_SCSR_RXFIFO RX FIFO Enable 2 3 I2C_SCSR_TREQ Transmit Request 1 2 I2C_SCSR_TXFIFO TX FIFO Enable 1 2 SDR I2C Slave Data 0x808 -1 read-write n 0x0 0x0 I2C_SDR_DATA Data for Transfer 0 8 SICR I2C Slave Interrupt Clear 0x818 -1 write-only n 0x0 0x0 I2C_SICR_DATAIC Data Interrupt Clear 0 1 write-only I2C_SICR_DMARXIC Receive DMA Interrupt Clear 3 4 write-only I2C_SICR_DMATXIC Transmit DMA Interrupt Clear 4 5 write-only I2C_SICR_RXFFIC Receive FIFO Full Interrupt Mask 8 9 write-only I2C_SICR_RXIC Receive Request Interrupt Mask 6 7 write-only I2C_SICR_STARTIC Start Condition Interrupt Clear 1 2 write-only I2C_SICR_STOPIC Stop Condition Interrupt Clear 2 3 write-only I2C_SICR_TXFEIC Transmit FIFO Empty Interrupt Mask 7 8 write-only I2C_SICR_TXIC Transmit Request Interrupt Mask 5 6 write-only SIMR I2C Slave Interrupt Mask 0x80C -1 read-write n 0x0 0x0 I2C_SIMR_DATAIM Data Interrupt Mask 0 1 I2C_SIMR_DMARXIM Receive DMA Interrupt Mask 3 4 I2C_SIMR_DMATXIM Transmit DMA Interrupt Mask 4 5 I2C_SIMR_RXFFIM Receive FIFO Full Interrupt Mask 8 9 I2C_SIMR_RXIM Receive FIFO Request Interrupt Mask 6 7 I2C_SIMR_STARTIM Start Condition Interrupt Mask 1 2 I2C_SIMR_STOPIM Stop Condition Interrupt Mask 2 3 I2C_SIMR_TXFEIM Transmit FIFO Empty Interrupt Mask 7 8 I2C_SIMR_TXIM Transmit FIFO Request Interrupt Mask 5 6 SMIS I2C Slave Masked Interrupt Status 0x814 -1 read-write n 0x0 0x0 I2C_SMIS_DATAMIS Data Masked Interrupt Status 0 1 I2C_SMIS_DMARXMIS Receive DMA Masked Interrupt Status 3 4 I2C_SMIS_DMATXMIS Transmit DMA Masked Interrupt Status 4 5 I2C_SMIS_RXFFMIS Receive FIFO Full Interrupt Mask 8 9 I2C_SMIS_RXMIS Receive FIFO Request Interrupt Mask 6 7 I2C_SMIS_STARTMIS Start Condition Masked Interrupt Status 1 2 I2C_SMIS_STOPMIS Stop Condition Masked Interrupt Status 2 3 I2C_SMIS_TXFEMIS Transmit FIFO Empty Interrupt Mask 7 8 I2C_SMIS_TXMIS Transmit FIFO Request Interrupt Mask 5 6 SOAR I2C Slave Own Address 0x800 -1 read-write n 0x0 0x0 I2C_SOAR_OAR I2C Slave Own Address 0 7 SOAR2 I2C Slave Own Address 2 0x81C -1 read-write n 0x0 0x0 I2C_SOAR2_OAR2 I2C Slave Own Address 2 0 7 I2C_SOAR2_OAR2EN I2C Slave Own Address 2 Enable 7 8 SRIS I2C Slave Raw Interrupt Status 0x810 -1 read-write n 0x0 0x0 I2C_SRIS_DATARIS Data Raw Interrupt Status 0 1 I2C_SRIS_DMARXRIS Receive DMA Raw Interrupt Status 3 4 I2C_SRIS_DMATXRIS Transmit DMA Raw Interrupt Status 4 5 I2C_SRIS_RXFFRIS Receive FIFO Full Raw Interrupt Status 8 9 I2C_SRIS_RXRIS Receive FIFO Request Raw Interrupt Status 6 7 I2C_SRIS_STARTRIS Start Condition Raw Interrupt Status 1 2 I2C_SRIS_STOPRIS Stop Condition Raw Interrupt Status 2 3 I2C_SRIS_TXFERIS Transmit FIFO Empty Raw Interrupt Status 7 8 I2C_SRIS_TXRIS Transmit Request Raw Interrupt Status 5 6 I2C9 Register map for I2C0 peripheral I2C 0x0 0x0 0x1000 registers n I2C9 110 FIFOCTL I2C FIFO Control 0xF04 -1 read-write n 0x0 0x0 I2C_FIFOCTL_DMARXENA DMA RX Channel Enable 29 30 I2C_FIFOCTL_DMATXENA DMA TX Channel Enable 13 14 I2C_FIFOCTL_RXASGNMT RX Control Assignment 31 32 I2C_FIFOCTL_RXFLUSH RX FIFO Flush 30 31 I2C_FIFOCTL_RXTRIG RX FIFO Trigger 16 19 I2C_FIFOCTL_TXASGNMT TX Control Assignment 15 16 I2C_FIFOCTL_TXFLUSH TX FIFO Flush 14 15 I2C_FIFOCTL_TXTRIG TX FIFO Trigger 0 3 FIFODATA I2C FIFO Data 0xF00 -1 read-write n 0x0 0x0 I2C_FIFODATA_DATA I2C TX FIFO Write Data Byte 0 8 FIFOSTATUS I2C FIFO Status 0xF08 -1 read-write n 0x0 0x0 I2C_FIFOSTATUS_RXABVTRIG RX FIFO Above Trigger Level 18 19 I2C_FIFOSTATUS_RXFE RX FIFO Empty 16 17 I2C_FIFOSTATUS_RXFF RX FIFO Full 17 18 I2C_FIFOSTATUS_TXBLWTRIG TX FIFO Below Trigger Level 2 3 I2C_FIFOSTATUS_TXFE TX FIFO Empty 0 1 I2C_FIFOSTATUS_TXFF TX FIFO Full 1 2 I2C0FIFOCTL I2C FIFO Control 0xF04 read-write n 0x0 0x0 I2C_FIFOCTL_DMARXENA DMA RX Channel Enable 29 30 I2C_FIFOCTL_DMATXENA DMA TX Channel Enable 13 14 I2C_FIFOCTL_RXASGNMT RX Control Assignment 31 32 I2C_FIFOCTL_RXFLUSH RX FIFO Flush 30 31 I2C_FIFOCTL_RXTRIG RX FIFO Trigger 16 19 I2C_FIFOCTL_TXASGNMT TX Control Assignment 15 16 I2C_FIFOCTL_TXFLUSH TX FIFO Flush 14 15 I2C_FIFOCTL_TXTRIG TX FIFO Trigger 0 3 I2C0FIFODATA I2C FIFO Data 0xF00 read-write n 0x0 0x0 I2C_FIFODATA_DATA I2C TX FIFO Write Data Byte 0 8 I2C0FIFOSTATUS I2C FIFO Status 0xF08 read-write n 0x0 0x0 I2C_FIFOSTATUS_RXABVTRIG RX FIFO Above Trigger Level 18 19 I2C_FIFOSTATUS_RXFE RX FIFO Empty 16 17 I2C_FIFOSTATUS_RXFF RX FIFO Full 17 18 I2C_FIFOSTATUS_TXBLWTRIG TX FIFO Below Trigger Level 2 3 I2C_FIFOSTATUS_TXFE TX FIFO Empty 0 1 I2C_FIFOSTATUS_TXFF TX FIFO Full 1 2 I2C0MBCNT I2C Master Burst Count 0x34 read-write n 0x0 0x0 I2C_MBCNT_CNTL I2C Master Burst Count 0 8 I2C0MBLEN I2C Master Burst Length 0x30 read-write n 0x0 0x0 I2C_MBLEN_CNTL I2C Burst Length 0 8 I2C0MBMON I2C Master Bus Monitor 0x2C read-write n 0x0 0x0 I2C_MBMON_SCL I2C SCL Status 0 1 I2C_MBMON_SDA I2C SDA Status 1 2 I2C0MCLKOCNT I2C Master Clock Low Timeout Count 0x24 read-write n 0x0 0x0 I2C_MCLKOCNT_CNTL I2C Master Count 0 8 I2C0MCR I2C Master Configuration 0x20 read-write n 0x0 0x0 I2C_MCR_LPBK I2C Loopback 0 1 I2C_MCR_MFE I2C Master Function Enable 4 5 I2C_MCR_SFE I2C Slave Function Enable 5 6 I2C0MCS I2C Master Control/Status 0x4 read-write n 0x0 0x0 I2C_MCS_ACK Data Acknowledge Enable 3 4 I2C_MCS_ACTDMARX DMA RX Active Status 31 32 I2C_MCS_ACTDMATX DMA TX Active Status 30 31 I2C_MCS_ADRACK Acknowledge Address 2 3 I2C_MCS_ARBLST Arbitration Lost 4 5 I2C_MCS_BURST Burst Enable 6 7 I2C_MCS_CLKTO Clock Timeout Error 7 8 I2C_MCS_IDLE I2C Idle 5 6 I2C_MCS_RUN I2C Master Enable 0 1 I2C_MCS_START Generate START 1 2 I2C0MDR I2C Master Data 0x8 read-write n 0x0 0x0 I2C_MDR_DATA This byte contains the data transferred during a transaction 0 8 I2C0MICR I2C Master Interrupt Clear 0x1C write-only n 0x0 0x0 I2C_MICR_ARBLOSTIC Arbitration Lost Interrupt Clear 7 8 write-only I2C_MICR_CLKIC Clock Timeout Interrupt Clear 1 2 write-only I2C_MICR_DMARXIC Receive DMA Interrupt Clear 2 3 write-only I2C_MICR_DMATXIC Transmit DMA Interrupt Clear 3 4 write-only I2C_MICR_IC Master Interrupt Clear 0 1 write-only I2C_MICR_NACKIC Address/Data NACK Interrupt Clear 4 5 write-only I2C_MICR_RXFFIC Receive FIFO Full Interrupt Clear 11 12 write-only I2C_MICR_RXIC Receive FIFO Request Interrupt Clear 9 10 write-only I2C_MICR_STARTIC START Detection Interrupt Clear 5 6 write-only I2C_MICR_STOPIC STOP Detection Interrupt Clear 6 7 write-only I2C_MICR_TXFEIC Transmit FIFO Empty Interrupt Clear 10 11 write-only I2C_MICR_TXIC Transmit FIFO Request Interrupt Clear 8 9 write-only I2C0MIMR I2C Master Interrupt Mask 0x10 read-write n 0x0 0x0 I2C_MIMR_ARBLOSTIM Arbitration Lost Interrupt Mask 7 8 I2C_MIMR_CLKIM Clock Timeout Interrupt Mask 1 2 I2C_MIMR_DMARXIM Receive DMA Interrupt Mask 2 3 I2C_MIMR_DMATXIM Transmit DMA Interrupt Mask 3 4 I2C_MIMR_IM Master Interrupt Mask 0 1 I2C_MIMR_NACKIM Address/Data NACK Interrupt Mask 4 5 I2C_MIMR_RXFFIM Receive FIFO Full Interrupt Mask 11 12 I2C_MIMR_RXIM Receive FIFO Request Interrupt Mask 9 10 I2C_MIMR_STARTIM START Detection Interrupt Mask 5 6 I2C_MIMR_STOPIM STOP Detection Interrupt Mask 6 7 I2C_MIMR_TXFEIM Transmit FIFO Empty Interrupt Mask 10 11 I2C_MIMR_TXIM Transmit FIFO Request Interrupt Mask 8 9 I2C0MMIS I2C Master Masked Interrupt Status 0x18 read-write n 0x0 0x0 I2C_MMIS_ARBLOSTMIS Arbitration Lost Interrupt Mask 7 8 I2C_MMIS_CLKMIS Clock Timeout Masked Interrupt Status 1 2 I2C_MMIS_DMARXMIS Receive DMA Interrupt Status 2 3 I2C_MMIS_DMATXMIS Transmit DMA Interrupt Status 3 4 I2C_MMIS_MIS Masked Interrupt Status 0 1 I2C_MMIS_NACKMIS Address/Data NACK Interrupt Mask 4 5 I2C_MMIS_RXFFMIS Receive FIFO Full Interrupt Mask 11 12 I2C_MMIS_RXMIS Receive FIFO Request Interrupt Mask 9 10 I2C_MMIS_STARTMIS START Detection Interrupt Mask 5 6 I2C_MMIS_STOPMIS STOP Detection Interrupt Mask 6 7 I2C_MMIS_TXFEMIS Transmit FIFO Empty Interrupt Mask 10 11 I2C_MMIS_TXMIS Transmit Request Interrupt Mask 8 9 I2C0MRIS I2C Master Raw Interrupt Status 0x14 read-write n 0x0 0x0 I2C_MRIS_ARBLOSTRIS Arbitration Lost Raw Interrupt Status 7 8 I2C_MRIS_CLKRIS Clock Timeout Raw Interrupt Status 1 2 I2C_MRIS_DMARXRIS Receive DMA Raw Interrupt Status 2 3 I2C_MRIS_DMATXRIS Transmit DMA Raw Interrupt Status 3 4 I2C_MRIS_NACKRIS Address/Data NACK Raw Interrupt Status 4 5 I2C_MRIS_RIS Master Raw Interrupt Status 0 1 I2C_MRIS_RXFFRIS Receive FIFO Full Raw Interrupt Status 11 12 I2C_MRIS_RXRIS Receive FIFO Request Raw Interrupt Status 9 10 I2C_MRIS_STARTRIS START Detection Raw Interrupt Status 5 6 I2C_MRIS_STOPRIS STOP Detection Raw Interrupt Status 6 7 I2C_MRIS_TXFERIS Transmit FIFO Empty Raw Interrupt Status 10 11 I2C_MRIS_TXRIS Transmit Request Raw Interrupt Status 8 9 I2C0MSA I2C Master Slave Address 0x0 read-write n 0x0 0x0 I2C_MSA_RS Receive not send 0 1 I2C_MSA_SA I2C Slave Address 1 8 I2C0MTPR I2C Master Timer Period 0xC read-write n 0x0 0x0 I2C_MTPR_HS High-Speed Enable 7 8 I2C_MTPR_PULSEL Glitch Suppression Pulse Width 16 19 I2C_MTPR_PULSEL_BYPASS Bypass 0x0 I2C_MTPR_PULSEL_1 1 clock 0x1 I2C_MTPR_PULSEL_2 2 clocks 0x2 I2C_MTPR_PULSEL_3 3 clocks 0x3 I2C_MTPR_PULSEL_4 4 clocks 0x4 I2C_MTPR_PULSEL_8 8 clocks 0x5 I2C_MTPR_PULSEL_16 16 clocks 0x6 I2C_MTPR_PULSEL_31 31 clocks 0x7 I2C_MTPR_TPR Timer Period 0 7 I2C0PC I2C Peripheral Configuration 0xFC4 read-write n 0x0 0x0 I2C_PC_HS High-Speed Capable 0 1 I2C0PP I2C Peripheral Properties 0xFC0 read-write n 0x0 0x0 I2C_PP_HS High-Speed Capable 0 1 I2C0SACKCTL I2C Slave ACK Control 0x820 read-write n 0x0 0x0 I2C_SACKCTL_ACKOEN I2C Slave ACK Override Enable 0 1 I2C_SACKCTL_ACKOVAL I2C Slave ACK Override Value 1 2 I2C0SCSR I2C Slave Control/Status 0x804 read-write n 0x0 0x0 I2C_SCSR_ACTDMARX DMA RX Active Status 31 32 I2C_SCSR_ACTDMATX DMA TX Active Status 30 31 I2C_SCSR_FBR First Byte Received 2 3 I2C_SCSR_OAR2SEL OAR2 Address Matched 3 4 I2C_SCSR_QCMDRW Quick Command Read / Write 5 6 I2C_SCSR_QCMDST Quick Command Status 4 5 I2C_SCSR_RREQ Receive Request 0 1 I2C_SCSR_TXFIFO TX FIFO Enable 1 2 I2C0SDR I2C Slave Data 0x808 read-write n 0x0 0x0 I2C_SDR_DATA Data for Transfer 0 8 I2C0SICR I2C Slave Interrupt Clear 0x818 write-only n 0x0 0x0 I2C_SICR_DATAIC Data Interrupt Clear 0 1 write-only I2C_SICR_DMARXIC Receive DMA Interrupt Clear 3 4 write-only I2C_SICR_DMATXIC Transmit DMA Interrupt Clear 4 5 write-only I2C_SICR_RXFFIC Receive FIFO Full Interrupt Mask 8 9 write-only I2C_SICR_RXIC Receive Request Interrupt Mask 6 7 write-only I2C_SICR_STARTIC Start Condition Interrupt Clear 1 2 write-only I2C_SICR_STOPIC Stop Condition Interrupt Clear 2 3 write-only I2C_SICR_TXFEIC Transmit FIFO Empty Interrupt Mask 7 8 write-only I2C_SICR_TXIC Transmit Request Interrupt Mask 5 6 write-only I2C0SIMR I2C Slave Interrupt Mask 0x80C read-write n 0x0 0x0 I2C_SIMR_DATAIM Data Interrupt Mask 0 1 I2C_SIMR_DMARXIM Receive DMA Interrupt Mask 3 4 I2C_SIMR_DMATXIM Transmit DMA Interrupt Mask 4 5 I2C_SIMR_RXFFIM Receive FIFO Full Interrupt Mask 8 9 I2C_SIMR_RXIM Receive FIFO Request Interrupt Mask 6 7 I2C_SIMR_STARTIM Start Condition Interrupt Mask 1 2 I2C_SIMR_STOPIM Stop Condition Interrupt Mask 2 3 I2C_SIMR_TXFEIM Transmit FIFO Empty Interrupt Mask 7 8 I2C_SIMR_TXIM Transmit FIFO Request Interrupt Mask 5 6 I2C0SMIS I2C Slave Masked Interrupt Status 0x814 read-write n 0x0 0x0 I2C_SMIS_DATAMIS Data Masked Interrupt Status 0 1 I2C_SMIS_DMARXMIS Receive DMA Masked Interrupt Status 3 4 I2C_SMIS_DMATXMIS Transmit DMA Masked Interrupt Status 4 5 I2C_SMIS_RXFFMIS Receive FIFO Full Interrupt Mask 8 9 I2C_SMIS_RXMIS Receive FIFO Request Interrupt Mask 6 7 I2C_SMIS_STARTMIS Start Condition Masked Interrupt Status 1 2 I2C_SMIS_STOPMIS Stop Condition Masked Interrupt Status 2 3 I2C_SMIS_TXFEMIS Transmit FIFO Empty Interrupt Mask 7 8 I2C_SMIS_TXMIS Transmit FIFO Request Interrupt Mask 5 6 I2C0SOAR I2C Slave Own Address 0x800 read-write n 0x0 0x0 I2C_SOAR_OAR I2C Slave Own Address 0 7 I2C0SOAR2 I2C Slave Own Address 2 0x81C read-write n 0x0 0x0 I2C_SOAR2_OAR2 I2C Slave Own Address 2 0 7 I2C_SOAR2_OAR2EN I2C Slave Own Address 2 Enable 7 8 I2C0SRIS I2C Slave Raw Interrupt Status 0x810 read-write n 0x0 0x0 I2C_SRIS_DATARIS Data Raw Interrupt Status 0 1 I2C_SRIS_DMARXRIS Receive DMA Raw Interrupt Status 3 4 I2C_SRIS_DMATXRIS Transmit DMA Raw Interrupt Status 4 5 I2C_SRIS_RXFFRIS Receive FIFO Full Raw Interrupt Status 8 9 I2C_SRIS_RXRIS Receive FIFO Request Raw Interrupt Status 6 7 I2C_SRIS_STARTRIS Start Condition Raw Interrupt Status 1 2 I2C_SRIS_STOPRIS Stop Condition Raw Interrupt Status 2 3 I2C_SRIS_TXFERIS Transmit FIFO Empty Raw Interrupt Status 7 8 I2C_SRIS_TXRIS Transmit Request Raw Interrupt Status 5 6 MBCNT I2C Master Burst Count 0x34 -1 read-write n 0x0 0x0 I2C_MBCNT_CNTL I2C Master Burst Count 0 8 MBLEN I2C Master Burst Length 0x30 -1 read-write n 0x0 0x0 I2C_MBLEN_CNTL I2C Burst Length 0 8 MBMON I2C Master Bus Monitor 0x2C -1 read-write n 0x0 0x0 I2C_MBMON_SCL I2C SCL Status 0 1 I2C_MBMON_SDA I2C SDA Status 1 2 MCLKOCNT I2C Master Clock Low Timeout Count 0x24 -1 read-write n 0x0 0x0 I2C_MCLKOCNT_CNTL I2C Master Count 0 8 MCR I2C Master Configuration 0x20 -1 read-write n 0x0 0x0 I2C_MCR_LPBK I2C Loopback 0 1 I2C_MCR_MFE I2C Master Function Enable 4 5 I2C_MCR_SFE I2C Slave Function Enable 5 6 MCS I2C Master Control/Status 0x4 -1 read-write n 0x0 0x0 I2C_MCS_ACK Data Acknowledge Enable 3 4 I2C_MCS_ACTDMARX DMA RX Active Status 31 32 I2C_MCS_ACTDMATX DMA TX Active Status 30 31 I2C_MCS_ADRACK Acknowledge Address 2 3 I2C_MCS_ARBLST Arbitration Lost 4 5 I2C_MCS_BURST Burst Enable 6 7 I2C_MCS_BUSBSY Bus Busy 6 7 I2C_MCS_BUSY I2C Busy 0 1 I2C_MCS_CLKTO Clock Timeout Error 7 8 I2C_MCS_DATACK Acknowledge Data 3 4 I2C_MCS_ERROR Error 1 2 I2C_MCS_HS High-Speed Enable 4 5 I2C_MCS_IDLE I2C Idle 5 6 I2C_MCS_QCMD Quick Command 5 6 I2C_MCS_RUN I2C Master Enable 0 1 I2C_MCS_START Generate START 1 2 I2C_MCS_STOP Generate STOP 2 3 MDR I2C Master Data 0x8 -1 read-write n 0x0 0x0 I2C_MDR_DATA This byte contains the data transferred during a transaction 0 8 MICR I2C Master Interrupt Clear 0x1C -1 write-only n 0x0 0x0 I2C_MICR_ARBLOSTIC Arbitration Lost Interrupt Clear 7 8 write-only I2C_MICR_CLKIC Clock Timeout Interrupt Clear 1 2 write-only I2C_MICR_DMARXIC Receive DMA Interrupt Clear 2 3 write-only I2C_MICR_DMATXIC Transmit DMA Interrupt Clear 3 4 write-only I2C_MICR_IC Master Interrupt Clear 0 1 write-only I2C_MICR_NACKIC Address/Data NACK Interrupt Clear 4 5 write-only I2C_MICR_RXFFIC Receive FIFO Full Interrupt Clear 11 12 write-only I2C_MICR_RXIC Receive FIFO Request Interrupt Clear 9 10 write-only I2C_MICR_STARTIC START Detection Interrupt Clear 5 6 write-only I2C_MICR_STOPIC STOP Detection Interrupt Clear 6 7 write-only I2C_MICR_TXFEIC Transmit FIFO Empty Interrupt Clear 10 11 write-only I2C_MICR_TXIC Transmit FIFO Request Interrupt Clear 8 9 write-only MIMR I2C Master Interrupt Mask 0x10 -1 read-write n 0x0 0x0 I2C_MIMR_ARBLOSTIM Arbitration Lost Interrupt Mask 7 8 I2C_MIMR_CLKIM Clock Timeout Interrupt Mask 1 2 I2C_MIMR_DMARXIM Receive DMA Interrupt Mask 2 3 I2C_MIMR_DMATXIM Transmit DMA Interrupt Mask 3 4 I2C_MIMR_IM Master Interrupt Mask 0 1 I2C_MIMR_NACKIM Address/Data NACK Interrupt Mask 4 5 I2C_MIMR_RXFFIM Receive FIFO Full Interrupt Mask 11 12 I2C_MIMR_RXIM Receive FIFO Request Interrupt Mask 9 10 I2C_MIMR_STARTIM START Detection Interrupt Mask 5 6 I2C_MIMR_STOPIM STOP Detection Interrupt Mask 6 7 I2C_MIMR_TXFEIM Transmit FIFO Empty Interrupt Mask 10 11 I2C_MIMR_TXIM Transmit FIFO Request Interrupt Mask 8 9 MMIS I2C Master Masked Interrupt Status 0x18 -1 read-write n 0x0 0x0 I2C_MMIS_ARBLOSTMIS Arbitration Lost Interrupt Mask 7 8 I2C_MMIS_CLKMIS Clock Timeout Masked Interrupt Status 1 2 I2C_MMIS_DMARXMIS Receive DMA Interrupt Status 2 3 I2C_MMIS_DMATXMIS Transmit DMA Interrupt Status 3 4 I2C_MMIS_MIS Masked Interrupt Status 0 1 I2C_MMIS_NACKMIS Address/Data NACK Interrupt Mask 4 5 I2C_MMIS_RXFFMIS Receive FIFO Full Interrupt Mask 11 12 I2C_MMIS_RXMIS Receive FIFO Request Interrupt Mask 9 10 I2C_MMIS_STARTMIS START Detection Interrupt Mask 5 6 I2C_MMIS_STOPMIS STOP Detection Interrupt Mask 6 7 I2C_MMIS_TXFEMIS Transmit FIFO Empty Interrupt Mask 10 11 I2C_MMIS_TXMIS Transmit Request Interrupt Mask 8 9 MRIS I2C Master Raw Interrupt Status 0x14 -1 read-write n 0x0 0x0 I2C_MRIS_ARBLOSTRIS Arbitration Lost Raw Interrupt Status 7 8 I2C_MRIS_CLKRIS Clock Timeout Raw Interrupt Status 1 2 I2C_MRIS_DMARXRIS Receive DMA Raw Interrupt Status 2 3 I2C_MRIS_DMATXRIS Transmit DMA Raw Interrupt Status 3 4 I2C_MRIS_NACKRIS Address/Data NACK Raw Interrupt Status 4 5 I2C_MRIS_RIS Master Raw Interrupt Status 0 1 I2C_MRIS_RXFFRIS Receive FIFO Full Raw Interrupt Status 11 12 I2C_MRIS_RXRIS Receive FIFO Request Raw Interrupt Status 9 10 I2C_MRIS_STARTRIS START Detection Raw Interrupt Status 5 6 I2C_MRIS_STOPRIS STOP Detection Raw Interrupt Status 6 7 I2C_MRIS_TXFERIS Transmit FIFO Empty Raw Interrupt Status 10 11 I2C_MRIS_TXRIS Transmit Request Raw Interrupt Status 8 9 MSA I2C Master Slave Address 0x0 -1 read-write n 0x0 0x0 I2C_MSA_RS Receive not send 0 1 I2C_MSA_SA I2C Slave Address 1 8 MTPR I2C Master Timer Period 0xC -1 read-write n 0x0 0x0 I2C_MTPR_HS High-Speed Enable 7 8 I2C_MTPR_PULSEL Glitch Suppression Pulse Width 16 19 I2C_MTPR_PULSEL_BYPASS Bypass 0x0 I2C_MTPR_PULSEL_1 1 clock 0x1 I2C_MTPR_PULSEL_2 2 clocks 0x2 I2C_MTPR_PULSEL_3 3 clocks 0x3 I2C_MTPR_PULSEL_4 4 clocks 0x4 I2C_MTPR_PULSEL_8 8 clocks 0x5 I2C_MTPR_PULSEL_16 16 clocks 0x6 I2C_MTPR_PULSEL_31 31 clocks 0x7 I2C_MTPR_TPR Timer Period 0 7 PC I2C Peripheral Configuration 0xFC4 -1 read-write n 0x0 0x0 I2C_PC_HS High-Speed Capable 0 1 PP I2C Peripheral Properties 0xFC0 -1 read-write n 0x0 0x0 I2C_PP_HS High-Speed Capable 0 1 SACKCTL I2C Slave ACK Control 0x820 -1 read-write n 0x0 0x0 I2C_SACKCTL_ACKOEN I2C Slave ACK Override Enable 0 1 I2C_SACKCTL_ACKOVAL I2C Slave ACK Override Value 1 2 SCSR I2C Slave Control/Status 0x804 -1 read-write n 0x0 0x0 I2C_SCSR_ACTDMARX DMA RX Active Status 31 32 I2C_SCSR_ACTDMATX DMA TX Active Status 30 31 I2C_SCSR_DA Device Active 0 1 I2C_SCSR_FBR First Byte Received 2 3 I2C_SCSR_OAR2SEL OAR2 Address Matched 3 4 I2C_SCSR_QCMDRW Quick Command Read / Write 5 6 I2C_SCSR_QCMDST Quick Command Status 4 5 I2C_SCSR_RREQ Receive Request 0 1 I2C_SCSR_RXFIFO RX FIFO Enable 2 3 I2C_SCSR_TREQ Transmit Request 1 2 I2C_SCSR_TXFIFO TX FIFO Enable 1 2 SDR I2C Slave Data 0x808 -1 read-write n 0x0 0x0 I2C_SDR_DATA Data for Transfer 0 8 SICR I2C Slave Interrupt Clear 0x818 -1 write-only n 0x0 0x0 I2C_SICR_DATAIC Data Interrupt Clear 0 1 write-only I2C_SICR_DMARXIC Receive DMA Interrupt Clear 3 4 write-only I2C_SICR_DMATXIC Transmit DMA Interrupt Clear 4 5 write-only I2C_SICR_RXFFIC Receive FIFO Full Interrupt Mask 8 9 write-only I2C_SICR_RXIC Receive Request Interrupt Mask 6 7 write-only I2C_SICR_STARTIC Start Condition Interrupt Clear 1 2 write-only I2C_SICR_STOPIC Stop Condition Interrupt Clear 2 3 write-only I2C_SICR_TXFEIC Transmit FIFO Empty Interrupt Mask 7 8 write-only I2C_SICR_TXIC Transmit Request Interrupt Mask 5 6 write-only SIMR I2C Slave Interrupt Mask 0x80C -1 read-write n 0x0 0x0 I2C_SIMR_DATAIM Data Interrupt Mask 0 1 I2C_SIMR_DMARXIM Receive DMA Interrupt Mask 3 4 I2C_SIMR_DMATXIM Transmit DMA Interrupt Mask 4 5 I2C_SIMR_RXFFIM Receive FIFO Full Interrupt Mask 8 9 I2C_SIMR_RXIM Receive FIFO Request Interrupt Mask 6 7 I2C_SIMR_STARTIM Start Condition Interrupt Mask 1 2 I2C_SIMR_STOPIM Stop Condition Interrupt Mask 2 3 I2C_SIMR_TXFEIM Transmit FIFO Empty Interrupt Mask 7 8 I2C_SIMR_TXIM Transmit FIFO Request Interrupt Mask 5 6 SMIS I2C Slave Masked Interrupt Status 0x814 -1 read-write n 0x0 0x0 I2C_SMIS_DATAMIS Data Masked Interrupt Status 0 1 I2C_SMIS_DMARXMIS Receive DMA Masked Interrupt Status 3 4 I2C_SMIS_DMATXMIS Transmit DMA Masked Interrupt Status 4 5 I2C_SMIS_RXFFMIS Receive FIFO Full Interrupt Mask 8 9 I2C_SMIS_RXMIS Receive FIFO Request Interrupt Mask 6 7 I2C_SMIS_STARTMIS Start Condition Masked Interrupt Status 1 2 I2C_SMIS_STOPMIS Stop Condition Masked Interrupt Status 2 3 I2C_SMIS_TXFEMIS Transmit FIFO Empty Interrupt Mask 7 8 I2C_SMIS_TXMIS Transmit FIFO Request Interrupt Mask 5 6 SOAR I2C Slave Own Address 0x800 -1 read-write n 0x0 0x0 I2C_SOAR_OAR I2C Slave Own Address 0 7 SOAR2 I2C Slave Own Address 2 0x81C -1 read-write n 0x0 0x0 I2C_SOAR2_OAR2 I2C Slave Own Address 2 0 7 I2C_SOAR2_OAR2EN I2C Slave Own Address 2 Enable 7 8 SRIS I2C Slave Raw Interrupt Status 0x810 -1 read-write n 0x0 0x0 I2C_SRIS_DATARIS Data Raw Interrupt Status 0 1 I2C_SRIS_DMARXRIS Receive DMA Raw Interrupt Status 3 4 I2C_SRIS_DMATXRIS Transmit DMA Raw Interrupt Status 4 5 I2C_SRIS_RXFFRIS Receive FIFO Full Raw Interrupt Status 8 9 I2C_SRIS_RXRIS Receive FIFO Request Raw Interrupt Status 6 7 I2C_SRIS_STARTRIS Start Condition Raw Interrupt Status 1 2 I2C_SRIS_STOPRIS Stop Condition Raw Interrupt Status 2 3 I2C_SRIS_TXFERIS Transmit FIFO Empty Raw Interrupt Status 7 8 I2C_SRIS_TXRIS Transmit Request Raw Interrupt Status 5 6 PWM0 Register map for PWM0 peripheral PWM 0x0 0x0 0x1000 registers n PWM0_FAULT 9 PWM0_0 10 PWM0_1 11 PWM0_2 12 PWM0_3 43 0_CMPA PWM0 Compare A 0x58 read-write n 0x0 0x0 PWM_0_CMPA Comparator A Value 0 16 0_CMPB PWM0 Compare B 0x5C read-write n 0x0 0x0 PWM_0_CMPB Comparator B Value 0 16 0_COUNT PWM0 Counter 0x54 read-write n 0x0 0x0 PWM_0_COUNT Counter Value 0 16 0_CTL PWM0 Control 0x40 read-write n 0x0 0x0 PWM_0_CTL_CMPAUPD Comparator A Update Mode 4 5 PWM_0_CTL_CMPBUPD Comparator B Update Mode 5 6 PWM_0_CTL_DBCTLUPD PWMnDBCTL Update Mode 10 12 PWM_0_CTL_DBCTLUPD_I Immediate 0x0 PWM_0_CTL_DBCTLUPD_LS Locally Synchronized 0x2 PWM_0_CTL_DBCTLUPD_GS Globally Synchronized 0x3 PWM_0_CTL_DBFALLUPD PWMnDBFALL Update Mode 14 16 PWM_0_CTL_DBFALLUPD_I Immediate 0x0 PWM_0_CTL_DBFALLUPD_LS Locally Synchronized 0x2 PWM_0_CTL_DBFALLUPD_GS Globally Synchronized 0x3 PWM_0_CTL_DBRISEUPD PWMnDBRISE Update Mode 12 14 PWM_0_CTL_DBRISEUPD_I Immediate 0x0 PWM_0_CTL_DBRISEUPD_LS Locally Synchronized 0x2 PWM_0_CTL_DBRISEUPD_GS Globally Synchronized 0x3 PWM_0_CTL_DEBUG Debug Mode 2 3 PWM_0_CTL_ENABLE PWM Block Enable 0 1 PWM_0_CTL_FLTSRC Fault Condition Source 16 17 PWM_0_CTL_GENAUPD PWMnGENA Update Mode 6 8 PWM_0_CTL_GENAUPD_I Immediate 0x0 PWM_0_CTL_GENAUPD_LS Locally Synchronized 0x2 PWM_0_CTL_GENAUPD_GS Globally Synchronized 0x3 PWM_0_CTL_GENBUPD PWMnGENB Update Mode 8 10 PWM_0_CTL_GENBUPD_I Immediate 0x0 PWM_0_CTL_GENBUPD_LS Locally Synchronized 0x2 PWM_0_CTL_GENBUPD_GS Globally Synchronized 0x3 PWM_0_CTL_LATCH Latch Fault Input 18 19 PWM_0_CTL_LOADUPD Load Register Update Mode 3 4 PWM_0_CTL_MINFLTPER Minimum Fault Period 17 18 PWM_0_CTL_MODE Counter Mode 1 2 0_DBCTL PWM0 Dead-Band Control 0x68 read-write n 0x0 0x0 PWM_0_DBCTL_ENABLE Dead-Band Generator Enable 0 1 0_DBFALL PWM0 Dead-Band Falling-Edge-Delay 0x70 read-write n 0x0 0x0 PWM_0_DBFALL_DELAY Dead-Band Fall Delay 0 12 0_DBRISE PWM0 Dead-Band Rising-Edge Delay 0x6C read-write n 0x0 0x0 PWM_0_DBRISE_DELAY Dead-Band Rise Delay 0 12 0_FLTSEN PWM0 Fault Pin Logic Sense 0x800 read-write n 0x0 0x0 PWM_0_FLTSEN_FAULT0 Fault0 Sense 0 1 PWM_0_FLTSEN_FAULT1 Fault1 Sense 1 2 PWM_0_FLTSEN_FAULT2 Fault2 Sense 2 3 PWM_0_FLTSEN_FAULT3 Fault3 Sense 3 4 0_FLTSRC0 PWM0 Fault Source 0 0x74 read-write n 0x0 0x0 PWM_0_FLTSRC0_FAULT0 Fault0 Input 0 1 PWM_0_FLTSRC0_FAULT1 Fault1 Input 1 2 PWM_0_FLTSRC0_FAULT2 Fault2 Input 2 3 PWM_0_FLTSRC0_FAULT3 Fault3 Input 3 4 0_FLTSRC1 PWM0 Fault Source 1 0x78 read-write n 0x0 0x0 PWM_0_FLTSRC1_DCMP0 Digital Comparator 0 0 1 PWM_0_FLTSRC1_DCMP1 Digital Comparator 1 1 2 PWM_0_FLTSRC1_DCMP2 Digital Comparator 2 2 3 PWM_0_FLTSRC1_DCMP3 Digital Comparator 3 3 4 PWM_0_FLTSRC1_DCMP4 Digital Comparator 4 4 5 PWM_0_FLTSRC1_DCMP5 Digital Comparator 5 5 6 PWM_0_FLTSRC1_DCMP6 Digital Comparator 6 6 7 PWM_0_FLTSRC1_DCMP7 Digital Comparator 7 7 8 0_FLTSTAT0 PWM0 Fault Status 0 0x804 read-only n 0x0 0x0 PWM_0_FLTSTAT0_FAULT0 Fault Input 0 0 1 read-only PWM_0_FLTSTAT0_FAULT1 Fault Input 1 1 2 read-only PWM_0_FLTSTAT0_FAULT2 Fault Input 2 2 3 read-only PWM_0_FLTSTAT0_FAULT3 Fault Input 3 3 4 read-only 0_FLTSTAT1 PWM0 Fault Status 1 0x808 read-only n 0x0 0x0 PWM_0_FLTSTAT1_DCMP0 Digital Comparator 0 Trigger 0 1 read-only PWM_0_FLTSTAT1_DCMP1 Digital Comparator 1 Trigger 1 2 read-only PWM_0_FLTSTAT1_DCMP2 Digital Comparator 2 Trigger 2 3 read-only PWM_0_FLTSTAT1_DCMP3 Digital Comparator 3 Trigger 3 4 read-only PWM_0_FLTSTAT1_DCMP4 Digital Comparator 4 Trigger 4 5 read-only PWM_0_FLTSTAT1_DCMP5 Digital Comparator 5 Trigger 5 6 read-only PWM_0_FLTSTAT1_DCMP6 Digital Comparator 6 Trigger 6 7 read-only PWM_0_FLTSTAT1_DCMP7 Digital Comparator 7 Trigger 7 8 read-only 0_GENA PWM0 Generator A Control 0x60 read-write n 0x0 0x0 PWM_0_GENA_ACTCMPAD Action for Comparator A Down 6 8 PWM_0_GENA_ACTCMPAD_NONE Do nothing 0x0 PWM_0_GENA_ACTCMPAD_INV Invert pwmA 0x1 PWM_0_GENA_ACTCMPAD_ZERO Drive pwmA Low 0x2 PWM_0_GENA_ACTCMPAD_ONE Drive pwmA High 0x3 PWM_0_GENA_ACTCMPAU Action for Comparator A Up 4 6 PWM_0_GENA_ACTCMPAU_NONE Do nothing 0x0 PWM_0_GENA_ACTCMPAU_INV Invert pwmA 0x1 PWM_0_GENA_ACTCMPAU_ZERO Drive pwmA Low 0x2 PWM_0_GENA_ACTCMPAU_ONE Drive pwmA High 0x3 PWM_0_GENA_ACTCMPBD Action for Comparator B Down 10 12 PWM_0_GENA_ACTCMPBD_NONE Do nothing 0x0 PWM_0_GENA_ACTCMPBD_INV Invert pwmA 0x1 PWM_0_GENA_ACTCMPBD_ZERO Drive pwmA Low 0x2 PWM_0_GENA_ACTCMPBD_ONE Drive pwmA High 0x3 PWM_0_GENA_ACTCMPBU Action for Comparator B Up 8 10 PWM_0_GENA_ACTCMPBU_NONE Do nothing 0x0 PWM_0_GENA_ACTCMPBU_INV Invert pwmA 0x1 PWM_0_GENA_ACTCMPBU_ZERO Drive pwmA Low 0x2 PWM_0_GENA_ACTCMPBU_ONE Drive pwmA High 0x3 PWM_0_GENA_ACTLOAD Action for Counter=LOAD 2 4 PWM_0_GENA_ACTLOAD_NONE Do nothing 0x0 PWM_0_GENA_ACTLOAD_INV Invert pwmA 0x1 PWM_0_GENA_ACTLOAD_ZERO Drive pwmA Low 0x2 PWM_0_GENA_ACTLOAD_ONE Drive pwmA High 0x3 PWM_0_GENA_ACTZERO Action for Counter=0 0 2 PWM_0_GENA_ACTZERO_NONE Do nothing 0x0 PWM_0_GENA_ACTZERO_INV Invert pwmA 0x1 PWM_0_GENA_ACTZERO_ZERO Drive pwmA Low 0x2 PWM_0_GENA_ACTZERO_ONE Drive pwmA High 0x3 0_GENB PWM0 Generator B Control 0x64 read-write n 0x0 0x0 PWM_0_GENB_ACTCMPAD Action for Comparator A Down 6 8 PWM_0_GENB_ACTCMPAD_NONE Do nothing 0x0 PWM_0_GENB_ACTCMPAD_INV Invert pwmB 0x1 PWM_0_GENB_ACTCMPAD_ZERO Drive pwmB Low 0x2 PWM_0_GENB_ACTCMPAD_ONE Drive pwmB High 0x3 PWM_0_GENB_ACTCMPAU Action for Comparator A Up 4 6 PWM_0_GENB_ACTCMPAU_NONE Do nothing 0x0 PWM_0_GENB_ACTCMPAU_INV Invert pwmB 0x1 PWM_0_GENB_ACTCMPAU_ZERO Drive pwmB Low 0x2 PWM_0_GENB_ACTCMPAU_ONE Drive pwmB High 0x3 PWM_0_GENB_ACTCMPBD Action for Comparator B Down 10 12 PWM_0_GENB_ACTCMPBD_NONE Do nothing 0x0 PWM_0_GENB_ACTCMPBD_INV Invert pwmB 0x1 PWM_0_GENB_ACTCMPBD_ZERO Drive pwmB Low 0x2 PWM_0_GENB_ACTCMPBD_ONE Drive pwmB High 0x3 PWM_0_GENB_ACTCMPBU Action for Comparator B Up 8 10 PWM_0_GENB_ACTCMPBU_NONE Do nothing 0x0 PWM_0_GENB_ACTCMPBU_INV Invert pwmB 0x1 PWM_0_GENB_ACTCMPBU_ZERO Drive pwmB Low 0x2 PWM_0_GENB_ACTCMPBU_ONE Drive pwmB High 0x3 PWM_0_GENB_ACTLOAD Action for Counter=LOAD 2 4 PWM_0_GENB_ACTLOAD_NONE Do nothing 0x0 PWM_0_GENB_ACTLOAD_INV Invert pwmB 0x1 PWM_0_GENB_ACTLOAD_ZERO Drive pwmB Low 0x2 PWM_0_GENB_ACTLOAD_ONE Drive pwmB High 0x3 PWM_0_GENB_ACTZERO Action for Counter=0 0 2 PWM_0_GENB_ACTZERO_NONE Do nothing 0x0 PWM_0_GENB_ACTZERO_INV Invert pwmB 0x1 PWM_0_GENB_ACTZERO_ZERO Drive pwmB Low 0x2 PWM_0_GENB_ACTZERO_ONE Drive pwmB High 0x3 0_INTEN PWM0 Interrupt and Trigger Enable 0x44 read-write n 0x0 0x0 PWM_0_INTEN_INTCMPAD Interrupt for Counter=PWMnCMPA Down 3 4 PWM_0_INTEN_INTCMPAU Interrupt for Counter=PWMnCMPA Up 2 3 PWM_0_INTEN_INTCMPBD Interrupt for Counter=PWMnCMPB Down 5 6 PWM_0_INTEN_INTCMPBU Interrupt for Counter=PWMnCMPB Up 4 5 PWM_0_INTEN_INTCNTLOAD Interrupt for Counter=PWMnLOAD 1 2 PWM_0_INTEN_INTCNTZERO Interrupt for Counter=0 0 1 PWM_0_INTEN_TRCMPAD Trigger for Counter=PWMnCMPA Down 11 12 PWM_0_INTEN_TRCMPAU Trigger for Counter=PWMnCMPA Up 10 11 PWM_0_INTEN_TRCMPBD Trigger for Counter=PWMnCMPB Down 13 14 PWM_0_INTEN_TRCMPBU Trigger for Counter=PWMnCMPB Up 12 13 PWM_0_INTEN_TRCNTLOAD Trigger for Counter=PWMnLOAD 9 10 PWM_0_INTEN_TRCNTZERO Trigger for Counter=0 8 9 0_ISC PWM0 Interrupt Status and Clear 0x4C read-write n 0x0 0x0 PWM_0_ISC_INTCMPAD Comparator A Down Interrupt 3 4 PWM_0_ISC_INTCMPAU Comparator A Up Interrupt 2 3 PWM_0_ISC_INTCMPBD Comparator B Down Interrupt 5 6 PWM_0_ISC_INTCMPBU Comparator B Up Interrupt 4 5 PWM_0_ISC_INTCNTLOAD Counter=Load Interrupt 1 2 PWM_0_ISC_INTCNTZERO Counter=0 Interrupt 0 1 0_LOAD PWM0 Load 0x50 read-write n 0x0 0x0 PWM_0_LOAD Counter Load Value 0 16 0_MINFLTPER PWM0 Minimum Fault Period 0x7C read-write n 0x0 0x0 PWM_0_MINFLTPER Minimum Fault Period 0 16 0_RIS PWM0 Raw Interrupt Status 0x48 read-write n 0x0 0x0 PWM_0_RIS_INTCMPAD Comparator A Down Interrupt Status 3 4 PWM_0_RIS_INTCMPAU Comparator A Up Interrupt Status 2 3 PWM_0_RIS_INTCMPBD Comparator B Down Interrupt Status 5 6 PWM_0_RIS_INTCMPBU Comparator B Up Interrupt Status 4 5 PWM_0_RIS_INTCNTLOAD Counter=Load Interrupt Status 1 2 PWM_0_RIS_INTCNTZERO Counter=0 Interrupt Status 0 1 1_CMPA PWM1 Compare A 0x98 read-write n 0x0 0x0 PWM_1_CMPA_COMPA Comparator A Value 0 16 1_CMPB PWM1 Compare B 0x9C read-write n 0x0 0x0 PWM_1_CMPB_COMPB Comparator B Value 0 16 1_COUNT PWM1 Counter 0x94 read-write n 0x0 0x0 PWM_1_COUNT_COUNT Counter Value 0 16 1_CTL PWM1 Control 0x80 read-write n 0x0 0x0 PWM_1_CTL_CMPAUPD Comparator A Update Mode 4 5 PWM_1_CTL_CMPBUPD Comparator B Update Mode 5 6 PWM_1_CTL_DBCTLUPD PWMnDBCTL Update Mode 10 12 PWM_1_CTL_DBCTLUPD_I Immediate 0x0 PWM_1_CTL_DBCTLUPD_LS Locally Synchronized 0x2 PWM_1_CTL_DBCTLUPD_GS Globally Synchronized 0x3 PWM_1_CTL_DBFALLUPD PWMnDBFALL Update Mode 14 16 PWM_1_CTL_DBFALLUPD_I Immediate 0x0 PWM_1_CTL_DBFALLUPD_LS Locally Synchronized 0x2 PWM_1_CTL_DBFALLUPD_GS Globally Synchronized 0x3 PWM_1_CTL_DBRISEUPD PWMnDBRISE Update Mode 12 14 PWM_1_CTL_DBRISEUPD_I Immediate 0x0 PWM_1_CTL_DBRISEUPD_LS Locally Synchronized 0x2 PWM_1_CTL_DBRISEUPD_GS Globally Synchronized 0x3 PWM_1_CTL_DEBUG Debug Mode 2 3 PWM_1_CTL_ENABLE PWM Block Enable 0 1 PWM_1_CTL_FLTSRC Fault Condition Source 16 17 PWM_1_CTL_GENAUPD PWMnGENA Update Mode 6 8 PWM_1_CTL_GENAUPD_I Immediate 0x0 PWM_1_CTL_GENAUPD_LS Locally Synchronized 0x2 PWM_1_CTL_GENAUPD_GS Globally Synchronized 0x3 PWM_1_CTL_GENBUPD PWMnGENB Update Mode 8 10 PWM_1_CTL_GENBUPD_I Immediate 0x0 PWM_1_CTL_GENBUPD_LS Locally Synchronized 0x2 PWM_1_CTL_GENBUPD_GS Globally Synchronized 0x3 PWM_1_CTL_LATCH Latch Fault Input 18 19 PWM_1_CTL_LOADUPD Load Register Update Mode 3 4 PWM_1_CTL_MINFLTPER Minimum Fault Period 17 18 PWM_1_CTL_MODE Counter Mode 1 2 1_DBCTL PWM1 Dead-Band Control 0xA8 read-write n 0x0 0x0 PWM_1_DBCTL_ENABLE Dead-Band Generator Enable 0 1 1_DBFALL PWM1 Dead-Band Falling-Edge-Delay 0xB0 read-write n 0x0 0x0 PWM_1_DBFALL_FALLDELAY Dead-Band Fall Delay 0 12 1_DBRISE PWM1 Dead-Band Rising-Edge Delay 0xAC read-write n 0x0 0x0 PWM_1_DBRISE_RISEDELAY Dead-Band Rise Delay 0 12 1_FLTSEN PWM1 Fault Pin Logic Sense 0x880 read-write n 0x0 0x0 PWM_1_FLTSEN_FAULT0 Fault0 Sense 0 1 PWM_1_FLTSEN_FAULT1 Fault1 Sense 1 2 PWM_1_FLTSEN_FAULT2 Fault2 Sense 2 3 PWM_1_FLTSEN_FAULT3 Fault3 Sense 3 4 1_FLTSRC0 PWM1 Fault Source 0 0xB4 read-write n 0x0 0x0 PWM_1_FLTSRC0_FAULT0 Fault0 Input 0 1 PWM_1_FLTSRC0_FAULT1 Fault1 Input 1 2 PWM_1_FLTSRC0_FAULT2 Fault2 Input 2 3 PWM_1_FLTSRC0_FAULT3 Fault3 Input 3 4 1_FLTSRC1 PWM1 Fault Source 1 0xB8 read-write n 0x0 0x0 PWM_1_FLTSRC1_DCMP0 Digital Comparator 0 0 1 PWM_1_FLTSRC1_DCMP1 Digital Comparator 1 1 2 PWM_1_FLTSRC1_DCMP2 Digital Comparator 2 2 3 PWM_1_FLTSRC1_DCMP3 Digital Comparator 3 3 4 PWM_1_FLTSRC1_DCMP4 Digital Comparator 4 4 5 PWM_1_FLTSRC1_DCMP5 Digital Comparator 5 5 6 PWM_1_FLTSRC1_DCMP6 Digital Comparator 6 6 7 PWM_1_FLTSRC1_DCMP7 Digital Comparator 7 7 8 1_FLTSTAT0 PWM1 Fault Status 0 0x884 read-only n 0x0 0x0 PWM_1_FLTSTAT0_FAULT0 Fault Input 0 0 1 read-only PWM_1_FLTSTAT0_FAULT1 Fault Input 1 1 2 read-only PWM_1_FLTSTAT0_FAULT2 Fault Input 2 2 3 read-only PWM_1_FLTSTAT0_FAULT3 Fault Input 3 3 4 read-only 1_FLTSTAT1 PWM1 Fault Status 1 0x888 read-only n 0x0 0x0 PWM_1_FLTSTAT1_DCMP0 Digital Comparator 0 Trigger 0 1 read-only PWM_1_FLTSTAT1_DCMP1 Digital Comparator 1 Trigger 1 2 read-only PWM_1_FLTSTAT1_DCMP2 Digital Comparator 2 Trigger 2 3 read-only PWM_1_FLTSTAT1_DCMP3 Digital Comparator 3 Trigger 3 4 read-only PWM_1_FLTSTAT1_DCMP4 Digital Comparator 4 Trigger 4 5 read-only PWM_1_FLTSTAT1_DCMP5 Digital Comparator 5 Trigger 5 6 read-only PWM_1_FLTSTAT1_DCMP6 Digital Comparator 6 Trigger 6 7 read-only PWM_1_FLTSTAT1_DCMP7 Digital Comparator 7 Trigger 7 8 read-only 1_GENA PWM1 Generator A Control 0xA0 read-write n 0x0 0x0 PWM_1_GENA_ACTCMPAD Action for Comparator A Down 6 8 PWM_1_GENA_ACTCMPAD_NONE Do nothing 0x0 PWM_1_GENA_ACTCMPAD_INV Invert pwmA 0x1 PWM_1_GENA_ACTCMPAD_ZERO Drive pwmA Low 0x2 PWM_1_GENA_ACTCMPAD_ONE Drive pwmA High 0x3 PWM_1_GENA_ACTCMPAU Action for Comparator A Up 4 6 PWM_1_GENA_ACTCMPAU_NONE Do nothing 0x0 PWM_1_GENA_ACTCMPAU_INV Invert pwmA 0x1 PWM_1_GENA_ACTCMPAU_ZERO Drive pwmA Low 0x2 PWM_1_GENA_ACTCMPAU_ONE Drive pwmA High 0x3 PWM_1_GENA_ACTCMPBD Action for Comparator B Down 10 12 PWM_1_GENA_ACTCMPBD_NONE Do nothing 0x0 PWM_1_GENA_ACTCMPBD_INV Invert pwmA 0x1 PWM_1_GENA_ACTCMPBD_ZERO Drive pwmA Low 0x2 PWM_1_GENA_ACTCMPBD_ONE Drive pwmA High 0x3 PWM_1_GENA_ACTCMPBU Action for Comparator B Up 8 10 PWM_1_GENA_ACTCMPBU_NONE Do nothing 0x0 PWM_1_GENA_ACTCMPBU_INV Invert pwmA 0x1 PWM_1_GENA_ACTCMPBU_ZERO Drive pwmA Low 0x2 PWM_1_GENA_ACTCMPBU_ONE Drive pwmA High 0x3 PWM_1_GENA_ACTLOAD Action for Counter=LOAD 2 4 PWM_1_GENA_ACTLOAD_NONE Do nothing 0x0 PWM_1_GENA_ACTLOAD_INV Invert pwmA 0x1 PWM_1_GENA_ACTLOAD_ZERO Drive pwmA Low 0x2 PWM_1_GENA_ACTLOAD_ONE Drive pwmA High 0x3 PWM_1_GENA_ACTZERO Action for Counter=0 0 2 PWM_1_GENA_ACTZERO_NONE Do nothing 0x0 PWM_1_GENA_ACTZERO_INV Invert pwmA 0x1 PWM_1_GENA_ACTZERO_ZERO Drive pwmA Low 0x2 PWM_1_GENA_ACTZERO_ONE Drive pwmA High 0x3 1_GENB PWM1 Generator B Control 0xA4 read-write n 0x0 0x0 PWM_1_GENB_ACTCMPAD Action for Comparator A Down 6 8 PWM_1_GENB_ACTCMPAD_NONE Do nothing 0x0 PWM_1_GENB_ACTCMPAD_INV Invert pwmB 0x1 PWM_1_GENB_ACTCMPAD_ZERO Drive pwmB Low 0x2 PWM_1_GENB_ACTCMPAD_ONE Drive pwmB High 0x3 PWM_1_GENB_ACTCMPAU Action for Comparator A Up 4 6 PWM_1_GENB_ACTCMPAU_NONE Do nothing 0x0 PWM_1_GENB_ACTCMPAU_INV Invert pwmB 0x1 PWM_1_GENB_ACTCMPAU_ZERO Drive pwmB Low 0x2 PWM_1_GENB_ACTCMPAU_ONE Drive pwmB High 0x3 PWM_1_GENB_ACTCMPBD Action for Comparator B Down 10 12 PWM_1_GENB_ACTCMPBD_NONE Do nothing 0x0 PWM_1_GENB_ACTCMPBD_INV Invert pwmB 0x1 PWM_1_GENB_ACTCMPBD_ZERO Drive pwmB Low 0x2 PWM_1_GENB_ACTCMPBD_ONE Drive pwmB High 0x3 PWM_1_GENB_ACTCMPBU Action for Comparator B Up 8 10 PWM_1_GENB_ACTCMPBU_NONE Do nothing 0x0 PWM_1_GENB_ACTCMPBU_INV Invert pwmB 0x1 PWM_1_GENB_ACTCMPBU_ZERO Drive pwmB Low 0x2 PWM_1_GENB_ACTCMPBU_ONE Drive pwmB High 0x3 PWM_1_GENB_ACTLOAD Action for Counter=LOAD 2 4 PWM_1_GENB_ACTLOAD_NONE Do nothing 0x0 PWM_1_GENB_ACTLOAD_INV Invert pwmB 0x1 PWM_1_GENB_ACTLOAD_ZERO Drive pwmB Low 0x2 PWM_1_GENB_ACTLOAD_ONE Drive pwmB High 0x3 PWM_1_GENB_ACTZERO Action for Counter=0 0 2 PWM_1_GENB_ACTZERO_NONE Do nothing 0x0 PWM_1_GENB_ACTZERO_INV Invert pwmB 0x1 PWM_1_GENB_ACTZERO_ZERO Drive pwmB Low 0x2 PWM_1_GENB_ACTZERO_ONE Drive pwmB High 0x3 1_INTEN PWM1 Interrupt and Trigger Enable 0x84 read-write n 0x0 0x0 PWM_1_INTEN_INTCMPAD Interrupt for Counter=PWMnCMPA Down 3 4 PWM_1_INTEN_INTCMPAU Interrupt for Counter=PWMnCMPA Up 2 3 PWM_1_INTEN_INTCMPBD Interrupt for Counter=PWMnCMPB Down 5 6 PWM_1_INTEN_INTCMPBU Interrupt for Counter=PWMnCMPB Up 4 5 PWM_1_INTEN_INTCNTLOAD Interrupt for Counter=PWMnLOAD 1 2 PWM_1_INTEN_INTCNTZERO Interrupt for Counter=0 0 1 PWM_1_INTEN_TRCMPAD Trigger for Counter=PWMnCMPA Down 11 12 PWM_1_INTEN_TRCMPAU Trigger for Counter=PWMnCMPA Up 10 11 PWM_1_INTEN_TRCMPBD Trigger for Counter=PWMnCMPB Down 13 14 PWM_1_INTEN_TRCMPBU Trigger for Counter=PWMnCMPB Up 12 13 PWM_1_INTEN_TRCNTLOAD Trigger for Counter=PWMnLOAD 9 10 PWM_1_INTEN_TRCNTZERO Trigger for Counter=0 8 9 1_ISC PWM1 Interrupt Status and Clear 0x8C read-write n 0x0 0x0 PWM_1_ISC_INTCMPAD Comparator A Down Interrupt 3 4 PWM_1_ISC_INTCMPAU Comparator A Up Interrupt 2 3 PWM_1_ISC_INTCMPBD Comparator B Down Interrupt 5 6 PWM_1_ISC_INTCMPBU Comparator B Up Interrupt 4 5 PWM_1_ISC_INTCNTLOAD Counter=Load Interrupt 1 2 PWM_1_ISC_INTCNTZERO Counter=0 Interrupt 0 1 1_LOAD PWM1 Load 0x90 read-write n 0x0 0x0 PWM_1_LOAD_LOAD Counter Load Value 0 16 1_MINFLTPER PWM1 Minimum Fault Period 0xBC read-write n 0x0 0x0 PWM_1_MINFLTPER_MFP Minimum Fault Period 0 16 1_RIS PWM1 Raw Interrupt Status 0x88 read-write n 0x0 0x0 PWM_1_RIS_INTCMPAD Comparator A Down Interrupt Status 3 4 PWM_1_RIS_INTCMPAU Comparator A Up Interrupt Status 2 3 PWM_1_RIS_INTCMPBD Comparator B Down Interrupt Status 5 6 PWM_1_RIS_INTCMPBU Comparator B Up Interrupt Status 4 5 PWM_1_RIS_INTCNTLOAD Counter=Load Interrupt Status 1 2 PWM_1_RIS_INTCNTZERO Counter=0 Interrupt Status 0 1 2_CMPA PWM2 Compare A 0xD8 read-write n 0x0 0x0 PWM_2_CMPA_COMPA Comparator A Value 0 16 2_CMPB PWM2 Compare B 0xDC read-write n 0x0 0x0 PWM_2_CMPB_COMPB Comparator B Value 0 16 2_COUNT PWM2 Counter 0xD4 read-write n 0x0 0x0 PWM_2_COUNT_COUNT Counter Value 0 16 2_CTL PWM2 Control 0xC0 read-write n 0x0 0x0 PWM_2_CTL_CMPAUPD Comparator A Update Mode 4 5 PWM_2_CTL_CMPBUPD Comparator B Update Mode 5 6 PWM_2_CTL_DBCTLUPD PWMnDBCTL Update Mode 10 12 PWM_2_CTL_DBCTLUPD_I Immediate 0x0 PWM_2_CTL_DBCTLUPD_LS Locally Synchronized 0x2 PWM_2_CTL_DBCTLUPD_GS Globally Synchronized 0x3 PWM_2_CTL_DBFALLUPD PWMnDBFALL Update Mode 14 16 PWM_2_CTL_DBFALLUPD_I Immediate 0x0 PWM_2_CTL_DBFALLUPD_LS Locally Synchronized 0x2 PWM_2_CTL_DBFALLUPD_GS Globally Synchronized 0x3 PWM_2_CTL_DBRISEUPD PWMnDBRISE Update Mode 12 14 PWM_2_CTL_DBRISEUPD_I Immediate 0x0 PWM_2_CTL_DBRISEUPD_LS Locally Synchronized 0x2 PWM_2_CTL_DBRISEUPD_GS Globally Synchronized 0x3 PWM_2_CTL_DEBUG Debug Mode 2 3 PWM_2_CTL_ENABLE PWM Block Enable 0 1 PWM_2_CTL_FLTSRC Fault Condition Source 16 17 PWM_2_CTL_GENAUPD PWMnGENA Update Mode 6 8 PWM_2_CTL_GENAUPD_I Immediate 0x0 PWM_2_CTL_GENAUPD_LS Locally Synchronized 0x2 PWM_2_CTL_GENAUPD_GS Globally Synchronized 0x3 PWM_2_CTL_GENBUPD PWMnGENB Update Mode 8 10 PWM_2_CTL_GENBUPD_I Immediate 0x0 PWM_2_CTL_GENBUPD_LS Locally Synchronized 0x2 PWM_2_CTL_GENBUPD_GS Globally Synchronized 0x3 PWM_2_CTL_LATCH Latch Fault Input 18 19 PWM_2_CTL_LOADUPD Load Register Update Mode 3 4 PWM_2_CTL_MINFLTPER Minimum Fault Period 17 18 PWM_2_CTL_MODE Counter Mode 1 2 2_DBCTL PWM2 Dead-Band Control 0xE8 read-write n 0x0 0x0 PWM_2_DBCTL_ENABLE Dead-Band Generator Enable 0 1 2_DBFALL PWM2 Dead-Band Falling-Edge-Delay 0xF0 read-write n 0x0 0x0 PWM_2_DBFALL_FALLDELAY Dead-Band Fall Delay 0 12 2_DBRISE PWM2 Dead-Band Rising-Edge Delay 0xEC read-write n 0x0 0x0 PWM_2_DBRISE_RISEDELAY Dead-Band Rise Delay 0 12 2_FLTSEN PWM2 Fault Pin Logic Sense 0x900 read-write n 0x0 0x0 PWM_2_FLTSEN_FAULT0 Fault0 Sense 0 1 PWM_2_FLTSEN_FAULT1 Fault1 Sense 1 2 PWM_2_FLTSEN_FAULT2 Fault2 Sense 2 3 PWM_2_FLTSEN_FAULT3 Fault3 Sense 3 4 2_FLTSRC0 PWM2 Fault Source 0 0xF4 read-write n 0x0 0x0 PWM_2_FLTSRC0_FAULT0 Fault0 Input 0 1 PWM_2_FLTSRC0_FAULT1 Fault1 Input 1 2 PWM_2_FLTSRC0_FAULT2 Fault2 Input 2 3 PWM_2_FLTSRC0_FAULT3 Fault3 Input 3 4 2_FLTSRC1 PWM2 Fault Source 1 0xF8 read-write n 0x0 0x0 PWM_2_FLTSRC1_DCMP0 Digital Comparator 0 0 1 PWM_2_FLTSRC1_DCMP1 Digital Comparator 1 1 2 PWM_2_FLTSRC1_DCMP2 Digital Comparator 2 2 3 PWM_2_FLTSRC1_DCMP3 Digital Comparator 3 3 4 PWM_2_FLTSRC1_DCMP4 Digital Comparator 4 4 5 PWM_2_FLTSRC1_DCMP5 Digital Comparator 5 5 6 PWM_2_FLTSRC1_DCMP6 Digital Comparator 6 6 7 PWM_2_FLTSRC1_DCMP7 Digital Comparator 7 7 8 2_FLTSTAT0 PWM2 Fault Status 0 0x904 read-only n 0x0 0x0 PWM_2_FLTSTAT0_FAULT0 Fault Input 0 0 1 read-only PWM_2_FLTSTAT0_FAULT1 Fault Input 1 1 2 read-only PWM_2_FLTSTAT0_FAULT2 Fault Input 2 2 3 read-only PWM_2_FLTSTAT0_FAULT3 Fault Input 3 3 4 read-only 2_FLTSTAT1 PWM2 Fault Status 1 0x908 read-only n 0x0 0x0 PWM_2_FLTSTAT1_DCMP0 Digital Comparator 0 Trigger 0 1 read-only PWM_2_FLTSTAT1_DCMP1 Digital Comparator 1 Trigger 1 2 read-only PWM_2_FLTSTAT1_DCMP2 Digital Comparator 2 Trigger 2 3 read-only PWM_2_FLTSTAT1_DCMP3 Digital Comparator 3 Trigger 3 4 read-only PWM_2_FLTSTAT1_DCMP4 Digital Comparator 4 Trigger 4 5 read-only PWM_2_FLTSTAT1_DCMP5 Digital Comparator 5 Trigger 5 6 read-only PWM_2_FLTSTAT1_DCMP6 Digital Comparator 6 Trigger 6 7 read-only PWM_2_FLTSTAT1_DCMP7 Digital Comparator 7 Trigger 7 8 read-only 2_GENA PWM2 Generator A Control 0xE0 read-write n 0x0 0x0 PWM_2_GENA_ACTCMPAD Action for Comparator A Down 6 8 PWM_2_GENA_ACTCMPAD_NONE Do nothing 0x0 PWM_2_GENA_ACTCMPAD_INV Invert pwmA 0x1 PWM_2_GENA_ACTCMPAD_ZERO Drive pwmA Low 0x2 PWM_2_GENA_ACTCMPAD_ONE Drive pwmA High 0x3 PWM_2_GENA_ACTCMPAU Action for Comparator A Up 4 6 PWM_2_GENA_ACTCMPAU_NONE Do nothing 0x0 PWM_2_GENA_ACTCMPAU_INV Invert pwmA 0x1 PWM_2_GENA_ACTCMPAU_ZERO Drive pwmA Low 0x2 PWM_2_GENA_ACTCMPAU_ONE Drive pwmA High 0x3 PWM_2_GENA_ACTCMPBD Action for Comparator B Down 10 12 PWM_2_GENA_ACTCMPBD_NONE Do nothing 0x0 PWM_2_GENA_ACTCMPBD_INV Invert pwmA 0x1 PWM_2_GENA_ACTCMPBD_ZERO Drive pwmA Low 0x2 PWM_2_GENA_ACTCMPBD_ONE Drive pwmA High 0x3 PWM_2_GENA_ACTCMPBU Action for Comparator B Up 8 10 PWM_2_GENA_ACTCMPBU_NONE Do nothing 0x0 PWM_2_GENA_ACTCMPBU_INV Invert pwmA 0x1 PWM_2_GENA_ACTCMPBU_ZERO Drive pwmA Low 0x2 PWM_2_GENA_ACTCMPBU_ONE Drive pwmA High 0x3 PWM_2_GENA_ACTLOAD Action for Counter=LOAD 2 4 PWM_2_GENA_ACTLOAD_NONE Do nothing 0x0 PWM_2_GENA_ACTLOAD_INV Invert pwmA 0x1 PWM_2_GENA_ACTLOAD_ZERO Drive pwmA Low 0x2 PWM_2_GENA_ACTLOAD_ONE Drive pwmA High 0x3 PWM_2_GENA_ACTZERO Action for Counter=0 0 2 PWM_2_GENA_ACTZERO_NONE Do nothing 0x0 PWM_2_GENA_ACTZERO_INV Invert pwmA 0x1 PWM_2_GENA_ACTZERO_ZERO Drive pwmA Low 0x2 PWM_2_GENA_ACTZERO_ONE Drive pwmA High 0x3 2_GENB PWM2 Generator B Control 0xE4 read-write n 0x0 0x0 PWM_2_GENB_ACTCMPAD Action for Comparator A Down 6 8 PWM_2_GENB_ACTCMPAD_NONE Do nothing 0x0 PWM_2_GENB_ACTCMPAD_INV Invert pwmB 0x1 PWM_2_GENB_ACTCMPAD_ZERO Drive pwmB Low 0x2 PWM_2_GENB_ACTCMPAD_ONE Drive pwmB High 0x3 PWM_2_GENB_ACTCMPAU Action for Comparator A Up 4 6 PWM_2_GENB_ACTCMPAU_NONE Do nothing 0x0 PWM_2_GENB_ACTCMPAU_INV Invert pwmB 0x1 PWM_2_GENB_ACTCMPAU_ZERO Drive pwmB Low 0x2 PWM_2_GENB_ACTCMPAU_ONE Drive pwmB High 0x3 PWM_2_GENB_ACTCMPBD Action for Comparator B Down 10 12 PWM_2_GENB_ACTCMPBD_NONE Do nothing 0x0 PWM_2_GENB_ACTCMPBD_INV Invert pwmB 0x1 PWM_2_GENB_ACTCMPBD_ZERO Drive pwmB Low 0x2 PWM_2_GENB_ACTCMPBD_ONE Drive pwmB High 0x3 PWM_2_GENB_ACTCMPBU Action for Comparator B Up 8 10 PWM_2_GENB_ACTCMPBU_NONE Do nothing 0x0 PWM_2_GENB_ACTCMPBU_INV Invert pwmB 0x1 PWM_2_GENB_ACTCMPBU_ZERO Drive pwmB Low 0x2 PWM_2_GENB_ACTCMPBU_ONE Drive pwmB High 0x3 PWM_2_GENB_ACTLOAD Action for Counter=LOAD 2 4 PWM_2_GENB_ACTLOAD_NONE Do nothing 0x0 PWM_2_GENB_ACTLOAD_INV Invert pwmB 0x1 PWM_2_GENB_ACTLOAD_ZERO Drive pwmB Low 0x2 PWM_2_GENB_ACTLOAD_ONE Drive pwmB High 0x3 PWM_2_GENB_ACTZERO Action for Counter=0 0 2 PWM_2_GENB_ACTZERO_NONE Do nothing 0x0 PWM_2_GENB_ACTZERO_INV Invert pwmB 0x1 PWM_2_GENB_ACTZERO_ZERO Drive pwmB Low 0x2 PWM_2_GENB_ACTZERO_ONE Drive pwmB High 0x3 2_INTEN PWM2 Interrupt and Trigger Enable 0xC4 read-write n 0x0 0x0 PWM_2_INTEN_INTCMPAD Interrupt for Counter=PWMnCMPA Down 3 4 PWM_2_INTEN_INTCMPAU Interrupt for Counter=PWMnCMPA Up 2 3 PWM_2_INTEN_INTCMPBD Interrupt for Counter=PWMnCMPB Down 5 6 PWM_2_INTEN_INTCMPBU Interrupt for Counter=PWMnCMPB Up 4 5 PWM_2_INTEN_INTCNTLOAD Interrupt for Counter=PWMnLOAD 1 2 PWM_2_INTEN_INTCNTZERO Interrupt for Counter=0 0 1 PWM_2_INTEN_TRCMPAD Trigger for Counter=PWMnCMPA Down 11 12 PWM_2_INTEN_TRCMPAU Trigger for Counter=PWMnCMPA Up 10 11 PWM_2_INTEN_TRCMPBD Trigger for Counter=PWMnCMPB Down 13 14 PWM_2_INTEN_TRCMPBU Trigger for Counter=PWMnCMPB Up 12 13 PWM_2_INTEN_TRCNTLOAD Trigger for Counter=PWMnLOAD 9 10 PWM_2_INTEN_TRCNTZERO Trigger for Counter=0 8 9 2_ISC PWM2 Interrupt Status and Clear 0xCC read-write n 0x0 0x0 PWM_2_ISC_INTCMPAD Comparator A Down Interrupt 3 4 PWM_2_ISC_INTCMPAU Comparator A Up Interrupt 2 3 PWM_2_ISC_INTCMPBD Comparator B Down Interrupt 5 6 PWM_2_ISC_INTCMPBU Comparator B Up Interrupt 4 5 PWM_2_ISC_INTCNTLOAD Counter=Load Interrupt 1 2 PWM_2_ISC_INTCNTZERO Counter=0 Interrupt 0 1 2_LOAD PWM2 Load 0xD0 read-write n 0x0 0x0 PWM_2_LOAD_LOAD Counter Load Value 0 16 2_MINFLTPER PWM2 Minimum Fault Period 0xFC read-write n 0x0 0x0 PWM_2_MINFLTPER_MFP Minimum Fault Period 0 16 2_RIS PWM2 Raw Interrupt Status 0xC8 read-write n 0x0 0x0 PWM_2_RIS_INTCMPAD Comparator A Down Interrupt Status 3 4 PWM_2_RIS_INTCMPAU Comparator A Up Interrupt Status 2 3 PWM_2_RIS_INTCMPBD Comparator B Down Interrupt Status 5 6 PWM_2_RIS_INTCMPBU Comparator B Up Interrupt Status 4 5 PWM_2_RIS_INTCNTLOAD Counter=Load Interrupt Status 1 2 PWM_2_RIS_INTCNTZERO Counter=0 Interrupt Status 0 1 3_CMPA PWM3 Compare A 0x118 read-write n 0x0 0x0 PWM_3_CMPA_COMPA Comparator A Value 0 16 3_CMPB PWM3 Compare B 0x11C read-write n 0x0 0x0 PWM_3_CMPB_COMPB Comparator B Value 0 16 3_COUNT PWM3 Counter 0x114 read-write n 0x0 0x0 PWM_3_COUNT_COUNT Counter Value 0 16 3_CTL PWM3 Control 0x100 read-write n 0x0 0x0 PWM_3_CTL_CMPAUPD Comparator A Update Mode 4 5 PWM_3_CTL_CMPBUPD Comparator B Update Mode 5 6 PWM_3_CTL_DBCTLUPD PWMnDBCTL Update Mode 10 12 PWM_3_CTL_DBCTLUPD_I Immediate 0x0 PWM_3_CTL_DBCTLUPD_LS Locally Synchronized 0x2 PWM_3_CTL_DBCTLUPD_GS Globally Synchronized 0x3 PWM_3_CTL_DBFALLUPD PWMnDBFALL Update Mode 14 16 PWM_3_CTL_DBFALLUPD_I Immediate 0x0 PWM_3_CTL_DBFALLUPD_LS Locally Synchronized 0x2 PWM_3_CTL_DBFALLUPD_GS Globally Synchronized 0x3 PWM_3_CTL_DBRISEUPD PWMnDBRISE Update Mode 12 14 PWM_3_CTL_DBRISEUPD_I Immediate 0x0 PWM_3_CTL_DBRISEUPD_LS Locally Synchronized 0x2 PWM_3_CTL_DBRISEUPD_GS Globally Synchronized 0x3 PWM_3_CTL_DEBUG Debug Mode 2 3 PWM_3_CTL_ENABLE PWM Block Enable 0 1 PWM_3_CTL_FLTSRC Fault Condition Source 16 17 PWM_3_CTL_GENAUPD PWMnGENA Update Mode 6 8 PWM_3_CTL_GENAUPD_I Immediate 0x0 PWM_3_CTL_GENAUPD_LS Locally Synchronized 0x2 PWM_3_CTL_GENAUPD_GS Globally Synchronized 0x3 PWM_3_CTL_GENBUPD PWMnGENB Update Mode 8 10 PWM_3_CTL_GENBUPD_I Immediate 0x0 PWM_3_CTL_GENBUPD_LS Locally Synchronized 0x2 PWM_3_CTL_GENBUPD_GS Globally Synchronized 0x3 PWM_3_CTL_LATCH Latch Fault Input 18 19 PWM_3_CTL_LOADUPD Load Register Update Mode 3 4 PWM_3_CTL_MINFLTPER Minimum Fault Period 17 18 PWM_3_CTL_MODE Counter Mode 1 2 3_DBCTL PWM3 Dead-Band Control 0x128 read-write n 0x0 0x0 PWM_3_DBCTL_ENABLE Dead-Band Generator Enable 0 1 3_DBFALL PWM3 Dead-Band Falling-Edge-Delay 0x130 read-write n 0x0 0x0 PWM_3_DBFALL_FALLDELAY Dead-Band Fall Delay 0 12 3_DBRISE PWM3 Dead-Band Rising-Edge Delay 0x12C read-write n 0x0 0x0 PWM_3_DBRISE_RISEDELAY Dead-Band Rise Delay 0 12 3_FLTSEN PWM3 Fault Pin Logic Sense 0x980 read-write n 0x0 0x0 PWM_3_FLTSEN_FAULT0 Fault0 Sense 0 1 PWM_3_FLTSEN_FAULT1 Fault1 Sense 1 2 PWM_3_FLTSEN_FAULT2 Fault2 Sense 2 3 PWM_3_FLTSEN_FAULT3 Fault3 Sense 3 4 3_FLTSRC0 PWM3 Fault Source 0 0x134 read-write n 0x0 0x0 PWM_3_FLTSRC0_FAULT0 Fault0 Input 0 1 PWM_3_FLTSRC0_FAULT1 Fault1 Input 1 2 PWM_3_FLTSRC0_FAULT2 Fault2 Input 2 3 PWM_3_FLTSRC0_FAULT3 Fault3 Input 3 4 3_FLTSRC1 PWM3 Fault Source 1 0x138 read-write n 0x0 0x0 PWM_3_FLTSRC1_DCMP0 Digital Comparator 0 0 1 PWM_3_FLTSRC1_DCMP1 Digital Comparator 1 1 2 PWM_3_FLTSRC1_DCMP2 Digital Comparator 2 2 3 PWM_3_FLTSRC1_DCMP3 Digital Comparator 3 3 4 PWM_3_FLTSRC1_DCMP4 Digital Comparator 4 4 5 PWM_3_FLTSRC1_DCMP5 Digital Comparator 5 5 6 PWM_3_FLTSRC1_DCMP6 Digital Comparator 6 6 7 PWM_3_FLTSRC1_DCMP7 Digital Comparator 7 7 8 3_FLTSTAT0 PWM3 Fault Status 0 0x984 read-only n 0x0 0x0 PWM_3_FLTSTAT0_FAULT0 Fault Input 0 0 1 read-only PWM_3_FLTSTAT0_FAULT1 Fault Input 1 1 2 read-only PWM_3_FLTSTAT0_FAULT2 Fault Input 2 2 3 read-only PWM_3_FLTSTAT0_FAULT3 Fault Input 3 3 4 read-only 3_FLTSTAT1 PWM3 Fault Status 1 0x988 read-only n 0x0 0x0 PWM_3_FLTSTAT1_DCMP0 Digital Comparator 0 Trigger 0 1 read-only PWM_3_FLTSTAT1_DCMP1 Digital Comparator 1 Trigger 1 2 read-only PWM_3_FLTSTAT1_DCMP2 Digital Comparator 2 Trigger 2 3 read-only PWM_3_FLTSTAT1_DCMP3 Digital Comparator 3 Trigger 3 4 read-only PWM_3_FLTSTAT1_DCMP4 Digital Comparator 4 Trigger 4 5 read-only PWM_3_FLTSTAT1_DCMP5 Digital Comparator 5 Trigger 5 6 read-only PWM_3_FLTSTAT1_DCMP6 Digital Comparator 6 Trigger 6 7 read-only PWM_3_FLTSTAT1_DCMP7 Digital Comparator 7 Trigger 7 8 read-only 3_GENA PWM3 Generator A Control 0x120 read-write n 0x0 0x0 PWM_3_GENA_ACTCMPAD Action for Comparator A Down 6 8 PWM_3_GENA_ACTCMPAD_NONE Do nothing 0x0 PWM_3_GENA_ACTCMPAD_INV Invert pwmA 0x1 PWM_3_GENA_ACTCMPAD_ZERO Drive pwmA Low 0x2 PWM_3_GENA_ACTCMPAD_ONE Drive pwmA High 0x3 PWM_3_GENA_ACTCMPAU Action for Comparator A Up 4 6 PWM_3_GENA_ACTCMPAU_NONE Do nothing 0x0 PWM_3_GENA_ACTCMPAU_INV Invert pwmA 0x1 PWM_3_GENA_ACTCMPAU_ZERO Drive pwmA Low 0x2 PWM_3_GENA_ACTCMPAU_ONE Drive pwmA High 0x3 PWM_3_GENA_ACTCMPBD Action for Comparator B Down 10 12 PWM_3_GENA_ACTCMPBD_NONE Do nothing 0x0 PWM_3_GENA_ACTCMPBD_INV Invert pwmA 0x1 PWM_3_GENA_ACTCMPBD_ZERO Drive pwmA Low 0x2 PWM_3_GENA_ACTCMPBD_ONE Drive pwmA High 0x3 PWM_3_GENA_ACTCMPBU Action for Comparator B Up 8 10 PWM_3_GENA_ACTCMPBU_NONE Do nothing 0x0 PWM_3_GENA_ACTCMPBU_INV Invert pwmA 0x1 PWM_3_GENA_ACTCMPBU_ZERO Drive pwmA Low 0x2 PWM_3_GENA_ACTCMPBU_ONE Drive pwmA High 0x3 PWM_3_GENA_ACTLOAD Action for Counter=LOAD 2 4 PWM_3_GENA_ACTLOAD_NONE Do nothing 0x0 PWM_3_GENA_ACTLOAD_INV Invert pwmA 0x1 PWM_3_GENA_ACTLOAD_ZERO Drive pwmA Low 0x2 PWM_3_GENA_ACTLOAD_ONE Drive pwmA High 0x3 PWM_3_GENA_ACTZERO Action for Counter=0 0 2 PWM_3_GENA_ACTZERO_NONE Do nothing 0x0 PWM_3_GENA_ACTZERO_INV Invert pwmA 0x1 PWM_3_GENA_ACTZERO_ZERO Drive pwmA Low 0x2 PWM_3_GENA_ACTZERO_ONE Drive pwmA High 0x3 3_GENB PWM3 Generator B Control 0x124 read-write n 0x0 0x0 PWM_3_GENB_ACTCMPAD Action for Comparator A Down 6 8 PWM_3_GENB_ACTCMPAD_NONE Do nothing 0x0 PWM_3_GENB_ACTCMPAD_INV Invert pwmB 0x1 PWM_3_GENB_ACTCMPAD_ZERO Drive pwmB Low 0x2 PWM_3_GENB_ACTCMPAD_ONE Drive pwmB High 0x3 PWM_3_GENB_ACTCMPAU Action for Comparator A Up 4 6 PWM_3_GENB_ACTCMPAU_NONE Do nothing 0x0 PWM_3_GENB_ACTCMPAU_INV Invert pwmB 0x1 PWM_3_GENB_ACTCMPAU_ZERO Drive pwmB Low 0x2 PWM_3_GENB_ACTCMPAU_ONE Drive pwmB High 0x3 PWM_3_GENB_ACTCMPBD Action for Comparator B Down 10 12 PWM_3_GENB_ACTCMPBD_NONE Do nothing 0x0 PWM_3_GENB_ACTCMPBD_INV Invert pwmB 0x1 PWM_3_GENB_ACTCMPBD_ZERO Drive pwmB Low 0x2 PWM_3_GENB_ACTCMPBD_ONE Drive pwmB High 0x3 PWM_3_GENB_ACTCMPBU Action for Comparator B Up 8 10 PWM_3_GENB_ACTCMPBU_NONE Do nothing 0x0 PWM_3_GENB_ACTCMPBU_INV Invert pwmB 0x1 PWM_3_GENB_ACTCMPBU_ZERO Drive pwmB Low 0x2 PWM_3_GENB_ACTCMPBU_ONE Drive pwmB High 0x3 PWM_3_GENB_ACTLOAD Action for Counter=LOAD 2 4 PWM_3_GENB_ACTLOAD_NONE Do nothing 0x0 PWM_3_GENB_ACTLOAD_INV Invert pwmB 0x1 PWM_3_GENB_ACTLOAD_ZERO Drive pwmB Low 0x2 PWM_3_GENB_ACTLOAD_ONE Drive pwmB High 0x3 PWM_3_GENB_ACTZERO Action for Counter=0 0 2 PWM_3_GENB_ACTZERO_NONE Do nothing 0x0 PWM_3_GENB_ACTZERO_INV Invert pwmB 0x1 PWM_3_GENB_ACTZERO_ZERO Drive pwmB Low 0x2 PWM_3_GENB_ACTZERO_ONE Drive pwmB High 0x3 3_INTEN PWM3 Interrupt and Trigger Enable 0x104 read-write n 0x0 0x0 PWM_3_INTEN_INTCMPAD Interrupt for Counter=PWMnCMPA Down 3 4 PWM_3_INTEN_INTCMPAU Interrupt for Counter=PWMnCMPA Up 2 3 PWM_3_INTEN_INTCMPBD Interrupt for Counter=PWMnCMPB Down 5 6 PWM_3_INTEN_INTCMPBU Interrupt for Counter=PWMnCMPB Up 4 5 PWM_3_INTEN_INTCNTLOAD Interrupt for Counter=PWMnLOAD 1 2 PWM_3_INTEN_INTCNTZERO Interrupt for Counter=0 0 1 PWM_3_INTEN_TRCMPAD Trigger for Counter=PWMnCMPA Down 11 12 PWM_3_INTEN_TRCMPAU Trigger for Counter=PWMnCMPA Up 10 11 PWM_3_INTEN_TRCMPBD Trigger for Counter=PWMnCMPB Down 13 14 PWM_3_INTEN_TRCMPBU Trigger for Counter=PWMnCMPB Up 12 13 PWM_3_INTEN_TRCNTLOAD Trigger for Counter=PWMnLOAD 9 10 PWM_3_INTEN_TRCNTZERO Trigger for Counter=0 8 9 3_ISC PWM3 Interrupt Status and Clear 0x10C read-write n 0x0 0x0 PWM_3_ISC_INTCMPAD Comparator A Down Interrupt 3 4 PWM_3_ISC_INTCMPAU Comparator A Up Interrupt 2 3 PWM_3_ISC_INTCMPBD Comparator B Down Interrupt 5 6 PWM_3_ISC_INTCMPBU Comparator B Up Interrupt 4 5 PWM_3_ISC_INTCNTLOAD Counter=Load Interrupt 1 2 PWM_3_ISC_INTCNTZERO Counter=0 Interrupt 0 1 3_LOAD PWM3 Load 0x110 read-write n 0x0 0x0 PWM_3_LOAD_LOAD Counter Load Value 0 16 3_MINFLTPER PWM3 Minimum Fault Period 0x13C read-write n 0x0 0x0 PWM_3_MINFLTPER_MFP Minimum Fault Period 0 16 3_RIS PWM3 Raw Interrupt Status 0x108 read-write n 0x0 0x0 PWM_3_RIS_INTCMPAD Comparator A Down Interrupt Status 3 4 PWM_3_RIS_INTCMPAU Comparator A Up Interrupt Status 2 3 PWM_3_RIS_INTCMPBD Comparator B Down Interrupt Status 5 6 PWM_3_RIS_INTCMPBU Comparator B Up Interrupt Status 4 5 PWM_3_RIS_INTCNTLOAD Counter=Load Interrupt Status 1 2 PWM_3_RIS_INTCNTZERO Counter=0 Interrupt Status 0 1 CC PWM Clock Configuration 0xFC8 -1 read-write n 0x0 0x0 PWM_CC_PWMDIV PWM Clock Divider 0 3 PWM_CC_PWMDIV_2 /2 0x0 PWM_CC_PWMDIV_4 /4 0x1 PWM_CC_PWMDIV_8 /8 0x2 PWM_CC_PWMDIV_16 /16 0x3 PWM_CC_PWMDIV_32 /32 0x4 PWM_CC_PWMDIV_64 /64 0x5 PWM_CC_USEPWM Use PWM Clock Divisor 8 9 CTL PWM Master Control 0x0 -1 read-write n 0x0 0x0 PWM_CTL_GLOBALSYNC0 Update PWM Generator 0 0 1 PWM_CTL_GLOBALSYNC1 Update PWM Generator 1 1 2 PWM_CTL_GLOBALSYNC2 Update PWM Generator 2 2 3 PWM_CTL_GLOBALSYNC3 Update PWM Generator 3 3 4 ENABLE PWM Output Enable 0x8 -1 read-write n 0x0 0x0 PWM_ENABLE_PWM0EN MnPWM0 Output Enable 0 1 PWM_ENABLE_PWM1EN MnPWM1 Output Enable 1 2 PWM_ENABLE_PWM2EN MnPWM2 Output Enable 2 3 PWM_ENABLE_PWM3EN MnPWM3 Output Enable 3 4 PWM_ENABLE_PWM4EN MnPWM4 Output Enable 4 5 PWM_ENABLE_PWM5EN MnPWM5 Output Enable 5 6 PWM_ENABLE_PWM6EN MnPWM6 Output Enable 6 7 PWM_ENABLE_PWM7EN MnPWM7 Output Enable 7 8 ENUPD PWM Enable Update 0x28 -1 read-write n 0x0 0x0 PWM_ENUPD_ENUPD0 MnPWM0 Enable Update Mode 0 2 PWM_ENUPD_ENUPD0_IMM Immediate 0x0 PWM_ENUPD_ENUPD0_LSYNC Locally Synchronized 0x2 PWM_ENUPD_ENUPD0_GSYNC Globally Synchronized 0x3 PWM_ENUPD_ENUPD1 MnPWM1 Enable Update Mode 2 4 PWM_ENUPD_ENUPD1_IMM Immediate 0x0 PWM_ENUPD_ENUPD1_LSYNC Locally Synchronized 0x2 PWM_ENUPD_ENUPD1_GSYNC Globally Synchronized 0x3 PWM_ENUPD_ENUPD2 MnPWM2 Enable Update Mode 4 6 PWM_ENUPD_ENUPD2_IMM Immediate 0x0 PWM_ENUPD_ENUPD2_LSYNC Locally Synchronized 0x2 PWM_ENUPD_ENUPD2_GSYNC Globally Synchronized 0x3 PWM_ENUPD_ENUPD3 MnPWM3 Enable Update Mode 6 8 PWM_ENUPD_ENUPD3_IMM Immediate 0x0 PWM_ENUPD_ENUPD3_LSYNC Locally Synchronized 0x2 PWM_ENUPD_ENUPD3_GSYNC Globally Synchronized 0x3 PWM_ENUPD_ENUPD4 MnPWM4 Enable Update Mode 8 10 PWM_ENUPD_ENUPD4_IMM Immediate 0x0 PWM_ENUPD_ENUPD4_LSYNC Locally Synchronized 0x2 PWM_ENUPD_ENUPD4_GSYNC Globally Synchronized 0x3 PWM_ENUPD_ENUPD5 MnPWM5 Enable Update Mode 10 12 PWM_ENUPD_ENUPD5_IMM Immediate 0x0 PWM_ENUPD_ENUPD5_LSYNC Locally Synchronized 0x2 PWM_ENUPD_ENUPD5_GSYNC Globally Synchronized 0x3 PWM_ENUPD_ENUPD6 MnPWM6 Enable Update Mode 12 14 PWM_ENUPD_ENUPD6_IMM Immediate 0x0 PWM_ENUPD_ENUPD6_LSYNC Locally Synchronized 0x2 PWM_ENUPD_ENUPD6_GSYNC Globally Synchronized 0x3 PWM_ENUPD_ENUPD7 MnPWM7 Enable Update Mode 14 16 PWM_ENUPD_ENUPD7_IMM Immediate 0x0 PWM_ENUPD_ENUPD7_LSYNC Locally Synchronized 0x2 PWM_ENUPD_ENUPD7_GSYNC Globally Synchronized 0x3 FAULT PWM Output Fault 0x10 -1 read-write n 0x0 0x0 PWM_FAULT_FAULT0 MnPWM0 Fault 0 1 PWM_FAULT_FAULT1 MnPWM1 Fault 1 2 PWM_FAULT_FAULT2 MnPWM2 Fault 2 3 PWM_FAULT_FAULT3 MnPWM3 Fault 3 4 PWM_FAULT_FAULT4 MnPWM4 Fault 4 5 PWM_FAULT_FAULT5 MnPWM5 Fault 5 6 PWM_FAULT_FAULT6 MnPWM6 Fault 6 7 PWM_FAULT_FAULT7 MnPWM7 Fault 7 8 FAULTVAL PWM Fault Condition Value 0x24 -1 read-write n 0x0 0x0 PWM_FAULTVAL_PWM0 MnPWM0 Fault Value 0 1 PWM_FAULTVAL_PWM1 MnPWM1 Fault Value 1 2 PWM_FAULTVAL_PWM2 MnPWM2 Fault Value 2 3 PWM_FAULTVAL_PWM3 MnPWM3 Fault Value 3 4 PWM_FAULTVAL_PWM4 MnPWM4 Fault Value 4 5 PWM_FAULTVAL_PWM5 MnPWM5 Fault Value 5 6 PWM_FAULTVAL_PWM6 MnPWM6 Fault Value 6 7 PWM_FAULTVAL_PWM7 MnPWM7 Fault Value 7 8 INTEN PWM Interrupt Enable 0x14 -1 read-write n 0x0 0x0 PWM_INTEN_INTFAULT0 Interrupt Fault 0 16 17 PWM_INTEN_INTFAULT1 Interrupt Fault 1 17 18 PWM_INTEN_INTFAULT2 Interrupt Fault 2 18 19 PWM_INTEN_INTFAULT3 Interrupt Fault 3 19 20 PWM_INTEN_INTPWM0 PWM0 Interrupt Enable 0 1 PWM_INTEN_INTPWM1 PWM1 Interrupt Enable 1 2 PWM_INTEN_INTPWM2 PWM2 Interrupt Enable 2 3 PWM_INTEN_INTPWM3 PWM3 Interrupt Enable 3 4 INVERT PWM Output Inversion 0xC -1 read-write n 0x0 0x0 PWM_INVERT_PWM0INV Invert MnPWM0 Signal 0 1 PWM_INVERT_PWM1INV Invert MnPWM1 Signal 1 2 PWM_INVERT_PWM2INV Invert MnPWM2 Signal 2 3 PWM_INVERT_PWM3INV Invert MnPWM3 Signal 3 4 PWM_INVERT_PWM4INV Invert MnPWM4 Signal 4 5 PWM_INVERT_PWM5INV Invert MnPWM5 Signal 5 6 PWM_INVERT_PWM6INV Invert MnPWM6 Signal 6 7 PWM_INVERT_PWM7INV Invert MnPWM7 Signal 7 8 ISC PWM Interrupt Status and Clear 0x1C -1 read-write n 0x0 0x0 PWM_ISC_INTFAULT0 FAULT0 Interrupt Asserted 16 17 PWM_ISC_INTFAULT1 FAULT1 Interrupt Asserted 17 18 PWM_ISC_INTFAULT2 FAULT2 Interrupt Asserted 18 19 PWM_ISC_INTFAULT3 FAULT3 Interrupt Asserted 19 20 PWM_ISC_INTPWM0 PWM0 Interrupt Status 0 1 PWM_ISC_INTPWM1 PWM1 Interrupt Status 1 2 PWM_ISC_INTPWM2 PWM2 Interrupt Status 2 3 PWM_ISC_INTPWM3 PWM3 Interrupt Status 3 4 PP PWM Peripheral Properties 0xFC0 -1 read-write n 0x0 0x0 PWM_PP_EFAULT Extended Fault 9 10 PWM_PP_ESYNC Extended Synchronization 8 9 PWM_PP_FCNT Fault Inputs (per PWM unit) 4 8 PWM_PP_GCNT Generators 0 4 PWM_PP_ONE One-Shot Mode 10 11 PWM0CC PWM Clock Configuration 0xFC8 read-write n 0x0 0x0 PWM_CC_PWMDIV PWM Clock Divider 0 3 PWM_CC_PWMDIV_2 /2 0x0 PWM_CC_PWMDIV_4 /4 0x1 PWM_CC_PWMDIV_8 /8 0x2 PWM_CC_PWMDIV_16 /16 0x3 PWM_CC_PWMDIV_32 /32 0x4 PWM_CC_PWMDIV_64 /64 0x5 PWM_CC_USEPWM Use PWM Clock Divisor 8 9 PWM0CTL PWM Master Control 0x0 read-write n 0x0 0x0 PWM_CTL_GLOBALSYNC0 Update PWM Generator 0 0 1 PWM_CTL_GLOBALSYNC1 Update PWM Generator 1 1 2 PWM_CTL_GLOBALSYNC2 Update PWM Generator 2 2 3 PWM_CTL_GLOBALSYNC3 Update PWM Generator 3 3 4 PWM0ENABLE PWM Output Enable 0x8 read-write n 0x0 0x0 PWM_ENABLE_PWM0EN MnPWM0 Output Enable 0 1 PWM_ENABLE_PWM1EN MnPWM1 Output Enable 1 2 PWM_ENABLE_PWM2EN MnPWM2 Output Enable 2 3 PWM_ENABLE_PWM3EN MnPWM3 Output Enable 3 4 PWM_ENABLE_PWM4EN MnPWM4 Output Enable 4 5 PWM_ENABLE_PWM5EN MnPWM5 Output Enable 5 6 PWM_ENABLE_PWM6EN MnPWM6 Output Enable 6 7 PWM_ENABLE_PWM7EN MnPWM7 Output Enable 7 8 PWM0ENUPD PWM Enable Update 0x28 read-write n 0x0 0x0 PWM_ENUPD_ENUPD0 MnPWM0 Enable Update Mode 0 2 PWM_ENUPD_ENUPD0_IMM Immediate 0x0 PWM_ENUPD_ENUPD0_LSYNC Locally Synchronized 0x2 PWM_ENUPD_ENUPD0_GSYNC Globally Synchronized 0x3 PWM_ENUPD_ENUPD1 MnPWM1 Enable Update Mode 2 4 PWM_ENUPD_ENUPD1_IMM Immediate 0x0 PWM_ENUPD_ENUPD1_LSYNC Locally Synchronized 0x2 PWM_ENUPD_ENUPD1_GSYNC Globally Synchronized 0x3 PWM_ENUPD_ENUPD2 MnPWM2 Enable Update Mode 4 6 PWM_ENUPD_ENUPD2_IMM Immediate 0x0 PWM_ENUPD_ENUPD2_LSYNC Locally Synchronized 0x2 PWM_ENUPD_ENUPD2_GSYNC Globally Synchronized 0x3 PWM_ENUPD_ENUPD3 MnPWM3 Enable Update Mode 6 8 PWM_ENUPD_ENUPD3_IMM Immediate 0x0 PWM_ENUPD_ENUPD3_LSYNC Locally Synchronized 0x2 PWM_ENUPD_ENUPD3_GSYNC Globally Synchronized 0x3 PWM_ENUPD_ENUPD4 MnPWM4 Enable Update Mode 8 10 PWM_ENUPD_ENUPD4_IMM Immediate 0x0 PWM_ENUPD_ENUPD4_LSYNC Locally Synchronized 0x2 PWM_ENUPD_ENUPD4_GSYNC Globally Synchronized 0x3 PWM_ENUPD_ENUPD5 MnPWM5 Enable Update Mode 10 12 PWM_ENUPD_ENUPD5_IMM Immediate 0x0 PWM_ENUPD_ENUPD5_LSYNC Locally Synchronized 0x2 PWM_ENUPD_ENUPD5_GSYNC Globally Synchronized 0x3 PWM_ENUPD_ENUPD6 MnPWM6 Enable Update Mode 12 14 PWM_ENUPD_ENUPD6_IMM Immediate 0x0 PWM_ENUPD_ENUPD6_LSYNC Locally Synchronized 0x2 PWM_ENUPD_ENUPD6_GSYNC Globally Synchronized 0x3 PWM_ENUPD_ENUPD7 MnPWM7 Enable Update Mode 14 16 PWM_ENUPD_ENUPD7_IMM Immediate 0x0 PWM_ENUPD_ENUPD7_LSYNC Locally Synchronized 0x2 PWM_ENUPD_ENUPD7_GSYNC Globally Synchronized 0x3 PWM0FAULT PWM Output Fault 0x10 read-write n 0x0 0x0 PWM_FAULT_FAULT0 MnPWM0 Fault 0 1 PWM_FAULT_FAULT1 MnPWM1 Fault 1 2 PWM_FAULT_FAULT2 MnPWM2 Fault 2 3 PWM_FAULT_FAULT3 MnPWM3 Fault 3 4 PWM_FAULT_FAULT4 MnPWM4 Fault 4 5 PWM_FAULT_FAULT5 MnPWM5 Fault 5 6 PWM_FAULT_FAULT6 MnPWM6 Fault 6 7 PWM_FAULT_FAULT7 MnPWM7 Fault 7 8 PWM0FAULTVAL PWM Fault Condition Value 0x24 read-write n 0x0 0x0 PWM_FAULTVAL_PWM0 MnPWM0 Fault Value 0 1 PWM_FAULTVAL_PWM1 MnPWM1 Fault Value 1 2 PWM_FAULTVAL_PWM2 MnPWM2 Fault Value 2 3 PWM_FAULTVAL_PWM3 MnPWM3 Fault Value 3 4 PWM_FAULTVAL_PWM4 MnPWM4 Fault Value 4 5 PWM_FAULTVAL_PWM5 MnPWM5 Fault Value 5 6 PWM_FAULTVAL_PWM6 MnPWM6 Fault Value 6 7 PWM_FAULTVAL_PWM7 MnPWM7 Fault Value 7 8 PWM0INTEN PWM Interrupt Enable 0x14 read-write n 0x0 0x0 PWM_INTEN_INTFAULT0 Interrupt Fault 0 16 17 PWM_INTEN_INTFAULT1 Interrupt Fault 1 17 18 PWM_INTEN_INTFAULT2 Interrupt Fault 2 18 19 PWM_INTEN_INTFAULT3 Interrupt Fault 3 19 20 PWM_INTEN_INTPWM0 PWM0 Interrupt Enable 0 1 PWM_INTEN_INTPWM1 PWM1 Interrupt Enable 1 2 PWM_INTEN_INTPWM2 PWM2 Interrupt Enable 2 3 PWM_INTEN_INTPWM3 PWM3 Interrupt Enable 3 4 PWM0INVERT PWM Output Inversion 0xC read-write n 0x0 0x0 PWM_INVERT_PWM0INV Invert MnPWM0 Signal 0 1 PWM_INVERT_PWM1INV Invert MnPWM1 Signal 1 2 PWM_INVERT_PWM2INV Invert MnPWM2 Signal 2 3 PWM_INVERT_PWM3INV Invert MnPWM3 Signal 3 4 PWM_INVERT_PWM4INV Invert MnPWM4 Signal 4 5 PWM_INVERT_PWM5INV Invert MnPWM5 Signal 5 6 PWM_INVERT_PWM6INV Invert MnPWM6 Signal 6 7 PWM_INVERT_PWM7INV Invert MnPWM7 Signal 7 8 PWM0ISC PWM Interrupt Status and Clear 0x1C read-write n 0x0 0x0 PWM_ISC_INTFAULT0 FAULT0 Interrupt Asserted 16 17 PWM_ISC_INTFAULT1 FAULT1 Interrupt Asserted 17 18 PWM_ISC_INTFAULT2 FAULT2 Interrupt Asserted 18 19 PWM_ISC_INTFAULT3 FAULT3 Interrupt Asserted 19 20 PWM_ISC_INTPWM0 PWM0 Interrupt Status 0 1 PWM_ISC_INTPWM1 PWM1 Interrupt Status 1 2 PWM_ISC_INTPWM2 PWM2 Interrupt Status 2 3 PWM_ISC_INTPWM3 PWM3 Interrupt Status 3 4 PWM0PP PWM Peripheral Properties 0xFC0 read-write n 0x0 0x0 PWM_PP_EFAULT Extended Fault 9 10 PWM_PP_ESYNC Extended Synchronization 8 9 PWM_PP_FCNT Fault Inputs (per PWM unit) 4 8 PWM_PP_GCNT Generators 0 4 PWM_PP_ONE One-Shot Mode 10 11 PWM0RIS PWM Raw Interrupt Status 0x18 read-write n 0x0 0x0 PWM_RIS_INTFAULT0 Interrupt Fault PWM 0 16 17 PWM_RIS_INTFAULT1 Interrupt Fault PWM 1 17 18 PWM_RIS_INTFAULT2 Interrupt Fault PWM 2 18 19 PWM_RIS_INTFAULT3 Interrupt Fault PWM 3 19 20 PWM_RIS_INTPWM0 PWM0 Interrupt Asserted 0 1 PWM_RIS_INTPWM1 PWM1 Interrupt Asserted 1 2 PWM_RIS_INTPWM2 PWM2 Interrupt Asserted 2 3 PWM_RIS_INTPWM3 PWM3 Interrupt Asserted 3 4 PWM0STATUS PWM Status 0x20 read-write n 0x0 0x0 PWM_STATUS_FAULT0 Generator 0 Fault Status 0 1 PWM_STATUS_FAULT1 Generator 1 Fault Status 1 2 PWM_STATUS_FAULT2 Generator 2 Fault Status 2 3 PWM_STATUS_FAULT3 Generator 3 Fault Status 3 4 PWM0SYNC PWM Time Base Sync 0x4 read-write n 0x0 0x0 PWM_SYNC_SYNC0 Reset Generator 0 Counter 0 1 PWM_SYNC_SYNC1 Reset Generator 1 Counter 1 2 PWM_SYNC_SYNC2 Reset Generator 2 Counter 2 3 PWM_SYNC_SYNC3 Reset Generator 3 Counter 3 4 RIS PWM Raw Interrupt Status 0x18 -1 read-write n 0x0 0x0 PWM_RIS_INTFAULT0 Interrupt Fault PWM 0 16 17 PWM_RIS_INTFAULT1 Interrupt Fault PWM 1 17 18 PWM_RIS_INTFAULT2 Interrupt Fault PWM 2 18 19 PWM_RIS_INTFAULT3 Interrupt Fault PWM 3 19 20 PWM_RIS_INTPWM0 PWM0 Interrupt Asserted 0 1 PWM_RIS_INTPWM1 PWM1 Interrupt Asserted 1 2 PWM_RIS_INTPWM2 PWM2 Interrupt Asserted 2 3 PWM_RIS_INTPWM3 PWM3 Interrupt Asserted 3 4 STATUS PWM Status 0x20 -1 read-write n 0x0 0x0 PWM_STATUS_FAULT0 Generator 0 Fault Status 0 1 PWM_STATUS_FAULT1 Generator 1 Fault Status 1 2 PWM_STATUS_FAULT2 Generator 2 Fault Status 2 3 PWM_STATUS_FAULT3 Generator 3 Fault Status 3 4 SYNC PWM Time Base Sync 0x4 -1 read-write n 0x0 0x0 PWM_SYNC_SYNC0 Reset Generator 0 Counter 0 1 PWM_SYNC_SYNC1 Reset Generator 1 Counter 1 2 PWM_SYNC_SYNC2 Reset Generator 2 Counter 2 3 PWM_SYNC_SYNC3 Reset Generator 3 Counter 3 4 _0_CMPA PWM0 Compare A 0x58 -1 read-write n 0x0 0x0 PWM_0_CMPA Comparator A Value 0 16 _0_CMPB PWM0 Compare B 0x5C -1 read-write n 0x0 0x0 PWM_0_CMPB Comparator B Value 0 16 _0_COUNT PWM0 Counter 0x54 -1 read-write n 0x0 0x0 PWM_0_COUNT Counter Value 0 16 _0_CTL PWM0 Control 0x40 -1 read-write n 0x0 0x0 PWM_0_CTL_CMPAUPD Comparator A Update Mode 4 5 PWM_0_CTL_CMPBUPD Comparator B Update Mode 5 6 PWM_0_CTL_DBCTLUPD PWMnDBCTL Update Mode 10 12 PWM_0_CTL_DBCTLUPD_I Immediate 0x0 PWM_0_CTL_DBCTLUPD_LS Locally Synchronized 0x2 PWM_0_CTL_DBCTLUPD_GS Globally Synchronized 0x3 PWM_0_CTL_DBFALLUPD PWMnDBFALL Update Mode 14 16 PWM_0_CTL_DBFALLUPD_I Immediate 0x0 PWM_0_CTL_DBFALLUPD_LS Locally Synchronized 0x2 PWM_0_CTL_DBFALLUPD_GS Globally Synchronized 0x3 PWM_0_CTL_DBRISEUPD PWMnDBRISE Update Mode 12 14 PWM_0_CTL_DBRISEUPD_I Immediate 0x0 PWM_0_CTL_DBRISEUPD_LS Locally Synchronized 0x2 PWM_0_CTL_DBRISEUPD_GS Globally Synchronized 0x3 PWM_0_CTL_DEBUG Debug Mode 2 3 PWM_0_CTL_ENABLE PWM Block Enable 0 1 PWM_0_CTL_FLTSRC Fault Condition Source 16 17 PWM_0_CTL_GENAUPD PWMnGENA Update Mode 6 8 PWM_0_CTL_GENAUPD_I Immediate 0x0 PWM_0_CTL_GENAUPD_LS Locally Synchronized 0x2 PWM_0_CTL_GENAUPD_GS Globally Synchronized 0x3 PWM_0_CTL_GENBUPD PWMnGENB Update Mode 8 10 PWM_0_CTL_GENBUPD_I Immediate 0x0 PWM_0_CTL_GENBUPD_LS Locally Synchronized 0x2 PWM_0_CTL_GENBUPD_GS Globally Synchronized 0x3 PWM_0_CTL_LATCH Latch Fault Input 18 19 PWM_0_CTL_LOADUPD Load Register Update Mode 3 4 PWM_0_CTL_MINFLTPER Minimum Fault Period 17 18 PWM_0_CTL_MODE Counter Mode 1 2 _0_DBCTL PWM0 Dead-Band Control 0x68 -1 read-write n 0x0 0x0 PWM_0_DBCTL_ENABLE Dead-Band Generator Enable 0 1 _0_DBFALL PWM0 Dead-Band Falling-Edge-Delay 0x70 -1 read-write n 0x0 0x0 PWM_0_DBFALL_DELAY Dead-Band Fall Delay 0 12 _0_DBRISE PWM0 Dead-Band Rising-Edge Delay 0x6C -1 read-write n 0x0 0x0 PWM_0_DBRISE_DELAY Dead-Band Rise Delay 0 12 _0_FLTSEN PWM0 Fault Pin Logic Sense 0x800 -1 read-write n 0x0 0x0 PWM_0_FLTSEN_FAULT0 Fault0 Sense 0 1 PWM_0_FLTSEN_FAULT1 Fault1 Sense 1 2 PWM_0_FLTSEN_FAULT2 Fault2 Sense 2 3 PWM_0_FLTSEN_FAULT3 Fault3 Sense 3 4 _0_FLTSRC0 PWM0 Fault Source 0 0x74 -1 read-write n 0x0 0x0 PWM_0_FLTSRC0_FAULT0 Fault0 Input 0 1 PWM_0_FLTSRC0_FAULT1 Fault1 Input 1 2 PWM_0_FLTSRC0_FAULT2 Fault2 Input 2 3 PWM_0_FLTSRC0_FAULT3 Fault3 Input 3 4 _0_FLTSRC1 PWM0 Fault Source 1 0x78 -1 read-write n 0x0 0x0 PWM_0_FLTSRC1_DCMP0 Digital Comparator 0 0 1 PWM_0_FLTSRC1_DCMP1 Digital Comparator 1 1 2 PWM_0_FLTSRC1_DCMP2 Digital Comparator 2 2 3 PWM_0_FLTSRC1_DCMP3 Digital Comparator 3 3 4 PWM_0_FLTSRC1_DCMP4 Digital Comparator 4 4 5 PWM_0_FLTSRC1_DCMP5 Digital Comparator 5 5 6 PWM_0_FLTSRC1_DCMP6 Digital Comparator 6 6 7 PWM_0_FLTSRC1_DCMP7 Digital Comparator 7 7 8 _0_FLTSTAT0 PWM0 Fault Status 0 0x804 -1 read-only n 0x0 0x0 PWM_0_FLTSTAT0_FAULT0 Fault Input 0 0 1 read-only PWM_0_FLTSTAT0_FAULT1 Fault Input 1 1 2 read-only PWM_0_FLTSTAT0_FAULT2 Fault Input 2 2 3 read-only PWM_0_FLTSTAT0_FAULT3 Fault Input 3 3 4 read-only _0_FLTSTAT1 PWM0 Fault Status 1 0x808 -1 read-only n 0x0 0x0 PWM_0_FLTSTAT1_DCMP0 Digital Comparator 0 Trigger 0 1 read-only PWM_0_FLTSTAT1_DCMP1 Digital Comparator 1 Trigger 1 2 read-only PWM_0_FLTSTAT1_DCMP2 Digital Comparator 2 Trigger 2 3 read-only PWM_0_FLTSTAT1_DCMP3 Digital Comparator 3 Trigger 3 4 read-only PWM_0_FLTSTAT1_DCMP4 Digital Comparator 4 Trigger 4 5 read-only PWM_0_FLTSTAT1_DCMP5 Digital Comparator 5 Trigger 5 6 read-only PWM_0_FLTSTAT1_DCMP6 Digital Comparator 6 Trigger 6 7 read-only PWM_0_FLTSTAT1_DCMP7 Digital Comparator 7 Trigger 7 8 read-only _0_GENA PWM0 Generator A Control 0x60 -1 read-write n 0x0 0x0 PWM_0_GENA_ACTCMPAD Action for Comparator A Down 6 8 PWM_0_GENA_ACTCMPAD_NONE Do nothing 0x0 PWM_0_GENA_ACTCMPAD_INV Invert pwmA 0x1 PWM_0_GENA_ACTCMPAD_ZERO Drive pwmA Low 0x2 PWM_0_GENA_ACTCMPAD_ONE Drive pwmA High 0x3 PWM_0_GENA_ACTCMPAU Action for Comparator A Up 4 6 PWM_0_GENA_ACTCMPAU_NONE Do nothing 0x0 PWM_0_GENA_ACTCMPAU_INV Invert pwmA 0x1 PWM_0_GENA_ACTCMPAU_ZERO Drive pwmA Low 0x2 PWM_0_GENA_ACTCMPAU_ONE Drive pwmA High 0x3 PWM_0_GENA_ACTCMPBD Action for Comparator B Down 10 12 PWM_0_GENA_ACTCMPBD_NONE Do nothing 0x0 PWM_0_GENA_ACTCMPBD_INV Invert pwmA 0x1 PWM_0_GENA_ACTCMPBD_ZERO Drive pwmA Low 0x2 PWM_0_GENA_ACTCMPBD_ONE Drive pwmA High 0x3 PWM_0_GENA_ACTCMPBU Action for Comparator B Up 8 10 PWM_0_GENA_ACTCMPBU_NONE Do nothing 0x0 PWM_0_GENA_ACTCMPBU_INV Invert pwmA 0x1 PWM_0_GENA_ACTCMPBU_ZERO Drive pwmA Low 0x2 PWM_0_GENA_ACTCMPBU_ONE Drive pwmA High 0x3 PWM_0_GENA_ACTLOAD Action for Counter=LOAD 2 4 PWM_0_GENA_ACTLOAD_NONE Do nothing 0x0 PWM_0_GENA_ACTLOAD_INV Invert pwmA 0x1 PWM_0_GENA_ACTLOAD_ZERO Drive pwmA Low 0x2 PWM_0_GENA_ACTLOAD_ONE Drive pwmA High 0x3 PWM_0_GENA_ACTZERO Action for Counter=0 0 2 PWM_0_GENA_ACTZERO_NONE Do nothing 0x0 PWM_0_GENA_ACTZERO_INV Invert pwmA 0x1 PWM_0_GENA_ACTZERO_ZERO Drive pwmA Low 0x2 PWM_0_GENA_ACTZERO_ONE Drive pwmA High 0x3 _0_GENB PWM0 Generator B Control 0x64 -1 read-write n 0x0 0x0 PWM_0_GENB_ACTCMPAD Action for Comparator A Down 6 8 PWM_0_GENB_ACTCMPAD_NONE Do nothing 0x0 PWM_0_GENB_ACTCMPAD_INV Invert pwmB 0x1 PWM_0_GENB_ACTCMPAD_ZERO Drive pwmB Low 0x2 PWM_0_GENB_ACTCMPAD_ONE Drive pwmB High 0x3 PWM_0_GENB_ACTCMPAU Action for Comparator A Up 4 6 PWM_0_GENB_ACTCMPAU_NONE Do nothing 0x0 PWM_0_GENB_ACTCMPAU_INV Invert pwmB 0x1 PWM_0_GENB_ACTCMPAU_ZERO Drive pwmB Low 0x2 PWM_0_GENB_ACTCMPAU_ONE Drive pwmB High 0x3 PWM_0_GENB_ACTCMPBD Action for Comparator B Down 10 12 PWM_0_GENB_ACTCMPBD_NONE Do nothing 0x0 PWM_0_GENB_ACTCMPBD_INV Invert pwmB 0x1 PWM_0_GENB_ACTCMPBD_ZERO Drive pwmB Low 0x2 PWM_0_GENB_ACTCMPBD_ONE Drive pwmB High 0x3 PWM_0_GENB_ACTCMPBU Action for Comparator B Up 8 10 PWM_0_GENB_ACTCMPBU_NONE Do nothing 0x0 PWM_0_GENB_ACTCMPBU_INV Invert pwmB 0x1 PWM_0_GENB_ACTCMPBU_ZERO Drive pwmB Low 0x2 PWM_0_GENB_ACTCMPBU_ONE Drive pwmB High 0x3 PWM_0_GENB_ACTLOAD Action for Counter=LOAD 2 4 PWM_0_GENB_ACTLOAD_NONE Do nothing 0x0 PWM_0_GENB_ACTLOAD_INV Invert pwmB 0x1 PWM_0_GENB_ACTLOAD_ZERO Drive pwmB Low 0x2 PWM_0_GENB_ACTLOAD_ONE Drive pwmB High 0x3 PWM_0_GENB_ACTZERO Action for Counter=0 0 2 PWM_0_GENB_ACTZERO_NONE Do nothing 0x0 PWM_0_GENB_ACTZERO_INV Invert pwmB 0x1 PWM_0_GENB_ACTZERO_ZERO Drive pwmB Low 0x2 PWM_0_GENB_ACTZERO_ONE Drive pwmB High 0x3 _0_INTEN PWM0 Interrupt and Trigger Enable 0x44 -1 read-write n 0x0 0x0 PWM_0_INTEN_INTCMPAD Interrupt for Counter=PWMnCMPA Down 3 4 PWM_0_INTEN_INTCMPAU Interrupt for Counter=PWMnCMPA Up 2 3 PWM_0_INTEN_INTCMPBD Interrupt for Counter=PWMnCMPB Down 5 6 PWM_0_INTEN_INTCMPBU Interrupt for Counter=PWMnCMPB Up 4 5 PWM_0_INTEN_INTCNTLOAD Interrupt for Counter=PWMnLOAD 1 2 PWM_0_INTEN_INTCNTZERO Interrupt for Counter=0 0 1 PWM_0_INTEN_TRCMPAD Trigger for Counter=PWMnCMPA Down 11 12 PWM_0_INTEN_TRCMPAU Trigger for Counter=PWMnCMPA Up 10 11 PWM_0_INTEN_TRCMPBD Trigger for Counter=PWMnCMPB Down 13 14 PWM_0_INTEN_TRCMPBU Trigger for Counter=PWMnCMPB Up 12 13 PWM_0_INTEN_TRCNTLOAD Trigger for Counter=PWMnLOAD 9 10 PWM_0_INTEN_TRCNTZERO Trigger for Counter=0 8 9 _0_ISC PWM0 Interrupt Status and Clear 0x4C -1 read-write n 0x0 0x0 PWM_0_ISC_INTCMPAD Comparator A Down Interrupt 3 4 PWM_0_ISC_INTCMPAU Comparator A Up Interrupt 2 3 PWM_0_ISC_INTCMPBD Comparator B Down Interrupt 5 6 PWM_0_ISC_INTCMPBU Comparator B Up Interrupt 4 5 PWM_0_ISC_INTCNTLOAD Counter=Load Interrupt 1 2 PWM_0_ISC_INTCNTZERO Counter=0 Interrupt 0 1 _0_LOAD PWM0 Load 0x50 -1 read-write n 0x0 0x0 PWM_0_LOAD Counter Load Value 0 16 _0_MINFLTPER PWM0 Minimum Fault Period 0x7C -1 read-write n 0x0 0x0 PWM_0_MINFLTPER Minimum Fault Period 0 16 _0_RIS PWM0 Raw Interrupt Status 0x48 -1 read-write n 0x0 0x0 PWM_0_RIS_INTCMPAD Comparator A Down Interrupt Status 3 4 PWM_0_RIS_INTCMPAU Comparator A Up Interrupt Status 2 3 PWM_0_RIS_INTCMPBD Comparator B Down Interrupt Status 5 6 PWM_0_RIS_INTCMPBU Comparator B Up Interrupt Status 4 5 PWM_0_RIS_INTCNTLOAD Counter=Load Interrupt Status 1 2 PWM_0_RIS_INTCNTZERO Counter=0 Interrupt Status 0 1 _1_CMPA PWM1 Compare A 0x98 -1 read-write n 0x0 0x0 PWM_1_CMPA_COMPA Comparator A Value 0 16 _1_CMPB PWM1 Compare B 0x9C -1 read-write n 0x0 0x0 PWM_1_CMPB_COMPB Comparator B Value 0 16 _1_COUNT PWM1 Counter 0x94 -1 read-write n 0x0 0x0 PWM_1_COUNT_COUNT Counter Value 0 16 _1_CTL PWM1 Control 0x80 -1 read-write n 0x0 0x0 PWM_1_CTL_CMPAUPD Comparator A Update Mode 4 5 PWM_1_CTL_CMPBUPD Comparator B Update Mode 5 6 PWM_1_CTL_DBCTLUPD PWMnDBCTL Update Mode 10 12 PWM_1_CTL_DBCTLUPD_I Immediate 0x0 PWM_1_CTL_DBCTLUPD_LS Locally Synchronized 0x2 PWM_1_CTL_DBCTLUPD_GS Globally Synchronized 0x3 PWM_1_CTL_DBFALLUPD PWMnDBFALL Update Mode 14 16 PWM_1_CTL_DBFALLUPD_I Immediate 0x0 PWM_1_CTL_DBFALLUPD_LS Locally Synchronized 0x2 PWM_1_CTL_DBFALLUPD_GS Globally Synchronized 0x3 PWM_1_CTL_DBRISEUPD PWMnDBRISE Update Mode 12 14 PWM_1_CTL_DBRISEUPD_I Immediate 0x0 PWM_1_CTL_DBRISEUPD_LS Locally Synchronized 0x2 PWM_1_CTL_DBRISEUPD_GS Globally Synchronized 0x3 PWM_1_CTL_DEBUG Debug Mode 2 3 PWM_1_CTL_ENABLE PWM Block Enable 0 1 PWM_1_CTL_FLTSRC Fault Condition Source 16 17 PWM_1_CTL_GENAUPD PWMnGENA Update Mode 6 8 PWM_1_CTL_GENAUPD_I Immediate 0x0 PWM_1_CTL_GENAUPD_LS Locally Synchronized 0x2 PWM_1_CTL_GENAUPD_GS Globally Synchronized 0x3 PWM_1_CTL_GENBUPD PWMnGENB Update Mode 8 10 PWM_1_CTL_GENBUPD_I Immediate 0x0 PWM_1_CTL_GENBUPD_LS Locally Synchronized 0x2 PWM_1_CTL_GENBUPD_GS Globally Synchronized 0x3 PWM_1_CTL_LATCH Latch Fault Input 18 19 PWM_1_CTL_LOADUPD Load Register Update Mode 3 4 PWM_1_CTL_MINFLTPER Minimum Fault Period 17 18 PWM_1_CTL_MODE Counter Mode 1 2 _1_DBCTL PWM1 Dead-Band Control 0xA8 -1 read-write n 0x0 0x0 PWM_1_DBCTL_ENABLE Dead-Band Generator Enable 0 1 _1_DBFALL PWM1 Dead-Band Falling-Edge-Delay 0xB0 -1 read-write n 0x0 0x0 PWM_1_DBFALL_FALLDELAY Dead-Band Fall Delay 0 12 _1_DBRISE PWM1 Dead-Band Rising-Edge Delay 0xAC -1 read-write n 0x0 0x0 PWM_1_DBRISE_RISEDELAY Dead-Band Rise Delay 0 12 _1_FLTSEN PWM1 Fault Pin Logic Sense 0x880 -1 read-write n 0x0 0x0 PWM_1_FLTSEN_FAULT0 Fault0 Sense 0 1 PWM_1_FLTSEN_FAULT1 Fault1 Sense 1 2 PWM_1_FLTSEN_FAULT2 Fault2 Sense 2 3 PWM_1_FLTSEN_FAULT3 Fault3 Sense 3 4 _1_FLTSRC0 PWM1 Fault Source 0 0xB4 -1 read-write n 0x0 0x0 PWM_1_FLTSRC0_FAULT0 Fault0 Input 0 1 PWM_1_FLTSRC0_FAULT1 Fault1 Input 1 2 PWM_1_FLTSRC0_FAULT2 Fault2 Input 2 3 PWM_1_FLTSRC0_FAULT3 Fault3 Input 3 4 _1_FLTSRC1 PWM1 Fault Source 1 0xB8 -1 read-write n 0x0 0x0 PWM_1_FLTSRC1_DCMP0 Digital Comparator 0 0 1 PWM_1_FLTSRC1_DCMP1 Digital Comparator 1 1 2 PWM_1_FLTSRC1_DCMP2 Digital Comparator 2 2 3 PWM_1_FLTSRC1_DCMP3 Digital Comparator 3 3 4 PWM_1_FLTSRC1_DCMP4 Digital Comparator 4 4 5 PWM_1_FLTSRC1_DCMP5 Digital Comparator 5 5 6 PWM_1_FLTSRC1_DCMP6 Digital Comparator 6 6 7 PWM_1_FLTSRC1_DCMP7 Digital Comparator 7 7 8 _1_FLTSTAT0 PWM1 Fault Status 0 0x884 -1 read-only n 0x0 0x0 PWM_1_FLTSTAT0_FAULT0 Fault Input 0 0 1 read-only PWM_1_FLTSTAT0_FAULT1 Fault Input 1 1 2 read-only PWM_1_FLTSTAT0_FAULT2 Fault Input 2 2 3 read-only PWM_1_FLTSTAT0_FAULT3 Fault Input 3 3 4 read-only _1_FLTSTAT1 PWM1 Fault Status 1 0x888 -1 read-only n 0x0 0x0 PWM_1_FLTSTAT1_DCMP0 Digital Comparator 0 Trigger 0 1 read-only PWM_1_FLTSTAT1_DCMP1 Digital Comparator 1 Trigger 1 2 read-only PWM_1_FLTSTAT1_DCMP2 Digital Comparator 2 Trigger 2 3 read-only PWM_1_FLTSTAT1_DCMP3 Digital Comparator 3 Trigger 3 4 read-only PWM_1_FLTSTAT1_DCMP4 Digital Comparator 4 Trigger 4 5 read-only PWM_1_FLTSTAT1_DCMP5 Digital Comparator 5 Trigger 5 6 read-only PWM_1_FLTSTAT1_DCMP6 Digital Comparator 6 Trigger 6 7 read-only PWM_1_FLTSTAT1_DCMP7 Digital Comparator 7 Trigger 7 8 read-only _1_GENA PWM1 Generator A Control 0xA0 -1 read-write n 0x0 0x0 PWM_1_GENA_ACTCMPAD Action for Comparator A Down 6 8 PWM_1_GENA_ACTCMPAD_NONE Do nothing 0x0 PWM_1_GENA_ACTCMPAD_INV Invert pwmA 0x1 PWM_1_GENA_ACTCMPAD_ZERO Drive pwmA Low 0x2 PWM_1_GENA_ACTCMPAD_ONE Drive pwmA High 0x3 PWM_1_GENA_ACTCMPAU Action for Comparator A Up 4 6 PWM_1_GENA_ACTCMPAU_NONE Do nothing 0x0 PWM_1_GENA_ACTCMPAU_INV Invert pwmA 0x1 PWM_1_GENA_ACTCMPAU_ZERO Drive pwmA Low 0x2 PWM_1_GENA_ACTCMPAU_ONE Drive pwmA High 0x3 PWM_1_GENA_ACTCMPBD Action for Comparator B Down 10 12 PWM_1_GENA_ACTCMPBD_NONE Do nothing 0x0 PWM_1_GENA_ACTCMPBD_INV Invert pwmA 0x1 PWM_1_GENA_ACTCMPBD_ZERO Drive pwmA Low 0x2 PWM_1_GENA_ACTCMPBD_ONE Drive pwmA High 0x3 PWM_1_GENA_ACTCMPBU Action for Comparator B Up 8 10 PWM_1_GENA_ACTCMPBU_NONE Do nothing 0x0 PWM_1_GENA_ACTCMPBU_INV Invert pwmA 0x1 PWM_1_GENA_ACTCMPBU_ZERO Drive pwmA Low 0x2 PWM_1_GENA_ACTCMPBU_ONE Drive pwmA High 0x3 PWM_1_GENA_ACTLOAD Action for Counter=LOAD 2 4 PWM_1_GENA_ACTLOAD_NONE Do nothing 0x0 PWM_1_GENA_ACTLOAD_INV Invert pwmA 0x1 PWM_1_GENA_ACTLOAD_ZERO Drive pwmA Low 0x2 PWM_1_GENA_ACTLOAD_ONE Drive pwmA High 0x3 PWM_1_GENA_ACTZERO Action for Counter=0 0 2 PWM_1_GENA_ACTZERO_NONE Do nothing 0x0 PWM_1_GENA_ACTZERO_INV Invert pwmA 0x1 PWM_1_GENA_ACTZERO_ZERO Drive pwmA Low 0x2 PWM_1_GENA_ACTZERO_ONE Drive pwmA High 0x3 _1_GENB PWM1 Generator B Control 0xA4 -1 read-write n 0x0 0x0 PWM_1_GENB_ACTCMPAD Action for Comparator A Down 6 8 PWM_1_GENB_ACTCMPAD_NONE Do nothing 0x0 PWM_1_GENB_ACTCMPAD_INV Invert pwmB 0x1 PWM_1_GENB_ACTCMPAD_ZERO Drive pwmB Low 0x2 PWM_1_GENB_ACTCMPAD_ONE Drive pwmB High 0x3 PWM_1_GENB_ACTCMPAU Action for Comparator A Up 4 6 PWM_1_GENB_ACTCMPAU_NONE Do nothing 0x0 PWM_1_GENB_ACTCMPAU_INV Invert pwmB 0x1 PWM_1_GENB_ACTCMPAU_ZERO Drive pwmB Low 0x2 PWM_1_GENB_ACTCMPAU_ONE Drive pwmB High 0x3 PWM_1_GENB_ACTCMPBD Action for Comparator B Down 10 12 PWM_1_GENB_ACTCMPBD_NONE Do nothing 0x0 PWM_1_GENB_ACTCMPBD_INV Invert pwmB 0x1 PWM_1_GENB_ACTCMPBD_ZERO Drive pwmB Low 0x2 PWM_1_GENB_ACTCMPBD_ONE Drive pwmB High 0x3 PWM_1_GENB_ACTCMPBU Action for Comparator B Up 8 10 PWM_1_GENB_ACTCMPBU_NONE Do nothing 0x0 PWM_1_GENB_ACTCMPBU_INV Invert pwmB 0x1 PWM_1_GENB_ACTCMPBU_ZERO Drive pwmB Low 0x2 PWM_1_GENB_ACTCMPBU_ONE Drive pwmB High 0x3 PWM_1_GENB_ACTLOAD Action for Counter=LOAD 2 4 PWM_1_GENB_ACTLOAD_NONE Do nothing 0x0 PWM_1_GENB_ACTLOAD_INV Invert pwmB 0x1 PWM_1_GENB_ACTLOAD_ZERO Drive pwmB Low 0x2 PWM_1_GENB_ACTLOAD_ONE Drive pwmB High 0x3 PWM_1_GENB_ACTZERO Action for Counter=0 0 2 PWM_1_GENB_ACTZERO_NONE Do nothing 0x0 PWM_1_GENB_ACTZERO_INV Invert pwmB 0x1 PWM_1_GENB_ACTZERO_ZERO Drive pwmB Low 0x2 PWM_1_GENB_ACTZERO_ONE Drive pwmB High 0x3 _1_INTEN PWM1 Interrupt and Trigger Enable 0x84 -1 read-write n 0x0 0x0 PWM_1_INTEN_INTCMPAD Interrupt for Counter=PWMnCMPA Down 3 4 PWM_1_INTEN_INTCMPAU Interrupt for Counter=PWMnCMPA Up 2 3 PWM_1_INTEN_INTCMPBD Interrupt for Counter=PWMnCMPB Down 5 6 PWM_1_INTEN_INTCMPBU Interrupt for Counter=PWMnCMPB Up 4 5 PWM_1_INTEN_INTCNTLOAD Interrupt for Counter=PWMnLOAD 1 2 PWM_1_INTEN_INTCNTZERO Interrupt for Counter=0 0 1 PWM_1_INTEN_TRCMPAD Trigger for Counter=PWMnCMPA Down 11 12 PWM_1_INTEN_TRCMPAU Trigger for Counter=PWMnCMPA Up 10 11 PWM_1_INTEN_TRCMPBD Trigger for Counter=PWMnCMPB Down 13 14 PWM_1_INTEN_TRCMPBU Trigger for Counter=PWMnCMPB Up 12 13 PWM_1_INTEN_TRCNTLOAD Trigger for Counter=PWMnLOAD 9 10 PWM_1_INTEN_TRCNTZERO Trigger for Counter=0 8 9 _1_ISC PWM1 Interrupt Status and Clear 0x8C -1 read-write n 0x0 0x0 PWM_1_ISC_INTCMPAD Comparator A Down Interrupt 3 4 PWM_1_ISC_INTCMPAU Comparator A Up Interrupt 2 3 PWM_1_ISC_INTCMPBD Comparator B Down Interrupt 5 6 PWM_1_ISC_INTCMPBU Comparator B Up Interrupt 4 5 PWM_1_ISC_INTCNTLOAD Counter=Load Interrupt 1 2 PWM_1_ISC_INTCNTZERO Counter=0 Interrupt 0 1 _1_LOAD PWM1 Load 0x90 -1 read-write n 0x0 0x0 PWM_1_LOAD_LOAD Counter Load Value 0 16 _1_MINFLTPER PWM1 Minimum Fault Period 0xBC -1 read-write n 0x0 0x0 PWM_1_MINFLTPER_MFP Minimum Fault Period 0 16 _1_RIS PWM1 Raw Interrupt Status 0x88 -1 read-write n 0x0 0x0 PWM_1_RIS_INTCMPAD Comparator A Down Interrupt Status 3 4 PWM_1_RIS_INTCMPAU Comparator A Up Interrupt Status 2 3 PWM_1_RIS_INTCMPBD Comparator B Down Interrupt Status 5 6 PWM_1_RIS_INTCMPBU Comparator B Up Interrupt Status 4 5 PWM_1_RIS_INTCNTLOAD Counter=Load Interrupt Status 1 2 PWM_1_RIS_INTCNTZERO Counter=0 Interrupt Status 0 1 _2_CMPA PWM2 Compare A 0xD8 -1 read-write n 0x0 0x0 PWM_2_CMPA_COMPA Comparator A Value 0 16 _2_CMPB PWM2 Compare B 0xDC -1 read-write n 0x0 0x0 PWM_2_CMPB_COMPB Comparator B Value 0 16 _2_COUNT PWM2 Counter 0xD4 -1 read-write n 0x0 0x0 PWM_2_COUNT_COUNT Counter Value 0 16 _2_CTL PWM2 Control 0xC0 -1 read-write n 0x0 0x0 PWM_2_CTL_CMPAUPD Comparator A Update Mode 4 5 PWM_2_CTL_CMPBUPD Comparator B Update Mode 5 6 PWM_2_CTL_DBCTLUPD PWMnDBCTL Update Mode 10 12 PWM_2_CTL_DBCTLUPD_I Immediate 0x0 PWM_2_CTL_DBCTLUPD_LS Locally Synchronized 0x2 PWM_2_CTL_DBCTLUPD_GS Globally Synchronized 0x3 PWM_2_CTL_DBFALLUPD PWMnDBFALL Update Mode 14 16 PWM_2_CTL_DBFALLUPD_I Immediate 0x0 PWM_2_CTL_DBFALLUPD_LS Locally Synchronized 0x2 PWM_2_CTL_DBFALLUPD_GS Globally Synchronized 0x3 PWM_2_CTL_DBRISEUPD PWMnDBRISE Update Mode 12 14 PWM_2_CTL_DBRISEUPD_I Immediate 0x0 PWM_2_CTL_DBRISEUPD_LS Locally Synchronized 0x2 PWM_2_CTL_DBRISEUPD_GS Globally Synchronized 0x3 PWM_2_CTL_DEBUG Debug Mode 2 3 PWM_2_CTL_ENABLE PWM Block Enable 0 1 PWM_2_CTL_FLTSRC Fault Condition Source 16 17 PWM_2_CTL_GENAUPD PWMnGENA Update Mode 6 8 PWM_2_CTL_GENAUPD_I Immediate 0x0 PWM_2_CTL_GENAUPD_LS Locally Synchronized 0x2 PWM_2_CTL_GENAUPD_GS Globally Synchronized 0x3 PWM_2_CTL_GENBUPD PWMnGENB Update Mode 8 10 PWM_2_CTL_GENBUPD_I Immediate 0x0 PWM_2_CTL_GENBUPD_LS Locally Synchronized 0x2 PWM_2_CTL_GENBUPD_GS Globally Synchronized 0x3 PWM_2_CTL_LATCH Latch Fault Input 18 19 PWM_2_CTL_LOADUPD Load Register Update Mode 3 4 PWM_2_CTL_MINFLTPER Minimum Fault Period 17 18 PWM_2_CTL_MODE Counter Mode 1 2 _2_DBCTL PWM2 Dead-Band Control 0xE8 -1 read-write n 0x0 0x0 PWM_2_DBCTL_ENABLE Dead-Band Generator Enable 0 1 _2_DBFALL PWM2 Dead-Band Falling-Edge-Delay 0xF0 -1 read-write n 0x0 0x0 PWM_2_DBFALL_FALLDELAY Dead-Band Fall Delay 0 12 _2_DBRISE PWM2 Dead-Band Rising-Edge Delay 0xEC -1 read-write n 0x0 0x0 PWM_2_DBRISE_RISEDELAY Dead-Band Rise Delay 0 12 _2_FLTSEN PWM2 Fault Pin Logic Sense 0x900 -1 read-write n 0x0 0x0 PWM_2_FLTSEN_FAULT0 Fault0 Sense 0 1 PWM_2_FLTSEN_FAULT1 Fault1 Sense 1 2 PWM_2_FLTSEN_FAULT2 Fault2 Sense 2 3 PWM_2_FLTSEN_FAULT3 Fault3 Sense 3 4 _2_FLTSRC0 PWM2 Fault Source 0 0xF4 -1 read-write n 0x0 0x0 PWM_2_FLTSRC0_FAULT0 Fault0 Input 0 1 PWM_2_FLTSRC0_FAULT1 Fault1 Input 1 2 PWM_2_FLTSRC0_FAULT2 Fault2 Input 2 3 PWM_2_FLTSRC0_FAULT3 Fault3 Input 3 4 _2_FLTSRC1 PWM2 Fault Source 1 0xF8 -1 read-write n 0x0 0x0 PWM_2_FLTSRC1_DCMP0 Digital Comparator 0 0 1 PWM_2_FLTSRC1_DCMP1 Digital Comparator 1 1 2 PWM_2_FLTSRC1_DCMP2 Digital Comparator 2 2 3 PWM_2_FLTSRC1_DCMP3 Digital Comparator 3 3 4 PWM_2_FLTSRC1_DCMP4 Digital Comparator 4 4 5 PWM_2_FLTSRC1_DCMP5 Digital Comparator 5 5 6 PWM_2_FLTSRC1_DCMP6 Digital Comparator 6 6 7 PWM_2_FLTSRC1_DCMP7 Digital Comparator 7 7 8 _2_FLTSTAT0 PWM2 Fault Status 0 0x904 -1 read-only n 0x0 0x0 PWM_2_FLTSTAT0_FAULT0 Fault Input 0 0 1 read-only PWM_2_FLTSTAT0_FAULT1 Fault Input 1 1 2 read-only PWM_2_FLTSTAT0_FAULT2 Fault Input 2 2 3 read-only PWM_2_FLTSTAT0_FAULT3 Fault Input 3 3 4 read-only _2_FLTSTAT1 PWM2 Fault Status 1 0x908 -1 read-only n 0x0 0x0 PWM_2_FLTSTAT1_DCMP0 Digital Comparator 0 Trigger 0 1 read-only PWM_2_FLTSTAT1_DCMP1 Digital Comparator 1 Trigger 1 2 read-only PWM_2_FLTSTAT1_DCMP2 Digital Comparator 2 Trigger 2 3 read-only PWM_2_FLTSTAT1_DCMP3 Digital Comparator 3 Trigger 3 4 read-only PWM_2_FLTSTAT1_DCMP4 Digital Comparator 4 Trigger 4 5 read-only PWM_2_FLTSTAT1_DCMP5 Digital Comparator 5 Trigger 5 6 read-only PWM_2_FLTSTAT1_DCMP6 Digital Comparator 6 Trigger 6 7 read-only PWM_2_FLTSTAT1_DCMP7 Digital Comparator 7 Trigger 7 8 read-only _2_GENA PWM2 Generator A Control 0xE0 -1 read-write n 0x0 0x0 PWM_2_GENA_ACTCMPAD Action for Comparator A Down 6 8 PWM_2_GENA_ACTCMPAD_NONE Do nothing 0x0 PWM_2_GENA_ACTCMPAD_INV Invert pwmA 0x1 PWM_2_GENA_ACTCMPAD_ZERO Drive pwmA Low 0x2 PWM_2_GENA_ACTCMPAD_ONE Drive pwmA High 0x3 PWM_2_GENA_ACTCMPAU Action for Comparator A Up 4 6 PWM_2_GENA_ACTCMPAU_NONE Do nothing 0x0 PWM_2_GENA_ACTCMPAU_INV Invert pwmA 0x1 PWM_2_GENA_ACTCMPAU_ZERO Drive pwmA Low 0x2 PWM_2_GENA_ACTCMPAU_ONE Drive pwmA High 0x3 PWM_2_GENA_ACTCMPBD Action for Comparator B Down 10 12 PWM_2_GENA_ACTCMPBD_NONE Do nothing 0x0 PWM_2_GENA_ACTCMPBD_INV Invert pwmA 0x1 PWM_2_GENA_ACTCMPBD_ZERO Drive pwmA Low 0x2 PWM_2_GENA_ACTCMPBD_ONE Drive pwmA High 0x3 PWM_2_GENA_ACTCMPBU Action for Comparator B Up 8 10 PWM_2_GENA_ACTCMPBU_NONE Do nothing 0x0 PWM_2_GENA_ACTCMPBU_INV Invert pwmA 0x1 PWM_2_GENA_ACTCMPBU_ZERO Drive pwmA Low 0x2 PWM_2_GENA_ACTCMPBU_ONE Drive pwmA High 0x3 PWM_2_GENA_ACTLOAD Action for Counter=LOAD 2 4 PWM_2_GENA_ACTLOAD_NONE Do nothing 0x0 PWM_2_GENA_ACTLOAD_INV Invert pwmA 0x1 PWM_2_GENA_ACTLOAD_ZERO Drive pwmA Low 0x2 PWM_2_GENA_ACTLOAD_ONE Drive pwmA High 0x3 PWM_2_GENA_ACTZERO Action for Counter=0 0 2 PWM_2_GENA_ACTZERO_NONE Do nothing 0x0 PWM_2_GENA_ACTZERO_INV Invert pwmA 0x1 PWM_2_GENA_ACTZERO_ZERO Drive pwmA Low 0x2 PWM_2_GENA_ACTZERO_ONE Drive pwmA High 0x3 _2_GENB PWM2 Generator B Control 0xE4 -1 read-write n 0x0 0x0 PWM_2_GENB_ACTCMPAD Action for Comparator A Down 6 8 PWM_2_GENB_ACTCMPAD_NONE Do nothing 0x0 PWM_2_GENB_ACTCMPAD_INV Invert pwmB 0x1 PWM_2_GENB_ACTCMPAD_ZERO Drive pwmB Low 0x2 PWM_2_GENB_ACTCMPAD_ONE Drive pwmB High 0x3 PWM_2_GENB_ACTCMPAU Action for Comparator A Up 4 6 PWM_2_GENB_ACTCMPAU_NONE Do nothing 0x0 PWM_2_GENB_ACTCMPAU_INV Invert pwmB 0x1 PWM_2_GENB_ACTCMPAU_ZERO Drive pwmB Low 0x2 PWM_2_GENB_ACTCMPAU_ONE Drive pwmB High 0x3 PWM_2_GENB_ACTCMPBD Action for Comparator B Down 10 12 PWM_2_GENB_ACTCMPBD_NONE Do nothing 0x0 PWM_2_GENB_ACTCMPBD_INV Invert pwmB 0x1 PWM_2_GENB_ACTCMPBD_ZERO Drive pwmB Low 0x2 PWM_2_GENB_ACTCMPBD_ONE Drive pwmB High 0x3 PWM_2_GENB_ACTCMPBU Action for Comparator B Up 8 10 PWM_2_GENB_ACTCMPBU_NONE Do nothing 0x0 PWM_2_GENB_ACTCMPBU_INV Invert pwmB 0x1 PWM_2_GENB_ACTCMPBU_ZERO Drive pwmB Low 0x2 PWM_2_GENB_ACTCMPBU_ONE Drive pwmB High 0x3 PWM_2_GENB_ACTLOAD Action for Counter=LOAD 2 4 PWM_2_GENB_ACTLOAD_NONE Do nothing 0x0 PWM_2_GENB_ACTLOAD_INV Invert pwmB 0x1 PWM_2_GENB_ACTLOAD_ZERO Drive pwmB Low 0x2 PWM_2_GENB_ACTLOAD_ONE Drive pwmB High 0x3 PWM_2_GENB_ACTZERO Action for Counter=0 0 2 PWM_2_GENB_ACTZERO_NONE Do nothing 0x0 PWM_2_GENB_ACTZERO_INV Invert pwmB 0x1 PWM_2_GENB_ACTZERO_ZERO Drive pwmB Low 0x2 PWM_2_GENB_ACTZERO_ONE Drive pwmB High 0x3 _2_INTEN PWM2 Interrupt and Trigger Enable 0xC4 -1 read-write n 0x0 0x0 PWM_2_INTEN_INTCMPAD Interrupt for Counter=PWMnCMPA Down 3 4 PWM_2_INTEN_INTCMPAU Interrupt for Counter=PWMnCMPA Up 2 3 PWM_2_INTEN_INTCMPBD Interrupt for Counter=PWMnCMPB Down 5 6 PWM_2_INTEN_INTCMPBU Interrupt for Counter=PWMnCMPB Up 4 5 PWM_2_INTEN_INTCNTLOAD Interrupt for Counter=PWMnLOAD 1 2 PWM_2_INTEN_INTCNTZERO Interrupt for Counter=0 0 1 PWM_2_INTEN_TRCMPAD Trigger for Counter=PWMnCMPA Down 11 12 PWM_2_INTEN_TRCMPAU Trigger for Counter=PWMnCMPA Up 10 11 PWM_2_INTEN_TRCMPBD Trigger for Counter=PWMnCMPB Down 13 14 PWM_2_INTEN_TRCMPBU Trigger for Counter=PWMnCMPB Up 12 13 PWM_2_INTEN_TRCNTLOAD Trigger for Counter=PWMnLOAD 9 10 PWM_2_INTEN_TRCNTZERO Trigger for Counter=0 8 9 _2_ISC PWM2 Interrupt Status and Clear 0xCC -1 read-write n 0x0 0x0 PWM_2_ISC_INTCMPAD Comparator A Down Interrupt 3 4 PWM_2_ISC_INTCMPAU Comparator A Up Interrupt 2 3 PWM_2_ISC_INTCMPBD Comparator B Down Interrupt 5 6 PWM_2_ISC_INTCMPBU Comparator B Up Interrupt 4 5 PWM_2_ISC_INTCNTLOAD Counter=Load Interrupt 1 2 PWM_2_ISC_INTCNTZERO Counter=0 Interrupt 0 1 _2_LOAD PWM2 Load 0xD0 -1 read-write n 0x0 0x0 PWM_2_LOAD_LOAD Counter Load Value 0 16 _2_MINFLTPER PWM2 Minimum Fault Period 0xFC -1 read-write n 0x0 0x0 PWM_2_MINFLTPER_MFP Minimum Fault Period 0 16 _2_RIS PWM2 Raw Interrupt Status 0xC8 -1 read-write n 0x0 0x0 PWM_2_RIS_INTCMPAD Comparator A Down Interrupt Status 3 4 PWM_2_RIS_INTCMPAU Comparator A Up Interrupt Status 2 3 PWM_2_RIS_INTCMPBD Comparator B Down Interrupt Status 5 6 PWM_2_RIS_INTCMPBU Comparator B Up Interrupt Status 4 5 PWM_2_RIS_INTCNTLOAD Counter=Load Interrupt Status 1 2 PWM_2_RIS_INTCNTZERO Counter=0 Interrupt Status 0 1 _3_CMPA PWM3 Compare A 0x118 -1 read-write n 0x0 0x0 PWM_3_CMPA_COMPA Comparator A Value 0 16 _3_CMPB PWM3 Compare B 0x11C -1 read-write n 0x0 0x0 PWM_3_CMPB_COMPB Comparator B Value 0 16 _3_COUNT PWM3 Counter 0x114 -1 read-write n 0x0 0x0 PWM_3_COUNT_COUNT Counter Value 0 16 _3_CTL PWM3 Control 0x100 -1 read-write n 0x0 0x0 PWM_3_CTL_CMPAUPD Comparator A Update Mode 4 5 PWM_3_CTL_CMPBUPD Comparator B Update Mode 5 6 PWM_3_CTL_DBCTLUPD PWMnDBCTL Update Mode 10 12 PWM_3_CTL_DBCTLUPD_I Immediate 0x0 PWM_3_CTL_DBCTLUPD_LS Locally Synchronized 0x2 PWM_3_CTL_DBCTLUPD_GS Globally Synchronized 0x3 PWM_3_CTL_DBFALLUPD PWMnDBFALL Update Mode 14 16 PWM_3_CTL_DBFALLUPD_I Immediate 0x0 PWM_3_CTL_DBFALLUPD_LS Locally Synchronized 0x2 PWM_3_CTL_DBFALLUPD_GS Globally Synchronized 0x3 PWM_3_CTL_DBRISEUPD PWMnDBRISE Update Mode 12 14 PWM_3_CTL_DBRISEUPD_I Immediate 0x0 PWM_3_CTL_DBRISEUPD_LS Locally Synchronized 0x2 PWM_3_CTL_DBRISEUPD_GS Globally Synchronized 0x3 PWM_3_CTL_DEBUG Debug Mode 2 3 PWM_3_CTL_ENABLE PWM Block Enable 0 1 PWM_3_CTL_FLTSRC Fault Condition Source 16 17 PWM_3_CTL_GENAUPD PWMnGENA Update Mode 6 8 PWM_3_CTL_GENAUPD_I Immediate 0x0 PWM_3_CTL_GENAUPD_LS Locally Synchronized 0x2 PWM_3_CTL_GENAUPD_GS Globally Synchronized 0x3 PWM_3_CTL_GENBUPD PWMnGENB Update Mode 8 10 PWM_3_CTL_GENBUPD_I Immediate 0x0 PWM_3_CTL_GENBUPD_LS Locally Synchronized 0x2 PWM_3_CTL_GENBUPD_GS Globally Synchronized 0x3 PWM_3_CTL_LATCH Latch Fault Input 18 19 PWM_3_CTL_LOADUPD Load Register Update Mode 3 4 PWM_3_CTL_MINFLTPER Minimum Fault Period 17 18 PWM_3_CTL_MODE Counter Mode 1 2 _3_DBCTL PWM3 Dead-Band Control 0x128 -1 read-write n 0x0 0x0 PWM_3_DBCTL_ENABLE Dead-Band Generator Enable 0 1 _3_DBFALL PWM3 Dead-Band Falling-Edge-Delay 0x130 -1 read-write n 0x0 0x0 PWM_3_DBFALL_FALLDELAY Dead-Band Fall Delay 0 12 _3_DBRISE PWM3 Dead-Band Rising-Edge Delay 0x12C -1 read-write n 0x0 0x0 PWM_3_DBRISE_RISEDELAY Dead-Band Rise Delay 0 12 _3_FLTSEN PWM3 Fault Pin Logic Sense 0x980 -1 read-write n 0x0 0x0 PWM_3_FLTSEN_FAULT0 Fault0 Sense 0 1 PWM_3_FLTSEN_FAULT1 Fault1 Sense 1 2 PWM_3_FLTSEN_FAULT2 Fault2 Sense 2 3 PWM_3_FLTSEN_FAULT3 Fault3 Sense 3 4 _3_FLTSRC0 PWM3 Fault Source 0 0x134 -1 read-write n 0x0 0x0 PWM_3_FLTSRC0_FAULT0 Fault0 Input 0 1 PWM_3_FLTSRC0_FAULT1 Fault1 Input 1 2 PWM_3_FLTSRC0_FAULT2 Fault2 Input 2 3 PWM_3_FLTSRC0_FAULT3 Fault3 Input 3 4 _3_FLTSRC1 PWM3 Fault Source 1 0x138 -1 read-write n 0x0 0x0 PWM_3_FLTSRC1_DCMP0 Digital Comparator 0 0 1 PWM_3_FLTSRC1_DCMP1 Digital Comparator 1 1 2 PWM_3_FLTSRC1_DCMP2 Digital Comparator 2 2 3 PWM_3_FLTSRC1_DCMP3 Digital Comparator 3 3 4 PWM_3_FLTSRC1_DCMP4 Digital Comparator 4 4 5 PWM_3_FLTSRC1_DCMP5 Digital Comparator 5 5 6 PWM_3_FLTSRC1_DCMP6 Digital Comparator 6 6 7 PWM_3_FLTSRC1_DCMP7 Digital Comparator 7 7 8 _3_FLTSTAT0 PWM3 Fault Status 0 0x984 -1 read-only n 0x0 0x0 PWM_3_FLTSTAT0_FAULT0 Fault Input 0 0 1 read-only PWM_3_FLTSTAT0_FAULT1 Fault Input 1 1 2 read-only PWM_3_FLTSTAT0_FAULT2 Fault Input 2 2 3 read-only PWM_3_FLTSTAT0_FAULT3 Fault Input 3 3 4 read-only _3_FLTSTAT1 PWM3 Fault Status 1 0x988 -1 read-only n 0x0 0x0 PWM_3_FLTSTAT1_DCMP0 Digital Comparator 0 Trigger 0 1 read-only PWM_3_FLTSTAT1_DCMP1 Digital Comparator 1 Trigger 1 2 read-only PWM_3_FLTSTAT1_DCMP2 Digital Comparator 2 Trigger 2 3 read-only PWM_3_FLTSTAT1_DCMP3 Digital Comparator 3 Trigger 3 4 read-only PWM_3_FLTSTAT1_DCMP4 Digital Comparator 4 Trigger 4 5 read-only PWM_3_FLTSTAT1_DCMP5 Digital Comparator 5 Trigger 5 6 read-only PWM_3_FLTSTAT1_DCMP6 Digital Comparator 6 Trigger 6 7 read-only PWM_3_FLTSTAT1_DCMP7 Digital Comparator 7 Trigger 7 8 read-only _3_GENA PWM3 Generator A Control 0x120 -1 read-write n 0x0 0x0 PWM_3_GENA_ACTCMPAD Action for Comparator A Down 6 8 PWM_3_GENA_ACTCMPAD_NONE Do nothing 0x0 PWM_3_GENA_ACTCMPAD_INV Invert pwmA 0x1 PWM_3_GENA_ACTCMPAD_ZERO Drive pwmA Low 0x2 PWM_3_GENA_ACTCMPAD_ONE Drive pwmA High 0x3 PWM_3_GENA_ACTCMPAU Action for Comparator A Up 4 6 PWM_3_GENA_ACTCMPAU_NONE Do nothing 0x0 PWM_3_GENA_ACTCMPAU_INV Invert pwmA 0x1 PWM_3_GENA_ACTCMPAU_ZERO Drive pwmA Low 0x2 PWM_3_GENA_ACTCMPAU_ONE Drive pwmA High 0x3 PWM_3_GENA_ACTCMPBD Action for Comparator B Down 10 12 PWM_3_GENA_ACTCMPBD_NONE Do nothing 0x0 PWM_3_GENA_ACTCMPBD_INV Invert pwmA 0x1 PWM_3_GENA_ACTCMPBD_ZERO Drive pwmA Low 0x2 PWM_3_GENA_ACTCMPBD_ONE Drive pwmA High 0x3 PWM_3_GENA_ACTCMPBU Action for Comparator B Up 8 10 PWM_3_GENA_ACTCMPBU_NONE Do nothing 0x0 PWM_3_GENA_ACTCMPBU_INV Invert pwmA 0x1 PWM_3_GENA_ACTCMPBU_ZERO Drive pwmA Low 0x2 PWM_3_GENA_ACTCMPBU_ONE Drive pwmA High 0x3 PWM_3_GENA_ACTLOAD Action for Counter=LOAD 2 4 PWM_3_GENA_ACTLOAD_NONE Do nothing 0x0 PWM_3_GENA_ACTLOAD_INV Invert pwmA 0x1 PWM_3_GENA_ACTLOAD_ZERO Drive pwmA Low 0x2 PWM_3_GENA_ACTLOAD_ONE Drive pwmA High 0x3 PWM_3_GENA_ACTZERO Action for Counter=0 0 2 PWM_3_GENA_ACTZERO_NONE Do nothing 0x0 PWM_3_GENA_ACTZERO_INV Invert pwmA 0x1 PWM_3_GENA_ACTZERO_ZERO Drive pwmA Low 0x2 PWM_3_GENA_ACTZERO_ONE Drive pwmA High 0x3 _3_GENB PWM3 Generator B Control 0x124 -1 read-write n 0x0 0x0 PWM_3_GENB_ACTCMPAD Action for Comparator A Down 6 8 PWM_3_GENB_ACTCMPAD_NONE Do nothing 0x0 PWM_3_GENB_ACTCMPAD_INV Invert pwmB 0x1 PWM_3_GENB_ACTCMPAD_ZERO Drive pwmB Low 0x2 PWM_3_GENB_ACTCMPAD_ONE Drive pwmB High 0x3 PWM_3_GENB_ACTCMPAU Action for Comparator A Up 4 6 PWM_3_GENB_ACTCMPAU_NONE Do nothing 0x0 PWM_3_GENB_ACTCMPAU_INV Invert pwmB 0x1 PWM_3_GENB_ACTCMPAU_ZERO Drive pwmB Low 0x2 PWM_3_GENB_ACTCMPAU_ONE Drive pwmB High 0x3 PWM_3_GENB_ACTCMPBD Action for Comparator B Down 10 12 PWM_3_GENB_ACTCMPBD_NONE Do nothing 0x0 PWM_3_GENB_ACTCMPBD_INV Invert pwmB 0x1 PWM_3_GENB_ACTCMPBD_ZERO Drive pwmB Low 0x2 PWM_3_GENB_ACTCMPBD_ONE Drive pwmB High 0x3 PWM_3_GENB_ACTCMPBU Action for Comparator B Up 8 10 PWM_3_GENB_ACTCMPBU_NONE Do nothing 0x0 PWM_3_GENB_ACTCMPBU_INV Invert pwmB 0x1 PWM_3_GENB_ACTCMPBU_ZERO Drive pwmB Low 0x2 PWM_3_GENB_ACTCMPBU_ONE Drive pwmB High 0x3 PWM_3_GENB_ACTLOAD Action for Counter=LOAD 2 4 PWM_3_GENB_ACTLOAD_NONE Do nothing 0x0 PWM_3_GENB_ACTLOAD_INV Invert pwmB 0x1 PWM_3_GENB_ACTLOAD_ZERO Drive pwmB Low 0x2 PWM_3_GENB_ACTLOAD_ONE Drive pwmB High 0x3 PWM_3_GENB_ACTZERO Action for Counter=0 0 2 PWM_3_GENB_ACTZERO_NONE Do nothing 0x0 PWM_3_GENB_ACTZERO_INV Invert pwmB 0x1 PWM_3_GENB_ACTZERO_ZERO Drive pwmB Low 0x2 PWM_3_GENB_ACTZERO_ONE Drive pwmB High 0x3 _3_INTEN PWM3 Interrupt and Trigger Enable 0x104 -1 read-write n 0x0 0x0 PWM_3_INTEN_INTCMPAD Interrupt for Counter=PWMnCMPA Down 3 4 PWM_3_INTEN_INTCMPAU Interrupt for Counter=PWMnCMPA Up 2 3 PWM_3_INTEN_INTCMPBD Interrupt for Counter=PWMnCMPB Down 5 6 PWM_3_INTEN_INTCMPBU Interrupt for Counter=PWMnCMPB Up 4 5 PWM_3_INTEN_INTCNTLOAD Interrupt for Counter=PWMnLOAD 1 2 PWM_3_INTEN_INTCNTZERO Interrupt for Counter=0 0 1 PWM_3_INTEN_TRCMPAD Trigger for Counter=PWMnCMPA Down 11 12 PWM_3_INTEN_TRCMPAU Trigger for Counter=PWMnCMPA Up 10 11 PWM_3_INTEN_TRCMPBD Trigger for Counter=PWMnCMPB Down 13 14 PWM_3_INTEN_TRCMPBU Trigger for Counter=PWMnCMPB Up 12 13 PWM_3_INTEN_TRCNTLOAD Trigger for Counter=PWMnLOAD 9 10 PWM_3_INTEN_TRCNTZERO Trigger for Counter=0 8 9 _3_ISC PWM3 Interrupt Status and Clear 0x10C -1 read-write n 0x0 0x0 PWM_3_ISC_INTCMPAD Comparator A Down Interrupt 3 4 PWM_3_ISC_INTCMPAU Comparator A Up Interrupt 2 3 PWM_3_ISC_INTCMPBD Comparator B Down Interrupt 5 6 PWM_3_ISC_INTCMPBU Comparator B Up Interrupt 4 5 PWM_3_ISC_INTCNTLOAD Counter=Load Interrupt 1 2 PWM_3_ISC_INTCNTZERO Counter=0 Interrupt 0 1 _3_LOAD PWM3 Load 0x110 -1 read-write n 0x0 0x0 PWM_3_LOAD_LOAD Counter Load Value 0 16 _3_MINFLTPER PWM3 Minimum Fault Period 0x13C -1 read-write n 0x0 0x0 PWM_3_MINFLTPER_MFP Minimum Fault Period 0 16 _3_RIS PWM3 Raw Interrupt Status 0x108 -1 read-write n 0x0 0x0 PWM_3_RIS_INTCMPAD Comparator A Down Interrupt Status 3 4 PWM_3_RIS_INTCMPAU Comparator A Up Interrupt Status 2 3 PWM_3_RIS_INTCMPBD Comparator B Down Interrupt Status 5 6 PWM_3_RIS_INTCMPBU Comparator B Up Interrupt Status 4 5 PWM_3_RIS_INTCNTLOAD Counter=Load Interrupt Status 1 2 PWM_3_RIS_INTCNTZERO Counter=0 Interrupt Status 0 1 QEI0 Register map for QEI0 peripheral QEI 0x0 0x0 0x1000 registers n QEI0 13 COUNT QEI Velocity Counter 0x18 -1 read-write n 0x0 0x0 QEI_COUNT Velocity Pulse Count 0 32 CTL QEI Control 0x0 -1 read-write n 0x0 0x0 QEI_CTL_CAPMODE Capture Mode 3 4 QEI_CTL_ENABLE Enable QEI 0 1 QEI_CTL_FILTCNT Input Filter Prescale Count 16 20 QEI_CTL_FILTEN Enable Input Filter 13 14 QEI_CTL_INVA Invert PhA 9 10 QEI_CTL_INVB Invert PhB 10 11 QEI_CTL_INVI Invert Index Pulse 11 12 QEI_CTL_RESMODE Reset Mode 4 5 QEI_CTL_SIGMODE Signal Mode 2 3 QEI_CTL_STALLEN Stall QEI 12 13 QEI_CTL_SWAP Swap Signals 1 2 QEI_CTL_VELDIV Predivide Velocity 6 9 QEI_CTL_VELDIV_1 QEI clock /1 0x0 QEI_CTL_VELDIV_2 QEI clock /2 0x1 QEI_CTL_VELDIV_4 QEI clock /4 0x2 QEI_CTL_VELDIV_8 QEI clock /8 0x3 QEI_CTL_VELDIV_16 QEI clock /16 0x4 QEI_CTL_VELDIV_32 QEI clock /32 0x5 QEI_CTL_VELDIV_64 QEI clock /64 0x6 QEI_CTL_VELDIV_128 QEI clock /128 0x7 QEI_CTL_VELEN Capture Velocity 5 6 INTEN QEI Interrupt Enable 0x20 -1 read-write n 0x0 0x0 QEI_INTEN_DIR Direction Change Interrupt Enable 2 3 QEI_INTEN_ERROR Phase Error Interrupt Enable 3 4 QEI_INTEN_INDEX Index Pulse Detected Interrupt Enable 0 1 QEI_INTEN_TIMER Timer Expires Interrupt Enable 1 2 ISC QEI Interrupt Status and Clear 0x28 -1 read-write n 0x0 0x0 QEI_ISC_DIR Direction Change Interrupt 2 3 QEI_ISC_ERROR Phase Error Interrupt 3 4 QEI_ISC_INDEX Index Pulse Interrupt 0 1 QEI_ISC_TIMER Velocity Timer Expired Interrupt 1 2 LOAD QEI Timer Load 0x10 -1 read-write n 0x0 0x0 QEI_LOAD Velocity Timer Load Value 0 32 MAXPOS QEI Maximum Position 0xC -1 read-write n 0x0 0x0 QEI_MAXPOS Maximum Position Integrator Value 0 32 POS QEI Position 0x8 -1 read-write n 0x0 0x0 QEI_POS Current Position Integrator Value 0 32 QEI0COUNT QEI Velocity Counter 0x18 read-write n 0x0 0x0 QEI_COUNT Velocity Pulse Count 0 32 QEI0CTL QEI Control 0x0 read-write n 0x0 0x0 QEI_CTL_CAPMODE Capture Mode 3 4 QEI_CTL_ENABLE Enable QEI 0 1 QEI_CTL_FILTCNT Input Filter Prescale Count 16 20 QEI_CTL_FILTEN Enable Input Filter 13 14 QEI_CTL_INVA Invert PhA 9 10 QEI_CTL_INVB Invert PhB 10 11 QEI_CTL_INVI Invert Index Pulse 11 12 QEI_CTL_RESMODE Reset Mode 4 5 QEI_CTL_SIGMODE Signal Mode 2 3 QEI_CTL_STALLEN Stall QEI 12 13 QEI_CTL_SWAP Swap Signals 1 2 QEI_CTL_VELDIV Predivide Velocity 6 9 QEI_CTL_VELDIV_1 QEI clock /1 0x0 QEI_CTL_VELDIV_2 QEI clock /2 0x1 QEI_CTL_VELDIV_4 QEI clock /4 0x2 QEI_CTL_VELDIV_8 QEI clock /8 0x3 QEI_CTL_VELDIV_16 QEI clock /16 0x4 QEI_CTL_VELDIV_32 QEI clock /32 0x5 QEI_CTL_VELDIV_64 QEI clock /64 0x6 QEI_CTL_VELDIV_128 QEI clock /128 0x7 QEI_CTL_VELEN Capture Velocity 5 6 QEI0INTEN QEI Interrupt Enable 0x20 read-write n 0x0 0x0 QEI_INTEN_DIR Direction Change Interrupt Enable 2 3 QEI_INTEN_ERROR Phase Error Interrupt Enable 3 4 QEI_INTEN_INDEX Index Pulse Detected Interrupt Enable 0 1 QEI_INTEN_TIMER Timer Expires Interrupt Enable 1 2 QEI0ISC QEI Interrupt Status and Clear 0x28 read-write n 0x0 0x0 QEI_ISC_DIR Direction Change Interrupt 2 3 QEI_ISC_ERROR Phase Error Interrupt 3 4 QEI_ISC_INDEX Index Pulse Interrupt 0 1 QEI_ISC_TIMER Velocity Timer Expired Interrupt 1 2 QEI0LOAD QEI Timer Load 0x10 read-write n 0x0 0x0 QEI_LOAD Velocity Timer Load Value 0 32 QEI0MAXPOS QEI Maximum Position 0xC read-write n 0x0 0x0 QEI_MAXPOS Maximum Position Integrator Value 0 32 QEI0POS QEI Position 0x8 read-write n 0x0 0x0 QEI_POS Current Position Integrator Value 0 32 QEI0RIS QEI Raw Interrupt Status 0x24 read-write n 0x0 0x0 QEI_RIS_DIR Direction Change Detected 2 3 QEI_RIS_ERROR Phase Error Detected 3 4 QEI_RIS_INDEX Index Pulse Asserted 0 1 QEI_RIS_TIMER Velocity Timer Expired 1 2 QEI0SPEED QEI Velocity 0x1C read-write n 0x0 0x0 QEI_SPEED Velocity 0 32 QEI0STAT QEI Status 0x4 read-write n 0x0 0x0 QEI_STAT_DIRECTION Direction of Rotation 1 2 QEI_STAT_ERROR Error Detected 0 1 QEI0TIME QEI Timer 0x14 read-write n 0x0 0x0 QEI_TIME Velocity Timer Current Value 0 32 RIS QEI Raw Interrupt Status 0x24 -1 read-write n 0x0 0x0 QEI_RIS_DIR Direction Change Detected 2 3 QEI_RIS_ERROR Phase Error Detected 3 4 QEI_RIS_INDEX Index Pulse Asserted 0 1 QEI_RIS_TIMER Velocity Timer Expired 1 2 SPEED QEI Velocity 0x1C -1 read-write n 0x0 0x0 QEI_SPEED Velocity 0 32 STAT QEI Status 0x4 -1 read-write n 0x0 0x0 QEI_STAT_DIRECTION Direction of Rotation 1 2 QEI_STAT_ERROR Error Detected 0 1 TIME QEI Timer 0x14 -1 read-write n 0x0 0x0 QEI_TIME Velocity Timer Current Value 0 32 SSI0 Register map for SSI0 peripheral SSI 0x0 0x0 0x1000 registers n SSI0 7 CC SSI Clock Configuration 0xFC8 -1 read-write n 0x0 0x0 SSI_CC_CS SSI Baud Clock Source 0 4 SSI_CC_CS_SYSPLL System clock (based on clock source and divisor factor) 0x0 SSI_CC_CS_PIOSC PIOSC 0x5 CPSR SSI Clock Prescale 0x10 -1 read-write n 0x0 0x0 SSI_CPSR_CPSDVSR SSI Clock Prescale Divisor 0 8 CR0 SSI Control 0 0x0 -1 read-write n 0x0 0x0 SSI_CR0_DSS SSI Data Size Select 0 4 SSI_CR0_DSS_4 4-bit data 0x3 SSI_CR0_DSS_5 5-bit data 0x4 SSI_CR0_DSS_6 6-bit data 0x5 SSI_CR0_DSS_7 7-bit data 0x6 SSI_CR0_DSS_8 8-bit data 0x7 SSI_CR0_DSS_9 9-bit data 0x8 SSI_CR0_DSS_10 10-bit data 0x9 SSI_CR0_DSS_11 11-bit data 0xa SSI_CR0_DSS_12 12-bit data 0xb SSI_CR0_DSS_13 13-bit data 0xc SSI_CR0_DSS_14 14-bit data 0xd SSI_CR0_DSS_15 15-bit data 0xe SSI_CR0_DSS_16 16-bit data 0xf SSI_CR0_FRF SSI Frame Format Select 4 6 SSI_CR0_FRF_MOTO Freescale SPI Frame Format 0x0 SSI_CR0_FRF_TI Synchronous Serial Frame Format 0x1 SSI_CR0_SCR SSI Serial Clock Rate 8 16 SSI_CR0_SPH SSI Serial Clock Phase 7 8 SSI_CR0_SPO SSI Serial Clock Polarity 6 7 CR1 SSI Control 1 0x4 -1 read-write n 0x0 0x0 SSI_CR1_DIR SSI Direction of Operation 8 9 SSI_CR1_EOM Stop Frame (End of Message) 11 12 SSI_CR1_EOT End of Transmission 4 5 SSI_CR1_FSSHLDFRM FSS Hold Frame 10 11 SSI_CR1_HSCLKEN High Speed Clock Enable 9 10 SSI_CR1_LBM SSI Loopback Mode 0 1 SSI_CR1_MODE SSI Mode 6 8 SSI_CR1_MODE_LEGACY Legacy SSI mode 0x0 SSI_CR1_MODE_BI Bi-SSI mode 0x1 SSI_CR1_MODE_QUAD Quad-SSI Mode 0x2 SSI_CR1_MODE_ADVANCED Advanced SSI Mode with 8-bit packet size 0x3 SSI_CR1_MS SSI Master/Slave Select 2 3 SSI_CR1_SSE SSI Synchronous Serial Port Enable 1 2 DMACTL SSI DMA Control 0x24 -1 read-write n 0x0 0x0 SSI_DMACTL_RXDMAE Receive DMA Enable 0 1 SSI_DMACTL_TXDMAE Transmit DMA Enable 1 2 DR SSI Data 0x8 -1 read-write n 0x0 0x0 SSI_DR_DATA SSI Receive/Transmit Data 0 16 ICR SSI Interrupt Clear 0x20 -1 write-only n 0x0 0x0 SSI_ICR_DMARXIC SSI Receive DMA Interrupt Clear 4 5 write-only SSI_ICR_DMATXIC SSI Transmit DMA Interrupt Clear 5 6 write-only SSI_ICR_EOTIC End of Transmit Interrupt Clear 6 7 write-only SSI_ICR_RORIC SSI Receive Overrun Interrupt Clear 0 1 write-only SSI_ICR_RTIC SSI Receive Time-Out Interrupt Clear 1 2 write-only IM SSI Interrupt Mask 0x14 -1 read-write n 0x0 0x0 SSI_IM_DMARXIM SSI Receive DMA Interrupt Mask 4 5 SSI_IM_DMATXIM SSI Transmit DMA Interrupt Mask 5 6 SSI_IM_EOTIM End of Transmit Interrupt Mask 6 7 SSI_IM_RORIM SSI Receive Overrun Interrupt Mask 0 1 SSI_IM_RTIM SSI Receive Time-Out Interrupt Mask 1 2 SSI_IM_RXIM SSI Receive FIFO Interrupt Mask 2 3 SSI_IM_TXIM SSI Transmit FIFO Interrupt Mask 3 4 MIS SSI Masked Interrupt Status 0x1C -1 read-write n 0x0 0x0 SSI_MIS_DMARXMIS SSI Receive DMA Masked Interrupt Status 4 5 SSI_MIS_DMATXMIS SSI Transmit DMA Masked Interrupt Status 5 6 SSI_MIS_EOTMIS End of Transmit Masked Interrupt Status 6 7 SSI_MIS_RORMIS SSI Receive Overrun Masked Interrupt Status 0 1 SSI_MIS_RTMIS SSI Receive Time-Out Masked Interrupt Status 1 2 SSI_MIS_RXMIS SSI Receive FIFO Masked Interrupt Status 2 3 SSI_MIS_TXMIS SSI Transmit FIFO Masked Interrupt Status 3 4 PP SSI Peripheral Properties 0xFC0 -1 read-write n 0x0 0x0 SSI_PP_FSSHLDFRM FSS Hold Frame Capability 3 4 SSI_PP_HSCLK High Speed Capability 0 1 SSI_PP_MODE Mode of Operation 1 3 SSI_PP_MODE_LEGACY Legacy SSI mode 0x0 SSI_PP_MODE_ADVBI Legacy mode, Advanced SSI mode and Bi-SSI mode enabled 0x1 SSI_PP_MODE_ADVBIQUAD Legacy mode, Advanced mode, Bi-SSI and Quad-SSI mode enabled 0x2 RIS SSI Raw Interrupt Status 0x18 -1 read-write n 0x0 0x0 SSI_RIS_DMARXRIS SSI Receive DMA Raw Interrupt Status 4 5 SSI_RIS_DMATXRIS SSI Transmit DMA Raw Interrupt Status 5 6 SSI_RIS_EOTRIS End of Transmit Raw Interrupt Status 6 7 SSI_RIS_RORRIS SSI Receive Overrun Raw Interrupt Status 0 1 SSI_RIS_RTRIS SSI Receive Time-Out Raw Interrupt Status 1 2 SSI_RIS_RXRIS SSI Receive FIFO Raw Interrupt Status 2 3 SSI_RIS_TXRIS SSI Transmit FIFO Raw Interrupt Status 3 4 SR SSI Status 0xC -1 read-write n 0x0 0x0 SSI_SR_BSY SSI Busy Bit 4 5 SSI_SR_RFF SSI Receive FIFO Full 3 4 SSI_SR_RNE SSI Receive FIFO Not Empty 2 3 SSI_SR_TFE SSI Transmit FIFO Empty 0 1 SSI_SR_TNF SSI Transmit FIFO Not Full 1 2 SSI0CC SSI Clock Configuration 0xFC8 read-write n 0x0 0x0 SSI_CC_CS SSI Baud Clock Source 0 4 SSI_CC_CS_SYSPLL System clock (based on clock source and divisor factor) 0x0 SSI_CC_CS_PIOSC PIOSC 0x5 SSI0CPSR SSI Clock Prescale 0x10 read-write n 0x0 0x0 SSI_CPSR_CPSDVSR SSI Clock Prescale Divisor 0 8 SSI0CR0 SSI Control 0 0x0 read-write n 0x0 0x0 SSI_CR0_DSS SSI Data Size Select 0 4 SSI_CR0_DSS_4 4-bit data 0x3 SSI_CR0_DSS_5 5-bit data 0x4 SSI_CR0_DSS_6 6-bit data 0x5 SSI_CR0_DSS_7 7-bit data 0x6 SSI_CR0_DSS_8 8-bit data 0x7 SSI_CR0_DSS_9 9-bit data 0x8 SSI_CR0_DSS_10 10-bit data 0x9 SSI_CR0_DSS_11 11-bit data 0xa SSI_CR0_DSS_12 12-bit data 0xb SSI_CR0_DSS_13 13-bit data 0xc SSI_CR0_DSS_14 14-bit data 0xd SSI_CR0_DSS_15 15-bit data 0xe SSI_CR0_DSS_16 16-bit data 0xf SSI_CR0_FRF SSI Frame Format Select 4 6 SSI_CR0_FRF_MOTO Freescale SPI Frame Format 0x0 SSI_CR0_FRF_TI Synchronous Serial Frame Format 0x1 SSI_CR0_SCR SSI Serial Clock Rate 8 16 SSI_CR0_SPH SSI Serial Clock Phase 7 8 SSI_CR0_SPO SSI Serial Clock Polarity 6 7 SSI0CR1 SSI Control 1 0x4 read-write n 0x0 0x0 SSI_CR1_DIR SSI Direction of Operation 8 9 SSI_CR1_EOM Stop Frame (End of Message) 11 12 SSI_CR1_EOT End of Transmission 4 5 SSI_CR1_FSSHLDFRM FSS Hold Frame 10 11 SSI_CR1_HSCLKEN High Speed Clock Enable 9 10 SSI_CR1_LBM SSI Loopback Mode 0 1 SSI_CR1_MODE SSI Mode 6 8 SSI_CR1_MODE_LEGACY Legacy SSI mode 0x0 SSI_CR1_MODE_BI Bi-SSI mode 0x1 SSI_CR1_MODE_QUAD Quad-SSI Mode 0x2 SSI_CR1_MODE_ADVANCED Advanced SSI Mode with 8-bit packet size 0x3 SSI_CR1_MS SSI Master/Slave Select 2 3 SSI_CR1_SSE SSI Synchronous Serial Port Enable 1 2 SSI0DMACTL SSI DMA Control 0x24 read-write n 0x0 0x0 SSI_DMACTL_RXDMAE Receive DMA Enable 0 1 SSI_DMACTL_TXDMAE Transmit DMA Enable 1 2 SSI0DR SSI Data 0x8 read-write n 0x0 0x0 SSI_DR_DATA SSI Receive/Transmit Data 0 16 SSI0ICR SSI Interrupt Clear 0x20 write-only n 0x0 0x0 SSI_ICR_DMARXIC SSI Receive DMA Interrupt Clear 4 5 write-only SSI_ICR_DMATXIC SSI Transmit DMA Interrupt Clear 5 6 write-only SSI_ICR_EOTIC End of Transmit Interrupt Clear 6 7 write-only SSI_ICR_RORIC SSI Receive Overrun Interrupt Clear 0 1 write-only SSI_ICR_RTIC SSI Receive Time-Out Interrupt Clear 1 2 write-only SSI0IM SSI Interrupt Mask 0x14 read-write n 0x0 0x0 SSI_IM_DMARXIM SSI Receive DMA Interrupt Mask 4 5 SSI_IM_DMATXIM SSI Transmit DMA Interrupt Mask 5 6 SSI_IM_EOTIM End of Transmit Interrupt Mask 6 7 SSI_IM_RORIM SSI Receive Overrun Interrupt Mask 0 1 SSI_IM_RTIM SSI Receive Time-Out Interrupt Mask 1 2 SSI_IM_RXIM SSI Receive FIFO Interrupt Mask 2 3 SSI_IM_TXIM SSI Transmit FIFO Interrupt Mask 3 4 SSI0MIS SSI Masked Interrupt Status 0x1C read-write n 0x0 0x0 SSI_MIS_DMARXMIS SSI Receive DMA Masked Interrupt Status 4 5 SSI_MIS_DMATXMIS SSI Transmit DMA Masked Interrupt Status 5 6 SSI_MIS_EOTMIS End of Transmit Masked Interrupt Status 6 7 SSI_MIS_RORMIS SSI Receive Overrun Masked Interrupt Status 0 1 SSI_MIS_RTMIS SSI Receive Time-Out Masked Interrupt Status 1 2 SSI_MIS_RXMIS SSI Receive FIFO Masked Interrupt Status 2 3 SSI_MIS_TXMIS SSI Transmit FIFO Masked Interrupt Status 3 4 SSI0PP SSI Peripheral Properties 0xFC0 read-write n 0x0 0x0 SSI_PP_FSSHLDFRM FSS Hold Frame Capability 3 4 SSI_PP_HSCLK High Speed Capability 0 1 SSI_PP_MODE Mode of Operation 1 3 SSI_PP_MODE_LEGACY Legacy SSI mode 0x0 SSI_PP_MODE_ADVBI Legacy mode, Advanced SSI mode and Bi-SSI mode enabled 0x1 SSI_PP_MODE_ADVBIQUAD Legacy mode, Advanced mode, Bi-SSI and Quad-SSI mode enabled 0x2 SSI0RIS SSI Raw Interrupt Status 0x18 read-write n 0x0 0x0 SSI_RIS_DMARXRIS SSI Receive DMA Raw Interrupt Status 4 5 SSI_RIS_DMATXRIS SSI Transmit DMA Raw Interrupt Status 5 6 SSI_RIS_EOTRIS End of Transmit Raw Interrupt Status 6 7 SSI_RIS_RORRIS SSI Receive Overrun Raw Interrupt Status 0 1 SSI_RIS_RTRIS SSI Receive Time-Out Raw Interrupt Status 1 2 SSI_RIS_RXRIS SSI Receive FIFO Raw Interrupt Status 2 3 SSI_RIS_TXRIS SSI Transmit FIFO Raw Interrupt Status 3 4 SSI0SR SSI Status 0xC read-write n 0x0 0x0 SSI_SR_BSY SSI Busy Bit 4 5 SSI_SR_RFF SSI Receive FIFO Full 3 4 SSI_SR_RNE SSI Receive FIFO Not Empty 2 3 SSI_SR_TFE SSI Transmit FIFO Empty 0 1 SSI_SR_TNF SSI Transmit FIFO Not Full 1 2 SSI1 Register map for SSI0 peripheral SSI 0x0 0x0 0x1000 registers n SSI1 34 CC SSI Clock Configuration 0xFC8 -1 read-write n 0x0 0x0 SSI_CC_CS SSI Baud Clock Source 0 4 SSI_CC_CS_SYSPLL System clock (based on clock source and divisor factor) 0x0 SSI_CC_CS_PIOSC PIOSC 0x5 CPSR SSI Clock Prescale 0x10 -1 read-write n 0x0 0x0 SSI_CPSR_CPSDVSR SSI Clock Prescale Divisor 0 8 CR0 SSI Control 0 0x0 -1 read-write n 0x0 0x0 SSI_CR0_DSS SSI Data Size Select 0 4 SSI_CR0_DSS_4 4-bit data 0x3 SSI_CR0_DSS_5 5-bit data 0x4 SSI_CR0_DSS_6 6-bit data 0x5 SSI_CR0_DSS_7 7-bit data 0x6 SSI_CR0_DSS_8 8-bit data 0x7 SSI_CR0_DSS_9 9-bit data 0x8 SSI_CR0_DSS_10 10-bit data 0x9 SSI_CR0_DSS_11 11-bit data 0xa SSI_CR0_DSS_12 12-bit data 0xb SSI_CR0_DSS_13 13-bit data 0xc SSI_CR0_DSS_14 14-bit data 0xd SSI_CR0_DSS_15 15-bit data 0xe SSI_CR0_DSS_16 16-bit data 0xf SSI_CR0_FRF SSI Frame Format Select 4 6 SSI_CR0_FRF_MOTO Freescale SPI Frame Format 0x0 SSI_CR0_FRF_TI Synchronous Serial Frame Format 0x1 SSI_CR0_SCR SSI Serial Clock Rate 8 16 SSI_CR0_SPH SSI Serial Clock Phase 7 8 SSI_CR0_SPO SSI Serial Clock Polarity 6 7 CR1 SSI Control 1 0x4 -1 read-write n 0x0 0x0 SSI_CR1_DIR SSI Direction of Operation 8 9 SSI_CR1_EOM Stop Frame (End of Message) 11 12 SSI_CR1_EOT End of Transmission 4 5 SSI_CR1_FSSHLDFRM FSS Hold Frame 10 11 SSI_CR1_HSCLKEN High Speed Clock Enable 9 10 SSI_CR1_LBM SSI Loopback Mode 0 1 SSI_CR1_MODE SSI Mode 6 8 SSI_CR1_MODE_LEGACY Legacy SSI mode 0x0 SSI_CR1_MODE_BI Bi-SSI mode 0x1 SSI_CR1_MODE_QUAD Quad-SSI Mode 0x2 SSI_CR1_MODE_ADVANCED Advanced SSI Mode with 8-bit packet size 0x3 SSI_CR1_MS SSI Master/Slave Select 2 3 SSI_CR1_SSE SSI Synchronous Serial Port Enable 1 2 DMACTL SSI DMA Control 0x24 -1 read-write n 0x0 0x0 SSI_DMACTL_RXDMAE Receive DMA Enable 0 1 SSI_DMACTL_TXDMAE Transmit DMA Enable 1 2 DR SSI Data 0x8 -1 read-write n 0x0 0x0 SSI_DR_DATA SSI Receive/Transmit Data 0 16 ICR SSI Interrupt Clear 0x20 -1 write-only n 0x0 0x0 SSI_ICR_DMARXIC SSI Receive DMA Interrupt Clear 4 5 write-only SSI_ICR_DMATXIC SSI Transmit DMA Interrupt Clear 5 6 write-only SSI_ICR_EOTIC End of Transmit Interrupt Clear 6 7 write-only SSI_ICR_RORIC SSI Receive Overrun Interrupt Clear 0 1 write-only SSI_ICR_RTIC SSI Receive Time-Out Interrupt Clear 1 2 write-only IM SSI Interrupt Mask 0x14 -1 read-write n 0x0 0x0 SSI_IM_DMARXIM SSI Receive DMA Interrupt Mask 4 5 SSI_IM_DMATXIM SSI Transmit DMA Interrupt Mask 5 6 SSI_IM_EOTIM End of Transmit Interrupt Mask 6 7 SSI_IM_RORIM SSI Receive Overrun Interrupt Mask 0 1 SSI_IM_RTIM SSI Receive Time-Out Interrupt Mask 1 2 SSI_IM_RXIM SSI Receive FIFO Interrupt Mask 2 3 SSI_IM_TXIM SSI Transmit FIFO Interrupt Mask 3 4 MIS SSI Masked Interrupt Status 0x1C -1 read-write n 0x0 0x0 SSI_MIS_DMARXMIS SSI Receive DMA Masked Interrupt Status 4 5 SSI_MIS_DMATXMIS SSI Transmit DMA Masked Interrupt Status 5 6 SSI_MIS_EOTMIS End of Transmit Masked Interrupt Status 6 7 SSI_MIS_RORMIS SSI Receive Overrun Masked Interrupt Status 0 1 SSI_MIS_RTMIS SSI Receive Time-Out Masked Interrupt Status 1 2 SSI_MIS_RXMIS SSI Receive FIFO Masked Interrupt Status 2 3 SSI_MIS_TXMIS SSI Transmit FIFO Masked Interrupt Status 3 4 PP SSI Peripheral Properties 0xFC0 -1 read-write n 0x0 0x0 SSI_PP_FSSHLDFRM FSS Hold Frame Capability 3 4 SSI_PP_HSCLK High Speed Capability 0 1 SSI_PP_MODE Mode of Operation 1 3 SSI_PP_MODE_LEGACY Legacy SSI mode 0x0 SSI_PP_MODE_ADVBI Legacy mode, Advanced SSI mode and Bi-SSI mode enabled 0x1 SSI_PP_MODE_ADVBIQUAD Legacy mode, Advanced mode, Bi-SSI and Quad-SSI mode enabled 0x2 RIS SSI Raw Interrupt Status 0x18 -1 read-write n 0x0 0x0 SSI_RIS_DMARXRIS SSI Receive DMA Raw Interrupt Status 4 5 SSI_RIS_DMATXRIS SSI Transmit DMA Raw Interrupt Status 5 6 SSI_RIS_EOTRIS End of Transmit Raw Interrupt Status 6 7 SSI_RIS_RORRIS SSI Receive Overrun Raw Interrupt Status 0 1 SSI_RIS_RTRIS SSI Receive Time-Out Raw Interrupt Status 1 2 SSI_RIS_RXRIS SSI Receive FIFO Raw Interrupt Status 2 3 SSI_RIS_TXRIS SSI Transmit FIFO Raw Interrupt Status 3 4 SR SSI Status 0xC -1 read-write n 0x0 0x0 SSI_SR_BSY SSI Busy Bit 4 5 SSI_SR_RFF SSI Receive FIFO Full 3 4 SSI_SR_RNE SSI Receive FIFO Not Empty 2 3 SSI_SR_TFE SSI Transmit FIFO Empty 0 1 SSI_SR_TNF SSI Transmit FIFO Not Full 1 2 SSI0CC SSI Clock Configuration 0xFC8 read-write n 0x0 0x0 SSI_CC_CS SSI Baud Clock Source 0 4 SSI_CC_CS_SYSPLL System clock (based on clock source and divisor factor) 0x0 SSI_CC_CS_PIOSC PIOSC 0x5 SSI0CPSR SSI Clock Prescale 0x10 read-write n 0x0 0x0 SSI_CPSR_CPSDVSR SSI Clock Prescale Divisor 0 8 SSI0CR0 SSI Control 0 0x0 read-write n 0x0 0x0 SSI_CR0_DSS SSI Data Size Select 0 4 SSI_CR0_DSS_4 4-bit data 0x3 SSI_CR0_DSS_5 5-bit data 0x4 SSI_CR0_DSS_6 6-bit data 0x5 SSI_CR0_DSS_7 7-bit data 0x6 SSI_CR0_DSS_8 8-bit data 0x7 SSI_CR0_DSS_9 9-bit data 0x8 SSI_CR0_DSS_10 10-bit data 0x9 SSI_CR0_DSS_11 11-bit data 0xa SSI_CR0_DSS_12 12-bit data 0xb SSI_CR0_DSS_13 13-bit data 0xc SSI_CR0_DSS_14 14-bit data 0xd SSI_CR0_DSS_15 15-bit data 0xe SSI_CR0_DSS_16 16-bit data 0xf SSI_CR0_FRF SSI Frame Format Select 4 6 SSI_CR0_FRF_MOTO Freescale SPI Frame Format 0x0 SSI_CR0_FRF_TI Synchronous Serial Frame Format 0x1 SSI_CR0_SCR SSI Serial Clock Rate 8 16 SSI_CR0_SPH SSI Serial Clock Phase 7 8 SSI_CR0_SPO SSI Serial Clock Polarity 6 7 SSI0CR1 SSI Control 1 0x4 read-write n 0x0 0x0 SSI_CR1_DIR SSI Direction of Operation 8 9 SSI_CR1_EOM Stop Frame (End of Message) 11 12 SSI_CR1_EOT End of Transmission 4 5 SSI_CR1_FSSHLDFRM FSS Hold Frame 10 11 SSI_CR1_HSCLKEN High Speed Clock Enable 9 10 SSI_CR1_LBM SSI Loopback Mode 0 1 SSI_CR1_MODE SSI Mode 6 8 SSI_CR1_MODE_LEGACY Legacy SSI mode 0x0 SSI_CR1_MODE_BI Bi-SSI mode 0x1 SSI_CR1_MODE_QUAD Quad-SSI Mode 0x2 SSI_CR1_MODE_ADVANCED Advanced SSI Mode with 8-bit packet size 0x3 SSI_CR1_MS SSI Master/Slave Select 2 3 SSI_CR1_SSE SSI Synchronous Serial Port Enable 1 2 SSI0DMACTL SSI DMA Control 0x24 read-write n 0x0 0x0 SSI_DMACTL_RXDMAE Receive DMA Enable 0 1 SSI_DMACTL_TXDMAE Transmit DMA Enable 1 2 SSI0DR SSI Data 0x8 read-write n 0x0 0x0 SSI_DR_DATA SSI Receive/Transmit Data 0 16 SSI0ICR SSI Interrupt Clear 0x20 write-only n 0x0 0x0 SSI_ICR_DMARXIC SSI Receive DMA Interrupt Clear 4 5 write-only SSI_ICR_DMATXIC SSI Transmit DMA Interrupt Clear 5 6 write-only SSI_ICR_EOTIC End of Transmit Interrupt Clear 6 7 write-only SSI_ICR_RORIC SSI Receive Overrun Interrupt Clear 0 1 write-only SSI_ICR_RTIC SSI Receive Time-Out Interrupt Clear 1 2 write-only SSI0IM SSI Interrupt Mask 0x14 read-write n 0x0 0x0 SSI_IM_DMARXIM SSI Receive DMA Interrupt Mask 4 5 SSI_IM_DMATXIM SSI Transmit DMA Interrupt Mask 5 6 SSI_IM_EOTIM End of Transmit Interrupt Mask 6 7 SSI_IM_RORIM SSI Receive Overrun Interrupt Mask 0 1 SSI_IM_RTIM SSI Receive Time-Out Interrupt Mask 1 2 SSI_IM_RXIM SSI Receive FIFO Interrupt Mask 2 3 SSI_IM_TXIM SSI Transmit FIFO Interrupt Mask 3 4 SSI0MIS SSI Masked Interrupt Status 0x1C read-write n 0x0 0x0 SSI_MIS_DMARXMIS SSI Receive DMA Masked Interrupt Status 4 5 SSI_MIS_DMATXMIS SSI Transmit DMA Masked Interrupt Status 5 6 SSI_MIS_EOTMIS End of Transmit Masked Interrupt Status 6 7 SSI_MIS_RORMIS SSI Receive Overrun Masked Interrupt Status 0 1 SSI_MIS_RTMIS SSI Receive Time-Out Masked Interrupt Status 1 2 SSI_MIS_RXMIS SSI Receive FIFO Masked Interrupt Status 2 3 SSI_MIS_TXMIS SSI Transmit FIFO Masked Interrupt Status 3 4 SSI0PP SSI Peripheral Properties 0xFC0 read-write n 0x0 0x0 SSI_PP_FSSHLDFRM FSS Hold Frame Capability 3 4 SSI_PP_HSCLK High Speed Capability 0 1 SSI_PP_MODE Mode of Operation 1 3 SSI_PP_MODE_LEGACY Legacy SSI mode 0x0 SSI_PP_MODE_ADVBI Legacy mode, Advanced SSI mode and Bi-SSI mode enabled 0x1 SSI_PP_MODE_ADVBIQUAD Legacy mode, Advanced mode, Bi-SSI and Quad-SSI mode enabled 0x2 SSI0RIS SSI Raw Interrupt Status 0x18 read-write n 0x0 0x0 SSI_RIS_DMARXRIS SSI Receive DMA Raw Interrupt Status 4 5 SSI_RIS_DMATXRIS SSI Transmit DMA Raw Interrupt Status 5 6 SSI_RIS_EOTRIS End of Transmit Raw Interrupt Status 6 7 SSI_RIS_RORRIS SSI Receive Overrun Raw Interrupt Status 0 1 SSI_RIS_RTRIS SSI Receive Time-Out Raw Interrupt Status 1 2 SSI_RIS_RXRIS SSI Receive FIFO Raw Interrupt Status 2 3 SSI_RIS_TXRIS SSI Transmit FIFO Raw Interrupt Status 3 4 SSI0SR SSI Status 0xC read-write n 0x0 0x0 SSI_SR_BSY SSI Busy Bit 4 5 SSI_SR_RFF SSI Receive FIFO Full 3 4 SSI_SR_RNE SSI Receive FIFO Not Empty 2 3 SSI_SR_TFE SSI Transmit FIFO Empty 0 1 SSI_SR_TNF SSI Transmit FIFO Not Full 1 2 SSI2 Register map for SSI0 peripheral SSI 0x0 0x0 0x1000 registers n SSI2 54 CC SSI Clock Configuration 0xFC8 -1 read-write n 0x0 0x0 SSI_CC_CS SSI Baud Clock Source 0 4 SSI_CC_CS_SYSPLL System clock (based on clock source and divisor factor) 0x0 SSI_CC_CS_PIOSC PIOSC 0x5 CPSR SSI Clock Prescale 0x10 -1 read-write n 0x0 0x0 SSI_CPSR_CPSDVSR SSI Clock Prescale Divisor 0 8 CR0 SSI Control 0 0x0 -1 read-write n 0x0 0x0 SSI_CR0_DSS SSI Data Size Select 0 4 SSI_CR0_DSS_4 4-bit data 0x3 SSI_CR0_DSS_5 5-bit data 0x4 SSI_CR0_DSS_6 6-bit data 0x5 SSI_CR0_DSS_7 7-bit data 0x6 SSI_CR0_DSS_8 8-bit data 0x7 SSI_CR0_DSS_9 9-bit data 0x8 SSI_CR0_DSS_10 10-bit data 0x9 SSI_CR0_DSS_11 11-bit data 0xa SSI_CR0_DSS_12 12-bit data 0xb SSI_CR0_DSS_13 13-bit data 0xc SSI_CR0_DSS_14 14-bit data 0xd SSI_CR0_DSS_15 15-bit data 0xe SSI_CR0_DSS_16 16-bit data 0xf SSI_CR0_FRF SSI Frame Format Select 4 6 SSI_CR0_FRF_MOTO Freescale SPI Frame Format 0x0 SSI_CR0_FRF_TI Synchronous Serial Frame Format 0x1 SSI_CR0_SCR SSI Serial Clock Rate 8 16 SSI_CR0_SPH SSI Serial Clock Phase 7 8 SSI_CR0_SPO SSI Serial Clock Polarity 6 7 CR1 SSI Control 1 0x4 -1 read-write n 0x0 0x0 SSI_CR1_DIR SSI Direction of Operation 8 9 SSI_CR1_EOM Stop Frame (End of Message) 11 12 SSI_CR1_EOT End of Transmission 4 5 SSI_CR1_FSSHLDFRM FSS Hold Frame 10 11 SSI_CR1_HSCLKEN High Speed Clock Enable 9 10 SSI_CR1_LBM SSI Loopback Mode 0 1 SSI_CR1_MODE SSI Mode 6 8 SSI_CR1_MODE_LEGACY Legacy SSI mode 0x0 SSI_CR1_MODE_BI Bi-SSI mode 0x1 SSI_CR1_MODE_QUAD Quad-SSI Mode 0x2 SSI_CR1_MODE_ADVANCED Advanced SSI Mode with 8-bit packet size 0x3 SSI_CR1_MS SSI Master/Slave Select 2 3 SSI_CR1_SSE SSI Synchronous Serial Port Enable 1 2 DMACTL SSI DMA Control 0x24 -1 read-write n 0x0 0x0 SSI_DMACTL_RXDMAE Receive DMA Enable 0 1 SSI_DMACTL_TXDMAE Transmit DMA Enable 1 2 DR SSI Data 0x8 -1 read-write n 0x0 0x0 SSI_DR_DATA SSI Receive/Transmit Data 0 16 ICR SSI Interrupt Clear 0x20 -1 write-only n 0x0 0x0 SSI_ICR_DMARXIC SSI Receive DMA Interrupt Clear 4 5 write-only SSI_ICR_DMATXIC SSI Transmit DMA Interrupt Clear 5 6 write-only SSI_ICR_EOTIC End of Transmit Interrupt Clear 6 7 write-only SSI_ICR_RORIC SSI Receive Overrun Interrupt Clear 0 1 write-only SSI_ICR_RTIC SSI Receive Time-Out Interrupt Clear 1 2 write-only IM SSI Interrupt Mask 0x14 -1 read-write n 0x0 0x0 SSI_IM_DMARXIM SSI Receive DMA Interrupt Mask 4 5 SSI_IM_DMATXIM SSI Transmit DMA Interrupt Mask 5 6 SSI_IM_EOTIM End of Transmit Interrupt Mask 6 7 SSI_IM_RORIM SSI Receive Overrun Interrupt Mask 0 1 SSI_IM_RTIM SSI Receive Time-Out Interrupt Mask 1 2 SSI_IM_RXIM SSI Receive FIFO Interrupt Mask 2 3 SSI_IM_TXIM SSI Transmit FIFO Interrupt Mask 3 4 MIS SSI Masked Interrupt Status 0x1C -1 read-write n 0x0 0x0 SSI_MIS_DMARXMIS SSI Receive DMA Masked Interrupt Status 4 5 SSI_MIS_DMATXMIS SSI Transmit DMA Masked Interrupt Status 5 6 SSI_MIS_EOTMIS End of Transmit Masked Interrupt Status 6 7 SSI_MIS_RORMIS SSI Receive Overrun Masked Interrupt Status 0 1 SSI_MIS_RTMIS SSI Receive Time-Out Masked Interrupt Status 1 2 SSI_MIS_RXMIS SSI Receive FIFO Masked Interrupt Status 2 3 SSI_MIS_TXMIS SSI Transmit FIFO Masked Interrupt Status 3 4 PP SSI Peripheral Properties 0xFC0 -1 read-write n 0x0 0x0 SSI_PP_FSSHLDFRM FSS Hold Frame Capability 3 4 SSI_PP_HSCLK High Speed Capability 0 1 SSI_PP_MODE Mode of Operation 1 3 SSI_PP_MODE_LEGACY Legacy SSI mode 0x0 SSI_PP_MODE_ADVBI Legacy mode, Advanced SSI mode and Bi-SSI mode enabled 0x1 SSI_PP_MODE_ADVBIQUAD Legacy mode, Advanced mode, Bi-SSI and Quad-SSI mode enabled 0x2 RIS SSI Raw Interrupt Status 0x18 -1 read-write n 0x0 0x0 SSI_RIS_DMARXRIS SSI Receive DMA Raw Interrupt Status 4 5 SSI_RIS_DMATXRIS SSI Transmit DMA Raw Interrupt Status 5 6 SSI_RIS_EOTRIS End of Transmit Raw Interrupt Status 6 7 SSI_RIS_RORRIS SSI Receive Overrun Raw Interrupt Status 0 1 SSI_RIS_RTRIS SSI Receive Time-Out Raw Interrupt Status 1 2 SSI_RIS_RXRIS SSI Receive FIFO Raw Interrupt Status 2 3 SSI_RIS_TXRIS SSI Transmit FIFO Raw Interrupt Status 3 4 SR SSI Status 0xC -1 read-write n 0x0 0x0 SSI_SR_BSY SSI Busy Bit 4 5 SSI_SR_RFF SSI Receive FIFO Full 3 4 SSI_SR_RNE SSI Receive FIFO Not Empty 2 3 SSI_SR_TFE SSI Transmit FIFO Empty 0 1 SSI_SR_TNF SSI Transmit FIFO Not Full 1 2 SSI0CC SSI Clock Configuration 0xFC8 read-write n 0x0 0x0 SSI_CC_CS SSI Baud Clock Source 0 4 SSI_CC_CS_SYSPLL System clock (based on clock source and divisor factor) 0x0 SSI_CC_CS_PIOSC PIOSC 0x5 SSI0CPSR SSI Clock Prescale 0x10 read-write n 0x0 0x0 SSI_CPSR_CPSDVSR SSI Clock Prescale Divisor 0 8 SSI0CR0 SSI Control 0 0x0 read-write n 0x0 0x0 SSI_CR0_DSS SSI Data Size Select 0 4 SSI_CR0_DSS_4 4-bit data 0x3 SSI_CR0_DSS_5 5-bit data 0x4 SSI_CR0_DSS_6 6-bit data 0x5 SSI_CR0_DSS_7 7-bit data 0x6 SSI_CR0_DSS_8 8-bit data 0x7 SSI_CR0_DSS_9 9-bit data 0x8 SSI_CR0_DSS_10 10-bit data 0x9 SSI_CR0_DSS_11 11-bit data 0xa SSI_CR0_DSS_12 12-bit data 0xb SSI_CR0_DSS_13 13-bit data 0xc SSI_CR0_DSS_14 14-bit data 0xd SSI_CR0_DSS_15 15-bit data 0xe SSI_CR0_DSS_16 16-bit data 0xf SSI_CR0_FRF SSI Frame Format Select 4 6 SSI_CR0_FRF_MOTO Freescale SPI Frame Format 0x0 SSI_CR0_FRF_TI Synchronous Serial Frame Format 0x1 SSI_CR0_SCR SSI Serial Clock Rate 8 16 SSI_CR0_SPH SSI Serial Clock Phase 7 8 SSI_CR0_SPO SSI Serial Clock Polarity 6 7 SSI0CR1 SSI Control 1 0x4 read-write n 0x0 0x0 SSI_CR1_DIR SSI Direction of Operation 8 9 SSI_CR1_EOM Stop Frame (End of Message) 11 12 SSI_CR1_EOT End of Transmission 4 5 SSI_CR1_FSSHLDFRM FSS Hold Frame 10 11 SSI_CR1_HSCLKEN High Speed Clock Enable 9 10 SSI_CR1_LBM SSI Loopback Mode 0 1 SSI_CR1_MODE SSI Mode 6 8 SSI_CR1_MODE_LEGACY Legacy SSI mode 0x0 SSI_CR1_MODE_BI Bi-SSI mode 0x1 SSI_CR1_MODE_QUAD Quad-SSI Mode 0x2 SSI_CR1_MODE_ADVANCED Advanced SSI Mode with 8-bit packet size 0x3 SSI_CR1_MS SSI Master/Slave Select 2 3 SSI_CR1_SSE SSI Synchronous Serial Port Enable 1 2 SSI0DMACTL SSI DMA Control 0x24 read-write n 0x0 0x0 SSI_DMACTL_RXDMAE Receive DMA Enable 0 1 SSI_DMACTL_TXDMAE Transmit DMA Enable 1 2 SSI0DR SSI Data 0x8 read-write n 0x0 0x0 SSI_DR_DATA SSI Receive/Transmit Data 0 16 SSI0ICR SSI Interrupt Clear 0x20 write-only n 0x0 0x0 SSI_ICR_DMARXIC SSI Receive DMA Interrupt Clear 4 5 write-only SSI_ICR_DMATXIC SSI Transmit DMA Interrupt Clear 5 6 write-only SSI_ICR_EOTIC End of Transmit Interrupt Clear 6 7 write-only SSI_ICR_RORIC SSI Receive Overrun Interrupt Clear 0 1 write-only SSI_ICR_RTIC SSI Receive Time-Out Interrupt Clear 1 2 write-only SSI0IM SSI Interrupt Mask 0x14 read-write n 0x0 0x0 SSI_IM_DMARXIM SSI Receive DMA Interrupt Mask 4 5 SSI_IM_DMATXIM SSI Transmit DMA Interrupt Mask 5 6 SSI_IM_EOTIM End of Transmit Interrupt Mask 6 7 SSI_IM_RORIM SSI Receive Overrun Interrupt Mask 0 1 SSI_IM_RTIM SSI Receive Time-Out Interrupt Mask 1 2 SSI_IM_RXIM SSI Receive FIFO Interrupt Mask 2 3 SSI_IM_TXIM SSI Transmit FIFO Interrupt Mask 3 4 SSI0MIS SSI Masked Interrupt Status 0x1C read-write n 0x0 0x0 SSI_MIS_DMARXMIS SSI Receive DMA Masked Interrupt Status 4 5 SSI_MIS_DMATXMIS SSI Transmit DMA Masked Interrupt Status 5 6 SSI_MIS_EOTMIS End of Transmit Masked Interrupt Status 6 7 SSI_MIS_RORMIS SSI Receive Overrun Masked Interrupt Status 0 1 SSI_MIS_RTMIS SSI Receive Time-Out Masked Interrupt Status 1 2 SSI_MIS_RXMIS SSI Receive FIFO Masked Interrupt Status 2 3 SSI_MIS_TXMIS SSI Transmit FIFO Masked Interrupt Status 3 4 SSI0PP SSI Peripheral Properties 0xFC0 read-write n 0x0 0x0 SSI_PP_FSSHLDFRM FSS Hold Frame Capability 3 4 SSI_PP_HSCLK High Speed Capability 0 1 SSI_PP_MODE Mode of Operation 1 3 SSI_PP_MODE_LEGACY Legacy SSI mode 0x0 SSI_PP_MODE_ADVBI Legacy mode, Advanced SSI mode and Bi-SSI mode enabled 0x1 SSI_PP_MODE_ADVBIQUAD Legacy mode, Advanced mode, Bi-SSI and Quad-SSI mode enabled 0x2 SSI0RIS SSI Raw Interrupt Status 0x18 read-write n 0x0 0x0 SSI_RIS_DMARXRIS SSI Receive DMA Raw Interrupt Status 4 5 SSI_RIS_DMATXRIS SSI Transmit DMA Raw Interrupt Status 5 6 SSI_RIS_EOTRIS End of Transmit Raw Interrupt Status 6 7 SSI_RIS_RORRIS SSI Receive Overrun Raw Interrupt Status 0 1 SSI_RIS_RTRIS SSI Receive Time-Out Raw Interrupt Status 1 2 SSI_RIS_RXRIS SSI Receive FIFO Raw Interrupt Status 2 3 SSI_RIS_TXRIS SSI Transmit FIFO Raw Interrupt Status 3 4 SSI0SR SSI Status 0xC read-write n 0x0 0x0 SSI_SR_BSY SSI Busy Bit 4 5 SSI_SR_RFF SSI Receive FIFO Full 3 4 SSI_SR_RNE SSI Receive FIFO Not Empty 2 3 SSI_SR_TFE SSI Transmit FIFO Empty 0 1 SSI_SR_TNF SSI Transmit FIFO Not Full 1 2 SSI3 Register map for SSI0 peripheral SSI 0x0 0x0 0x1000 registers n SSI3 55 CC SSI Clock Configuration 0xFC8 -1 read-write n 0x0 0x0 SSI_CC_CS SSI Baud Clock Source 0 4 SSI_CC_CS_SYSPLL System clock (based on clock source and divisor factor) 0x0 SSI_CC_CS_PIOSC PIOSC 0x5 CPSR SSI Clock Prescale 0x10 -1 read-write n 0x0 0x0 SSI_CPSR_CPSDVSR SSI Clock Prescale Divisor 0 8 CR0 SSI Control 0 0x0 -1 read-write n 0x0 0x0 SSI_CR0_DSS SSI Data Size Select 0 4 SSI_CR0_DSS_4 4-bit data 0x3 SSI_CR0_DSS_5 5-bit data 0x4 SSI_CR0_DSS_6 6-bit data 0x5 SSI_CR0_DSS_7 7-bit data 0x6 SSI_CR0_DSS_8 8-bit data 0x7 SSI_CR0_DSS_9 9-bit data 0x8 SSI_CR0_DSS_10 10-bit data 0x9 SSI_CR0_DSS_11 11-bit data 0xa SSI_CR0_DSS_12 12-bit data 0xb SSI_CR0_DSS_13 13-bit data 0xc SSI_CR0_DSS_14 14-bit data 0xd SSI_CR0_DSS_15 15-bit data 0xe SSI_CR0_DSS_16 16-bit data 0xf SSI_CR0_FRF SSI Frame Format Select 4 6 SSI_CR0_FRF_MOTO Freescale SPI Frame Format 0x0 SSI_CR0_FRF_TI Synchronous Serial Frame Format 0x1 SSI_CR0_SCR SSI Serial Clock Rate 8 16 SSI_CR0_SPH SSI Serial Clock Phase 7 8 SSI_CR0_SPO SSI Serial Clock Polarity 6 7 CR1 SSI Control 1 0x4 -1 read-write n 0x0 0x0 SSI_CR1_DIR SSI Direction of Operation 8 9 SSI_CR1_EOM Stop Frame (End of Message) 11 12 SSI_CR1_EOT End of Transmission 4 5 SSI_CR1_FSSHLDFRM FSS Hold Frame 10 11 SSI_CR1_HSCLKEN High Speed Clock Enable 9 10 SSI_CR1_LBM SSI Loopback Mode 0 1 SSI_CR1_MODE SSI Mode 6 8 SSI_CR1_MODE_LEGACY Legacy SSI mode 0x0 SSI_CR1_MODE_BI Bi-SSI mode 0x1 SSI_CR1_MODE_QUAD Quad-SSI Mode 0x2 SSI_CR1_MODE_ADVANCED Advanced SSI Mode with 8-bit packet size 0x3 SSI_CR1_MS SSI Master/Slave Select 2 3 SSI_CR1_SSE SSI Synchronous Serial Port Enable 1 2 DMACTL SSI DMA Control 0x24 -1 read-write n 0x0 0x0 SSI_DMACTL_RXDMAE Receive DMA Enable 0 1 SSI_DMACTL_TXDMAE Transmit DMA Enable 1 2 DR SSI Data 0x8 -1 read-write n 0x0 0x0 SSI_DR_DATA SSI Receive/Transmit Data 0 16 ICR SSI Interrupt Clear 0x20 -1 write-only n 0x0 0x0 SSI_ICR_DMARXIC SSI Receive DMA Interrupt Clear 4 5 write-only SSI_ICR_DMATXIC SSI Transmit DMA Interrupt Clear 5 6 write-only SSI_ICR_EOTIC End of Transmit Interrupt Clear 6 7 write-only SSI_ICR_RORIC SSI Receive Overrun Interrupt Clear 0 1 write-only SSI_ICR_RTIC SSI Receive Time-Out Interrupt Clear 1 2 write-only IM SSI Interrupt Mask 0x14 -1 read-write n 0x0 0x0 SSI_IM_DMARXIM SSI Receive DMA Interrupt Mask 4 5 SSI_IM_DMATXIM SSI Transmit DMA Interrupt Mask 5 6 SSI_IM_EOTIM End of Transmit Interrupt Mask 6 7 SSI_IM_RORIM SSI Receive Overrun Interrupt Mask 0 1 SSI_IM_RTIM SSI Receive Time-Out Interrupt Mask 1 2 SSI_IM_RXIM SSI Receive FIFO Interrupt Mask 2 3 SSI_IM_TXIM SSI Transmit FIFO Interrupt Mask 3 4 MIS SSI Masked Interrupt Status 0x1C -1 read-write n 0x0 0x0 SSI_MIS_DMARXMIS SSI Receive DMA Masked Interrupt Status 4 5 SSI_MIS_DMATXMIS SSI Transmit DMA Masked Interrupt Status 5 6 SSI_MIS_EOTMIS End of Transmit Masked Interrupt Status 6 7 SSI_MIS_RORMIS SSI Receive Overrun Masked Interrupt Status 0 1 SSI_MIS_RTMIS SSI Receive Time-Out Masked Interrupt Status 1 2 SSI_MIS_RXMIS SSI Receive FIFO Masked Interrupt Status 2 3 SSI_MIS_TXMIS SSI Transmit FIFO Masked Interrupt Status 3 4 PP SSI Peripheral Properties 0xFC0 -1 read-write n 0x0 0x0 SSI_PP_FSSHLDFRM FSS Hold Frame Capability 3 4 SSI_PP_HSCLK High Speed Capability 0 1 SSI_PP_MODE Mode of Operation 1 3 SSI_PP_MODE_LEGACY Legacy SSI mode 0x0 SSI_PP_MODE_ADVBI Legacy mode, Advanced SSI mode and Bi-SSI mode enabled 0x1 SSI_PP_MODE_ADVBIQUAD Legacy mode, Advanced mode, Bi-SSI and Quad-SSI mode enabled 0x2 RIS SSI Raw Interrupt Status 0x18 -1 read-write n 0x0 0x0 SSI_RIS_DMARXRIS SSI Receive DMA Raw Interrupt Status 4 5 SSI_RIS_DMATXRIS SSI Transmit DMA Raw Interrupt Status 5 6 SSI_RIS_EOTRIS End of Transmit Raw Interrupt Status 6 7 SSI_RIS_RORRIS SSI Receive Overrun Raw Interrupt Status 0 1 SSI_RIS_RTRIS SSI Receive Time-Out Raw Interrupt Status 1 2 SSI_RIS_RXRIS SSI Receive FIFO Raw Interrupt Status 2 3 SSI_RIS_TXRIS SSI Transmit FIFO Raw Interrupt Status 3 4 SR SSI Status 0xC -1 read-write n 0x0 0x0 SSI_SR_BSY SSI Busy Bit 4 5 SSI_SR_RFF SSI Receive FIFO Full 3 4 SSI_SR_RNE SSI Receive FIFO Not Empty 2 3 SSI_SR_TFE SSI Transmit FIFO Empty 0 1 SSI_SR_TNF SSI Transmit FIFO Not Full 1 2 SSI0CC SSI Clock Configuration 0xFC8 read-write n 0x0 0x0 SSI_CC_CS SSI Baud Clock Source 0 4 SSI_CC_CS_SYSPLL System clock (based on clock source and divisor factor) 0x0 SSI_CC_CS_PIOSC PIOSC 0x5 SSI0CPSR SSI Clock Prescale 0x10 read-write n 0x0 0x0 SSI_CPSR_CPSDVSR SSI Clock Prescale Divisor 0 8 SSI0CR0 SSI Control 0 0x0 read-write n 0x0 0x0 SSI_CR0_DSS SSI Data Size Select 0 4 SSI_CR0_DSS_4 4-bit data 0x3 SSI_CR0_DSS_5 5-bit data 0x4 SSI_CR0_DSS_6 6-bit data 0x5 SSI_CR0_DSS_7 7-bit data 0x6 SSI_CR0_DSS_8 8-bit data 0x7 SSI_CR0_DSS_9 9-bit data 0x8 SSI_CR0_DSS_10 10-bit data 0x9 SSI_CR0_DSS_11 11-bit data 0xa SSI_CR0_DSS_12 12-bit data 0xb SSI_CR0_DSS_13 13-bit data 0xc SSI_CR0_DSS_14 14-bit data 0xd SSI_CR0_DSS_15 15-bit data 0xe SSI_CR0_DSS_16 16-bit data 0xf SSI_CR0_FRF SSI Frame Format Select 4 6 SSI_CR0_FRF_MOTO Freescale SPI Frame Format 0x0 SSI_CR0_FRF_TI Synchronous Serial Frame Format 0x1 SSI_CR0_SCR SSI Serial Clock Rate 8 16 SSI_CR0_SPH SSI Serial Clock Phase 7 8 SSI_CR0_SPO SSI Serial Clock Polarity 6 7 SSI0CR1 SSI Control 1 0x4 read-write n 0x0 0x0 SSI_CR1_DIR SSI Direction of Operation 8 9 SSI_CR1_EOM Stop Frame (End of Message) 11 12 SSI_CR1_EOT End of Transmission 4 5 SSI_CR1_FSSHLDFRM FSS Hold Frame 10 11 SSI_CR1_HSCLKEN High Speed Clock Enable 9 10 SSI_CR1_LBM SSI Loopback Mode 0 1 SSI_CR1_MODE SSI Mode 6 8 SSI_CR1_MODE_LEGACY Legacy SSI mode 0x0 SSI_CR1_MODE_BI Bi-SSI mode 0x1 SSI_CR1_MODE_QUAD Quad-SSI Mode 0x2 SSI_CR1_MODE_ADVANCED Advanced SSI Mode with 8-bit packet size 0x3 SSI_CR1_MS SSI Master/Slave Select 2 3 SSI_CR1_SSE SSI Synchronous Serial Port Enable 1 2 SSI0DMACTL SSI DMA Control 0x24 read-write n 0x0 0x0 SSI_DMACTL_RXDMAE Receive DMA Enable 0 1 SSI_DMACTL_TXDMAE Transmit DMA Enable 1 2 SSI0DR SSI Data 0x8 read-write n 0x0 0x0 SSI_DR_DATA SSI Receive/Transmit Data 0 16 SSI0ICR SSI Interrupt Clear 0x20 write-only n 0x0 0x0 SSI_ICR_DMARXIC SSI Receive DMA Interrupt Clear 4 5 write-only SSI_ICR_DMATXIC SSI Transmit DMA Interrupt Clear 5 6 write-only SSI_ICR_EOTIC End of Transmit Interrupt Clear 6 7 write-only SSI_ICR_RORIC SSI Receive Overrun Interrupt Clear 0 1 write-only SSI_ICR_RTIC SSI Receive Time-Out Interrupt Clear 1 2 write-only SSI0IM SSI Interrupt Mask 0x14 read-write n 0x0 0x0 SSI_IM_DMARXIM SSI Receive DMA Interrupt Mask 4 5 SSI_IM_DMATXIM SSI Transmit DMA Interrupt Mask 5 6 SSI_IM_EOTIM End of Transmit Interrupt Mask 6 7 SSI_IM_RORIM SSI Receive Overrun Interrupt Mask 0 1 SSI_IM_RTIM SSI Receive Time-Out Interrupt Mask 1 2 SSI_IM_RXIM SSI Receive FIFO Interrupt Mask 2 3 SSI_IM_TXIM SSI Transmit FIFO Interrupt Mask 3 4 SSI0MIS SSI Masked Interrupt Status 0x1C read-write n 0x0 0x0 SSI_MIS_DMARXMIS SSI Receive DMA Masked Interrupt Status 4 5 SSI_MIS_DMATXMIS SSI Transmit DMA Masked Interrupt Status 5 6 SSI_MIS_EOTMIS End of Transmit Masked Interrupt Status 6 7 SSI_MIS_RORMIS SSI Receive Overrun Masked Interrupt Status 0 1 SSI_MIS_RTMIS SSI Receive Time-Out Masked Interrupt Status 1 2 SSI_MIS_RXMIS SSI Receive FIFO Masked Interrupt Status 2 3 SSI_MIS_TXMIS SSI Transmit FIFO Masked Interrupt Status 3 4 SSI0PP SSI Peripheral Properties 0xFC0 read-write n 0x0 0x0 SSI_PP_FSSHLDFRM FSS Hold Frame Capability 3 4 SSI_PP_HSCLK High Speed Capability 0 1 SSI_PP_MODE Mode of Operation 1 3 SSI_PP_MODE_LEGACY Legacy SSI mode 0x0 SSI_PP_MODE_ADVBI Legacy mode, Advanced SSI mode and Bi-SSI mode enabled 0x1 SSI_PP_MODE_ADVBIQUAD Legacy mode, Advanced mode, Bi-SSI and Quad-SSI mode enabled 0x2 SSI0RIS SSI Raw Interrupt Status 0x18 read-write n 0x0 0x0 SSI_RIS_DMARXRIS SSI Receive DMA Raw Interrupt Status 4 5 SSI_RIS_DMATXRIS SSI Transmit DMA Raw Interrupt Status 5 6 SSI_RIS_EOTRIS End of Transmit Raw Interrupt Status 6 7 SSI_RIS_RORRIS SSI Receive Overrun Raw Interrupt Status 0 1 SSI_RIS_RTRIS SSI Receive Time-Out Raw Interrupt Status 1 2 SSI_RIS_RXRIS SSI Receive FIFO Raw Interrupt Status 2 3 SSI_RIS_TXRIS SSI Transmit FIFO Raw Interrupt Status 3 4 SSI0SR SSI Status 0xC read-write n 0x0 0x0 SSI_SR_BSY SSI Busy Bit 4 5 SSI_SR_RFF SSI Receive FIFO Full 3 4 SSI_SR_RNE SSI Receive FIFO Not Empty 2 3 SSI_SR_TFE SSI Transmit FIFO Empty 0 1 SSI_SR_TNF SSI Transmit FIFO Not Full 1 2 SYSCTL Register map for SYSCTL peripheral SYSCTL 0x0 0x0 0x1000 registers n SYSCTL 28 ALTCLKCFG Alternate Clock Configuration 0x138 -1 read-write n 0x0 0x0 SYSCTL_ALTCLKCFG_ALTCLK Alternate Clock Source 0 4 SYSCTL_ALTCLKCFG_ALTCLK_PIOSC PIOSC 0x0 SYSCTL_ALTCLKCFG_ALTCLK_RTCOSC Hibernation Module Real-time clock output (RTCOSC) 0x3 SYSCTL_ALTCLKCFG_ALTCLK_LFIOSC Low-frequency internal oscillator (LFIOSC) 0x4 DCGCACMP Analog Comparator Deep-Sleep Mode Clock Gating Control 0x83C -1 read-write n 0x0 0x0 SYSCTL_DCGCACMP_D0 Analog Comparator Module 0 Deep-Sleep Mode Clock Gating Control 0 1 DCGCADC Analog-to-Digital Converter Deep-Sleep Mode Clock Gating Control 0x838 -1 read-write n 0x0 0x0 SYSCTL_DCGCADC_D0 ADC Module 0 Deep-Sleep Mode Clock Gating Control 0 1 SYSCTL_DCGCADC_D1 ADC Module 1 Deep-Sleep Mode Clock Gating Control 1 2 DCGCCAN Controller Area Network Deep-Sleep Mode Clock Gating Control 0x834 -1 read-write n 0x0 0x0 SYSCTL_DCGCCAN_D0 CAN Module 0 Deep-Sleep Mode Clock Gating Control 0 1 SYSCTL_DCGCCAN_D1 CAN Module 1 Deep-Sleep Mode Clock Gating Control 1 2 DCGCCCM CRC and Cryptographic Modules Deep-Sleep Mode Clock Gating Control 0x874 -1 read-write n 0x0 0x0 SYSCTL_DCGCCCM_D0 CRC and Cryptographic Modules Deep-Sleep Mode Clock Gating Control 0 1 DCGCDMA Micro Direct Memory Access Deep-Sleep Mode Clock Gating Control 0x80C -1 read-write n 0x0 0x0 SYSCTL_DCGCDMA_D0 uDMA Module Deep-Sleep Mode Clock Gating Control 0 1 DCGCEEPROM EEPROM Deep-Sleep Mode Clock Gating Control 0x858 -1 read-write n 0x0 0x0 SYSCTL_DCGCEEPROM_D0 EEPROM Module Deep-Sleep Mode Clock Gating Control 0 1 DCGCEPI EPI Deep-Sleep Mode Clock Gating Control 0x810 -1 read-write n 0x0 0x0 SYSCTL_DCGCEPI_D0 EPI Module Deep-Sleep Mode Clock Gating Control 0 1 DCGCGPIO General-Purpose Input/Output Deep-Sleep Mode Clock Gating Control 0x808 -1 read-write n 0x0 0x0 SYSCTL_DCGCGPIO_D0 GPIO Port A Deep-Sleep Mode Clock Gating Control 0 1 SYSCTL_DCGCGPIO_D1 GPIO Port B Deep-Sleep Mode Clock Gating Control 1 2 SYSCTL_DCGCGPIO_D10 GPIO Port L Deep-Sleep Mode Clock Gating Control 10 11 SYSCTL_DCGCGPIO_D11 GPIO Port M Deep-Sleep Mode Clock Gating Control 11 12 SYSCTL_DCGCGPIO_D12 GPIO Port N Deep-Sleep Mode Clock Gating Control 12 13 SYSCTL_DCGCGPIO_D13 GPIO Port P Deep-Sleep Mode Clock Gating Control 13 14 SYSCTL_DCGCGPIO_D14 GPIO Port Q Deep-Sleep Mode Clock Gating Control 14 15 SYSCTL_DCGCGPIO_D15 GPIO Port R Deep-Sleep Mode Clock Gating Control 15 16 SYSCTL_DCGCGPIO_D16 GPIO Port S Deep-Sleep Mode Clock Gating Control 16 17 SYSCTL_DCGCGPIO_D17 GPIO Port T Deep-Sleep Mode Clock Gating Control 17 18 SYSCTL_DCGCGPIO_D2 GPIO Port C Deep-Sleep Mode Clock Gating Control 2 3 SYSCTL_DCGCGPIO_D3 GPIO Port D Deep-Sleep Mode Clock Gating Control 3 4 SYSCTL_DCGCGPIO_D4 GPIO Port E Deep-Sleep Mode Clock Gating Control 4 5 SYSCTL_DCGCGPIO_D5 GPIO Port F Deep-Sleep Mode Clock Gating Control 5 6 SYSCTL_DCGCGPIO_D6 GPIO Port G Deep-Sleep Mode Clock Gating Control 6 7 SYSCTL_DCGCGPIO_D7 GPIO Port H Deep-Sleep Mode Clock Gating Control 7 8 SYSCTL_DCGCGPIO_D8 GPIO Port J Deep-Sleep Mode Clock Gating Control 8 9 SYSCTL_DCGCGPIO_D9 GPIO Port K Deep-Sleep Mode Clock Gating Control 9 10 DCGCHIB Hibernation Deep-Sleep Mode Clock Gating Control 0x814 -1 read-write n 0x0 0x0 SYSCTL_DCGCHIB_D0 Hibernation Module Deep-Sleep Mode Clock Gating Control 0 1 DCGCI2C Inter-Integrated Circuit Deep-Sleep Mode Clock Gating Control 0x820 -1 read-write n 0x0 0x0 SYSCTL_DCGCI2C_D0 I2C Module 0 Deep-Sleep Mode Clock Gating Control 0 1 SYSCTL_DCGCI2C_D1 I2C Module 1 Deep-Sleep Mode Clock Gating Control 1 2 SYSCTL_DCGCI2C_D2 I2C Module 2 Deep-Sleep Mode Clock Gating Control 2 3 SYSCTL_DCGCI2C_D3 I2C Module 3 Deep-Sleep Mode Clock Gating Control 3 4 SYSCTL_DCGCI2C_D4 I2C Module 4 Deep-Sleep Mode Clock Gating Control 4 5 SYSCTL_DCGCI2C_D5 I2C Module 5 Deep-Sleep Mode Clock Gating Control 5 6 SYSCTL_DCGCI2C_D6 I2C Module 6 Deep-Sleep Mode Clock Gating Control 6 7 SYSCTL_DCGCI2C_D7 I2C Module 7 Deep-Sleep Mode Clock Gating Control 7 8 SYSCTL_DCGCI2C_D8 I2C Module 8 Deep-Sleep Mode Clock Gating Control 8 9 SYSCTL_DCGCI2C_D9 I2C Module 9 Deep-Sleep Mode Clock Gating Control 9 10 DCGCPWM Pulse Width Modulator Deep-Sleep Mode Clock Gating Control 0x840 -1 read-write n 0x0 0x0 SYSCTL_DCGCPWM_D0 PWM Module 0 Deep-Sleep Mode Clock Gating Control 0 1 DCGCQEI Quadrature Encoder Interface Deep-Sleep Mode Clock Gating Control 0x844 -1 read-write n 0x0 0x0 SYSCTL_DCGCQEI_D0 QEI Module 0 Deep-Sleep Mode Clock Gating Control 0 1 DCGCSSI Synchronous Serial Interface Deep-Sleep Mode Clock Gating Control 0x81C -1 read-write n 0x0 0x0 SYSCTL_DCGCSSI_D0 SSI Module 0 Deep-Sleep Mode Clock Gating Control 0 1 SYSCTL_DCGCSSI_D1 SSI Module 1 Deep-Sleep Mode Clock Gating Control 1 2 SYSCTL_DCGCSSI_D2 SSI Module 2 Deep-Sleep Mode Clock Gating Control 2 3 SYSCTL_DCGCSSI_D3 SSI Module 3 Deep-Sleep Mode Clock Gating Control 3 4 DCGCTIMER 16/32-Bit General-Purpose Timer Deep-Sleep Mode Clock Gating Control 0x804 -1 read-write n 0x0 0x0 SYSCTL_DCGCTIMER_D0 16/32-Bit General-Purpose Timer 0 Deep-Sleep Mode Clock Gating Control 0 1 SYSCTL_DCGCTIMER_D1 16/32-Bit General-Purpose Timer 1 Deep-Sleep Mode Clock Gating Control 1 2 SYSCTL_DCGCTIMER_D2 16/32-Bit General-Purpose Timer 2 Deep-Sleep Mode Clock Gating Control 2 3 SYSCTL_DCGCTIMER_D3 16/32-Bit General-Purpose Timer 3 Deep-Sleep Mode Clock Gating Control 3 4 SYSCTL_DCGCTIMER_D4 16/32-Bit General-Purpose Timer 4 Deep-Sleep Mode Clock Gating Control 4 5 SYSCTL_DCGCTIMER_D5 16/32-Bit General-Purpose Timer 5 Deep-Sleep Mode Clock Gating Control 5 6 SYSCTL_DCGCTIMER_D6 16/32-Bit General-Purpose Timer 6 Deep-Sleep Mode Clock Gating Control 6 7 SYSCTL_DCGCTIMER_D7 16/32-Bit General-Purpose Timer 7 Deep-Sleep Mode Clock Gating Control 7 8 DCGCUART Universal Asynchronous Receiver/Transmitter Deep-Sleep Mode Clock Gating Control 0x818 -1 read-write n 0x0 0x0 SYSCTL_DCGCUART_D0 UART Module 0 Deep-Sleep Mode Clock Gating Control 0 1 SYSCTL_DCGCUART_D1 UART Module 1 Deep-Sleep Mode Clock Gating Control 1 2 SYSCTL_DCGCUART_D2 UART Module 2 Deep-Sleep Mode Clock Gating Control 2 3 SYSCTL_DCGCUART_D3 UART Module 3 Deep-Sleep Mode Clock Gating Control 3 4 SYSCTL_DCGCUART_D4 UART Module 4 Deep-Sleep Mode Clock Gating Control 4 5 SYSCTL_DCGCUART_D5 UART Module 5 Deep-Sleep Mode Clock Gating Control 5 6 SYSCTL_DCGCUART_D6 UART Module 6 Deep-Sleep Mode Clock Gating Control 6 7 SYSCTL_DCGCUART_D7 UART Module 7 Deep-Sleep Mode Clock Gating Control 7 8 DCGCUSB Universal Serial Bus Deep-Sleep Mode Clock Gating Control 0x828 -1 read-write n 0x0 0x0 SYSCTL_DCGCUSB_D0 USB Module Deep-Sleep Mode Clock Gating Control 0 1 DCGCWD Watchdog Timer Deep-Sleep Mode Clock Gating Control 0x800 -1 read-write n 0x0 0x0 SYSCTL_DCGCWD_D0 Watchdog Timer 0 Deep-Sleep Mode Clock Gating Control 0 1 SYSCTL_DCGCWD_D1 Watchdog Timer 1 Deep-Sleep Mode Clock Gating Control 1 2 DID0 Device Identification 0 0x0 -1 read-write n 0x0 0x0 SYSCTL_DID0_CLASS Device Class 16 24 SYSCTL_DID0_CLASS_TM4C129 Tiva(TM) TM4C129-class microcontrollers 0xa SYSCTL_DID0_MAJ Major Revision 8 16 SYSCTL_DID0_MAJ_REVA Revision A (initial device) 0x0 SYSCTL_DID0_MAJ_REVB Revision B (first base layer revision) 0x1 SYSCTL_DID0_MAJ_REVC Revision C (second base layer revision) 0x2 SYSCTL_DID0_MIN Minor Revision 0 8 SYSCTL_DID0_MIN_0 Initial device, or a major revision update 0x0 SYSCTL_DID0_MIN_1 First metal layer change 0x1 SYSCTL_DID0_MIN_2 Second metal layer change 0x2 SYSCTL_DID0_VER DID0 Version 28 31 SYSCTL_DID0_VER_1 Second version of the DID0 register format. 0x1 DID1 Device Identification 1 0x4 -1 read-write n 0x0 0x0 SYSCTL_DID1_FAM Family 24 28 SYSCTL_DID1_PINCNT Package Pin Count 13 16 SYSCTL_DID1_PINCNT_100 100-pin LQFP package 0x2 SYSCTL_DID1_PINCNT_64 64-pin LQFP package 0x3 SYSCTL_DID1_PINCNT_144 144-pin LQFP package 0x4 SYSCTL_DID1_PINCNT_157 157-pin BGA package 0x5 SYSCTL_DID1_PINCNT_128 128-pin TQFP package 0x6 SYSCTL_DID1_PKG Package Type 3 5 SYSCTL_DID1_PKG_QFP QFP package 0x1 SYSCTL_DID1_PKG_BGA BGA package 0x2 SYSCTL_DID1_PRTNO Part Number 16 24 SYSCTL_DID1_QUAL Qualification Status 0 2 SYSCTL_DID1_QUAL_ES Engineering Sample (unqualified) 0x0 SYSCTL_DID1_QUAL_PP Pilot Production (unqualified) 0x1 SYSCTL_DID1_QUAL_FQ Fully Qualified 0x2 SYSCTL_DID1_ROHS RoHS-Compliance 2 3 SYSCTL_DID1_TEMP Temperature Range 5 8 SYSCTL_DID1_TEMP_C Commercial temperature range 0x0 SYSCTL_DID1_TEMP_I Industrial temperature range 0x1 SYSCTL_DID1_TEMP_E Extended temperature range 0x2 SYSCTL_DID1_VER DID1 Version 28 32 DIVSCLK Divisor and Source Clock Configuration 0x148 -1 read-write n 0x0 0x0 SYSCTL_DIVSCLK_DIV Divisor Value 0 8 SYSCTL_DIVSCLK_EN DIVSCLK Enable 31 32 SYSCTL_DIVSCLK_SRC Clock Source 16 18 SYSCTL_DIVSCLK_SRC_SYSCLK System Clock 0x0 SYSCTL_DIVSCLK_SRC_PIOSC PIOSC 0x1 SYSCTL_DIVSCLK_SRC_MOSC MOSC 0x2 DSCLKCFG Deep Sleep Clock Configuration Register 0x144 -1 read-write n 0x0 0x0 SYSCTL_DSCLKCFG_DSOSCSRC Deep Sleep Oscillator Source 20 24 SYSCTL_DSCLKCFG_DSOSCSRC_PIOSC PIOSC 0x0 SYSCTL_DSCLKCFG_DSOSCSRC_LFIOSC LFIOSC 0x2 SYSCTL_DSCLKCFG_DSOSCSRC_MOSC MOSC 0x3 SYSCTL_DSCLKCFG_DSOSCSRC_RTC Hibernation Module RTCOSC 0x4 SYSCTL_DSCLKCFG_DSSYSDIV Deep Sleep Clock Divisor 0 10 SYSCTL_DSCLKCFG_MOSCDPD MOSC Disable Power Down 30 31 SYSCTL_DSCLKCFG_PIOSCPD PIOSC Power Down 31 32 DSLPPWRCFG Deep-Sleep Power Configuration 0x18C -1 read-write n 0x0 0x0 SYSCTL_DSLPPWRCFG_FLASHPM Flash Power Modes 4 6 SYSCTL_DSLPPWRCFG_FLASHPM_NRM Active Mode 0x0 SYSCTL_DSLPPWRCFG_FLASHPM_SLP Low Power Mode 0x2 SYSCTL_DSLPPWRCFG_LDOSM LDO Sleep Mode 9 10 SYSCTL_DSLPPWRCFG_SRAMPM SRAM Power Modes 0 2 SYSCTL_DSLPPWRCFG_SRAMPM_NRM Active Mode 0x0 SYSCTL_DSLPPWRCFG_SRAMPM_SBY Standby Mode 0x1 SYSCTL_DSLPPWRCFG_SRAMPM_LP Low Power Mode 0x3 SYSCTL_DSLPPWRCFG_TSPD Temperature Sense Power Down 8 9 HSSR Hardware System Service Request 0x1F4 -1 read-write n 0x0 0x0 SYSCTL_HSSR_CDOFF Command Descriptor Pointer 0 24 SYSCTL_HSSR_KEY Write Key 24 32 IMC Interrupt Mask Control 0x54 -1 read-write n 0x0 0x0 SYSCTL_IMC_BORIM Brown-Out Reset Interrupt Mask 1 2 SYSCTL_IMC_MOFIM Main Oscillator Failure Interrupt Mask 3 4 SYSCTL_IMC_MOSCPUPIM MOSC Power Up Interrupt Mask 8 9 SYSCTL_IMC_PLLLIM PLL Lock Interrupt Mask 6 7 LDODPCTL LDO Deep-Sleep Power Control 0x1BC -1 read-write n 0x0 0x0 SYSCTL_LDODPCTL_VADJEN Voltage Adjust Enable 31 32 SYSCTL_LDODPCTL_VLDO LDO Output Voltage 0 8 SYSCTL_LDODPCTL_VLDO_0_90V 0.90 V 0x12 SYSCTL_LDODPCTL_VLDO_0_95V 0.95 V 0x13 SYSCTL_LDODPCTL_VLDO_1_00V 1.00 V 0x14 SYSCTL_LDODPCTL_VLDO_1_05V 1.05 V 0x15 SYSCTL_LDODPCTL_VLDO_1_10V 1.10 V 0x16 SYSCTL_LDODPCTL_VLDO_1_15V 1.15 V 0x17 SYSCTL_LDODPCTL_VLDO_1_20V 1.20 V 0x18 SYSCTL_LDODPCTL_VLDO_1_25V 1.25 V 0x19 SYSCTL_LDODPCTL_VLDO_1_30V 1.30 V 0x1a SYSCTL_LDODPCTL_VLDO_1_35V 1.35 V 0x1b LDOSPCTL LDO Sleep Power Control 0x1B4 -1 read-write n 0x0 0x0 SYSCTL_LDOSPCTL_VADJEN Voltage Adjust Enable 31 32 SYSCTL_LDOSPCTL_VLDO LDO Output Voltage 0 8 SYSCTL_LDOSPCTL_VLDO_0_90V 0.90 V 0x12 SYSCTL_LDOSPCTL_VLDO_0_95V 0.95 V 0x13 SYSCTL_LDOSPCTL_VLDO_1_00V 1.00 V 0x14 SYSCTL_LDOSPCTL_VLDO_1_05V 1.05 V 0x15 SYSCTL_LDOSPCTL_VLDO_1_10V 1.10 V 0x16 SYSCTL_LDOSPCTL_VLDO_1_15V 1.15 V 0x17 SYSCTL_LDOSPCTL_VLDO_1_20V 1.20 V 0x18 MEMTIM0 Memory Timing Parameter Register 0 for Main Flash and EEPROM 0xC0 -1 read-write n 0x0 0x0 SYSCTL_MEMTIM0_EBCE EEPROM Bank Clock Edge 21 22 SYSCTL_MEMTIM0_EBCHT EEPROM Clock High Time 22 26 SYSCTL_MEMTIM0_EBCHT_0_5 1/2 system clock period 0x0 SYSCTL_MEMTIM0_EBCHT_1 1 system clock period 0x1 SYSCTL_MEMTIM0_EBCHT_1_5 1.5 system clock periods 0x2 SYSCTL_MEMTIM0_EBCHT_2 2 system clock periods 0x3 SYSCTL_MEMTIM0_EBCHT_2_5 2.5 system clock periods 0x4 SYSCTL_MEMTIM0_EBCHT_3 3 system clock periods 0x5 SYSCTL_MEMTIM0_EBCHT_3_5 3.5 system clock periods 0x6 SYSCTL_MEMTIM0_EBCHT_4 4 system clock periods 0x7 SYSCTL_MEMTIM0_EBCHT_4_5 4.5 system clock periods 0x8 SYSCTL_MEMTIM0_EWS EEPROM Wait States 16 20 SYSCTL_MEMTIM0_FBCE Flash Bank Clock Edge 5 6 SYSCTL_MEMTIM0_FBCHT Flash Bank Clock High Time 6 10 SYSCTL_MEMTIM0_FBCHT_0_5 1/2 system clock period 0x0 SYSCTL_MEMTIM0_FBCHT_1 1 system clock period 0x1 SYSCTL_MEMTIM0_FBCHT_1_5 1.5 system clock periods 0x2 SYSCTL_MEMTIM0_FBCHT_2 2 system clock periods 0x3 SYSCTL_MEMTIM0_FBCHT_2_5 2.5 system clock periods 0x4 SYSCTL_MEMTIM0_FBCHT_3 3 system clock periods 0x5 SYSCTL_MEMTIM0_FBCHT_3_5 3.5 system clock periods 0x6 SYSCTL_MEMTIM0_FBCHT_4 4 system clock periods 0x7 SYSCTL_MEMTIM0_FBCHT_4_5 4.5 system clock periods 0x8 SYSCTL_MEMTIM0_FWS Flash Wait State 0 4 MISC Masked Interrupt Status and Clear 0x58 -1 read-write n 0x0 0x0 SYSCTL_MISC_BORMIS BOR Masked Interrupt Status 1 2 SYSCTL_MISC_MOFMIS Main Oscillator Failure Masked Interrupt Status 3 4 SYSCTL_MISC_MOSCPUPMIS MOSC Power Up Masked Interrupt Status 8 9 SYSCTL_MISC_PLLLMIS PLL Lock Masked Interrupt Status 6 7 MOSCCTL Main Oscillator Control 0x7C -1 read-write n 0x0 0x0 SYSCTL_MOSCCTL_CVAL Clock Validation for MOSC 0 1 SYSCTL_MOSCCTL_MOSCIM MOSC Failure Action 1 2 SYSCTL_MOSCCTL_NOXTAL No Crystal Connected 2 3 SYSCTL_MOSCCTL_OSCRNG Oscillator Range 4 5 SYSCTL_MOSCCTL_PWRDN Power Down 3 4 NMIC NMI Cause Register 0x64 -1 read-write n 0x0 0x0 SYSCTL_NMIC_EXTERNAL External Pin NMI 0 1 SYSCTL_NMIC_MOSCFAIL MOSC Failure NMI 16 17 SYSCTL_NMIC_POWER Power/Brown Out Event NMI 2 3 SYSCTL_NMIC_TAMPER Tamper Event NMI 9 10 SYSCTL_NMIC_WDT0 Watch Dog Timer (WDT) 0 NMI 3 4 SYSCTL_NMIC_WDT1 Watch Dog Timer (WDT) 1 NMI 5 6 NVMSTAT Non-Volatile Memory Information 0x1A0 -1 read-write n 0x0 0x0 SYSCTL_NVMSTAT_FWB 32 Word Flash Write Buffer Available 0 1 PCACMP Analog Comparator Power Control 0x93C -1 read-write n 0x0 0x0 SYSCTL_PCACMP_P0 Analog Comparator Module 0 Power Control 0 1 PCADC Analog-to-Digital Converter Power Control 0x938 -1 read-write n 0x0 0x0 SYSCTL_PCADC_P0 ADC Module 0 Power Control 0 1 SYSCTL_PCADC_P1 ADC Module 1 Power Control 1 2 PCCAN Controller Area Network Power Control 0x934 -1 read-write n 0x0 0x0 SYSCTL_PCCAN_P0 CAN Module 0 Power Control 0 1 SYSCTL_PCCAN_P1 CAN Module 1 Power Control 1 2 PCCCM CRC and Cryptographic Modules Power Control 0x974 -1 read-write n 0x0 0x0 SYSCTL_PCCCM_P0 CRC and Cryptographic Modules Power Control 0 1 PCDMA Micro Direct Memory Access Power Control 0x90C -1 read-write n 0x0 0x0 SYSCTL_PCDMA_P0 uDMA Module Power Control 0 1 PCEEPROM EEPROM Power Control 0x958 -1 read-write n 0x0 0x0 SYSCTL_PCEEPROM_P0 EEPROM Module 0 Power Control 0 1 PCEPI External Peripheral Interface Power Control 0x910 -1 read-write n 0x0 0x0 SYSCTL_PCEPI_P0 EPI Module Power Control 0 1 PCGPIO General-Purpose Input/Output Power Control 0x908 -1 read-write n 0x0 0x0 SYSCTL_PCGPIO_P0 GPIO Port A Power Control 0 1 SYSCTL_PCGPIO_P1 GPIO Port B Power Control 1 2 SYSCTL_PCGPIO_P10 GPIO Port L Power Control 10 11 SYSCTL_PCGPIO_P11 GPIO Port M Power Control 11 12 SYSCTL_PCGPIO_P12 GPIO Port N Power Control 12 13 SYSCTL_PCGPIO_P13 GPIO Port P Power Control 13 14 SYSCTL_PCGPIO_P14 GPIO Port Q Power Control 14 15 SYSCTL_PCGPIO_P15 GPIO Port R Power Control 15 16 SYSCTL_PCGPIO_P16 GPIO Port S Power Control 16 17 SYSCTL_PCGPIO_P17 GPIO Port T Power Control 17 18 SYSCTL_PCGPIO_P2 GPIO Port C Power Control 2 3 SYSCTL_PCGPIO_P3 GPIO Port D Power Control 3 4 SYSCTL_PCGPIO_P4 GPIO Port E Power Control 4 5 SYSCTL_PCGPIO_P5 GPIO Port F Power Control 5 6 SYSCTL_PCGPIO_P6 GPIO Port G Power Control 6 7 SYSCTL_PCGPIO_P7 GPIO Port H Power Control 7 8 SYSCTL_PCGPIO_P8 GPIO Port J Power Control 8 9 SYSCTL_PCGPIO_P9 GPIO Port K Power Control 9 10 PCHIB Hibernation Power Control 0x914 -1 read-write n 0x0 0x0 SYSCTL_PCHIB_P0 Hibernation Module Power Control 0 1 PCI2C Inter-Integrated Circuit Power Control 0x920 -1 read-write n 0x0 0x0 SYSCTL_PCI2C_P0 I2C Module 0 Power Control 0 1 SYSCTL_PCI2C_P1 I2C Module 1 Power Control 1 2 SYSCTL_PCI2C_P2 I2C Module 2 Power Control 2 3 SYSCTL_PCI2C_P3 I2C Module 3 Power Control 3 4 SYSCTL_PCI2C_P4 I2C Module 4 Power Control 4 5 SYSCTL_PCI2C_P5 I2C Module 5 Power Control 5 6 SYSCTL_PCI2C_P6 I2C Module 6 Power Control 6 7 SYSCTL_PCI2C_P7 I2C Module 7 Power Control 7 8 SYSCTL_PCI2C_P8 I2C Module 8 Power Control 8 9 SYSCTL_PCI2C_P9 I2C Module 9 Power Control 9 10 PCPWM Pulse Width Modulator Power Control 0x940 -1 read-write n 0x0 0x0 SYSCTL_PCPWM_P0 PWM Module 0 Power Control 0 1 PCQEI Quadrature Encoder Interface Power Control 0x944 -1 read-write n 0x0 0x0 SYSCTL_PCQEI_P0 QEI Module 0 Power Control 0 1 PCSSI Synchronous Serial Interface Power Control 0x91C -1 read-write n 0x0 0x0 SYSCTL_PCSSI_P0 SSI Module 0 Power Control 0 1 SYSCTL_PCSSI_P1 SSI Module 1 Power Control 1 2 SYSCTL_PCSSI_P2 SSI Module 2 Power Control 2 3 SYSCTL_PCSSI_P3 SSI Module 3 Power Control 3 4 PCTIMER 16/32-Bit General-Purpose Timer Power Control 0x904 -1 read-write n 0x0 0x0 SYSCTL_PCTIMER_P0 General-Purpose Timer 0 Power Control 0 1 SYSCTL_PCTIMER_P1 General-Purpose Timer 1 Power Control 1 2 SYSCTL_PCTIMER_P2 General-Purpose Timer 2 Power Control 2 3 SYSCTL_PCTIMER_P3 General-Purpose Timer 3 Power Control 3 4 SYSCTL_PCTIMER_P4 General-Purpose Timer 4 Power Control 4 5 SYSCTL_PCTIMER_P5 General-Purpose Timer 5 Power Control 5 6 SYSCTL_PCTIMER_P6 General-Purpose Timer 6 Power Control 6 7 SYSCTL_PCTIMER_P7 General-Purpose Timer 7 Power Control 7 8 PCUART Universal Asynchronous Receiver/Transmitter Power Control 0x918 -1 read-write n 0x0 0x0 SYSCTL_PCUART_P0 UART Module 0 Power Control 0 1 SYSCTL_PCUART_P1 UART Module 1 Power Control 1 2 SYSCTL_PCUART_P2 UART Module 2 Power Control 2 3 SYSCTL_PCUART_P3 UART Module 3 Power Control 3 4 SYSCTL_PCUART_P4 UART Module 4 Power Control 4 5 SYSCTL_PCUART_P5 UART Module 5 Power Control 5 6 SYSCTL_PCUART_P6 UART Module 6 Power Control 6 7 SYSCTL_PCUART_P7 UART Module 7 Power Control 7 8 PCUSB Universal Serial Bus Power Control 0x928 -1 read-write n 0x0 0x0 SYSCTL_PCUSB_P0 USB Module Power Control 0 1 PCWD Watchdog Timer Power Control 0x900 -1 read-write n 0x0 0x0 SYSCTL_PCWD_P0 Watchdog Timer 0 Power Control 0 1 SYSCTL_PCWD_P1 Watchdog Timer 1 Power Control 1 2 PIOSCCAL Precision Internal Oscillator Calibration 0x150 -1 read-write n 0x0 0x0 SYSCTL_PIOSCCAL_CAL Start Calibration 9 10 SYSCTL_PIOSCCAL_UPDATE Update Trim 8 9 SYSCTL_PIOSCCAL_UT User Trim Value 0 7 SYSCTL_PIOSCCAL_UTEN Use User Trim Value 31 32 PIOSCSTAT Precision Internal Oscillator Statistics 0x154 -1 read-write n 0x0 0x0 SYSCTL_PIOSCSTAT_CR Calibration Result 8 10 SYSCTL_PIOSCSTAT_CRNONE Calibration has not been attempted 0x0 SYSCTL_PIOSCSTAT_CRPASS The last calibration operation completed to meet 1% accuracy 0x1 SYSCTL_PIOSCSTAT_CRFAIL The last calibration operation failed to meet 1% accuracy 0x2 SYSCTL_PIOSCSTAT_CT Calibration Trim Value 0 7 SYSCTL_PIOSCSTAT_DT Default Trim Value 16 23 PLLFREQ0 PLL Frequency 0 0x160 -1 read-write n 0x0 0x0 SYSCTL_PLLFREQ0_MFRAC PLL M Fractional Value 10 20 SYSCTL_PLLFREQ0_MINT PLL M Integer Value 0 10 SYSCTL_PLLFREQ0_PLLPWR PLL Power 23 24 PLLFREQ1 PLL Frequency 1 0x164 -1 read-write n 0x0 0x0 SYSCTL_PLLFREQ1_N PLL N Value 0 5 SYSCTL_PLLFREQ1_Q PLL Q Value 8 13 PLLSTAT PLL Status 0x168 -1 read-write n 0x0 0x0 SYSCTL_PLLSTAT_LOCK PLL Lock 0 1 PPACMP Analog Comparator Peripheral Present 0x33C -1 read-write n 0x0 0x0 SYSCTL_PPACMP_P0 Analog Comparator Module Present 0 1 PPADC Analog-to-Digital Converter Peripheral Present 0x338 -1 read-write n 0x0 0x0 SYSCTL_PPADC_P0 ADC Module 0 Present 0 1 SYSCTL_PPADC_P1 ADC Module 1 Present 1 2 PPCAN Controller Area Network Peripheral Present 0x334 -1 read-write n 0x0 0x0 SYSCTL_PPCAN_P0 CAN Module 0 Present 0 1 SYSCTL_PPCAN_P1 CAN Module 1 Present 1 2 PPCCM CRC and Cryptographic Modules Peripheral Present 0x374 -1 read-write n 0x0 0x0 SYSCTL_PPCCM_P0 CRC and Cryptographic Modules Present 0 1 PPDMA Micro Direct Memory Access Peripheral Present 0x30C -1 read-write n 0x0 0x0 SYSCTL_PPDMA_P0 uDMA Module Present 0 1 PPEEPROM EEPROM Peripheral Present 0x358 -1 read-write n 0x0 0x0 SYSCTL_PPEEPROM_P0 EEPROM Module Present 0 1 PPEMAC Ethernet MAC Peripheral Present 0x39C -1 read-write n 0x0 0x0 SYSCTL_PPEMAC_P0 Ethernet Controller Module Present 0 1 PPEPHY Ethernet PHY Peripheral Present 0x330 -1 read-write n 0x0 0x0 SYSCTL_PPEPHY_P0 Ethernet PHY Module Present 0 1 PPEPI EPI Peripheral Present 0x310 -1 read-write n 0x0 0x0 SYSCTL_PPEPI_P0 EPI Module Present 0 1 PPFAN Fan Control Peripheral Present 0x354 -1 read-write n 0x0 0x0 SYSCTL_PPFAN_P0 FAN Module 0 Present 0 1 PPGPIO General-Purpose Input/Output Peripheral Present 0x308 -1 read-write n 0x0 0x0 SYSCTL_PPGPIO_P0 GPIO Port A Present 0 1 SYSCTL_PPGPIO_P1 GPIO Port B Present 1 2 SYSCTL_PPGPIO_P10 GPIO Port L Present 10 11 SYSCTL_PPGPIO_P11 GPIO Port M Present 11 12 SYSCTL_PPGPIO_P12 GPIO Port N Present 12 13 SYSCTL_PPGPIO_P13 GPIO Port P Present 13 14 SYSCTL_PPGPIO_P14 GPIO Port Q Present 14 15 SYSCTL_PPGPIO_P15 GPIO Port R Present 15 16 SYSCTL_PPGPIO_P16 GPIO Port S Present 16 17 SYSCTL_PPGPIO_P17 GPIO Port T Present 17 18 SYSCTL_PPGPIO_P2 GPIO Port C Present 2 3 SYSCTL_PPGPIO_P3 GPIO Port D Present 3 4 SYSCTL_PPGPIO_P4 GPIO Port E Present 4 5 SYSCTL_PPGPIO_P5 GPIO Port F Present 5 6 SYSCTL_PPGPIO_P6 GPIO Port G Present 6 7 SYSCTL_PPGPIO_P7 GPIO Port H Present 7 8 SYSCTL_PPGPIO_P8 GPIO Port J Present 8 9 SYSCTL_PPGPIO_P9 GPIO Port K Present 9 10 PPHIB Hibernation Peripheral Present 0x314 -1 read-write n 0x0 0x0 SYSCTL_PPHIB_P0 Hibernation Module Present 0 1 PPHIM Human Interface Master Peripheral Present 0x3A4 -1 read-write n 0x0 0x0 SYSCTL_PPHIM_P0 HIM Module Present 0 1 PPI2C Inter-Integrated Circuit Peripheral Present 0x320 -1 read-write n 0x0 0x0 SYSCTL_PPI2C_P0 I2C Module 0 Present 0 1 SYSCTL_PPI2C_P1 I2C Module 1 Present 1 2 SYSCTL_PPI2C_P2 I2C Module 2 Present 2 3 SYSCTL_PPI2C_P3 I2C Module 3 Present 3 4 SYSCTL_PPI2C_P4 I2C Module 4 Present 4 5 SYSCTL_PPI2C_P5 I2C Module 5 Present 5 6 SYSCTL_PPI2C_P6 I2C Module 6 Present 6 7 SYSCTL_PPI2C_P7 I2C Module 7 Present 7 8 SYSCTL_PPI2C_P8 I2C Module 8 Present 8 9 SYSCTL_PPI2C_P9 I2C Module 9 Present 9 10 PPLCD LCD Peripheral Present 0x390 -1 read-write n 0x0 0x0 SYSCTL_PPLCD_P0 LCD Module Present 0 1 PPLPC Low Pin Count Interface Peripheral Present 0x348 -1 read-write n 0x0 0x0 SYSCTL_PPLPC_P0 LPC Module Present 0 1 PPOWIRE 1-Wire Peripheral Present 0x398 -1 read-write n 0x0 0x0 SYSCTL_PPOWIRE_P0 1-Wire Module Present 0 1 PPPECI Platform Environment Control Interface Peripheral Present 0x350 -1 read-write n 0x0 0x0 SYSCTL_PPPECI_P0 PECI Module Present 0 1 PPPWM Pulse Width Modulator Peripheral Present 0x340 -1 read-write n 0x0 0x0 SYSCTL_PPPWM_P0 PWM Module 0 Present 0 1 PPQEI Quadrature Encoder Interface Peripheral Present 0x344 -1 read-write n 0x0 0x0 SYSCTL_PPQEI_P0 QEI Module 0 Present 0 1 PPRTS Remote Temperature Sensor Peripheral Present 0x370 -1 read-write n 0x0 0x0 SYSCTL_PPRTS_P0 RTS Module Present 0 1 PPSSI Synchronous Serial Interface Peripheral Present 0x31C -1 read-write n 0x0 0x0 SYSCTL_PPSSI_P0 SSI Module 0 Present 0 1 SYSCTL_PPSSI_P1 SSI Module 1 Present 1 2 SYSCTL_PPSSI_P2 SSI Module 2 Present 2 3 SYSCTL_PPSSI_P3 SSI Module 3 Present 3 4 PPTIMER 16/32-Bit General-Purpose Timer Peripheral Present 0x304 -1 read-write n 0x0 0x0 SYSCTL_PPTIMER_P0 16/32-Bit General-Purpose Timer 0 Present 0 1 SYSCTL_PPTIMER_P1 16/32-Bit General-Purpose Timer 1 Present 1 2 SYSCTL_PPTIMER_P2 16/32-Bit General-Purpose Timer 2 Present 2 3 SYSCTL_PPTIMER_P3 16/32-Bit General-Purpose Timer 3 Present 3 4 SYSCTL_PPTIMER_P4 16/32-Bit General-Purpose Timer 4 Present 4 5 SYSCTL_PPTIMER_P5 16/32-Bit General-Purpose Timer 5 Present 5 6 SYSCTL_PPTIMER_P6 16/32-Bit General-Purpose Timer 6 Present 6 7 SYSCTL_PPTIMER_P7 16/32-Bit General-Purpose Timer 7 Present 7 8 PPUART Universal Asynchronous Receiver/Transmitter Peripheral Present 0x318 -1 read-write n 0x0 0x0 SYSCTL_PPUART_P0 UART Module 0 Present 0 1 SYSCTL_PPUART_P1 UART Module 1 Present 1 2 SYSCTL_PPUART_P2 UART Module 2 Present 2 3 SYSCTL_PPUART_P3 UART Module 3 Present 3 4 SYSCTL_PPUART_P4 UART Module 4 Present 4 5 SYSCTL_PPUART_P5 UART Module 5 Present 5 6 SYSCTL_PPUART_P6 UART Module 6 Present 6 7 SYSCTL_PPUART_P7 UART Module 7 Present 7 8 PPUSB Universal Serial Bus Peripheral Present 0x328 -1 read-write n 0x0 0x0 SYSCTL_PPUSB_P0 USB Module Present 0 1 PPWD Watchdog Timer Peripheral Present 0x300 -1 read-write n 0x0 0x0 SYSCTL_PPWD_P0 Watchdog Timer 0 Present 0 1 SYSCTL_PPWD_P1 Watchdog Timer 1 Present 1 2 PPWTIMER 32/64-Bit Wide General-Purpose Timer Peripheral Present 0x35C -1 read-write n 0x0 0x0 SYSCTL_PPWTIMER_P0 32/64-Bit Wide General-Purpose Timer 0 Present 0 1 PRACMP Analog Comparator Peripheral Ready 0xA3C -1 read-write n 0x0 0x0 SYSCTL_PRACMP_R0 Analog Comparator Module 0 Peripheral Ready 0 1 PRADC Analog-to-Digital Converter Peripheral Ready 0xA38 -1 read-write n 0x0 0x0 SYSCTL_PRADC_R0 ADC Module 0 Peripheral Ready 0 1 SYSCTL_PRADC_R1 ADC Module 1 Peripheral Ready 1 2 PRCAN Controller Area Network Peripheral Ready 0xA34 -1 read-write n 0x0 0x0 SYSCTL_PRCAN_R0 CAN Module 0 Peripheral Ready 0 1 SYSCTL_PRCAN_R1 CAN Module 1 Peripheral Ready 1 2 PRCCM CRC and Cryptographic Modules Peripheral Ready 0xA74 -1 read-write n 0x0 0x0 SYSCTL_PRCCM_R0 CRC and Cryptographic Modules Peripheral Ready 0 1 PRDMA Micro Direct Memory Access Peripheral Ready 0xA0C -1 read-write n 0x0 0x0 SYSCTL_PRDMA_R0 uDMA Module Peripheral Ready 0 1 PREEPROM EEPROM Peripheral Ready 0xA58 -1 read-write n 0x0 0x0 SYSCTL_PREEPROM_R0 EEPROM Module Peripheral Ready 0 1 PREPI EPI Peripheral Ready 0xA10 -1 read-write n 0x0 0x0 SYSCTL_PREPI_R0 EPI Module Peripheral Ready 0 1 PRGPIO General-Purpose Input/Output Peripheral Ready 0xA08 -1 read-write n 0x0 0x0 SYSCTL_PRGPIO_R0 GPIO Port A Peripheral Ready 0 1 SYSCTL_PRGPIO_R1 GPIO Port B Peripheral Ready 1 2 SYSCTL_PRGPIO_R10 GPIO Port L Peripheral Ready 10 11 SYSCTL_PRGPIO_R11 GPIO Port M Peripheral Ready 11 12 SYSCTL_PRGPIO_R12 GPIO Port N Peripheral Ready 12 13 SYSCTL_PRGPIO_R13 GPIO Port P Peripheral Ready 13 14 SYSCTL_PRGPIO_R14 GPIO Port Q Peripheral Ready 14 15 SYSCTL_PRGPIO_R15 GPIO Port R Peripheral Ready 15 16 SYSCTL_PRGPIO_R16 GPIO Port S Peripheral Ready 16 17 SYSCTL_PRGPIO_R17 GPIO Port T Peripheral Ready 17 18 SYSCTL_PRGPIO_R2 GPIO Port C Peripheral Ready 2 3 SYSCTL_PRGPIO_R3 GPIO Port D Peripheral Ready 3 4 SYSCTL_PRGPIO_R4 GPIO Port E Peripheral Ready 4 5 SYSCTL_PRGPIO_R5 GPIO Port F Peripheral Ready 5 6 SYSCTL_PRGPIO_R6 GPIO Port G Peripheral Ready 6 7 SYSCTL_PRGPIO_R7 GPIO Port H Peripheral Ready 7 8 SYSCTL_PRGPIO_R8 GPIO Port J Peripheral Ready 8 9 SYSCTL_PRGPIO_R9 GPIO Port K Peripheral Ready 9 10 PRHIB Hibernation Peripheral Ready 0xA14 -1 read-write n 0x0 0x0 SYSCTL_PRHIB_R0 Hibernation Module Peripheral Ready 0 1 PRI2C Inter-Integrated Circuit Peripheral Ready 0xA20 -1 read-write n 0x0 0x0 SYSCTL_PRI2C_R0 I2C Module 0 Peripheral Ready 0 1 SYSCTL_PRI2C_R1 I2C Module 1 Peripheral Ready 1 2 SYSCTL_PRI2C_R2 I2C Module 2 Peripheral Ready 2 3 SYSCTL_PRI2C_R3 I2C Module 3 Peripheral Ready 3 4 SYSCTL_PRI2C_R4 I2C Module 4 Peripheral Ready 4 5 SYSCTL_PRI2C_R5 I2C Module 5 Peripheral Ready 5 6 SYSCTL_PRI2C_R6 I2C Module 6 Peripheral Ready 6 7 SYSCTL_PRI2C_R7 I2C Module 7 Peripheral Ready 7 8 SYSCTL_PRI2C_R8 I2C Module 8 Peripheral Ready 8 9 SYSCTL_PRI2C_R9 I2C Module 9 Peripheral Ready 9 10 PRPWM Pulse Width Modulator Peripheral Ready 0xA40 -1 read-write n 0x0 0x0 SYSCTL_PRPWM_R0 PWM Module 0 Peripheral Ready 0 1 PRQEI Quadrature Encoder Interface Peripheral Ready 0xA44 -1 read-write n 0x0 0x0 SYSCTL_PRQEI_R0 QEI Module 0 Peripheral Ready 0 1 PRSSI Synchronous Serial Interface Peripheral Ready 0xA1C -1 read-write n 0x0 0x0 SYSCTL_PRSSI_R0 SSI Module 0 Peripheral Ready 0 1 SYSCTL_PRSSI_R1 SSI Module 1 Peripheral Ready 1 2 SYSCTL_PRSSI_R2 SSI Module 2 Peripheral Ready 2 3 SYSCTL_PRSSI_R3 SSI Module 3 Peripheral Ready 3 4 PRTIMER 16/32-Bit General-Purpose Timer Peripheral Ready 0xA04 -1 read-write n 0x0 0x0 SYSCTL_PRTIMER_R0 16/32-Bit General-Purpose Timer 0 Peripheral Ready 0 1 SYSCTL_PRTIMER_R1 16/32-Bit General-Purpose Timer 1 Peripheral Ready 1 2 SYSCTL_PRTIMER_R2 16/32-Bit General-Purpose Timer 2 Peripheral Ready 2 3 SYSCTL_PRTIMER_R3 16/32-Bit General-Purpose Timer 3 Peripheral Ready 3 4 SYSCTL_PRTIMER_R4 16/32-Bit General-Purpose Timer 4 Peripheral Ready 4 5 SYSCTL_PRTIMER_R5 16/32-Bit General-Purpose Timer 5 Peripheral Ready 5 6 SYSCTL_PRTIMER_R6 16/32-Bit General-Purpose Timer 6 Peripheral Ready 6 7 SYSCTL_PRTIMER_R7 16/32-Bit General-Purpose Timer 7 Peripheral Ready 7 8 PRUART Universal Asynchronous Receiver/Transmitter Peripheral Ready 0xA18 -1 read-write n 0x0 0x0 SYSCTL_PRUART_R0 UART Module 0 Peripheral Ready 0 1 SYSCTL_PRUART_R1 UART Module 1 Peripheral Ready 1 2 SYSCTL_PRUART_R2 UART Module 2 Peripheral Ready 2 3 SYSCTL_PRUART_R3 UART Module 3 Peripheral Ready 3 4 SYSCTL_PRUART_R4 UART Module 4 Peripheral Ready 4 5 SYSCTL_PRUART_R5 UART Module 5 Peripheral Ready 5 6 SYSCTL_PRUART_R6 UART Module 6 Peripheral Ready 6 7 SYSCTL_PRUART_R7 UART Module 7 Peripheral Ready 7 8 PRUSB Universal Serial Bus Peripheral Ready 0xA28 -1 read-write n 0x0 0x0 SYSCTL_PRUSB_R0 USB Module Peripheral Ready 0 1 PRWD Watchdog Timer Peripheral Ready 0xA00 -1 read-write n 0x0 0x0 SYSCTL_PRWD_R0 Watchdog Timer 0 Peripheral Ready 0 1 SYSCTL_PRWD_R1 Watchdog Timer 1 Peripheral Ready 1 2 PTBOCTL Power-Temp Brown Out Control 0x38 -1 read-write n 0x0 0x0 SYSCTL_PTBOCTL_VDDA_UBOR VDDA under BOR Event Action 8 10 SYSCTL_PTBOCTL_VDDA_UBOR_NONE No Action 0x0 SYSCTL_PTBOCTL_VDDA_UBOR_SYSINT System control interrupt 0x1 SYSCTL_PTBOCTL_VDDA_UBOR_NMI NMI 0x2 SYSCTL_PTBOCTL_VDDA_UBOR_RST Reset 0x3 SYSCTL_PTBOCTL_VDD_UBOR VDD (VDDS) under BOR Event Action 0 2 SYSCTL_PTBOCTL_VDD_UBOR_NONE No Action 0x0 SYSCTL_PTBOCTL_VDD_UBOR_SYSINT System control interrupt 0x1 SYSCTL_PTBOCTL_VDD_UBOR_NMI NMI 0x2 SYSCTL_PTBOCTL_VDD_UBOR_RST Reset 0x3 PWRTC Power-Temperature Cause 0x60 -1 read-write n 0x0 0x0 SYSCTL_PWRTC_VDDA_UBOR VDDA Under BOR Status 4 5 SYSCTL_PWRTC_VDD_UBOR VDD Under BOR Status 0 1 RCGCACMP Analog Comparator Run Mode Clock Gating Control 0x63C -1 read-write n 0x0 0x0 SYSCTL_RCGCACMP_R0 Analog Comparator Module 0 Run Mode Clock Gating Control 0 1 RCGCADC Analog-to-Digital Converter Run Mode Clock Gating Control 0x638 -1 read-write n 0x0 0x0 SYSCTL_RCGCADC_R0 ADC Module 0 Run Mode Clock Gating Control 0 1 SYSCTL_RCGCADC_R1 ADC Module 1 Run Mode Clock Gating Control 1 2 RCGCCAN Controller Area Network Run Mode Clock Gating Control 0x634 -1 read-write n 0x0 0x0 SYSCTL_RCGCCAN_R0 CAN Module 0 Run Mode Clock Gating Control 0 1 SYSCTL_RCGCCAN_R1 CAN Module 1 Run Mode Clock Gating Control 1 2 RCGCCCM CRC and Cryptographic Modules Run Mode Clock Gating Control 0x674 -1 read-write n 0x0 0x0 SYSCTL_RCGCCCM_R0 CRC and Cryptographic Modules Run Mode Clock Gating Control 0 1 RCGCDMA Micro Direct Memory Access Run Mode Clock Gating Control 0x60C -1 read-write n 0x0 0x0 SYSCTL_RCGCDMA_R0 uDMA Module Run Mode Clock Gating Control 0 1 RCGCEEPROM EEPROM Run Mode Clock Gating Control 0x658 -1 read-write n 0x0 0x0 SYSCTL_RCGCEEPROM_R0 EEPROM Module Run Mode Clock Gating Control 0 1 RCGCEPI EPI Run Mode Clock Gating Control 0x610 -1 read-write n 0x0 0x0 SYSCTL_RCGCEPI_R0 EPI Module Run Mode Clock Gating Control 0 1 RCGCGPIO General-Purpose Input/Output Run Mode Clock Gating Control 0x608 -1 read-write n 0x0 0x0 SYSCTL_RCGCGPIO_R0 GPIO Port A Run Mode Clock Gating Control 0 1 SYSCTL_RCGCGPIO_R1 GPIO Port B Run Mode Clock Gating Control 1 2 SYSCTL_RCGCGPIO_R10 GPIO Port L Run Mode Clock Gating Control 10 11 SYSCTL_RCGCGPIO_R11 GPIO Port M Run Mode Clock Gating Control 11 12 SYSCTL_RCGCGPIO_R12 GPIO Port N Run Mode Clock Gating Control 12 13 SYSCTL_RCGCGPIO_R13 GPIO Port P Run Mode Clock Gating Control 13 14 SYSCTL_RCGCGPIO_R14 GPIO Port Q Run Mode Clock Gating Control 14 15 SYSCTL_RCGCGPIO_R15 GPIO Port R Run Mode Clock Gating Control 15 16 SYSCTL_RCGCGPIO_R16 GPIO Port S Run Mode Clock Gating Control 16 17 SYSCTL_RCGCGPIO_R17 GPIO Port T Run Mode Clock Gating Control 17 18 SYSCTL_RCGCGPIO_R2 GPIO Port C Run Mode Clock Gating Control 2 3 SYSCTL_RCGCGPIO_R3 GPIO Port D Run Mode Clock Gating Control 3 4 SYSCTL_RCGCGPIO_R4 GPIO Port E Run Mode Clock Gating Control 4 5 SYSCTL_RCGCGPIO_R5 GPIO Port F Run Mode Clock Gating Control 5 6 SYSCTL_RCGCGPIO_R6 GPIO Port G Run Mode Clock Gating Control 6 7 SYSCTL_RCGCGPIO_R7 GPIO Port H Run Mode Clock Gating Control 7 8 SYSCTL_RCGCGPIO_R8 GPIO Port J Run Mode Clock Gating Control 8 9 SYSCTL_RCGCGPIO_R9 GPIO Port K Run Mode Clock Gating Control 9 10 RCGCHIB Hibernation Run Mode Clock Gating Control 0x614 -1 read-write n 0x0 0x0 SYSCTL_RCGCHIB_R0 Hibernation Module Run Mode Clock Gating Control 0 1 RCGCI2C Inter-Integrated Circuit Run Mode Clock Gating Control 0x620 -1 read-write n 0x0 0x0 SYSCTL_RCGCI2C_R0 I2C Module 0 Run Mode Clock Gating Control 0 1 SYSCTL_RCGCI2C_R1 I2C Module 1 Run Mode Clock Gating Control 1 2 SYSCTL_RCGCI2C_R2 I2C Module 2 Run Mode Clock Gating Control 2 3 SYSCTL_RCGCI2C_R3 I2C Module 3 Run Mode Clock Gating Control 3 4 SYSCTL_RCGCI2C_R4 I2C Module 4 Run Mode Clock Gating Control 4 5 SYSCTL_RCGCI2C_R5 I2C Module 5 Run Mode Clock Gating Control 5 6 SYSCTL_RCGCI2C_R6 I2C Module 6 Run Mode Clock Gating Control 6 7 SYSCTL_RCGCI2C_R7 I2C Module 7 Run Mode Clock Gating Control 7 8 SYSCTL_RCGCI2C_R8 I2C Module 8 Run Mode Clock Gating Control 8 9 SYSCTL_RCGCI2C_R9 I2C Module 9 Run Mode Clock Gating Control 9 10 RCGCPWM Pulse Width Modulator Run Mode Clock Gating Control 0x640 -1 read-write n 0x0 0x0 SYSCTL_RCGCPWM_R0 PWM Module 0 Run Mode Clock Gating Control 0 1 RCGCQEI Quadrature Encoder Interface Run Mode Clock Gating Control 0x644 -1 read-write n 0x0 0x0 SYSCTL_RCGCQEI_R0 QEI Module 0 Run Mode Clock Gating Control 0 1 RCGCSSI Synchronous Serial Interface Run Mode Clock Gating Control 0x61C -1 read-write n 0x0 0x0 SYSCTL_RCGCSSI_R0 SSI Module 0 Run Mode Clock Gating Control 0 1 SYSCTL_RCGCSSI_R1 SSI Module 1 Run Mode Clock Gating Control 1 2 SYSCTL_RCGCSSI_R2 SSI Module 2 Run Mode Clock Gating Control 2 3 SYSCTL_RCGCSSI_R3 SSI Module 3 Run Mode Clock Gating Control 3 4 RCGCTIMER 16/32-Bit General-Purpose Timer Run Mode Clock Gating Control 0x604 -1 read-write n 0x0 0x0 SYSCTL_RCGCTIMER_R0 16/32-Bit General-Purpose Timer 0 Run Mode Clock Gating Control 0 1 SYSCTL_RCGCTIMER_R1 16/32-Bit General-Purpose Timer 1 Run Mode Clock Gating Control 1 2 SYSCTL_RCGCTIMER_R2 16/32-Bit General-Purpose Timer 2 Run Mode Clock Gating Control 2 3 SYSCTL_RCGCTIMER_R3 16/32-Bit General-Purpose Timer 3 Run Mode Clock Gating Control 3 4 SYSCTL_RCGCTIMER_R4 16/32-Bit General-Purpose Timer 4 Run Mode Clock Gating Control 4 5 SYSCTL_RCGCTIMER_R5 16/32-Bit General-Purpose Timer 5 Run Mode Clock Gating Control 5 6 SYSCTL_RCGCTIMER_R6 16/32-Bit General-Purpose Timer 6 Run Mode Clock Gating Control 6 7 SYSCTL_RCGCTIMER_R7 16/32-Bit General-Purpose Timer 7 Run Mode Clock Gating Control 7 8 RCGCUART Universal Asynchronous Receiver/Transmitter Run Mode Clock Gating Control 0x618 -1 read-write n 0x0 0x0 SYSCTL_RCGCUART_R0 UART Module 0 Run Mode Clock Gating Control 0 1 SYSCTL_RCGCUART_R1 UART Module 1 Run Mode Clock Gating Control 1 2 SYSCTL_RCGCUART_R2 UART Module 2 Run Mode Clock Gating Control 2 3 SYSCTL_RCGCUART_R3 UART Module 3 Run Mode Clock Gating Control 3 4 SYSCTL_RCGCUART_R4 UART Module 4 Run Mode Clock Gating Control 4 5 SYSCTL_RCGCUART_R5 UART Module 5 Run Mode Clock Gating Control 5 6 SYSCTL_RCGCUART_R6 UART Module 6 Run Mode Clock Gating Control 6 7 SYSCTL_RCGCUART_R7 UART Module 7 Run Mode Clock Gating Control 7 8 RCGCUSB Universal Serial Bus Run Mode Clock Gating Control 0x628 -1 read-write n 0x0 0x0 SYSCTL_RCGCUSB_R0 USB Module Run Mode Clock Gating Control 0 1 RCGCWD Watchdog Timer Run Mode Clock Gating Control 0x600 -1 read-write n 0x0 0x0 SYSCTL_RCGCWD_R0 Watchdog Timer 0 Run Mode Clock Gating Control 0 1 SYSCTL_RCGCWD_R1 Watchdog Timer 1 Run Mode Clock Gating Control 1 2 RESBEHAVCTL Reset Behavior Control Register 0x1D8 -1 read-write n 0x0 0x0 SYSCTL_RESBEHAVCTL_BOR BOR Reset operation 2 4 SYSCTL_RESBEHAVCTL_BOR_SYSRST Brown Out Reset issues system reset. The application starts within 10 us 0x2 SYSCTL_RESBEHAVCTL_BOR_POR Brown Out Reset issues a simulated POR sequence. The application starts less than 500 us after deassertion (Default) 0x3 SYSCTL_RESBEHAVCTL_EXTRES External RST Pin Operation 0 2 SYSCTL_RESBEHAVCTL_EXTRES_SYSRST External RST assertion issues a system reset. The application starts within 10 us 0x2 SYSCTL_RESBEHAVCTL_EXTRES_POR External RST assertion issues a simulated POR sequence. Application starts less than 500 us after deassertion (Default) 0x3 SYSCTL_RESBEHAVCTL_WDOG0 Watchdog 0 Reset Operation 4 6 SYSCTL_RESBEHAVCTL_WDOG0_SYSRST Watchdog 0 issues a system reset. The application starts within 10 us 0x2 SYSCTL_RESBEHAVCTL_WDOG0_POR Watchdog 0 issues a simulated POR sequence. Application starts less than 500 us after deassertion (Default) 0x3 SYSCTL_RESBEHAVCTL_WDOG1 Watchdog 1 Reset Operation 6 8 SYSCTL_RESBEHAVCTL_WDOG1_SYSRST Watchdog 1 issues a system reset. The application starts within 10 us 0x2 SYSCTL_RESBEHAVCTL_WDOG1_POR Watchdog 1 issues a simulated POR sequence. Application starts less than 500 us after deassertion (Default) 0x3 RESC Reset Cause 0x5C -1 read-write n 0x0 0x0 SYSCTL_RESC_BOR Brown-Out Reset 2 3 SYSCTL_RESC_EXT External Reset 0 1 SYSCTL_RESC_HIB HIB Reset 6 7 SYSCTL_RESC_HSSR HSSR Reset 12 13 SYSCTL_RESC_MOSCFAIL MOSC Failure Reset 16 17 SYSCTL_RESC_POR Power-On Reset 1 2 SYSCTL_RESC_SW Software Reset 4 5 SYSCTL_RESC_WDT0 Watchdog Timer 0 Reset 3 4 SYSCTL_RESC_WDT1 Watchdog Timer 1 Reset 5 6 RIS Raw Interrupt Status 0x50 -1 read-write n 0x0 0x0 SYSCTL_RIS_BORRIS Brown-Out Reset Raw Interrupt Status 1 2 SYSCTL_RIS_MOFRIS Main Oscillator Failure Raw Interrupt Status 3 4 SYSCTL_RIS_MOSCPUPRIS MOSC Power Up Raw Interrupt Status 8 9 SYSCTL_RIS_PLLLRIS PLL Lock Raw Interrupt Status 6 7 RSCLKCFG Run and Sleep Mode Configuration Register 0xB0 -1 read-write n 0x0 0x0 SYSCTL_RSCLKCFG_ACG Auto Clock Gating 29 30 SYSCTL_RSCLKCFG_MEMTIMU Memory Timing Register Update 31 32 SYSCTL_RSCLKCFG_NEWFREQ New PLLFREQ Accept 30 31 SYSCTL_RSCLKCFG_OSCSRC Oscillator Source 20 24 SYSCTL_RSCLKCFG_OSCSRC_PIOSC PIOSC is oscillator source 0x0 SYSCTL_RSCLKCFG_OSCSRC_LFIOSC LFIOSC is oscillator source 0x2 SYSCTL_RSCLKCFG_OSCSRC_MOSC MOSC is oscillator source 0x3 SYSCTL_RSCLKCFG_OSCSRC_RTC Hibernation Module RTC Oscillator (RTCOSC) 0x4 SYSCTL_RSCLKCFG_OSYSDIV Oscillator System Clock Divisor 10 20 SYSCTL_RSCLKCFG_PLLSRC PLL Source 24 28 SYSCTL_RSCLKCFG_PLLSRC_PIOSC PIOSC is PLL input clock source 0x0 SYSCTL_RSCLKCFG_PLLSRC_MOSC MOSC is the PLL input clock source 0x3 SYSCTL_RSCLKCFG_PSYSDIV PLL System Clock Divisor 0 10 SYSCTL_RSCLKCFG_USEPLL Use PLL 28 29 SCGCACMP Analog Comparator Sleep Mode Clock Gating Control 0x73C -1 read-write n 0x0 0x0 SYSCTL_SCGCACMP_S0 Analog Comparator Module 0 Sleep Mode Clock Gating Control 0 1 SCGCADC Analog-to-Digital Converter Sleep Mode Clock Gating Control 0x738 -1 read-write n 0x0 0x0 SYSCTL_SCGCADC_S0 ADC Module 0 Sleep Mode Clock Gating Control 0 1 SYSCTL_SCGCADC_S1 ADC Module 1 Sleep Mode Clock Gating Control 1 2 SCGCCAN Controller Area Network Sleep Mode Clock Gating Control 0x734 -1 read-write n 0x0 0x0 SYSCTL_SCGCCAN_S0 CAN Module 0 Sleep Mode Clock Gating Control 0 1 SYSCTL_SCGCCAN_S1 CAN Module 1 Sleep Mode Clock Gating Control 1 2 SCGCCCM CRC and Cryptographic Modules Sleep Mode Clock Gating Control 0x774 -1 read-write n 0x0 0x0 SYSCTL_SCGCCCM_S0 CRC and Cryptographic Modules Sleep Mode Clock Gating Control 0 1 SCGCDMA Micro Direct Memory Access Sleep Mode Clock Gating Control 0x70C -1 read-write n 0x0 0x0 SYSCTL_SCGCDMA_S0 uDMA Module Sleep Mode Clock Gating Control 0 1 SCGCEEPROM EEPROM Sleep Mode Clock Gating Control 0x758 -1 read-write n 0x0 0x0 SYSCTL_SCGCEEPROM_S0 EEPROM Module Sleep Mode Clock Gating Control 0 1 SCGCEPI EPI Sleep Mode Clock Gating Control 0x710 -1 read-write n 0x0 0x0 SYSCTL_SCGCEPI_S0 EPI Module Sleep Mode Clock Gating Control 0 1 SCGCGPIO General-Purpose Input/Output Sleep Mode Clock Gating Control 0x708 -1 read-write n 0x0 0x0 SYSCTL_SCGCGPIO_S0 GPIO Port A Sleep Mode Clock Gating Control 0 1 SYSCTL_SCGCGPIO_S1 GPIO Port B Sleep Mode Clock Gating Control 1 2 SYSCTL_SCGCGPIO_S10 GPIO Port L Sleep Mode Clock Gating Control 10 11 SYSCTL_SCGCGPIO_S11 GPIO Port M Sleep Mode Clock Gating Control 11 12 SYSCTL_SCGCGPIO_S12 GPIO Port N Sleep Mode Clock Gating Control 12 13 SYSCTL_SCGCGPIO_S13 GPIO Port P Sleep Mode Clock Gating Control 13 14 SYSCTL_SCGCGPIO_S14 GPIO Port Q Sleep Mode Clock Gating Control 14 15 SYSCTL_SCGCGPIO_S15 GPIO Port R Sleep Mode Clock Gating Control 15 16 SYSCTL_SCGCGPIO_S16 GPIO Port S Sleep Mode Clock Gating Control 16 17 SYSCTL_SCGCGPIO_S17 GPIO Port T Sleep Mode Clock Gating Control 17 18 SYSCTL_SCGCGPIO_S2 GPIO Port C Sleep Mode Clock Gating Control 2 3 SYSCTL_SCGCGPIO_S3 GPIO Port D Sleep Mode Clock Gating Control 3 4 SYSCTL_SCGCGPIO_S4 GPIO Port E Sleep Mode Clock Gating Control 4 5 SYSCTL_SCGCGPIO_S5 GPIO Port F Sleep Mode Clock Gating Control 5 6 SYSCTL_SCGCGPIO_S6 GPIO Port G Sleep Mode Clock Gating Control 6 7 SYSCTL_SCGCGPIO_S7 GPIO Port H Sleep Mode Clock Gating Control 7 8 SYSCTL_SCGCGPIO_S8 GPIO Port J Sleep Mode Clock Gating Control 8 9 SYSCTL_SCGCGPIO_S9 GPIO Port K Sleep Mode Clock Gating Control 9 10 SCGCHIB Hibernation Sleep Mode Clock Gating Control 0x714 -1 read-write n 0x0 0x0 SYSCTL_SCGCHIB_S0 Hibernation Module Sleep Mode Clock Gating Control 0 1 SCGCI2C Inter-Integrated Circuit Sleep Mode Clock Gating Control 0x720 -1 read-write n 0x0 0x0 SYSCTL_SCGCI2C_S0 I2C Module 0 Sleep Mode Clock Gating Control 0 1 SYSCTL_SCGCI2C_S1 I2C Module 1 Sleep Mode Clock Gating Control 1 2 SYSCTL_SCGCI2C_S2 I2C Module 2 Sleep Mode Clock Gating Control 2 3 SYSCTL_SCGCI2C_S3 I2C Module 3 Sleep Mode Clock Gating Control 3 4 SYSCTL_SCGCI2C_S4 I2C Module 4 Sleep Mode Clock Gating Control 4 5 SYSCTL_SCGCI2C_S5 I2C Module 5 Sleep Mode Clock Gating Control 5 6 SYSCTL_SCGCI2C_S6 I2C Module 6 Sleep Mode Clock Gating Control 6 7 SYSCTL_SCGCI2C_S7 I2C Module 7 Sleep Mode Clock Gating Control 7 8 SYSCTL_SCGCI2C_S8 I2C Module 8 Sleep Mode Clock Gating Control 8 9 SYSCTL_SCGCI2C_S9 I2C Module 9 Sleep Mode Clock Gating Control 9 10 SCGCPWM Pulse Width Modulator Sleep Mode Clock Gating Control 0x740 -1 read-write n 0x0 0x0 SYSCTL_SCGCPWM_S0 PWM Module 0 Sleep Mode Clock Gating Control 0 1 SCGCQEI Quadrature Encoder Interface Sleep Mode Clock Gating Control 0x744 -1 read-write n 0x0 0x0 SYSCTL_SCGCQEI_S0 QEI Module 0 Sleep Mode Clock Gating Control 0 1 SCGCSSI Synchronous Serial Interface Sleep Mode Clock Gating Control 0x71C -1 read-write n 0x0 0x0 SYSCTL_SCGCSSI_S0 SSI Module 0 Sleep Mode Clock Gating Control 0 1 SYSCTL_SCGCSSI_S1 SSI Module 1 Sleep Mode Clock Gating Control 1 2 SYSCTL_SCGCSSI_S2 SSI Module 2 Sleep Mode Clock Gating Control 2 3 SYSCTL_SCGCSSI_S3 SSI Module 3 Sleep Mode Clock Gating Control 3 4 SCGCTIMER 16/32-Bit General-Purpose Timer Sleep Mode Clock Gating Control 0x704 -1 read-write n 0x0 0x0 SYSCTL_SCGCTIMER_S0 16/32-Bit General-Purpose Timer 0 Sleep Mode Clock Gating Control 0 1 SYSCTL_SCGCTIMER_S1 16/32-Bit General-Purpose Timer 1 Sleep Mode Clock Gating Control 1 2 SYSCTL_SCGCTIMER_S2 16/32-Bit General-Purpose Timer 2 Sleep Mode Clock Gating Control 2 3 SYSCTL_SCGCTIMER_S3 16/32-Bit General-Purpose Timer 3 Sleep Mode Clock Gating Control 3 4 SYSCTL_SCGCTIMER_S4 16/32-Bit General-Purpose Timer 4 Sleep Mode Clock Gating Control 4 5 SYSCTL_SCGCTIMER_S5 16/32-Bit General-Purpose Timer 5 Sleep Mode Clock Gating Control 5 6 SYSCTL_SCGCTIMER_S6 16/32-Bit General-Purpose Timer 6 Sleep Mode Clock Gating Control 6 7 SYSCTL_SCGCTIMER_S7 16/32-Bit General-Purpose Timer 7 Sleep Mode Clock Gating Control 7 8 SCGCUART Universal Asynchronous Receiver/Transmitter Sleep Mode Clock Gating Control 0x718 -1 read-write n 0x0 0x0 SYSCTL_SCGCUART_S0 UART Module 0 Sleep Mode Clock Gating Control 0 1 SYSCTL_SCGCUART_S1 UART Module 1 Sleep Mode Clock Gating Control 1 2 SYSCTL_SCGCUART_S2 UART Module 2 Sleep Mode Clock Gating Control 2 3 SYSCTL_SCGCUART_S3 UART Module 3 Sleep Mode Clock Gating Control 3 4 SYSCTL_SCGCUART_S4 UART Module 4 Sleep Mode Clock Gating Control 4 5 SYSCTL_SCGCUART_S5 UART Module 5 Sleep Mode Clock Gating Control 5 6 SYSCTL_SCGCUART_S6 UART Module 6 Sleep Mode Clock Gating Control 6 7 SYSCTL_SCGCUART_S7 UART Module 7 Sleep Mode Clock Gating Control 7 8 SCGCUSB Universal Serial Bus Sleep Mode Clock Gating Control 0x728 -1 read-write n 0x0 0x0 SYSCTL_SCGCUSB_S0 USB Module Sleep Mode Clock Gating Control 0 1 SCGCWD Watchdog Timer Sleep Mode Clock Gating Control 0x700 -1 read-write n 0x0 0x0 SYSCTL_SCGCWD_S0 Watchdog Timer 0 Sleep Mode Clock Gating Control 0 1 SYSCTL_SCGCWD_S1 Watchdog Timer 1 Sleep Mode Clock Gating Control 1 2 SLPPWRCFG Sleep Power Configuration 0x188 -1 read-write n 0x0 0x0 SYSCTL_SLPPWRCFG_FLASHPM Flash Power Modes 4 6 SYSCTL_SLPPWRCFG_FLASHPM_NRM Active Mode 0x0 SYSCTL_SLPPWRCFG_FLASHPM_SLP Low Power Mode 0x2 SYSCTL_SLPPWRCFG_SRAMPM SRAM Power Modes 0 2 SYSCTL_SLPPWRCFG_SRAMPM_NRM Active Mode 0x0 SYSCTL_SLPPWRCFG_SRAMPM_SBY Standby Mode 0x1 SYSCTL_SLPPWRCFG_SRAMPM_LP Low Power Mode 0x3 SRACMP Analog Comparator Software Reset 0x53C -1 read-write n 0x0 0x0 SYSCTL_SRACMP_R0 Analog Comparator Module 0 Software Reset 0 1 SRADC Analog-to-Digital Converter Software Reset 0x538 -1 read-write n 0x0 0x0 SYSCTL_SRADC_R0 ADC Module 0 Software Reset 0 1 SYSCTL_SRADC_R1 ADC Module 1 Software Reset 1 2 SRCAN Controller Area Network Software Reset 0x534 -1 read-write n 0x0 0x0 SYSCTL_SRCAN_R0 CAN Module 0 Software Reset 0 1 SYSCTL_SRCAN_R1 CAN Module 1 Software Reset 1 2 SRCCM CRC and Cryptographic Modules Software Reset 0x574 -1 read-write n 0x0 0x0 SYSCTL_SRCCM_R0 CRC and Cryptographic Modules Software Reset 0 1 SRDMA Micro Direct Memory Access Software Reset 0x50C -1 read-write n 0x0 0x0 SYSCTL_SRDMA_R0 uDMA Module Software Reset 0 1 SREEPROM EEPROM Software Reset 0x558 -1 read-write n 0x0 0x0 SYSCTL_SREEPROM_R0 EEPROM Module Software Reset 0 1 SREPI EPI Software Reset 0x510 -1 read-write n 0x0 0x0 SYSCTL_SREPI_R0 EPI Module Software Reset 0 1 SRGPIO General-Purpose Input/Output Software Reset 0x508 -1 read-write n 0x0 0x0 SYSCTL_SRGPIO_R0 GPIO Port A Software Reset 0 1 SYSCTL_SRGPIO_R1 GPIO Port B Software Reset 1 2 SYSCTL_SRGPIO_R10 GPIO Port L Software Reset 10 11 SYSCTL_SRGPIO_R11 GPIO Port M Software Reset 11 12 SYSCTL_SRGPIO_R12 GPIO Port N Software Reset 12 13 SYSCTL_SRGPIO_R13 GPIO Port P Software Reset 13 14 SYSCTL_SRGPIO_R14 GPIO Port Q Software Reset 14 15 SYSCTL_SRGPIO_R15 GPIO Port R Software Reset 15 16 SYSCTL_SRGPIO_R16 GPIO Port S Software Reset 16 17 SYSCTL_SRGPIO_R17 GPIO Port T Software Reset 17 18 SYSCTL_SRGPIO_R2 GPIO Port C Software Reset 2 3 SYSCTL_SRGPIO_R3 GPIO Port D Software Reset 3 4 SYSCTL_SRGPIO_R4 GPIO Port E Software Reset 4 5 SYSCTL_SRGPIO_R5 GPIO Port F Software Reset 5 6 SYSCTL_SRGPIO_R6 GPIO Port G Software Reset 6 7 SYSCTL_SRGPIO_R7 GPIO Port H Software Reset 7 8 SYSCTL_SRGPIO_R8 GPIO Port J Software Reset 8 9 SYSCTL_SRGPIO_R9 GPIO Port K Software Reset 9 10 SRHIB Hibernation Software Reset 0x514 -1 read-write n 0x0 0x0 SYSCTL_SRHIB_R0 Hibernation Module Software Reset 0 1 SRI2C Inter-Integrated Circuit Software Reset 0x520 -1 read-write n 0x0 0x0 SYSCTL_SRI2C_R0 I2C Module 0 Software Reset 0 1 SYSCTL_SRI2C_R1 I2C Module 1 Software Reset 1 2 SYSCTL_SRI2C_R2 I2C Module 2 Software Reset 2 3 SYSCTL_SRI2C_R3 I2C Module 3 Software Reset 3 4 SYSCTL_SRI2C_R4 I2C Module 4 Software Reset 4 5 SYSCTL_SRI2C_R5 I2C Module 5 Software Reset 5 6 SYSCTL_SRI2C_R6 I2C Module 6 Software Reset 6 7 SYSCTL_SRI2C_R7 I2C Module 7 Software Reset 7 8 SYSCTL_SRI2C_R8 I2C Module 8 Software Reset 8 9 SYSCTL_SRI2C_R9 I2C Module 9 Software Reset 9 10 SRPWM Pulse Width Modulator Software Reset 0x540 -1 read-write n 0x0 0x0 SYSCTL_SRPWM_R0 PWM Module 0 Software Reset 0 1 SRQEI Quadrature Encoder Interface Software Reset 0x544 -1 read-write n 0x0 0x0 SYSCTL_SRQEI_R0 QEI Module 0 Software Reset 0 1 SRSSI Synchronous Serial Interface Software Reset 0x51C -1 read-write n 0x0 0x0 SYSCTL_SRSSI_R0 SSI Module 0 Software Reset 0 1 SYSCTL_SRSSI_R1 SSI Module 1 Software Reset 1 2 SYSCTL_SRSSI_R2 SSI Module 2 Software Reset 2 3 SYSCTL_SRSSI_R3 SSI Module 3 Software Reset 3 4 SRTIMER 16/32-Bit General-Purpose Timer Software Reset 0x504 -1 read-write n 0x0 0x0 SYSCTL_SRTIMER_R0 16/32-Bit General-Purpose Timer 0 Software Reset 0 1 SYSCTL_SRTIMER_R1 16/32-Bit General-Purpose Timer 1 Software Reset 1 2 SYSCTL_SRTIMER_R2 16/32-Bit General-Purpose Timer 2 Software Reset 2 3 SYSCTL_SRTIMER_R3 16/32-Bit General-Purpose Timer 3 Software Reset 3 4 SYSCTL_SRTIMER_R4 16/32-Bit General-Purpose Timer 4 Software Reset 4 5 SYSCTL_SRTIMER_R5 16/32-Bit General-Purpose Timer 5 Software Reset 5 6 SYSCTL_SRTIMER_R6 16/32-Bit General-Purpose Timer 6 Software Reset 6 7 SYSCTL_SRTIMER_R7 16/32-Bit General-Purpose Timer 7 Software Reset 7 8 SRUART Universal Asynchronous Receiver/Transmitter Software Reset 0x518 -1 read-write n 0x0 0x0 SYSCTL_SRUART_R0 UART Module 0 Software Reset 0 1 SYSCTL_SRUART_R1 UART Module 1 Software Reset 1 2 SYSCTL_SRUART_R2 UART Module 2 Software Reset 2 3 SYSCTL_SRUART_R3 UART Module 3 Software Reset 3 4 SYSCTL_SRUART_R4 UART Module 4 Software Reset 4 5 SYSCTL_SRUART_R5 UART Module 5 Software Reset 5 6 SYSCTL_SRUART_R6 UART Module 6 Software Reset 6 7 SYSCTL_SRUART_R7 UART Module 7 Software Reset 7 8 SRUSB Universal Serial Bus Software Reset 0x528 -1 read-write n 0x0 0x0 SYSCTL_SRUSB_R0 USB Module Software Reset 0 1 SRWD Watchdog Timer Software Reset 0x500 -1 read-write n 0x0 0x0 SYSCTL_SRWD_R0 Watchdog Timer 0 Software Reset 0 1 SYSCTL_SRWD_R1 Watchdog Timer 1 Software Reset 1 2 SYSCTLALTCLKCFG Alternate Clock Configuration 0x138 read-write n 0x0 0x0 SYSCTL_ALTCLKCFG_ALTCLK Alternate Clock Source 0 4 SYSCTL_ALTCLKCFG_ALTCLK_PIOSC PIOSC 0x0 SYSCTL_ALTCLKCFG_ALTCLK_RTCOSC Hibernation Module Real-time clock output (RTCOSC) 0x3 SYSCTL_ALTCLKCFG_ALTCLK_LFIOSC Low-frequency internal oscillator (LFIOSC) 0x4 SYSCTLDCGCACMP Analog Comparator Deep-Sleep Mode Clock Gating Control 0x83C read-write n 0x0 0x0 SYSCTL_DCGCACMP_D0 Analog Comparator Module 0 Deep-Sleep Mode Clock Gating Control 0 1 SYSCTLDCGCADC Analog-to-Digital Converter Deep-Sleep Mode Clock Gating Control 0x838 read-write n 0x0 0x0 SYSCTL_DCGCADC_D0 ADC Module 0 Deep-Sleep Mode Clock Gating Control 0 1 SYSCTL_DCGCADC_D1 ADC Module 1 Deep-Sleep Mode Clock Gating Control 1 2 SYSCTLDCGCCAN Controller Area Network Deep-Sleep Mode Clock Gating Control 0x834 read-write n 0x0 0x0 SYSCTL_DCGCCAN_D0 CAN Module 0 Deep-Sleep Mode Clock Gating Control 0 1 SYSCTL_DCGCCAN_D1 CAN Module 1 Deep-Sleep Mode Clock Gating Control 1 2 SYSCTLDCGCCCM CRC and Cryptographic Modules Deep-Sleep Mode Clock Gating Control 0x874 read-write n 0x0 0x0 SYSCTL_DCGCCCM_D0 CRC and Cryptographic Modules Deep-Sleep Mode Clock Gating Control 0 1 SYSCTLDCGCDMA Micro Direct Memory Access Deep-Sleep Mode Clock Gating Control 0x80C read-write n 0x0 0x0 SYSCTL_DCGCDMA_D0 uDMA Module Deep-Sleep Mode Clock Gating Control 0 1 SYSCTLDCGCEEPROM EEPROM Deep-Sleep Mode Clock Gating Control 0x858 read-write n 0x0 0x0 SYSCTL_DCGCEEPROM_D0 EEPROM Module Deep-Sleep Mode Clock Gating Control 0 1 SYSCTLDCGCEPI EPI Deep-Sleep Mode Clock Gating Control 0x810 read-write n 0x0 0x0 SYSCTL_DCGCEPI_D0 EPI Module Deep-Sleep Mode Clock Gating Control 0 1 SYSCTLDCGCGPIO General-Purpose Input/Output Deep-Sleep Mode Clock Gating Control 0x808 read-write n 0x0 0x0 SYSCTL_DCGCGPIO_D0 GPIO Port A Deep-Sleep Mode Clock Gating Control 0 1 SYSCTL_DCGCGPIO_D1 GPIO Port B Deep-Sleep Mode Clock Gating Control 1 2 SYSCTL_DCGCGPIO_D10 GPIO Port L Deep-Sleep Mode Clock Gating Control 10 11 SYSCTL_DCGCGPIO_D11 GPIO Port M Deep-Sleep Mode Clock Gating Control 11 12 SYSCTL_DCGCGPIO_D12 GPIO Port N Deep-Sleep Mode Clock Gating Control 12 13 SYSCTL_DCGCGPIO_D13 GPIO Port P Deep-Sleep Mode Clock Gating Control 13 14 SYSCTL_DCGCGPIO_D14 GPIO Port Q Deep-Sleep Mode Clock Gating Control 14 15 SYSCTL_DCGCGPIO_D15 GPIO Port R Deep-Sleep Mode Clock Gating Control 15 16 SYSCTL_DCGCGPIO_D16 GPIO Port S Deep-Sleep Mode Clock Gating Control 16 17 SYSCTL_DCGCGPIO_D17 GPIO Port T Deep-Sleep Mode Clock Gating Control 17 18 SYSCTL_DCGCGPIO_D2 GPIO Port C Deep-Sleep Mode Clock Gating Control 2 3 SYSCTL_DCGCGPIO_D3 GPIO Port D Deep-Sleep Mode Clock Gating Control 3 4 SYSCTL_DCGCGPIO_D4 GPIO Port E Deep-Sleep Mode Clock Gating Control 4 5 SYSCTL_DCGCGPIO_D5 GPIO Port F Deep-Sleep Mode Clock Gating Control 5 6 SYSCTL_DCGCGPIO_D6 GPIO Port G Deep-Sleep Mode Clock Gating Control 6 7 SYSCTL_DCGCGPIO_D7 GPIO Port H Deep-Sleep Mode Clock Gating Control 7 8 SYSCTL_DCGCGPIO_D8 GPIO Port J Deep-Sleep Mode Clock Gating Control 8 9 SYSCTL_DCGCGPIO_D9 GPIO Port K Deep-Sleep Mode Clock Gating Control 9 10 SYSCTLDCGCHIB Hibernation Deep-Sleep Mode Clock Gating Control 0x814 read-write n 0x0 0x0 SYSCTL_DCGCHIB_D0 Hibernation Module Deep-Sleep Mode Clock Gating Control 0 1 SYSCTLDCGCI2C Inter-Integrated Circuit Deep-Sleep Mode Clock Gating Control 0x820 read-write n 0x0 0x0 SYSCTL_DCGCI2C_D0 I2C Module 0 Deep-Sleep Mode Clock Gating Control 0 1 SYSCTL_DCGCI2C_D1 I2C Module 1 Deep-Sleep Mode Clock Gating Control 1 2 SYSCTL_DCGCI2C_D2 I2C Module 2 Deep-Sleep Mode Clock Gating Control 2 3 SYSCTL_DCGCI2C_D3 I2C Module 3 Deep-Sleep Mode Clock Gating Control 3 4 SYSCTL_DCGCI2C_D4 I2C Module 4 Deep-Sleep Mode Clock Gating Control 4 5 SYSCTL_DCGCI2C_D5 I2C Module 5 Deep-Sleep Mode Clock Gating Control 5 6 SYSCTL_DCGCI2C_D6 I2C Module 6 Deep-Sleep Mode Clock Gating Control 6 7 SYSCTL_DCGCI2C_D7 I2C Module 7 Deep-Sleep Mode Clock Gating Control 7 8 SYSCTL_DCGCI2C_D8 I2C Module 8 Deep-Sleep Mode Clock Gating Control 8 9 SYSCTL_DCGCI2C_D9 I2C Module 9 Deep-Sleep Mode Clock Gating Control 9 10 SYSCTLDCGCPWM Pulse Width Modulator Deep-Sleep Mode Clock Gating Control 0x840 read-write n 0x0 0x0 SYSCTL_DCGCPWM_D0 PWM Module 0 Deep-Sleep Mode Clock Gating Control 0 1 SYSCTLDCGCQEI Quadrature Encoder Interface Deep-Sleep Mode Clock Gating Control 0x844 read-write n 0x0 0x0 SYSCTL_DCGCQEI_D0 QEI Module 0 Deep-Sleep Mode Clock Gating Control 0 1 SYSCTLDCGCSSI Synchronous Serial Interface Deep-Sleep Mode Clock Gating Control 0x81C read-write n 0x0 0x0 SYSCTL_DCGCSSI_D0 SSI Module 0 Deep-Sleep Mode Clock Gating Control 0 1 SYSCTL_DCGCSSI_D1 SSI Module 1 Deep-Sleep Mode Clock Gating Control 1 2 SYSCTL_DCGCSSI_D2 SSI Module 2 Deep-Sleep Mode Clock Gating Control 2 3 SYSCTL_DCGCSSI_D3 SSI Module 3 Deep-Sleep Mode Clock Gating Control 3 4 SYSCTLDCGCTIMER 16/32-Bit General-Purpose Timer Deep-Sleep Mode Clock Gating Control 0x804 read-write n 0x0 0x0 SYSCTL_DCGCTIMER_D0 16/32-Bit General-Purpose Timer 0 Deep-Sleep Mode Clock Gating Control 0 1 SYSCTL_DCGCTIMER_D1 16/32-Bit General-Purpose Timer 1 Deep-Sleep Mode Clock Gating Control 1 2 SYSCTL_DCGCTIMER_D2 16/32-Bit General-Purpose Timer 2 Deep-Sleep Mode Clock Gating Control 2 3 SYSCTL_DCGCTIMER_D3 16/32-Bit General-Purpose Timer 3 Deep-Sleep Mode Clock Gating Control 3 4 SYSCTL_DCGCTIMER_D4 16/32-Bit General-Purpose Timer 4 Deep-Sleep Mode Clock Gating Control 4 5 SYSCTL_DCGCTIMER_D5 16/32-Bit General-Purpose Timer 5 Deep-Sleep Mode Clock Gating Control 5 6 SYSCTL_DCGCTIMER_D6 16/32-Bit General-Purpose Timer 6 Deep-Sleep Mode Clock Gating Control 6 7 SYSCTL_DCGCTIMER_D7 16/32-Bit General-Purpose Timer 7 Deep-Sleep Mode Clock Gating Control 7 8 SYSCTLDCGCUART Universal Asynchronous Receiver/Transmitter Deep-Sleep Mode Clock Gating Control 0x818 read-write n 0x0 0x0 SYSCTL_DCGCUART_D0 UART Module 0 Deep-Sleep Mode Clock Gating Control 0 1 SYSCTL_DCGCUART_D1 UART Module 1 Deep-Sleep Mode Clock Gating Control 1 2 SYSCTL_DCGCUART_D2 UART Module 2 Deep-Sleep Mode Clock Gating Control 2 3 SYSCTL_DCGCUART_D3 UART Module 3 Deep-Sleep Mode Clock Gating Control 3 4 SYSCTL_DCGCUART_D4 UART Module 4 Deep-Sleep Mode Clock Gating Control 4 5 SYSCTL_DCGCUART_D5 UART Module 5 Deep-Sleep Mode Clock Gating Control 5 6 SYSCTL_DCGCUART_D6 UART Module 6 Deep-Sleep Mode Clock Gating Control 6 7 SYSCTL_DCGCUART_D7 UART Module 7 Deep-Sleep Mode Clock Gating Control 7 8 SYSCTLDCGCUSB Universal Serial Bus Deep-Sleep Mode Clock Gating Control 0x828 read-write n 0x0 0x0 SYSCTL_DCGCUSB_D0 USB Module Deep-Sleep Mode Clock Gating Control 0 1 SYSCTLDCGCWD Watchdog Timer Deep-Sleep Mode Clock Gating Control 0x800 read-write n 0x0 0x0 SYSCTL_DCGCWD_D0 Watchdog Timer 0 Deep-Sleep Mode Clock Gating Control 0 1 SYSCTL_DCGCWD_D1 Watchdog Timer 1 Deep-Sleep Mode Clock Gating Control 1 2 SYSCTLDID0 Device Identification 0 0x0 read-write n 0x0 0x0 SYSCTL_DID0_CLASS Device Class 16 24 SYSCTL_DID0_CLASS_TM4C129 Tiva(TM) TM4C129-class microcontrollers 0xa SYSCTL_DID0_MAJ Major Revision 8 16 SYSCTL_DID0_MAJ_REVA Revision A (initial device) 0x0 SYSCTL_DID0_MAJ_REVB Revision B (first base layer revision) 0x1 SYSCTL_DID0_MAJ_REVC Revision C (second base layer revision) 0x2 SYSCTL_DID0_MIN Minor Revision 0 8 SYSCTL_DID0_MIN_0 Initial device, or a major revision update 0x0 SYSCTL_DID0_MIN_1 First metal layer change 0x1 SYSCTL_DID0_MIN_2 Second metal layer change 0x2 SYSCTL_DID0_VER DID0 Version 28 31 SYSCTL_DID0_VER_1 Second version of the DID0 register format. 0x1 SYSCTLDID1 Device Identification 1 0x4 read-write n 0x0 0x0 SYSCTL_DID1_FAM Family 24 28 SYSCTL_DID1_PINCNT Package Pin Count 13 16 SYSCTL_DID1_PINCNT_100 100-pin LQFP package 0x2 SYSCTL_DID1_PINCNT_64 64-pin LQFP package 0x3 SYSCTL_DID1_PINCNT_144 144-pin LQFP package 0x4 SYSCTL_DID1_PINCNT_157 157-pin BGA package 0x5 SYSCTL_DID1_PINCNT_128 128-pin TQFP package 0x6 SYSCTL_DID1_PKG Package Type 3 5 SYSCTL_DID1_PKG_QFP QFP package 0x1 SYSCTL_DID1_PKG_BGA BGA package 0x2 SYSCTL_DID1_PRTNO Part Number 16 24 SYSCTL_DID1_QUAL Qualification Status 0 2 SYSCTL_DID1_QUAL_ES Engineering Sample (unqualified) 0x0 SYSCTL_DID1_QUAL_PP Pilot Production (unqualified) 0x1 SYSCTL_DID1_QUAL_FQ Fully Qualified 0x2 SYSCTL_DID1_ROHS RoHS-Compliance 2 3 SYSCTL_DID1_TEMP Temperature Range 5 8 SYSCTL_DID1_TEMP_C Commercial temperature range 0x0 SYSCTL_DID1_TEMP_I Industrial temperature range 0x1 SYSCTL_DID1_TEMP_E Extended temperature range 0x2 SYSCTL_DID1_VER DID1 Version 28 32 SYSCTLDIVSCLK Divisor and Source Clock Configuration 0x148 read-write n 0x0 0x0 SYSCTL_DIVSCLK_DIV Divisor Value 0 8 SYSCTL_DIVSCLK_EN DIVSCLK Enable 31 32 SYSCTL_DIVSCLK_SRC Clock Source 16 18 SYSCTL_DIVSCLK_SRC_SYSCLK System Clock 0x0 SYSCTL_DIVSCLK_SRC_PIOSC PIOSC 0x1 SYSCTL_DIVSCLK_SRC_MOSC MOSC 0x2 SYSCTLDSCLKCFG Deep Sleep Clock Configuration Register 0x144 read-write n 0x0 0x0 SYSCTL_DSCLKCFG_DSOSCSRC Deep Sleep Oscillator Source 20 24 SYSCTL_DSCLKCFG_DSOSCSRC_PIOSC PIOSC 0x0 SYSCTL_DSCLKCFG_DSOSCSRC_LFIOSC LFIOSC 0x2 SYSCTL_DSCLKCFG_DSOSCSRC_MOSC MOSC 0x3 SYSCTL_DSCLKCFG_DSOSCSRC_RTC Hibernation Module RTCOSC 0x4 SYSCTL_DSCLKCFG_DSSYSDIV Deep Sleep Clock Divisor 0 10 SYSCTL_DSCLKCFG_MOSCDPD MOSC Disable Power Down 30 31 SYSCTL_DSCLKCFG_PIOSCPD PIOSC Power Down 31 32 SYSCTLDSLPPWRCFG Deep-Sleep Power Configuration 0x18C read-write n 0x0 0x0 SYSCTL_DSLPPWRCFG_FLASHPM Flash Power Modes 4 6 SYSCTL_DSLPPWRCFG_FLASHPM_NRM Active Mode 0x0 SYSCTL_DSLPPWRCFG_FLASHPM_SLP Low Power Mode 0x2 SYSCTL_DSLPPWRCFG_LDOSM LDO Sleep Mode 9 10 SYSCTL_DSLPPWRCFG_SRAMPM SRAM Power Modes 0 2 SYSCTL_DSLPPWRCFG_SRAMPM_NRM Active Mode 0x0 SYSCTL_DSLPPWRCFG_SRAMPM_SBY Standby Mode 0x1 SYSCTL_DSLPPWRCFG_SRAMPM_LP Low Power Mode 0x3 SYSCTL_DSLPPWRCFG_TSPD Temperature Sense Power Down 8 9 SYSCTLHSSR Hardware System Service Request 0x1F4 read-write n 0x0 0x0 SYSCTL_HSSR_CDOFF Command Descriptor Pointer 0 24 SYSCTL_HSSR_KEY Write Key 24 32 SYSCTLIMC Interrupt Mask Control 0x54 read-write n 0x0 0x0 SYSCTL_IMC_BORIM Brown-Out Reset Interrupt Mask 1 2 SYSCTL_IMC_MOFIM Main Oscillator Failure Interrupt Mask 3 4 SYSCTL_IMC_MOSCPUPIM MOSC Power Up Interrupt Mask 8 9 SYSCTL_IMC_PLLLIM PLL Lock Interrupt Mask 6 7 SYSCTLLDODPCTL LDO Deep-Sleep Power Control 0x1BC read-write n 0x0 0x0 SYSCTL_LDODPCTL_VADJEN Voltage Adjust Enable 31 32 SYSCTL_LDODPCTL_VLDO LDO Output Voltage 0 8 SYSCTL_LDODPCTL_VLDO_0_90V 0.90 V 0x12 SYSCTL_LDODPCTL_VLDO_0_95V 0.95 V 0x13 SYSCTL_LDODPCTL_VLDO_1_00V 1.00 V 0x14 SYSCTL_LDODPCTL_VLDO_1_05V 1.05 V 0x15 SYSCTL_LDODPCTL_VLDO_1_10V 1.10 V 0x16 SYSCTL_LDODPCTL_VLDO_1_15V 1.15 V 0x17 SYSCTL_LDODPCTL_VLDO_1_20V 1.20 V 0x18 SYSCTL_LDODPCTL_VLDO_1_25V 1.25 V 0x19 SYSCTL_LDODPCTL_VLDO_1_30V 1.30 V 0x1a SYSCTL_LDODPCTL_VLDO_1_35V 1.35 V 0x1b SYSCTLLDOSPCTL LDO Sleep Power Control 0x1B4 read-write n 0x0 0x0 SYSCTL_LDOSPCTL_VADJEN Voltage Adjust Enable 31 32 SYSCTL_LDOSPCTL_VLDO LDO Output Voltage 0 8 SYSCTL_LDOSPCTL_VLDO_0_90V 0.90 V 0x12 SYSCTL_LDOSPCTL_VLDO_0_95V 0.95 V 0x13 SYSCTL_LDOSPCTL_VLDO_1_00V 1.00 V 0x14 SYSCTL_LDOSPCTL_VLDO_1_05V 1.05 V 0x15 SYSCTL_LDOSPCTL_VLDO_1_10V 1.10 V 0x16 SYSCTL_LDOSPCTL_VLDO_1_15V 1.15 V 0x17 SYSCTL_LDOSPCTL_VLDO_1_20V 1.20 V 0x18 SYSCTLMEMTIM0 Memory Timing Parameter Register 0 for Main Flash and EEPROM 0xC0 read-write n 0x0 0x0 SYSCTL_MEMTIM0_EBCE EEPROM Bank Clock Edge 21 22 SYSCTL_MEMTIM0_EBCHT EEPROM Clock High Time 22 26 SYSCTL_MEMTIM0_EBCHT_0_5 1/2 system clock period 0x0 SYSCTL_MEMTIM0_EBCHT_1 1 system clock period 0x1 SYSCTL_MEMTIM0_EBCHT_1_5 1.5 system clock periods 0x2 SYSCTL_MEMTIM0_EBCHT_2 2 system clock periods 0x3 SYSCTL_MEMTIM0_EBCHT_2_5 2.5 system clock periods 0x4 SYSCTL_MEMTIM0_EBCHT_3 3 system clock periods 0x5 SYSCTL_MEMTIM0_EBCHT_3_5 3.5 system clock periods 0x6 SYSCTL_MEMTIM0_EBCHT_4 4 system clock periods 0x7 SYSCTL_MEMTIM0_EBCHT_4_5 4.5 system clock periods 0x8 SYSCTL_MEMTIM0_EWS EEPROM Wait States 16 20 SYSCTL_MEMTIM0_FBCE Flash Bank Clock Edge 5 6 SYSCTL_MEMTIM0_FBCHT Flash Bank Clock High Time 6 10 SYSCTL_MEMTIM0_FBCHT_0_5 1/2 system clock period 0x0 SYSCTL_MEMTIM0_FBCHT_1 1 system clock period 0x1 SYSCTL_MEMTIM0_FBCHT_1_5 1.5 system clock periods 0x2 SYSCTL_MEMTIM0_FBCHT_2 2 system clock periods 0x3 SYSCTL_MEMTIM0_FBCHT_2_5 2.5 system clock periods 0x4 SYSCTL_MEMTIM0_FBCHT_3 3 system clock periods 0x5 SYSCTL_MEMTIM0_FBCHT_3_5 3.5 system clock periods 0x6 SYSCTL_MEMTIM0_FBCHT_4 4 system clock periods 0x7 SYSCTL_MEMTIM0_FBCHT_4_5 4.5 system clock periods 0x8 SYSCTL_MEMTIM0_FWS Flash Wait State 0 4 SYSCTLMISC Masked Interrupt Status and Clear 0x58 read-write n 0x0 0x0 SYSCTL_MISC_BORMIS BOR Masked Interrupt Status 1 2 SYSCTL_MISC_MOFMIS Main Oscillator Failure Masked Interrupt Status 3 4 SYSCTL_MISC_MOSCPUPMIS MOSC Power Up Masked Interrupt Status 8 9 SYSCTL_MISC_PLLLMIS PLL Lock Masked Interrupt Status 6 7 SYSCTLMOSCCTL Main Oscillator Control 0x7C read-write n 0x0 0x0 SYSCTL_MOSCCTL_CVAL Clock Validation for MOSC 0 1 SYSCTL_MOSCCTL_MOSCIM MOSC Failure Action 1 2 SYSCTL_MOSCCTL_NOXTAL No Crystal Connected 2 3 SYSCTL_MOSCCTL_OSCRNG Oscillator Range 4 5 SYSCTL_MOSCCTL_PWRDN Power Down 3 4 SYSCTLNMIC NMI Cause Register 0x64 read-write n 0x0 0x0 SYSCTL_NMIC_EXTERNAL External Pin NMI 0 1 SYSCTL_NMIC_MOSCFAIL MOSC Failure NMI 16 17 SYSCTL_NMIC_POWER Power/Brown Out Event NMI 2 3 SYSCTL_NMIC_TAMPER Tamper Event NMI 9 10 SYSCTL_NMIC_WDT0 Watch Dog Timer (WDT) 0 NMI 3 4 SYSCTL_NMIC_WDT1 Watch Dog Timer (WDT) 1 NMI 5 6 SYSCTLNVMSTAT Non-Volatile Memory Information 0x1A0 read-write n 0x0 0x0 SYSCTL_NVMSTAT_FWB 32 Word Flash Write Buffer Available 0 1 SYSCTLPCACMP Analog Comparator Power Control 0x93C read-write n 0x0 0x0 SYSCTL_PCACMP_P0 Analog Comparator Module 0 Power Control 0 1 SYSCTLPCADC Analog-to-Digital Converter Power Control 0x938 read-write n 0x0 0x0 SYSCTL_PCADC_P0 ADC Module 0 Power Control 0 1 SYSCTL_PCADC_P1 ADC Module 1 Power Control 1 2 SYSCTLPCCAN Controller Area Network Power Control 0x934 read-write n 0x0 0x0 SYSCTL_PCCAN_P0 CAN Module 0 Power Control 0 1 SYSCTL_PCCAN_P1 CAN Module 1 Power Control 1 2 SYSCTLPCCCM CRC and Cryptographic Modules Power Control 0x974 read-write n 0x0 0x0 SYSCTL_PCCCM_P0 CRC and Cryptographic Modules Power Control 0 1 SYSCTLPCDMA Micro Direct Memory Access Power Control 0x90C read-write n 0x0 0x0 SYSCTL_PCDMA_P0 uDMA Module Power Control 0 1 SYSCTLPCEEPROM EEPROM Power Control 0x958 read-write n 0x0 0x0 SYSCTL_PCEEPROM_P0 EEPROM Module 0 Power Control 0 1 SYSCTLPCEPI External Peripheral Interface Power Control 0x910 read-write n 0x0 0x0 SYSCTL_PCEPI_P0 EPI Module Power Control 0 1 SYSCTLPCGPIO General-Purpose Input/Output Power Control 0x908 read-write n 0x0 0x0 SYSCTL_PCGPIO_P0 GPIO Port A Power Control 0 1 SYSCTL_PCGPIO_P1 GPIO Port B Power Control 1 2 SYSCTL_PCGPIO_P10 GPIO Port L Power Control 10 11 SYSCTL_PCGPIO_P11 GPIO Port M Power Control 11 12 SYSCTL_PCGPIO_P12 GPIO Port N Power Control 12 13 SYSCTL_PCGPIO_P13 GPIO Port P Power Control 13 14 SYSCTL_PCGPIO_P14 GPIO Port Q Power Control 14 15 SYSCTL_PCGPIO_P15 GPIO Port R Power Control 15 16 SYSCTL_PCGPIO_P16 GPIO Port S Power Control 16 17 SYSCTL_PCGPIO_P17 GPIO Port T Power Control 17 18 SYSCTL_PCGPIO_P2 GPIO Port C Power Control 2 3 SYSCTL_PCGPIO_P3 GPIO Port D Power Control 3 4 SYSCTL_PCGPIO_P4 GPIO Port E Power Control 4 5 SYSCTL_PCGPIO_P5 GPIO Port F Power Control 5 6 SYSCTL_PCGPIO_P6 GPIO Port G Power Control 6 7 SYSCTL_PCGPIO_P7 GPIO Port H Power Control 7 8 SYSCTL_PCGPIO_P8 GPIO Port J Power Control 8 9 SYSCTL_PCGPIO_P9 GPIO Port K Power Control 9 10 SYSCTLPCHIB Hibernation Power Control 0x914 read-write n 0x0 0x0 SYSCTL_PCHIB_P0 Hibernation Module Power Control 0 1 SYSCTLPCI2C Inter-Integrated Circuit Power Control 0x920 read-write n 0x0 0x0 SYSCTL_PCI2C_P0 I2C Module 0 Power Control 0 1 SYSCTL_PCI2C_P1 I2C Module 1 Power Control 1 2 SYSCTL_PCI2C_P2 I2C Module 2 Power Control 2 3 SYSCTL_PCI2C_P3 I2C Module 3 Power Control 3 4 SYSCTL_PCI2C_P4 I2C Module 4 Power Control 4 5 SYSCTL_PCI2C_P5 I2C Module 5 Power Control 5 6 SYSCTL_PCI2C_P6 I2C Module 6 Power Control 6 7 SYSCTL_PCI2C_P7 I2C Module 7 Power Control 7 8 SYSCTL_PCI2C_P8 I2C Module 8 Power Control 8 9 SYSCTL_PCI2C_P9 I2C Module 9 Power Control 9 10 SYSCTLPCPWM Pulse Width Modulator Power Control 0x940 read-write n 0x0 0x0 SYSCTL_PCPWM_P0 PWM Module 0 Power Control 0 1 SYSCTLPCQEI Quadrature Encoder Interface Power Control 0x944 read-write n 0x0 0x0 SYSCTL_PCQEI_P0 QEI Module 0 Power Control 0 1 SYSCTLPCSSI Synchronous Serial Interface Power Control 0x91C read-write n 0x0 0x0 SYSCTL_PCSSI_P0 SSI Module 0 Power Control 0 1 SYSCTL_PCSSI_P1 SSI Module 1 Power Control 1 2 SYSCTL_PCSSI_P2 SSI Module 2 Power Control 2 3 SYSCTL_PCSSI_P3 SSI Module 3 Power Control 3 4 SYSCTLPCTIMER 16/32-Bit General-Purpose Timer Power Control 0x904 read-write n 0x0 0x0 SYSCTL_PCTIMER_P0 General-Purpose Timer 0 Power Control 0 1 SYSCTL_PCTIMER_P1 General-Purpose Timer 1 Power Control 1 2 SYSCTL_PCTIMER_P2 General-Purpose Timer 2 Power Control 2 3 SYSCTL_PCTIMER_P3 General-Purpose Timer 3 Power Control 3 4 SYSCTL_PCTIMER_P4 General-Purpose Timer 4 Power Control 4 5 SYSCTL_PCTIMER_P5 General-Purpose Timer 5 Power Control 5 6 SYSCTL_PCTIMER_P6 General-Purpose Timer 6 Power Control 6 7 SYSCTL_PCTIMER_P7 General-Purpose Timer 7 Power Control 7 8 SYSCTLPCUART Universal Asynchronous Receiver/Transmitter Power Control 0x918 read-write n 0x0 0x0 SYSCTL_PCUART_P0 UART Module 0 Power Control 0 1 SYSCTL_PCUART_P1 UART Module 1 Power Control 1 2 SYSCTL_PCUART_P2 UART Module 2 Power Control 2 3 SYSCTL_PCUART_P3 UART Module 3 Power Control 3 4 SYSCTL_PCUART_P4 UART Module 4 Power Control 4 5 SYSCTL_PCUART_P5 UART Module 5 Power Control 5 6 SYSCTL_PCUART_P6 UART Module 6 Power Control 6 7 SYSCTL_PCUART_P7 UART Module 7 Power Control 7 8 SYSCTLPCUSB Universal Serial Bus Power Control 0x928 read-write n 0x0 0x0 SYSCTL_PCUSB_P0 USB Module Power Control 0 1 SYSCTLPCWD Watchdog Timer Power Control 0x900 read-write n 0x0 0x0 SYSCTL_PCWD_P0 Watchdog Timer 0 Power Control 0 1 SYSCTL_PCWD_P1 Watchdog Timer 1 Power Control 1 2 SYSCTLPIOSCCAL Precision Internal Oscillator Calibration 0x150 read-write n 0x0 0x0 SYSCTL_PIOSCCAL_CAL Start Calibration 9 10 SYSCTL_PIOSCCAL_UPDATE Update Trim 8 9 SYSCTL_PIOSCCAL_UT User Trim Value 0 7 SYSCTL_PIOSCCAL_UTEN Use User Trim Value 31 32 SYSCTLPIOSCSTAT Precision Internal Oscillator Statistics 0x154 read-write n 0x0 0x0 SYSCTL_PIOSCSTAT_CR Calibration Result 8 10 SYSCTL_PIOSCSTAT_CRNONE Calibration has not been attempted 0x0 SYSCTL_PIOSCSTAT_CRPASS The last calibration operation completed to meet 1% accuracy 0x1 SYSCTL_PIOSCSTAT_CRFAIL The last calibration operation failed to meet 1% accuracy 0x2 SYSCTL_PIOSCSTAT_CT Calibration Trim Value 0 7 SYSCTL_PIOSCSTAT_DT Default Trim Value 16 23 SYSCTLPLLFREQ0 PLL Frequency 0 0x160 read-write n 0x0 0x0 SYSCTL_PLLFREQ0_MFRAC PLL M Fractional Value 10 20 SYSCTL_PLLFREQ0_MINT PLL M Integer Value 0 10 SYSCTL_PLLFREQ0_PLLPWR PLL Power 23 24 SYSCTLPLLFREQ1 PLL Frequency 1 0x164 read-write n 0x0 0x0 SYSCTL_PLLFREQ1_N PLL N Value 0 5 SYSCTL_PLLFREQ1_Q PLL Q Value 8 13 SYSCTLPLLSTAT PLL Status 0x168 read-write n 0x0 0x0 SYSCTL_PLLSTAT_LOCK PLL Lock 0 1 SYSCTLPPACMP Analog Comparator Peripheral Present 0x33C read-write n 0x0 0x0 SYSCTL_PPACMP_P0 Analog Comparator Module Present 0 1 SYSCTLPPADC Analog-to-Digital Converter Peripheral Present 0x338 read-write n 0x0 0x0 SYSCTL_PPADC_P0 ADC Module 0 Present 0 1 SYSCTL_PPADC_P1 ADC Module 1 Present 1 2 SYSCTLPPCAN Controller Area Network Peripheral Present 0x334 read-write n 0x0 0x0 SYSCTL_PPCAN_P0 CAN Module 0 Present 0 1 SYSCTL_PPCAN_P1 CAN Module 1 Present 1 2 SYSCTLPPCCM CRC and Cryptographic Modules Peripheral Present 0x374 read-write n 0x0 0x0 SYSCTL_PPCCM_P0 CRC and Cryptographic Modules Present 0 1 SYSCTLPPDMA Micro Direct Memory Access Peripheral Present 0x30C read-write n 0x0 0x0 SYSCTL_PPDMA_P0 uDMA Module Present 0 1 SYSCTLPPEEPROM EEPROM Peripheral Present 0x358 read-write n 0x0 0x0 SYSCTL_PPEEPROM_P0 EEPROM Module Present 0 1 SYSCTLPPEMAC Ethernet MAC Peripheral Present 0x39C read-write n 0x0 0x0 SYSCTL_PPEMAC_P0 Ethernet Controller Module Present 0 1 SYSCTLPPEPHY Ethernet PHY Peripheral Present 0x330 read-write n 0x0 0x0 SYSCTL_PPEPHY_P0 Ethernet PHY Module Present 0 1 SYSCTLPPEPI EPI Peripheral Present 0x310 read-write n 0x0 0x0 SYSCTL_PPEPI_P0 EPI Module Present 0 1 SYSCTLPPFAN Fan Control Peripheral Present 0x354 read-write n 0x0 0x0 SYSCTL_PPFAN_P0 FAN Module 0 Present 0 1 SYSCTLPPGPIO General-Purpose Input/Output Peripheral Present 0x308 read-write n 0x0 0x0 SYSCTL_PPGPIO_P0 GPIO Port A Present 0 1 SYSCTL_PPGPIO_P1 GPIO Port B Present 1 2 SYSCTL_PPGPIO_P10 GPIO Port L Present 10 11 SYSCTL_PPGPIO_P11 GPIO Port M Present 11 12 SYSCTL_PPGPIO_P12 GPIO Port N Present 12 13 SYSCTL_PPGPIO_P13 GPIO Port P Present 13 14 SYSCTL_PPGPIO_P14 GPIO Port Q Present 14 15 SYSCTL_PPGPIO_P15 GPIO Port R Present 15 16 SYSCTL_PPGPIO_P16 GPIO Port S Present 16 17 SYSCTL_PPGPIO_P17 GPIO Port T Present 17 18 SYSCTL_PPGPIO_P2 GPIO Port C Present 2 3 SYSCTL_PPGPIO_P3 GPIO Port D Present 3 4 SYSCTL_PPGPIO_P4 GPIO Port E Present 4 5 SYSCTL_PPGPIO_P5 GPIO Port F Present 5 6 SYSCTL_PPGPIO_P6 GPIO Port G Present 6 7 SYSCTL_PPGPIO_P7 GPIO Port H Present 7 8 SYSCTL_PPGPIO_P8 GPIO Port J Present 8 9 SYSCTL_PPGPIO_P9 GPIO Port K Present 9 10 SYSCTLPPHIB Hibernation Peripheral Present 0x314 read-write n 0x0 0x0 SYSCTL_PPHIB_P0 Hibernation Module Present 0 1 SYSCTLPPHIM Human Interface Master Peripheral Present 0x3A4 read-write n 0x0 0x0 SYSCTL_PPHIM_P0 HIM Module Present 0 1 SYSCTLPPI2C Inter-Integrated Circuit Peripheral Present 0x320 read-write n 0x0 0x0 SYSCTL_PPI2C_P0 I2C Module 0 Present 0 1 SYSCTL_PPI2C_P1 I2C Module 1 Present 1 2 SYSCTL_PPI2C_P2 I2C Module 2 Present 2 3 SYSCTL_PPI2C_P3 I2C Module 3 Present 3 4 SYSCTL_PPI2C_P4 I2C Module 4 Present 4 5 SYSCTL_PPI2C_P5 I2C Module 5 Present 5 6 SYSCTL_PPI2C_P6 I2C Module 6 Present 6 7 SYSCTL_PPI2C_P7 I2C Module 7 Present 7 8 SYSCTL_PPI2C_P8 I2C Module 8 Present 8 9 SYSCTL_PPI2C_P9 I2C Module 9 Present 9 10 SYSCTLPPLCD LCD Peripheral Present 0x390 read-write n 0x0 0x0 SYSCTL_PPLCD_P0 LCD Module Present 0 1 SYSCTLPPLPC Low Pin Count Interface Peripheral Present 0x348 read-write n 0x0 0x0 SYSCTL_PPLPC_P0 LPC Module Present 0 1 SYSCTLPPOWIRE 1-Wire Peripheral Present 0x398 read-write n 0x0 0x0 SYSCTL_PPOWIRE_P0 1-Wire Module Present 0 1 SYSCTLPPPECI Platform Environment Control Interface Peripheral Present 0x350 read-write n 0x0 0x0 SYSCTL_PPPECI_P0 PECI Module Present 0 1 SYSCTLPPPWM Pulse Width Modulator Peripheral Present 0x340 read-write n 0x0 0x0 SYSCTL_PPPWM_P0 PWM Module 0 Present 0 1 SYSCTLPPQEI Quadrature Encoder Interface Peripheral Present 0x344 read-write n 0x0 0x0 SYSCTL_PPQEI_P0 QEI Module 0 Present 0 1 SYSCTLPPRTS Remote Temperature Sensor Peripheral Present 0x370 read-write n 0x0 0x0 SYSCTL_PPRTS_P0 RTS Module Present 0 1 SYSCTLPPSSI Synchronous Serial Interface Peripheral Present 0x31C read-write n 0x0 0x0 SYSCTL_PPSSI_P0 SSI Module 0 Present 0 1 SYSCTL_PPSSI_P1 SSI Module 1 Present 1 2 SYSCTL_PPSSI_P2 SSI Module 2 Present 2 3 SYSCTL_PPSSI_P3 SSI Module 3 Present 3 4 SYSCTLPPTIMER 16/32-Bit General-Purpose Timer Peripheral Present 0x304 read-write n 0x0 0x0 SYSCTL_PPTIMER_P0 16/32-Bit General-Purpose Timer 0 Present 0 1 SYSCTL_PPTIMER_P1 16/32-Bit General-Purpose Timer 1 Present 1 2 SYSCTL_PPTIMER_P2 16/32-Bit General-Purpose Timer 2 Present 2 3 SYSCTL_PPTIMER_P3 16/32-Bit General-Purpose Timer 3 Present 3 4 SYSCTL_PPTIMER_P4 16/32-Bit General-Purpose Timer 4 Present 4 5 SYSCTL_PPTIMER_P5 16/32-Bit General-Purpose Timer 5 Present 5 6 SYSCTL_PPTIMER_P6 16/32-Bit General-Purpose Timer 6 Present 6 7 SYSCTL_PPTIMER_P7 16/32-Bit General-Purpose Timer 7 Present 7 8 SYSCTLPPUART Universal Asynchronous Receiver/Transmitter Peripheral Present 0x318 read-write n 0x0 0x0 SYSCTL_PPUART_P0 UART Module 0 Present 0 1 SYSCTL_PPUART_P1 UART Module 1 Present 1 2 SYSCTL_PPUART_P2 UART Module 2 Present 2 3 SYSCTL_PPUART_P3 UART Module 3 Present 3 4 SYSCTL_PPUART_P4 UART Module 4 Present 4 5 SYSCTL_PPUART_P5 UART Module 5 Present 5 6 SYSCTL_PPUART_P6 UART Module 6 Present 6 7 SYSCTL_PPUART_P7 UART Module 7 Present 7 8 SYSCTLPPUSB Universal Serial Bus Peripheral Present 0x328 read-write n 0x0 0x0 SYSCTL_PPUSB_P0 USB Module Present 0 1 SYSCTLPPWD Watchdog Timer Peripheral Present 0x300 read-write n 0x0 0x0 SYSCTL_PPWD_P0 Watchdog Timer 0 Present 0 1 SYSCTL_PPWD_P1 Watchdog Timer 1 Present 1 2 SYSCTLPPWTIMER 32/64-Bit Wide General-Purpose Timer Peripheral Present 0x35C read-write n 0x0 0x0 SYSCTL_PPWTIMER_P0 32/64-Bit Wide General-Purpose Timer 0 Present 0 1 SYSCTLPRACMP Analog Comparator Peripheral Ready 0xA3C read-write n 0x0 0x0 SYSCTL_PRACMP_R0 Analog Comparator Module 0 Peripheral Ready 0 1 SYSCTLPRADC Analog-to-Digital Converter Peripheral Ready 0xA38 read-write n 0x0 0x0 SYSCTL_PRADC_R0 ADC Module 0 Peripheral Ready 0 1 SYSCTL_PRADC_R1 ADC Module 1 Peripheral Ready 1 2 SYSCTLPRCAN Controller Area Network Peripheral Ready 0xA34 read-write n 0x0 0x0 SYSCTL_PRCAN_R0 CAN Module 0 Peripheral Ready 0 1 SYSCTL_PRCAN_R1 CAN Module 1 Peripheral Ready 1 2 SYSCTLPRCCM CRC and Cryptographic Modules Peripheral Ready 0xA74 read-write n 0x0 0x0 SYSCTL_PRCCM_R0 CRC and Cryptographic Modules Peripheral Ready 0 1 SYSCTLPRDMA Micro Direct Memory Access Peripheral Ready 0xA0C read-write n 0x0 0x0 SYSCTL_PRDMA_R0 uDMA Module Peripheral Ready 0 1 SYSCTLPREEPROM EEPROM Peripheral Ready 0xA58 read-write n 0x0 0x0 SYSCTL_PREEPROM_R0 EEPROM Module Peripheral Ready 0 1 SYSCTLPREPI EPI Peripheral Ready 0xA10 read-write n 0x0 0x0 SYSCTL_PREPI_R0 EPI Module Peripheral Ready 0 1 SYSCTLPRGPIO General-Purpose Input/Output Peripheral Ready 0xA08 read-write n 0x0 0x0 SYSCTL_PRGPIO_R0 GPIO Port A Peripheral Ready 0 1 SYSCTL_PRGPIO_R1 GPIO Port B Peripheral Ready 1 2 SYSCTL_PRGPIO_R10 GPIO Port L Peripheral Ready 10 11 SYSCTL_PRGPIO_R11 GPIO Port M Peripheral Ready 11 12 SYSCTL_PRGPIO_R12 GPIO Port N Peripheral Ready 12 13 SYSCTL_PRGPIO_R13 GPIO Port P Peripheral Ready 13 14 SYSCTL_PRGPIO_R14 GPIO Port Q Peripheral Ready 14 15 SYSCTL_PRGPIO_R15 GPIO Port R Peripheral Ready 15 16 SYSCTL_PRGPIO_R16 GPIO Port S Peripheral Ready 16 17 SYSCTL_PRGPIO_R17 GPIO Port T Peripheral Ready 17 18 SYSCTL_PRGPIO_R2 GPIO Port C Peripheral Ready 2 3 SYSCTL_PRGPIO_R3 GPIO Port D Peripheral Ready 3 4 SYSCTL_PRGPIO_R4 GPIO Port E Peripheral Ready 4 5 SYSCTL_PRGPIO_R5 GPIO Port F Peripheral Ready 5 6 SYSCTL_PRGPIO_R6 GPIO Port G Peripheral Ready 6 7 SYSCTL_PRGPIO_R7 GPIO Port H Peripheral Ready 7 8 SYSCTL_PRGPIO_R8 GPIO Port J Peripheral Ready 8 9 SYSCTL_PRGPIO_R9 GPIO Port K Peripheral Ready 9 10 SYSCTLPRHIB Hibernation Peripheral Ready 0xA14 read-write n 0x0 0x0 SYSCTL_PRHIB_R0 Hibernation Module Peripheral Ready 0 1 SYSCTLPRI2C Inter-Integrated Circuit Peripheral Ready 0xA20 read-write n 0x0 0x0 SYSCTL_PRI2C_R0 I2C Module 0 Peripheral Ready 0 1 SYSCTL_PRI2C_R1 I2C Module 1 Peripheral Ready 1 2 SYSCTL_PRI2C_R2 I2C Module 2 Peripheral Ready 2 3 SYSCTL_PRI2C_R3 I2C Module 3 Peripheral Ready 3 4 SYSCTL_PRI2C_R4 I2C Module 4 Peripheral Ready 4 5 SYSCTL_PRI2C_R5 I2C Module 5 Peripheral Ready 5 6 SYSCTL_PRI2C_R6 I2C Module 6 Peripheral Ready 6 7 SYSCTL_PRI2C_R7 I2C Module 7 Peripheral Ready 7 8 SYSCTL_PRI2C_R8 I2C Module 8 Peripheral Ready 8 9 SYSCTL_PRI2C_R9 I2C Module 9 Peripheral Ready 9 10 SYSCTLPRPWM Pulse Width Modulator Peripheral Ready 0xA40 read-write n 0x0 0x0 SYSCTL_PRPWM_R0 PWM Module 0 Peripheral Ready 0 1 SYSCTLPRQEI Quadrature Encoder Interface Peripheral Ready 0xA44 read-write n 0x0 0x0 SYSCTL_PRQEI_R0 QEI Module 0 Peripheral Ready 0 1 SYSCTLPRSSI Synchronous Serial Interface Peripheral Ready 0xA1C read-write n 0x0 0x0 SYSCTL_PRSSI_R0 SSI Module 0 Peripheral Ready 0 1 SYSCTL_PRSSI_R1 SSI Module 1 Peripheral Ready 1 2 SYSCTL_PRSSI_R2 SSI Module 2 Peripheral Ready 2 3 SYSCTL_PRSSI_R3 SSI Module 3 Peripheral Ready 3 4 SYSCTLPRTIMER 16/32-Bit General-Purpose Timer Peripheral Ready 0xA04 read-write n 0x0 0x0 SYSCTL_PRTIMER_R0 16/32-Bit General-Purpose Timer 0 Peripheral Ready 0 1 SYSCTL_PRTIMER_R1 16/32-Bit General-Purpose Timer 1 Peripheral Ready 1 2 SYSCTL_PRTIMER_R2 16/32-Bit General-Purpose Timer 2 Peripheral Ready 2 3 SYSCTL_PRTIMER_R3 16/32-Bit General-Purpose Timer 3 Peripheral Ready 3 4 SYSCTL_PRTIMER_R4 16/32-Bit General-Purpose Timer 4 Peripheral Ready 4 5 SYSCTL_PRTIMER_R5 16/32-Bit General-Purpose Timer 5 Peripheral Ready 5 6 SYSCTL_PRTIMER_R6 16/32-Bit General-Purpose Timer 6 Peripheral Ready 6 7 SYSCTL_PRTIMER_R7 16/32-Bit General-Purpose Timer 7 Peripheral Ready 7 8 SYSCTLPRUART Universal Asynchronous Receiver/Transmitter Peripheral Ready 0xA18 read-write n 0x0 0x0 SYSCTL_PRUART_R0 UART Module 0 Peripheral Ready 0 1 SYSCTL_PRUART_R1 UART Module 1 Peripheral Ready 1 2 SYSCTL_PRUART_R2 UART Module 2 Peripheral Ready 2 3 SYSCTL_PRUART_R3 UART Module 3 Peripheral Ready 3 4 SYSCTL_PRUART_R4 UART Module 4 Peripheral Ready 4 5 SYSCTL_PRUART_R5 UART Module 5 Peripheral Ready 5 6 SYSCTL_PRUART_R6 UART Module 6 Peripheral Ready 6 7 SYSCTL_PRUART_R7 UART Module 7 Peripheral Ready 7 8 SYSCTLPRUSB Universal Serial Bus Peripheral Ready 0xA28 read-write n 0x0 0x0 SYSCTL_PRUSB_R0 USB Module Peripheral Ready 0 1 SYSCTLPRWD Watchdog Timer Peripheral Ready 0xA00 read-write n 0x0 0x0 SYSCTL_PRWD_R0 Watchdog Timer 0 Peripheral Ready 0 1 SYSCTL_PRWD_R1 Watchdog Timer 1 Peripheral Ready 1 2 SYSCTLPTBOCTL Power-Temp Brown Out Control 0x38 read-write n 0x0 0x0 SYSCTL_PTBOCTL_VDDA_UBOR VDDA under BOR Event Action 8 10 SYSCTL_PTBOCTL_VDDA_UBOR_NONE No Action 0x0 SYSCTL_PTBOCTL_VDDA_UBOR_SYSINT System control interrupt 0x1 SYSCTL_PTBOCTL_VDDA_UBOR_NMI NMI 0x2 SYSCTL_PTBOCTL_VDDA_UBOR_RST Reset 0x3 SYSCTL_PTBOCTL_VDD_UBOR VDD (VDDS) under BOR Event Action 0 2 SYSCTL_PTBOCTL_VDD_UBOR_NONE No Action 0x0 SYSCTL_PTBOCTL_VDD_UBOR_SYSINT System control interrupt 0x1 SYSCTL_PTBOCTL_VDD_UBOR_NMI NMI 0x2 SYSCTL_PTBOCTL_VDD_UBOR_RST Reset 0x3 SYSCTLPWRTC Power-Temperature Cause 0x60 read-write n 0x0 0x0 SYSCTL_PWRTC_VDDA_UBOR VDDA Under BOR Status 4 5 SYSCTL_PWRTC_VDD_UBOR VDD Under BOR Status 0 1 SYSCTLRCGCACMP Analog Comparator Run Mode Clock Gating Control 0x63C read-write n 0x0 0x0 SYSCTL_RCGCACMP_R0 Analog Comparator Module 0 Run Mode Clock Gating Control 0 1 SYSCTLRCGCADC Analog-to-Digital Converter Run Mode Clock Gating Control 0x638 read-write n 0x0 0x0 SYSCTL_RCGCADC_R0 ADC Module 0 Run Mode Clock Gating Control 0 1 SYSCTL_RCGCADC_R1 ADC Module 1 Run Mode Clock Gating Control 1 2 SYSCTLRCGCCAN Controller Area Network Run Mode Clock Gating Control 0x634 read-write n 0x0 0x0 SYSCTL_RCGCCAN_R0 CAN Module 0 Run Mode Clock Gating Control 0 1 SYSCTL_RCGCCAN_R1 CAN Module 1 Run Mode Clock Gating Control 1 2 SYSCTLRCGCCCM CRC and Cryptographic Modules Run Mode Clock Gating Control 0x674 read-write n 0x0 0x0 SYSCTL_RCGCCCM_R0 CRC and Cryptographic Modules Run Mode Clock Gating Control 0 1 SYSCTLRCGCDMA Micro Direct Memory Access Run Mode Clock Gating Control 0x60C read-write n 0x0 0x0 SYSCTL_RCGCDMA_R0 uDMA Module Run Mode Clock Gating Control 0 1 SYSCTLRCGCEEPROM EEPROM Run Mode Clock Gating Control 0x658 read-write n 0x0 0x0 SYSCTL_RCGCEEPROM_R0 EEPROM Module Run Mode Clock Gating Control 0 1 SYSCTLRCGCEPI EPI Run Mode Clock Gating Control 0x610 read-write n 0x0 0x0 SYSCTL_RCGCEPI_R0 EPI Module Run Mode Clock Gating Control 0 1 SYSCTLRCGCGPIO General-Purpose Input/Output Run Mode Clock Gating Control 0x608 read-write n 0x0 0x0 SYSCTL_RCGCGPIO_R0 GPIO Port A Run Mode Clock Gating Control 0 1 SYSCTL_RCGCGPIO_R1 GPIO Port B Run Mode Clock Gating Control 1 2 SYSCTL_RCGCGPIO_R10 GPIO Port L Run Mode Clock Gating Control 10 11 SYSCTL_RCGCGPIO_R11 GPIO Port M Run Mode Clock Gating Control 11 12 SYSCTL_RCGCGPIO_R12 GPIO Port N Run Mode Clock Gating Control 12 13 SYSCTL_RCGCGPIO_R13 GPIO Port P Run Mode Clock Gating Control 13 14 SYSCTL_RCGCGPIO_R14 GPIO Port Q Run Mode Clock Gating Control 14 15 SYSCTL_RCGCGPIO_R15 GPIO Port R Run Mode Clock Gating Control 15 16 SYSCTL_RCGCGPIO_R16 GPIO Port S Run Mode Clock Gating Control 16 17 SYSCTL_RCGCGPIO_R17 GPIO Port T Run Mode Clock Gating Control 17 18 SYSCTL_RCGCGPIO_R2 GPIO Port C Run Mode Clock Gating Control 2 3 SYSCTL_RCGCGPIO_R3 GPIO Port D Run Mode Clock Gating Control 3 4 SYSCTL_RCGCGPIO_R4 GPIO Port E Run Mode Clock Gating Control 4 5 SYSCTL_RCGCGPIO_R5 GPIO Port F Run Mode Clock Gating Control 5 6 SYSCTL_RCGCGPIO_R6 GPIO Port G Run Mode Clock Gating Control 6 7 SYSCTL_RCGCGPIO_R7 GPIO Port H Run Mode Clock Gating Control 7 8 SYSCTL_RCGCGPIO_R8 GPIO Port J Run Mode Clock Gating Control 8 9 SYSCTL_RCGCGPIO_R9 GPIO Port K Run Mode Clock Gating Control 9 10 SYSCTLRCGCHIB Hibernation Run Mode Clock Gating Control 0x614 read-write n 0x0 0x0 SYSCTL_RCGCHIB_R0 Hibernation Module Run Mode Clock Gating Control 0 1 SYSCTLRCGCI2C Inter-Integrated Circuit Run Mode Clock Gating Control 0x620 read-write n 0x0 0x0 SYSCTL_RCGCI2C_R0 I2C Module 0 Run Mode Clock Gating Control 0 1 SYSCTL_RCGCI2C_R1 I2C Module 1 Run Mode Clock Gating Control 1 2 SYSCTL_RCGCI2C_R2 I2C Module 2 Run Mode Clock Gating Control 2 3 SYSCTL_RCGCI2C_R3 I2C Module 3 Run Mode Clock Gating Control 3 4 SYSCTL_RCGCI2C_R4 I2C Module 4 Run Mode Clock Gating Control 4 5 SYSCTL_RCGCI2C_R5 I2C Module 5 Run Mode Clock Gating Control 5 6 SYSCTL_RCGCI2C_R6 I2C Module 6 Run Mode Clock Gating Control 6 7 SYSCTL_RCGCI2C_R7 I2C Module 7 Run Mode Clock Gating Control 7 8 SYSCTL_RCGCI2C_R8 I2C Module 8 Run Mode Clock Gating Control 8 9 SYSCTL_RCGCI2C_R9 I2C Module 9 Run Mode Clock Gating Control 9 10 SYSCTLRCGCPWM Pulse Width Modulator Run Mode Clock Gating Control 0x640 read-write n 0x0 0x0 SYSCTL_RCGCPWM_R0 PWM Module 0 Run Mode Clock Gating Control 0 1 SYSCTLRCGCQEI Quadrature Encoder Interface Run Mode Clock Gating Control 0x644 read-write n 0x0 0x0 SYSCTL_RCGCQEI_R0 QEI Module 0 Run Mode Clock Gating Control 0 1 SYSCTLRCGCSSI Synchronous Serial Interface Run Mode Clock Gating Control 0x61C read-write n 0x0 0x0 SYSCTL_RCGCSSI_R0 SSI Module 0 Run Mode Clock Gating Control 0 1 SYSCTL_RCGCSSI_R1 SSI Module 1 Run Mode Clock Gating Control 1 2 SYSCTL_RCGCSSI_R2 SSI Module 2 Run Mode Clock Gating Control 2 3 SYSCTL_RCGCSSI_R3 SSI Module 3 Run Mode Clock Gating Control 3 4 SYSCTLRCGCTIMER 16/32-Bit General-Purpose Timer Run Mode Clock Gating Control 0x604 read-write n 0x0 0x0 SYSCTL_RCGCTIMER_R0 16/32-Bit General-Purpose Timer 0 Run Mode Clock Gating Control 0 1 SYSCTL_RCGCTIMER_R1 16/32-Bit General-Purpose Timer 1 Run Mode Clock Gating Control 1 2 SYSCTL_RCGCTIMER_R2 16/32-Bit General-Purpose Timer 2 Run Mode Clock Gating Control 2 3 SYSCTL_RCGCTIMER_R3 16/32-Bit General-Purpose Timer 3 Run Mode Clock Gating Control 3 4 SYSCTL_RCGCTIMER_R4 16/32-Bit General-Purpose Timer 4 Run Mode Clock Gating Control 4 5 SYSCTL_RCGCTIMER_R5 16/32-Bit General-Purpose Timer 5 Run Mode Clock Gating Control 5 6 SYSCTL_RCGCTIMER_R6 16/32-Bit General-Purpose Timer 6 Run Mode Clock Gating Control 6 7 SYSCTL_RCGCTIMER_R7 16/32-Bit General-Purpose Timer 7 Run Mode Clock Gating Control 7 8 SYSCTLRCGCUART Universal Asynchronous Receiver/Transmitter Run Mode Clock Gating Control 0x618 read-write n 0x0 0x0 SYSCTL_RCGCUART_R0 UART Module 0 Run Mode Clock Gating Control 0 1 SYSCTL_RCGCUART_R1 UART Module 1 Run Mode Clock Gating Control 1 2 SYSCTL_RCGCUART_R2 UART Module 2 Run Mode Clock Gating Control 2 3 SYSCTL_RCGCUART_R3 UART Module 3 Run Mode Clock Gating Control 3 4 SYSCTL_RCGCUART_R4 UART Module 4 Run Mode Clock Gating Control 4 5 SYSCTL_RCGCUART_R5 UART Module 5 Run Mode Clock Gating Control 5 6 SYSCTL_RCGCUART_R6 UART Module 6 Run Mode Clock Gating Control 6 7 SYSCTL_RCGCUART_R7 UART Module 7 Run Mode Clock Gating Control 7 8 SYSCTLRCGCUSB Universal Serial Bus Run Mode Clock Gating Control 0x628 read-write n 0x0 0x0 SYSCTL_RCGCUSB_R0 USB Module Run Mode Clock Gating Control 0 1 SYSCTLRCGCWD Watchdog Timer Run Mode Clock Gating Control 0x600 read-write n 0x0 0x0 SYSCTL_RCGCWD_R0 Watchdog Timer 0 Run Mode Clock Gating Control 0 1 SYSCTL_RCGCWD_R1 Watchdog Timer 1 Run Mode Clock Gating Control 1 2 SYSCTLRESBEHAVCTL Reset Behavior Control Register 0x1D8 read-write n 0x0 0x0 SYSCTL_RESBEHAVCTL_BOR BOR Reset operation 2 4 SYSCTL_RESBEHAVCTL_BOR_SYSRST Brown Out Reset issues system reset. The application starts within 10 us 0x2 SYSCTL_RESBEHAVCTL_BOR_POR Brown Out Reset issues a simulated POR sequence. The application starts less than 500 us after deassertion (Default) 0x3 SYSCTL_RESBEHAVCTL_EXTRES External RST Pin Operation 0 2 SYSCTL_RESBEHAVCTL_EXTRES_SYSRST External RST assertion issues a system reset. The application starts within 10 us 0x2 SYSCTL_RESBEHAVCTL_EXTRES_POR External RST assertion issues a simulated POR sequence. Application starts less than 500 us after deassertion (Default) 0x3 SYSCTL_RESBEHAVCTL_WDOG0 Watchdog 0 Reset Operation 4 6 SYSCTL_RESBEHAVCTL_WDOG0_SYSRST Watchdog 0 issues a system reset. The application starts within 10 us 0x2 SYSCTL_RESBEHAVCTL_WDOG0_POR Watchdog 0 issues a simulated POR sequence. Application starts less than 500 us after deassertion (Default) 0x3 SYSCTL_RESBEHAVCTL_WDOG1 Watchdog 1 Reset Operation 6 8 SYSCTL_RESBEHAVCTL_WDOG1_SYSRST Watchdog 1 issues a system reset. The application starts within 10 us 0x2 SYSCTL_RESBEHAVCTL_WDOG1_POR Watchdog 1 issues a simulated POR sequence. Application starts less than 500 us after deassertion (Default) 0x3 SYSCTLRESC Reset Cause 0x5C read-write n 0x0 0x0 SYSCTL_RESC_BOR Brown-Out Reset 2 3 SYSCTL_RESC_EXT External Reset 0 1 SYSCTL_RESC_HIB HIB Reset 6 7 SYSCTL_RESC_HSSR HSSR Reset 12 13 SYSCTL_RESC_MOSCFAIL MOSC Failure Reset 16 17 SYSCTL_RESC_POR Power-On Reset 1 2 SYSCTL_RESC_SW Software Reset 4 5 SYSCTL_RESC_WDT0 Watchdog Timer 0 Reset 3 4 SYSCTL_RESC_WDT1 Watchdog Timer 1 Reset 5 6 SYSCTLRIS Raw Interrupt Status 0x50 read-write n 0x0 0x0 SYSCTL_RIS_BORRIS Brown-Out Reset Raw Interrupt Status 1 2 SYSCTL_RIS_MOFRIS Main Oscillator Failure Raw Interrupt Status 3 4 SYSCTL_RIS_MOSCPUPRIS MOSC Power Up Raw Interrupt Status 8 9 SYSCTL_RIS_PLLLRIS PLL Lock Raw Interrupt Status 6 7 SYSCTLRSCLKCFG Run and Sleep Mode Configuration Register 0xB0 read-write n 0x0 0x0 SYSCTL_RSCLKCFG_ACG Auto Clock Gating 29 30 SYSCTL_RSCLKCFG_MEMTIMU Memory Timing Register Update 31 32 SYSCTL_RSCLKCFG_NEWFREQ New PLLFREQ Accept 30 31 SYSCTL_RSCLKCFG_OSCSRC Oscillator Source 20 24 SYSCTL_RSCLKCFG_OSCSRC_PIOSC PIOSC is oscillator source 0x0 SYSCTL_RSCLKCFG_OSCSRC_LFIOSC LFIOSC is oscillator source 0x2 SYSCTL_RSCLKCFG_OSCSRC_MOSC MOSC is oscillator source 0x3 SYSCTL_RSCLKCFG_OSCSRC_RTC Hibernation Module RTC Oscillator (RTCOSC) 0x4 SYSCTL_RSCLKCFG_OSYSDIV Oscillator System Clock Divisor 10 20 SYSCTL_RSCLKCFG_PLLSRC PLL Source 24 28 SYSCTL_RSCLKCFG_PLLSRC_PIOSC PIOSC is PLL input clock source 0x0 SYSCTL_RSCLKCFG_PLLSRC_MOSC MOSC is the PLL input clock source 0x3 SYSCTL_RSCLKCFG_PSYSDIV PLL System Clock Divisor 0 10 SYSCTL_RSCLKCFG_USEPLL Use PLL 28 29 SYSCTLSCGCACMP Analog Comparator Sleep Mode Clock Gating Control 0x73C read-write n 0x0 0x0 SYSCTL_SCGCACMP_S0 Analog Comparator Module 0 Sleep Mode Clock Gating Control 0 1 SYSCTLSCGCADC Analog-to-Digital Converter Sleep Mode Clock Gating Control 0x738 read-write n 0x0 0x0 SYSCTL_SCGCADC_S0 ADC Module 0 Sleep Mode Clock Gating Control 0 1 SYSCTL_SCGCADC_S1 ADC Module 1 Sleep Mode Clock Gating Control 1 2 SYSCTLSCGCCAN Controller Area Network Sleep Mode Clock Gating Control 0x734 read-write n 0x0 0x0 SYSCTL_SCGCCAN_S0 CAN Module 0 Sleep Mode Clock Gating Control 0 1 SYSCTL_SCGCCAN_S1 CAN Module 1 Sleep Mode Clock Gating Control 1 2 SYSCTLSCGCCCM CRC and Cryptographic Modules Sleep Mode Clock Gating Control 0x774 read-write n 0x0 0x0 SYSCTL_SCGCCCM_S0 CRC and Cryptographic Modules Sleep Mode Clock Gating Control 0 1 SYSCTLSCGCDMA Micro Direct Memory Access Sleep Mode Clock Gating Control 0x70C read-write n 0x0 0x0 SYSCTL_SCGCDMA_S0 uDMA Module Sleep Mode Clock Gating Control 0 1 SYSCTLSCGCEEPROM EEPROM Sleep Mode Clock Gating Control 0x758 read-write n 0x0 0x0 SYSCTL_SCGCEEPROM_S0 EEPROM Module Sleep Mode Clock Gating Control 0 1 SYSCTLSCGCEPI EPI Sleep Mode Clock Gating Control 0x710 read-write n 0x0 0x0 SYSCTL_SCGCEPI_S0 EPI Module Sleep Mode Clock Gating Control 0 1 SYSCTLSCGCGPIO General-Purpose Input/Output Sleep Mode Clock Gating Control 0x708 read-write n 0x0 0x0 SYSCTL_SCGCGPIO_S0 GPIO Port A Sleep Mode Clock Gating Control 0 1 SYSCTL_SCGCGPIO_S1 GPIO Port B Sleep Mode Clock Gating Control 1 2 SYSCTL_SCGCGPIO_S10 GPIO Port L Sleep Mode Clock Gating Control 10 11 SYSCTL_SCGCGPIO_S11 GPIO Port M Sleep Mode Clock Gating Control 11 12 SYSCTL_SCGCGPIO_S12 GPIO Port N Sleep Mode Clock Gating Control 12 13 SYSCTL_SCGCGPIO_S13 GPIO Port P Sleep Mode Clock Gating Control 13 14 SYSCTL_SCGCGPIO_S14 GPIO Port Q Sleep Mode Clock Gating Control 14 15 SYSCTL_SCGCGPIO_S15 GPIO Port R Sleep Mode Clock Gating Control 15 16 SYSCTL_SCGCGPIO_S16 GPIO Port S Sleep Mode Clock Gating Control 16 17 SYSCTL_SCGCGPIO_S17 GPIO Port T Sleep Mode Clock Gating Control 17 18 SYSCTL_SCGCGPIO_S2 GPIO Port C Sleep Mode Clock Gating Control 2 3 SYSCTL_SCGCGPIO_S3 GPIO Port D Sleep Mode Clock Gating Control 3 4 SYSCTL_SCGCGPIO_S4 GPIO Port E Sleep Mode Clock Gating Control 4 5 SYSCTL_SCGCGPIO_S5 GPIO Port F Sleep Mode Clock Gating Control 5 6 SYSCTL_SCGCGPIO_S6 GPIO Port G Sleep Mode Clock Gating Control 6 7 SYSCTL_SCGCGPIO_S7 GPIO Port H Sleep Mode Clock Gating Control 7 8 SYSCTL_SCGCGPIO_S8 GPIO Port J Sleep Mode Clock Gating Control 8 9 SYSCTL_SCGCGPIO_S9 GPIO Port K Sleep Mode Clock Gating Control 9 10 SYSCTLSCGCHIB Hibernation Sleep Mode Clock Gating Control 0x714 read-write n 0x0 0x0 SYSCTL_SCGCHIB_S0 Hibernation Module Sleep Mode Clock Gating Control 0 1 SYSCTLSCGCI2C Inter-Integrated Circuit Sleep Mode Clock Gating Control 0x720 read-write n 0x0 0x0 SYSCTL_SCGCI2C_S0 I2C Module 0 Sleep Mode Clock Gating Control 0 1 SYSCTL_SCGCI2C_S1 I2C Module 1 Sleep Mode Clock Gating Control 1 2 SYSCTL_SCGCI2C_S2 I2C Module 2 Sleep Mode Clock Gating Control 2 3 SYSCTL_SCGCI2C_S3 I2C Module 3 Sleep Mode Clock Gating Control 3 4 SYSCTL_SCGCI2C_S4 I2C Module 4 Sleep Mode Clock Gating Control 4 5 SYSCTL_SCGCI2C_S5 I2C Module 5 Sleep Mode Clock Gating Control 5 6 SYSCTL_SCGCI2C_S6 I2C Module 6 Sleep Mode Clock Gating Control 6 7 SYSCTL_SCGCI2C_S7 I2C Module 7 Sleep Mode Clock Gating Control 7 8 SYSCTL_SCGCI2C_S8 I2C Module 8 Sleep Mode Clock Gating Control 8 9 SYSCTL_SCGCI2C_S9 I2C Module 9 Sleep Mode Clock Gating Control 9 10 SYSCTLSCGCPWM Pulse Width Modulator Sleep Mode Clock Gating Control 0x740 read-write n 0x0 0x0 SYSCTL_SCGCPWM_S0 PWM Module 0 Sleep Mode Clock Gating Control 0 1 SYSCTLSCGCQEI Quadrature Encoder Interface Sleep Mode Clock Gating Control 0x744 read-write n 0x0 0x0 SYSCTL_SCGCQEI_S0 QEI Module 0 Sleep Mode Clock Gating Control 0 1 SYSCTLSCGCSSI Synchronous Serial Interface Sleep Mode Clock Gating Control 0x71C read-write n 0x0 0x0 SYSCTL_SCGCSSI_S0 SSI Module 0 Sleep Mode Clock Gating Control 0 1 SYSCTL_SCGCSSI_S1 SSI Module 1 Sleep Mode Clock Gating Control 1 2 SYSCTL_SCGCSSI_S2 SSI Module 2 Sleep Mode Clock Gating Control 2 3 SYSCTL_SCGCSSI_S3 SSI Module 3 Sleep Mode Clock Gating Control 3 4 SYSCTLSCGCTIMER 16/32-Bit General-Purpose Timer Sleep Mode Clock Gating Control 0x704 read-write n 0x0 0x0 SYSCTL_SCGCTIMER_S0 16/32-Bit General-Purpose Timer 0 Sleep Mode Clock Gating Control 0 1 SYSCTL_SCGCTIMER_S1 16/32-Bit General-Purpose Timer 1 Sleep Mode Clock Gating Control 1 2 SYSCTL_SCGCTIMER_S2 16/32-Bit General-Purpose Timer 2 Sleep Mode Clock Gating Control 2 3 SYSCTL_SCGCTIMER_S3 16/32-Bit General-Purpose Timer 3 Sleep Mode Clock Gating Control 3 4 SYSCTL_SCGCTIMER_S4 16/32-Bit General-Purpose Timer 4 Sleep Mode Clock Gating Control 4 5 SYSCTL_SCGCTIMER_S5 16/32-Bit General-Purpose Timer 5 Sleep Mode Clock Gating Control 5 6 SYSCTL_SCGCTIMER_S6 16/32-Bit General-Purpose Timer 6 Sleep Mode Clock Gating Control 6 7 SYSCTL_SCGCTIMER_S7 16/32-Bit General-Purpose Timer 7 Sleep Mode Clock Gating Control 7 8 SYSCTLSCGCUART Universal Asynchronous Receiver/Transmitter Sleep Mode Clock Gating Control 0x718 read-write n 0x0 0x0 SYSCTL_SCGCUART_S0 UART Module 0 Sleep Mode Clock Gating Control 0 1 SYSCTL_SCGCUART_S1 UART Module 1 Sleep Mode Clock Gating Control 1 2 SYSCTL_SCGCUART_S2 UART Module 2 Sleep Mode Clock Gating Control 2 3 SYSCTL_SCGCUART_S3 UART Module 3 Sleep Mode Clock Gating Control 3 4 SYSCTL_SCGCUART_S4 UART Module 4 Sleep Mode Clock Gating Control 4 5 SYSCTL_SCGCUART_S5 UART Module 5 Sleep Mode Clock Gating Control 5 6 SYSCTL_SCGCUART_S6 UART Module 6 Sleep Mode Clock Gating Control 6 7 SYSCTL_SCGCUART_S7 UART Module 7 Sleep Mode Clock Gating Control 7 8 SYSCTLSCGCUSB Universal Serial Bus Sleep Mode Clock Gating Control 0x728 read-write n 0x0 0x0 SYSCTL_SCGCUSB_S0 USB Module Sleep Mode Clock Gating Control 0 1 SYSCTLSCGCWD Watchdog Timer Sleep Mode Clock Gating Control 0x700 read-write n 0x0 0x0 SYSCTL_SCGCWD_S0 Watchdog Timer 0 Sleep Mode Clock Gating Control 0 1 SYSCTL_SCGCWD_S1 Watchdog Timer 1 Sleep Mode Clock Gating Control 1 2 SYSCTLSLPPWRCFG Sleep Power Configuration 0x188 read-write n 0x0 0x0 SYSCTL_SLPPWRCFG_FLASHPM Flash Power Modes 4 6 SYSCTL_SLPPWRCFG_FLASHPM_NRM Active Mode 0x0 SYSCTL_SLPPWRCFG_FLASHPM_SLP Low Power Mode 0x2 SYSCTL_SLPPWRCFG_SRAMPM SRAM Power Modes 0 2 SYSCTL_SLPPWRCFG_SRAMPM_NRM Active Mode 0x0 SYSCTL_SLPPWRCFG_SRAMPM_SBY Standby Mode 0x1 SYSCTL_SLPPWRCFG_SRAMPM_LP Low Power Mode 0x3 SYSCTLSRACMP Analog Comparator Software Reset 0x53C read-write n 0x0 0x0 SYSCTL_SRACMP_R0 Analog Comparator Module 0 Software Reset 0 1 SYSCTLSRADC Analog-to-Digital Converter Software Reset 0x538 read-write n 0x0 0x0 SYSCTL_SRADC_R0 ADC Module 0 Software Reset 0 1 SYSCTL_SRADC_R1 ADC Module 1 Software Reset 1 2 SYSCTLSRCAN Controller Area Network Software Reset 0x534 read-write n 0x0 0x0 SYSCTL_SRCAN_R0 CAN Module 0 Software Reset 0 1 SYSCTL_SRCAN_R1 CAN Module 1 Software Reset 1 2 SYSCTLSRCCM CRC and Cryptographic Modules Software Reset 0x574 read-write n 0x0 0x0 SYSCTL_SRCCM_R0 CRC and Cryptographic Modules Software Reset 0 1 SYSCTLSRDMA Micro Direct Memory Access Software Reset 0x50C read-write n 0x0 0x0 SYSCTL_SRDMA_R0 uDMA Module Software Reset 0 1 SYSCTLSREEPROM EEPROM Software Reset 0x558 read-write n 0x0 0x0 SYSCTL_SREEPROM_R0 EEPROM Module Software Reset 0 1 SYSCTLSREPI EPI Software Reset 0x510 read-write n 0x0 0x0 SYSCTL_SREPI_R0 EPI Module Software Reset 0 1 SYSCTLSRGPIO General-Purpose Input/Output Software Reset 0x508 read-write n 0x0 0x0 SYSCTL_SRGPIO_R0 GPIO Port A Software Reset 0 1 SYSCTL_SRGPIO_R1 GPIO Port B Software Reset 1 2 SYSCTL_SRGPIO_R10 GPIO Port L Software Reset 10 11 SYSCTL_SRGPIO_R11 GPIO Port M Software Reset 11 12 SYSCTL_SRGPIO_R12 GPIO Port N Software Reset 12 13 SYSCTL_SRGPIO_R13 GPIO Port P Software Reset 13 14 SYSCTL_SRGPIO_R14 GPIO Port Q Software Reset 14 15 SYSCTL_SRGPIO_R15 GPIO Port R Software Reset 15 16 SYSCTL_SRGPIO_R16 GPIO Port S Software Reset 16 17 SYSCTL_SRGPIO_R17 GPIO Port T Software Reset 17 18 SYSCTL_SRGPIO_R2 GPIO Port C Software Reset 2 3 SYSCTL_SRGPIO_R3 GPIO Port D Software Reset 3 4 SYSCTL_SRGPIO_R4 GPIO Port E Software Reset 4 5 SYSCTL_SRGPIO_R5 GPIO Port F Software Reset 5 6 SYSCTL_SRGPIO_R6 GPIO Port G Software Reset 6 7 SYSCTL_SRGPIO_R7 GPIO Port H Software Reset 7 8 SYSCTL_SRGPIO_R8 GPIO Port J Software Reset 8 9 SYSCTL_SRGPIO_R9 GPIO Port K Software Reset 9 10 SYSCTLSRHIB Hibernation Software Reset 0x514 read-write n 0x0 0x0 SYSCTL_SRHIB_R0 Hibernation Module Software Reset 0 1 SYSCTLSRI2C Inter-Integrated Circuit Software Reset 0x520 read-write n 0x0 0x0 SYSCTL_SRI2C_R0 I2C Module 0 Software Reset 0 1 SYSCTL_SRI2C_R1 I2C Module 1 Software Reset 1 2 SYSCTL_SRI2C_R2 I2C Module 2 Software Reset 2 3 SYSCTL_SRI2C_R3 I2C Module 3 Software Reset 3 4 SYSCTL_SRI2C_R4 I2C Module 4 Software Reset 4 5 SYSCTL_SRI2C_R5 I2C Module 5 Software Reset 5 6 SYSCTL_SRI2C_R6 I2C Module 6 Software Reset 6 7 SYSCTL_SRI2C_R7 I2C Module 7 Software Reset 7 8 SYSCTL_SRI2C_R8 I2C Module 8 Software Reset 8 9 SYSCTL_SRI2C_R9 I2C Module 9 Software Reset 9 10 SYSCTLSRPWM Pulse Width Modulator Software Reset 0x540 read-write n 0x0 0x0 SYSCTL_SRPWM_R0 PWM Module 0 Software Reset 0 1 SYSCTLSRQEI Quadrature Encoder Interface Software Reset 0x544 read-write n 0x0 0x0 SYSCTL_SRQEI_R0 QEI Module 0 Software Reset 0 1 SYSCTLSRSSI Synchronous Serial Interface Software Reset 0x51C read-write n 0x0 0x0 SYSCTL_SRSSI_R0 SSI Module 0 Software Reset 0 1 SYSCTL_SRSSI_R1 SSI Module 1 Software Reset 1 2 SYSCTL_SRSSI_R2 SSI Module 2 Software Reset 2 3 SYSCTL_SRSSI_R3 SSI Module 3 Software Reset 3 4 SYSCTLSRTIMER 16/32-Bit General-Purpose Timer Software Reset 0x504 read-write n 0x0 0x0 SYSCTL_SRTIMER_R0 16/32-Bit General-Purpose Timer 0 Software Reset 0 1 SYSCTL_SRTIMER_R1 16/32-Bit General-Purpose Timer 1 Software Reset 1 2 SYSCTL_SRTIMER_R2 16/32-Bit General-Purpose Timer 2 Software Reset 2 3 SYSCTL_SRTIMER_R3 16/32-Bit General-Purpose Timer 3 Software Reset 3 4 SYSCTL_SRTIMER_R4 16/32-Bit General-Purpose Timer 4 Software Reset 4 5 SYSCTL_SRTIMER_R5 16/32-Bit General-Purpose Timer 5 Software Reset 5 6 SYSCTL_SRTIMER_R6 16/32-Bit General-Purpose Timer 6 Software Reset 6 7 SYSCTL_SRTIMER_R7 16/32-Bit General-Purpose Timer 7 Software Reset 7 8 SYSCTLSRUART Universal Asynchronous Receiver/Transmitter Software Reset 0x518 read-write n 0x0 0x0 SYSCTL_SRUART_R0 UART Module 0 Software Reset 0 1 SYSCTL_SRUART_R1 UART Module 1 Software Reset 1 2 SYSCTL_SRUART_R2 UART Module 2 Software Reset 2 3 SYSCTL_SRUART_R3 UART Module 3 Software Reset 3 4 SYSCTL_SRUART_R4 UART Module 4 Software Reset 4 5 SYSCTL_SRUART_R5 UART Module 5 Software Reset 5 6 SYSCTL_SRUART_R6 UART Module 6 Software Reset 6 7 SYSCTL_SRUART_R7 UART Module 7 Software Reset 7 8 SYSCTLSRUSB Universal Serial Bus Software Reset 0x528 read-write n 0x0 0x0 SYSCTL_SRUSB_R0 USB Module Software Reset 0 1 SYSCTLSRWD Watchdog Timer Software Reset 0x500 read-write n 0x0 0x0 SYSCTL_SRWD_R0 Watchdog Timer 0 Software Reset 0 1 SYSCTL_SRWD_R1 Watchdog Timer 1 Software Reset 1 2 SYSCTLSYSPROP System Properties 0x14C read-write n 0x0 0x0 SYSCTL_SYSPROP_FPU FPU Present 0 1 SYSCTLUSBMPC USB Memory Power Control 0x284 read-write n 0x0 0x0 SYSCTL_USBMPC_PWRCTL Memory Array Power Control 0 2 SYSCTL_USBMPC_PWRCTL_OFF Array OFF 0x0 SYSCTL_USBMPC_PWRCTL_RETAIN SRAM Retention 0x1 SYSCTL_USBMPC_PWRCTL_ON Array On 0x3 SYSCTLUSBPDS USB Power Domain Status 0x280 read-write n 0x0 0x0 SYSCTL_USBPDS_MEMSTAT Memory Array Power Status 2 4 SYSCTL_USBPDS_MEMSTAT_OFF Array OFF 0x0 SYSCTL_USBPDS_MEMSTAT_RETAIN SRAM Retention 0x1 SYSCTL_USBPDS_MEMSTAT_ON Array On 0x3 SYSCTL_USBPDS_PWRSTAT Power Domain Status 0 2 SYSCTL_USBPDS_PWRSTAT_OFF OFF 0x0 SYSCTL_USBPDS_PWRSTAT_ON ON 0x3 SYSPROP System Properties 0x14C -1 read-write n 0x0 0x0 SYSCTL_SYSPROP_FPU FPU Present 0 1 USBMPC USB Memory Power Control 0x284 -1 read-write n 0x0 0x0 SYSCTL_USBMPC_PWRCTL Memory Array Power Control 0 2 SYSCTL_USBMPC_PWRCTL_OFF Array OFF 0x0 SYSCTL_USBMPC_PWRCTL_RETAIN SRAM Retention 0x1 SYSCTL_USBMPC_PWRCTL_ON Array On 0x3 USBPDS USB Power Domain Status 0x280 -1 read-write n 0x0 0x0 SYSCTL_USBPDS_MEMSTAT Memory Array Power Status 2 4 SYSCTL_USBPDS_MEMSTAT_OFF Array OFF 0x0 SYSCTL_USBPDS_MEMSTAT_RETAIN SRAM Retention 0x1 SYSCTL_USBPDS_MEMSTAT_ON Array On 0x3 SYSCTL_USBPDS_PWRSTAT Power Domain Status 0 2 SYSCTL_USBPDS_PWRSTAT_OFF OFF 0x0 SYSCTL_USBPDS_PWRSTAT_ON ON 0x3 SYSEXC Register map for SYSEXC peripheral SYSEXC 0x0 0x0 0x1000 registers n SYSEXC 67 IC System Exception Interrupt Clear 0xC -1 write-only n 0x0 0x0 SYSEXC_IC_FPDZCIC Floating-Point Divide By 0 Exception Interrupt Clear 1 2 write-only SYSEXC_IC_FPIDCIC Floating-Point Input Denormal Exception Interrupt Clear 0 1 write-only SYSEXC_IC_FPIOCIC Floating-Point Invalid Operation Interrupt Clear 2 3 write-only SYSEXC_IC_FPIXCIC Floating-Point Inexact Exception Interrupt Clear 5 6 write-only SYSEXC_IC_FPOFCIC Floating-Point Overflow Exception Interrupt Clear 4 5 write-only SYSEXC_IC_FPUFCIC Floating-Point Underflow Exception Interrupt Clear 3 4 write-only IM System Exception Interrupt Mask 0x4 -1 read-write n 0x0 0x0 SYSEXC_IM_FPDZCIM Floating-Point Divide By 0 Exception Interrupt Mask 1 2 SYSEXC_IM_FPIDCIM Floating-Point Input Denormal Exception Interrupt Mask 0 1 SYSEXC_IM_FPIOCIM Floating-Point Invalid Operation Interrupt Mask 2 3 SYSEXC_IM_FPIXCIM Floating-Point Inexact Exception Interrupt Mask 5 6 SYSEXC_IM_FPOFCIM Floating-Point Overflow Exception Interrupt Mask 4 5 SYSEXC_IM_FPUFCIM Floating-Point Underflow Exception Interrupt Mask 3 4 MIS System Exception Masked Interrupt Status 0x8 -1 read-write n 0x0 0x0 SYSEXC_MIS_FPDZCMIS Floating-Point Divide By 0 Exception Masked Interrupt Status 1 2 SYSEXC_MIS_FPIDCMIS Floating-Point Input Denormal Exception Masked Interrupt Status 0 1 SYSEXC_MIS_FPIOCMIS Floating-Point Invalid Operation Masked Interrupt Status 2 3 SYSEXC_MIS_FPIXCMIS Floating-Point Inexact Exception Masked Interrupt Status 5 6 SYSEXC_MIS_FPOFCMIS Floating-Point Overflow Exception Masked Interrupt Status 4 5 SYSEXC_MIS_FPUFCMIS Floating-Point Underflow Exception Masked Interrupt Status 3 4 RIS System Exception Raw Interrupt Status 0x0 -1 read-write n 0x0 0x0 SYSEXC_RIS_FPDZCRIS Floating-Point Divide By 0 Exception Raw Interrupt Status 1 2 SYSEXC_RIS_FPIDCRIS Floating-Point Input Denormal Exception Raw Interrupt Status 0 1 SYSEXC_RIS_FPIOCRIS Floating-Point Invalid Operation Raw Interrupt Status 2 3 SYSEXC_RIS_FPIXCRIS Floating-Point Inexact Exception Raw Interrupt Status 5 6 SYSEXC_RIS_FPOFCRIS Floating-Point Overflow Exception Raw Interrupt Status 4 5 SYSEXC_RIS_FPUFCRIS Floating-Point Underflow Exception Raw Interrupt Status 3 4 SYSEXCIC System Exception Interrupt Clear 0xC write-only n 0x0 0x0 SYSEXC_IC_FPDZCIC Floating-Point Divide By 0 Exception Interrupt Clear 1 2 write-only SYSEXC_IC_FPIDCIC Floating-Point Input Denormal Exception Interrupt Clear 0 1 write-only SYSEXC_IC_FPIOCIC Floating-Point Invalid Operation Interrupt Clear 2 3 write-only SYSEXC_IC_FPIXCIC Floating-Point Inexact Exception Interrupt Clear 5 6 write-only SYSEXC_IC_FPOFCIC Floating-Point Overflow Exception Interrupt Clear 4 5 write-only SYSEXC_IC_FPUFCIC Floating-Point Underflow Exception Interrupt Clear 3 4 write-only SYSEXCIM System Exception Interrupt Mask 0x4 read-write n 0x0 0x0 SYSEXC_IM_FPDZCIM Floating-Point Divide By 0 Exception Interrupt Mask 1 2 SYSEXC_IM_FPIDCIM Floating-Point Input Denormal Exception Interrupt Mask 0 1 SYSEXC_IM_FPIOCIM Floating-Point Invalid Operation Interrupt Mask 2 3 SYSEXC_IM_FPIXCIM Floating-Point Inexact Exception Interrupt Mask 5 6 SYSEXC_IM_FPOFCIM Floating-Point Overflow Exception Interrupt Mask 4 5 SYSEXC_IM_FPUFCIM Floating-Point Underflow Exception Interrupt Mask 3 4 SYSEXCMIS System Exception Masked Interrupt Status 0x8 read-write n 0x0 0x0 SYSEXC_MIS_FPDZCMIS Floating-Point Divide By 0 Exception Masked Interrupt Status 1 2 SYSEXC_MIS_FPIDCMIS Floating-Point Input Denormal Exception Masked Interrupt Status 0 1 SYSEXC_MIS_FPIOCMIS Floating-Point Invalid Operation Masked Interrupt Status 2 3 SYSEXC_MIS_FPIXCMIS Floating-Point Inexact Exception Masked Interrupt Status 5 6 SYSEXC_MIS_FPOFCMIS Floating-Point Overflow Exception Masked Interrupt Status 4 5 SYSEXC_MIS_FPUFCMIS Floating-Point Underflow Exception Masked Interrupt Status 3 4 SYSEXCRIS System Exception Raw Interrupt Status 0x0 read-write n 0x0 0x0 SYSEXC_RIS_FPDZCRIS Floating-Point Divide By 0 Exception Raw Interrupt Status 1 2 SYSEXC_RIS_FPIDCRIS Floating-Point Input Denormal Exception Raw Interrupt Status 0 1 SYSEXC_RIS_FPIOCRIS Floating-Point Invalid Operation Raw Interrupt Status 2 3 SYSEXC_RIS_FPIXCRIS Floating-Point Inexact Exception Raw Interrupt Status 5 6 SYSEXC_RIS_FPOFCRIS Floating-Point Overflow Exception Raw Interrupt Status 4 5 SYSEXC_RIS_FPUFCRIS Floating-Point Underflow Exception Raw Interrupt Status 3 4 TIMER0 Register map for TIMER0 peripheral TIMER 0x0 0x0 0x1000 registers n TIMER0A 19 TIMER0B 20 ADCEV GPTM ADC Event 0x70 -1 read-write n 0x0 0x0 TIMER_ADCEV_CAEADCEN GPTM A Capture Event ADC Trigger Enable 2 3 TIMER_ADCEV_CAMADCEN GPTM A Capture Match Event ADC Trigger Enable 1 2 TIMER_ADCEV_CBEADCEN GPTM B Capture Event ADC Trigger Enable 10 11 TIMER_ADCEV_CBMADCEN GPTM B Capture Match Event ADC Trigger Enable 9 10 TIMER_ADCEV_RTCADCEN GPTM RTC Match Event ADC Trigger Enable 3 4 TIMER_ADCEV_TAMADCEN GPTM A Mode Match Event ADC Trigger Enable 4 5 TIMER_ADCEV_TATOADCEN GPTM A Time-Out Event ADC Trigger Enable 0 1 TIMER_ADCEV_TBMADCEN GPTM B Mode Match Event ADC Trigger Enable 11 12 TIMER_ADCEV_TBTOADCEN GPTM B Time-Out Event ADC Trigger Enable 8 9 CC GPTM Clock Configuration 0xFC8 -1 read-write n 0x0 0x0 TIMER_CC_ALTCLK Alternate Clock Source 0 1 CFG GPTM Configuration 0x0 -1 read-write n 0x0 0x0 TIMER_CFG GPTM Configuration 0 3 TIMER_CFG_32_BIT_TIMER For a 16/32-bit timer, this value selects the 32-bit timer configuration 0x0 TIMER_CFG_32_BIT_RTC For a 16/32-bit timer, this value selects the 32-bit real-time clock (RTC) counter configuration 0x1 TIMER_CFG_16_BIT For a 16/32-bit timer, this value selects the 16-bit timer configuration 0x4 CTL GPTM Control 0xC -1 read-write n 0x0 0x0 TIMER_CTL_RTCEN GPTM RTC Stall Enable 4 5 TIMER_CTL_TAEN GPTM Timer A Enable 0 1 TIMER_CTL_TAEVENT GPTM Timer A Event Mode 2 4 TIMER_CTL_TAEVENT_POS Positive edge 0x0 TIMER_CTL_TAEVENT_NEG Negative edge 0x1 TIMER_CTL_TAEVENT_BOTH Both edges 0x3 TIMER_CTL_TAOTE GPTM Timer A Output Trigger Enable 5 6 TIMER_CTL_TAPWML GPTM Timer A PWM Output Level 6 7 TIMER_CTL_TASTALL GPTM Timer A Stall Enable 1 2 TIMER_CTL_TBEN GPTM Timer B Enable 8 9 TIMER_CTL_TBEVENT GPTM Timer B Event Mode 10 12 TIMER_CTL_TBEVENT_POS Positive edge 0x0 TIMER_CTL_TBEVENT_NEG Negative edge 0x1 TIMER_CTL_TBEVENT_BOTH Both edges 0x3 TIMER_CTL_TBOTE GPTM Timer B Output Trigger Enable 13 14 TIMER_CTL_TBPWML GPTM Timer B PWM Output Level 14 15 TIMER_CTL_TBSTALL GPTM Timer B Stall Enable 9 10 DMAEV GPTM DMA Event 0x6C -1 read-write n 0x0 0x0 TIMER_DMAEV_CAEDMAEN GPTM A Capture Event DMA Trigger Enable 2 3 TIMER_DMAEV_CAMDMAEN GPTM A Capture Match Event DMA Trigger Enable 1 2 TIMER_DMAEV_CBEDMAEN GPTM B Capture Event DMA Trigger Enable 10 11 TIMER_DMAEV_CBMDMAEN GPTM B Capture Match Event DMA Trigger Enable 9 10 TIMER_DMAEV_RTCDMAEN GPTM A RTC Match Event DMA Trigger Enable 3 4 TIMER_DMAEV_TAMDMAEN GPTM A Mode Match Event DMA Trigger Enable 4 5 TIMER_DMAEV_TATODMAEN GPTM A Time-Out Event DMA Trigger Enable 0 1 TIMER_DMAEV_TBMDMAEN GPTM B Mode Match Event DMA Trigger Enable 11 12 TIMER_DMAEV_TBTODMAEN GPTM B Time-Out Event DMA Trigger Enable 8 9 ICR GPTM Interrupt Clear 0x24 -1 write-only n 0x0 0x0 TIMER_ICR_CAECINT GPTM Timer A Capture Mode Event Interrupt Clear 2 3 write-only TIMER_ICR_CAMCINT GPTM Timer A Capture Mode Match Interrupt Clear 1 2 write-only TIMER_ICR_CBECINT GPTM Timer B Capture Mode Event Interrupt Clear 10 11 write-only TIMER_ICR_CBMCINT GPTM Timer B Capture Mode Match Interrupt Clear 9 10 write-only TIMER_ICR_DMAAINT GPTM Timer A DMA Done Interrupt Clear 5 6 write-only TIMER_ICR_DMABINT GPTM Timer B DMA Done Interrupt Clear 13 14 write-only TIMER_ICR_RTCCINT GPTM RTC Interrupt Clear 3 4 write-only TIMER_ICR_TAMCINT GPTM Timer A Match Interrupt Clear 4 5 write-only TIMER_ICR_TATOCINT GPTM Timer A Time-Out Raw Interrupt 0 1 write-only TIMER_ICR_TBMCINT GPTM Timer B Match Interrupt Clear 11 12 write-only TIMER_ICR_TBTOCINT GPTM Timer B Time-Out Interrupt Clear 8 9 write-only IMR GPTM Interrupt Mask 0x18 -1 read-write n 0x0 0x0 TIMER_IMR_CAEIM GPTM Timer A Capture Mode Event Interrupt Mask 2 3 TIMER_IMR_CAMIM GPTM Timer A Capture Mode Match Interrupt Mask 1 2 TIMER_IMR_CBEIM GPTM Timer B Capture Mode Event Interrupt Mask 10 11 TIMER_IMR_CBMIM GPTM Timer B Capture Mode Match Interrupt Mask 9 10 TIMER_IMR_DMAAIM GPTM Timer A DMA Done Interrupt Mask 5 6 TIMER_IMR_DMABIM GPTM Timer B DMA Done Interrupt Mask 13 14 TIMER_IMR_RTCIM GPTM RTC Interrupt Mask 3 4 TIMER_IMR_TAMIM GPTM Timer A Match Interrupt Mask 4 5 TIMER_IMR_TATOIM GPTM Timer A Time-Out Interrupt Mask 0 1 TIMER_IMR_TBMIM GPTM Timer B Match Interrupt Mask 11 12 TIMER_IMR_TBTOIM GPTM Timer B Time-Out Interrupt Mask 8 9 MIS GPTM Masked Interrupt Status 0x20 -1 read-write n 0x0 0x0 TIMER_MIS_CAEMIS GPTM Timer A Capture Mode Event Masked Interrupt 2 3 TIMER_MIS_CAMMIS GPTM Timer A Capture Mode Match Masked Interrupt 1 2 TIMER_MIS_CBEMIS GPTM Timer B Capture Mode Event Masked Interrupt 10 11 TIMER_MIS_CBMMIS GPTM Timer B Capture Mode Match Masked Interrupt 9 10 TIMER_MIS_DMAAMIS GPTM Timer A DMA Done Masked Interrupt 5 6 TIMER_MIS_DMABMIS GPTM Timer B DMA Done Masked Interrupt 13 14 TIMER_MIS_RTCMIS GPTM RTC Masked Interrupt 3 4 TIMER_MIS_TAMMIS GPTM Timer A Match Masked Interrupt 4 5 TIMER_MIS_TATOMIS GPTM Timer A Time-Out Masked Interrupt 0 1 TIMER_MIS_TBMMIS GPTM Timer B Match Masked Interrupt 11 12 TIMER_MIS_TBTOMIS GPTM Timer B Time-Out Masked Interrupt 8 9 PP GPTM Peripheral Properties 0xFC0 -1 read-write n 0x0 0x0 TIMER_PP_ALTCLK Alternate Clock Source 6 7 TIMER_PP_CHAIN Chain with Other Timers 4 5 TIMER_PP_SIZE Count Size 0 4 TIMER_PP_SIZE_16 Timer A and Timer B counters are 16 bits each with an 8-bit prescale counter 0x0 TIMER_PP_SIZE_32 Timer A and Timer B counters are 32 bits each with a 16-bit prescale counter 0x1 TIMER_PP_SYNCCNT Synchronize Start 5 6 RIS GPTM Raw Interrupt Status 0x1C -1 read-write n 0x0 0x0 TIMER_RIS_CAERIS GPTM Timer A Capture Mode Event Raw Interrupt 2 3 TIMER_RIS_CAMRIS GPTM Timer A Capture Mode Match Raw Interrupt 1 2 TIMER_RIS_CBERIS GPTM Timer B Capture Mode Event Raw Interrupt 10 11 TIMER_RIS_CBMRIS GPTM Timer B Capture Mode Match Raw Interrupt 9 10 TIMER_RIS_DMAARIS GPTM Timer A DMA Done Raw Interrupt Status 5 6 TIMER_RIS_DMABRIS GPTM Timer B DMA Done Raw Interrupt Status 13 14 TIMER_RIS_RTCRIS GPTM RTC Raw Interrupt 3 4 TIMER_RIS_TAMRIS GPTM Timer A Match Raw Interrupt 4 5 TIMER_RIS_TATORIS GPTM Timer A Time-Out Raw Interrupt 0 1 TIMER_RIS_TBMRIS GPTM Timer B Match Raw Interrupt 11 12 TIMER_RIS_TBTORIS GPTM Timer B Time-Out Raw Interrupt 8 9 RTCPD GPTM RTC Predivide 0x58 -1 read-write n 0x0 0x0 TIMER_RTCPD_RTCPD RTC Predivide Counter Value 0 16 SYNC GPTM Synchronize 0x10 -1 read-write n 0x0 0x0 TIMER_SYNC_SYNCT0 Synchronize GPTM Timer 0 0 2 TIMER_SYNC_SYNCT0_NONE GPTM0 is not affected 0x0 TIMER_SYNC_SYNCT0_TA A timeout event for Timer A of GPTM0 is triggered 0x1 TIMER_SYNC_SYNCT0_TB A timeout event for Timer B of GPTM0 is triggered 0x2 TIMER_SYNC_SYNCT0_TATB A timeout event for both Timer A and Timer B of GPTM0 is triggered 0x3 TIMER_SYNC_SYNCT1 Synchronize GPTM Timer 1 2 4 TIMER_SYNC_SYNCT1_NONE GPTM1 is not affected 0x0 TIMER_SYNC_SYNCT1_TA A timeout event for Timer A of GPTM1 is triggered 0x1 TIMER_SYNC_SYNCT1_TB A timeout event for Timer B of GPTM1 is triggered 0x2 TIMER_SYNC_SYNCT1_TATB A timeout event for both Timer A and Timer B of GPTM1 is triggered 0x3 TIMER_SYNC_SYNCT2 Synchronize GPTM Timer 2 4 6 TIMER_SYNC_SYNCT2_NONE GPTM2 is not affected 0x0 TIMER_SYNC_SYNCT2_TA A timeout event for Timer A of GPTM2 is triggered 0x1 TIMER_SYNC_SYNCT2_TB A timeout event for Timer B of GPTM2 is triggered 0x2 TIMER_SYNC_SYNCT2_TATB A timeout event for both Timer A and Timer B of GPTM2 is triggered 0x3 TIMER_SYNC_SYNCT3 Synchronize GPTM Timer 3 6 8 TIMER_SYNC_SYNCT3_NONE GPTM3 is not affected 0x0 TIMER_SYNC_SYNCT3_TA A timeout event for Timer A of GPTM3 is triggered 0x1 TIMER_SYNC_SYNCT3_TB A timeout event for Timer B of GPTM3 is triggered 0x2 TIMER_SYNC_SYNCT3_TATB A timeout event for both Timer A and Timer B of GPTM3 is triggered 0x3 TIMER_SYNC_SYNCT4 Synchronize GPTM Timer 4 8 10 TIMER_SYNC_SYNCT4_NONE GPTM4 is not affected 0x0 TIMER_SYNC_SYNCT4_TA A timeout event for Timer A of GPTM4 is triggered 0x1 TIMER_SYNC_SYNCT4_TB A timeout event for Timer B of GPTM4 is triggered 0x2 TIMER_SYNC_SYNCT4_TATB A timeout event for both Timer A and Timer B of GPTM4 is triggered 0x3 TIMER_SYNC_SYNCT5 Synchronize GPTM Timer 5 10 12 TIMER_SYNC_SYNCT5_NONE GPTM5 is not affected 0x0 TIMER_SYNC_SYNCT5_TA A timeout event for Timer A of GPTM5 is triggered 0x1 TIMER_SYNC_SYNCT5_TB A timeout event for Timer B of GPTM5 is triggered 0x2 TIMER_SYNC_SYNCT5_TATB A timeout event for both Timer A and Timer B of GPTM5 is triggered 0x3 TIMER_SYNC_SYNCT6 Synchronize GPTM Timer 6 12 14 TIMER_SYNC_SYNCT6_NONE GPTM6 is not affected 0x0 TIMER_SYNC_SYNCT6_TA A timeout event for Timer A of GPTM6 is triggered 0x1 TIMER_SYNC_SYNCT6_TB A timeout event for Timer B of GPTM6 is triggered 0x2 TIMER_SYNC_SYNCT6_TATB A timeout event for both Timer A and Timer B of GPTM6 is triggered 0x3 TIMER_SYNC_SYNCT7 Synchronize GPTM Timer 7 14 16 TIMER_SYNC_SYNCT7_NONE GPT7 is not affected 0x0 TIMER_SYNC_SYNCT7_TA A timeout event for Timer A of GPTM7 is triggered 0x1 TIMER_SYNC_SYNCT7_TB A timeout event for Timer B of GPTM7 is triggered 0x2 TIMER_SYNC_SYNCT7_TATB A timeout event for both Timer A and Timer B of GPTM7 is triggered 0x3 TAILR GPTM Timer A Interval Load 0x28 -1 read-write n 0x0 0x0 TAMATCHR GPTM Timer A Match 0x30 -1 read-write n 0x0 0x0 TAMR GPTM Timer A Mode 0x4 -1 read-write n 0x0 0x0 TIMER_TAMR_TAAMS GPTM Timer A Alternate Mode Select 3 4 TIMER_TAMR_TACDIR GPTM Timer A Count Direction 4 5 TIMER_TAMR_TACINTD One-shot/Periodic Interrupt Disable 12 13 TIMER_TAMR_TACMR GPTM Timer A Capture Mode 2 3 TIMER_TAMR_TAILD GPTM Timer A Interval Load Write 8 9 TIMER_TAMR_TAMIE GPTM Timer A Match Interrupt Enable 5 6 TIMER_TAMR_TAMR GPTM Timer A Mode 0 2 TIMER_TAMR_TAMR_1_SHOT One-Shot Timer mode 0x1 TIMER_TAMR_TAMR_PERIOD Periodic Timer mode 0x2 TIMER_TAMR_TAMR_CAP Capture mode 0x3 TIMER_TAMR_TAMRSU GPTM Timer A Match Register Update 10 11 TIMER_TAMR_TAPLO GPTM Timer A PWM Legacy Operation 11 12 TIMER_TAMR_TAPWMIE GPTM Timer A PWM Interrupt Enable 9 10 TIMER_TAMR_TASNAPS GPTM Timer A Snap-Shot Mode 7 8 TIMER_TAMR_TAWOT GPTM Timer A Wait-on-Trigger 6 7 TIMER_TAMR_TCACT Timer Compare Action Select 13 16 TIMER_TAMR_TCACT_NONE Disable compare operations 0x0 TIMER_TAMR_TCACT_TOGGLE Toggle State on Time-Out 0x1 TIMER_TAMR_TCACT_CLRTO Clear CCP on Time-Out 0x2 TIMER_TAMR_TCACT_SETTO Set CCP on Time-Out 0x3 TIMER_TAMR_TCACT_SETTOGTO Set CCP immediately and toggle on Time-Out 0x4 TIMER_TAMR_TCACT_CLRTOGTO Clear CCP immediately and toggle on Time-Out 0x5 TIMER_TAMR_TCACT_SETCLRTO Set CCP immediately and clear on Time-Out 0x6 TIMER_TAMR_TCACT_CLRSETTO Clear CCP immediately and set on Time-Out 0x7 TAPMR GPTM TimerA Prescale Match 0x40 -1 read-write n 0x0 0x0 TIMER_TAPMR_TAPSMR GPTM TimerA Prescale Match 0 8 TAPR GPTM Timer A Prescale 0x38 -1 read-write n 0x0 0x0 TIMER_TAPR_TAPSR GPTM Timer A Prescale 0 8 TAPS GPTM Timer A Prescale Snapshot 0x5C -1 read-write n 0x0 0x0 TIMER_TAPS_PSS GPTM Timer A Prescaler Snapshot 0 16 TAR GPTM Timer A 0x48 -1 read-write n 0x0 0x0 TAV GPTM Timer A Value 0x50 -1 read-write n 0x0 0x0 TBILR GPTM Timer B Interval Load 0x2C -1 read-write n 0x0 0x0 TBMATCHR GPTM Timer B Match 0x34 -1 read-write n 0x0 0x0 TBMR GPTM Timer B Mode 0x8 -1 read-write n 0x0 0x0 TIMER_TBMR_TBAMS GPTM Timer B Alternate Mode Select 3 4 TIMER_TBMR_TBCDIR GPTM Timer B Count Direction 4 5 TIMER_TBMR_TBCINTD One-Shot/Periodic Interrupt Disable 12 13 TIMER_TBMR_TBCMR GPTM Timer B Capture Mode 2 3 TIMER_TBMR_TBILD GPTM Timer B Interval Load Write 8 9 TIMER_TBMR_TBMIE GPTM Timer B Match Interrupt Enable 5 6 TIMER_TBMR_TBMR GPTM Timer B Mode 0 2 TIMER_TBMR_TBMR_1_SHOT One-Shot Timer mode 0x1 TIMER_TBMR_TBMR_PERIOD Periodic Timer mode 0x2 TIMER_TBMR_TBMR_CAP Capture mode 0x3 TIMER_TBMR_TBMRSU GPTM Timer B Match Register Update 10 11 TIMER_TBMR_TBPLO GPTM Timer B PWM Legacy Operation 11 12 TIMER_TBMR_TBPWMIE GPTM Timer B PWM Interrupt Enable 9 10 TIMER_TBMR_TBSNAPS GPTM Timer B Snap-Shot Mode 7 8 TIMER_TBMR_TBWOT GPTM Timer B Wait-on-Trigger 6 7 TIMER_TBMR_TCACT Timer Compare Action Select 13 16 TIMER_TBMR_TCACT_NONE Disable compare operations 0x0 TIMER_TBMR_TCACT_TOGGLE Toggle State on Time-Out 0x1 TIMER_TBMR_TCACT_CLRTO Clear CCP on Time-Out 0x2 TIMER_TBMR_TCACT_SETTO Set CCP on Time-Out 0x3 TIMER_TBMR_TCACT_SETTOGTO Set CCP immediately and toggle on Time-Out 0x4 TIMER_TBMR_TCACT_CLRTOGTO Clear CCP immediately and toggle on Time-Out 0x5 TIMER_TBMR_TCACT_SETCLRTO Set CCP immediately and clear on Time-Out 0x6 TIMER_TBMR_TCACT_CLRSETTO Clear CCP immediately and set on Time-Out 0x7 TBPMR GPTM TimerB Prescale Match 0x44 -1 read-write n 0x0 0x0 TIMER_TBPMR_TBPSMR GPTM TimerB Prescale Match 0 8 TBPR GPTM Timer B Prescale 0x3C -1 read-write n 0x0 0x0 TIMER_TBPR_TBPSR GPTM Timer B Prescale 0 8 TBPS GPTM Timer B Prescale Snapshot 0x60 -1 read-write n 0x0 0x0 TIMER_TBPS_PSS GPTM Timer A Prescaler Value 0 16 TBR GPTM Timer B 0x4C -1 read-write n 0x0 0x0 TBV GPTM Timer B Value 0x54 -1 read-write n 0x0 0x0 TIMER0ADCEV GPTM ADC Event 0x70 read-write n 0x0 0x0 TIMER_ADCEV_CAEADCEN GPTM A Capture Event ADC Trigger Enable 2 3 TIMER_ADCEV_CAMADCEN GPTM A Capture Match Event ADC Trigger Enable 1 2 TIMER_ADCEV_CBEADCEN GPTM B Capture Event ADC Trigger Enable 10 11 TIMER_ADCEV_CBMADCEN GPTM B Capture Match Event ADC Trigger Enable 9 10 TIMER_ADCEV_RTCADCEN GPTM RTC Match Event ADC Trigger Enable 3 4 TIMER_ADCEV_TAMADCEN GPTM A Mode Match Event ADC Trigger Enable 4 5 TIMER_ADCEV_TATOADCEN GPTM A Time-Out Event ADC Trigger Enable 0 1 TIMER_ADCEV_TBMADCEN GPTM B Mode Match Event ADC Trigger Enable 11 12 TIMER_ADCEV_TBTOADCEN GPTM B Time-Out Event ADC Trigger Enable 8 9 TIMER0CC GPTM Clock Configuration 0xFC8 read-write n 0x0 0x0 TIMER_CC_ALTCLK Alternate Clock Source 0 1 TIMER0CFG GPTM Configuration 0x0 read-write n 0x0 0x0 TIMER_CFG GPTM Configuration 0 3 TIMER_CFG_32_BIT_TIMER For a 16/32-bit timer, this value selects the 32-bit timer configuration 0x0 TIMER_CFG_32_BIT_RTC For a 16/32-bit timer, this value selects the 32-bit real-time clock (RTC) counter configuration 0x1 TIMER_CFG_16_BIT For a 16/32-bit timer, this value selects the 16-bit timer configuration 0x4 TIMER0CTL GPTM Control 0xC read-write n 0x0 0x0 TIMER_CTL_RTCEN GPTM RTC Stall Enable 4 5 TIMER_CTL_TAEN GPTM Timer A Enable 0 1 TIMER_CTL_TAEVENT GPTM Timer A Event Mode 2 4 TIMER_CTL_TAEVENT_POS Positive edge 0x0 TIMER_CTL_TAEVENT_NEG Negative edge 0x1 TIMER_CTL_TAEVENT_BOTH Both edges 0x3 TIMER_CTL_TAOTE GPTM Timer A Output Trigger Enable 5 6 TIMER_CTL_TAPWML GPTM Timer A PWM Output Level 6 7 TIMER_CTL_TASTALL GPTM Timer A Stall Enable 1 2 TIMER_CTL_TBEN GPTM Timer B Enable 8 9 TIMER_CTL_TBEVENT GPTM Timer B Event Mode 10 12 TIMER_CTL_TBEVENT_POS Positive edge 0x0 TIMER_CTL_TBEVENT_NEG Negative edge 0x1 TIMER_CTL_TBEVENT_BOTH Both edges 0x3 TIMER_CTL_TBOTE GPTM Timer B Output Trigger Enable 13 14 TIMER_CTL_TBPWML GPTM Timer B PWM Output Level 14 15 TIMER_CTL_TBSTALL GPTM Timer B Stall Enable 9 10 TIMER0DMAEV GPTM DMA Event 0x6C read-write n 0x0 0x0 TIMER_DMAEV_CAEDMAEN GPTM A Capture Event DMA Trigger Enable 2 3 TIMER_DMAEV_CAMDMAEN GPTM A Capture Match Event DMA Trigger Enable 1 2 TIMER_DMAEV_CBEDMAEN GPTM B Capture Event DMA Trigger Enable 10 11 TIMER_DMAEV_CBMDMAEN GPTM B Capture Match Event DMA Trigger Enable 9 10 TIMER_DMAEV_RTCDMAEN GPTM A RTC Match Event DMA Trigger Enable 3 4 TIMER_DMAEV_TAMDMAEN GPTM A Mode Match Event DMA Trigger Enable 4 5 TIMER_DMAEV_TATODMAEN GPTM A Time-Out Event DMA Trigger Enable 0 1 TIMER_DMAEV_TBMDMAEN GPTM B Mode Match Event DMA Trigger Enable 11 12 TIMER_DMAEV_TBTODMAEN GPTM B Time-Out Event DMA Trigger Enable 8 9 TIMER0ICR GPTM Interrupt Clear 0x24 write-only n 0x0 0x0 TIMER_ICR_CAECINT GPTM Timer A Capture Mode Event Interrupt Clear 2 3 write-only TIMER_ICR_CAMCINT GPTM Timer A Capture Mode Match Interrupt Clear 1 2 write-only TIMER_ICR_CBECINT GPTM Timer B Capture Mode Event Interrupt Clear 10 11 write-only TIMER_ICR_CBMCINT GPTM Timer B Capture Mode Match Interrupt Clear 9 10 write-only TIMER_ICR_DMAAINT GPTM Timer A DMA Done Interrupt Clear 5 6 write-only TIMER_ICR_DMABINT GPTM Timer B DMA Done Interrupt Clear 13 14 write-only TIMER_ICR_RTCCINT GPTM RTC Interrupt Clear 3 4 write-only TIMER_ICR_TAMCINT GPTM Timer A Match Interrupt Clear 4 5 write-only TIMER_ICR_TATOCINT GPTM Timer A Time-Out Raw Interrupt 0 1 write-only TIMER_ICR_TBMCINT GPTM Timer B Match Interrupt Clear 11 12 write-only TIMER_ICR_TBTOCINT GPTM Timer B Time-Out Interrupt Clear 8 9 write-only TIMER0IMR GPTM Interrupt Mask 0x18 read-write n 0x0 0x0 TIMER_IMR_CAEIM GPTM Timer A Capture Mode Event Interrupt Mask 2 3 TIMER_IMR_CAMIM GPTM Timer A Capture Mode Match Interrupt Mask 1 2 TIMER_IMR_CBEIM GPTM Timer B Capture Mode Event Interrupt Mask 10 11 TIMER_IMR_CBMIM GPTM Timer B Capture Mode Match Interrupt Mask 9 10 TIMER_IMR_DMAAIM GPTM Timer A DMA Done Interrupt Mask 5 6 TIMER_IMR_DMABIM GPTM Timer B DMA Done Interrupt Mask 13 14 TIMER_IMR_RTCIM GPTM RTC Interrupt Mask 3 4 TIMER_IMR_TAMIM GPTM Timer A Match Interrupt Mask 4 5 TIMER_IMR_TATOIM GPTM Timer A Time-Out Interrupt Mask 0 1 TIMER_IMR_TBMIM GPTM Timer B Match Interrupt Mask 11 12 TIMER_IMR_TBTOIM GPTM Timer B Time-Out Interrupt Mask 8 9 TIMER0MIS GPTM Masked Interrupt Status 0x20 read-write n 0x0 0x0 TIMER_MIS_CAEMIS GPTM Timer A Capture Mode Event Masked Interrupt 2 3 TIMER_MIS_CAMMIS GPTM Timer A Capture Mode Match Masked Interrupt 1 2 TIMER_MIS_CBEMIS GPTM Timer B Capture Mode Event Masked Interrupt 10 11 TIMER_MIS_CBMMIS GPTM Timer B Capture Mode Match Masked Interrupt 9 10 TIMER_MIS_DMAAMIS GPTM Timer A DMA Done Masked Interrupt 5 6 TIMER_MIS_DMABMIS GPTM Timer B DMA Done Masked Interrupt 13 14 TIMER_MIS_RTCMIS GPTM RTC Masked Interrupt 3 4 TIMER_MIS_TAMMIS GPTM Timer A Match Masked Interrupt 4 5 TIMER_MIS_TATOMIS GPTM Timer A Time-Out Masked Interrupt 0 1 TIMER_MIS_TBMMIS GPTM Timer B Match Masked Interrupt 11 12 TIMER_MIS_TBTOMIS GPTM Timer B Time-Out Masked Interrupt 8 9 TIMER0PP GPTM Peripheral Properties 0xFC0 read-write n 0x0 0x0 TIMER_PP_ALTCLK Alternate Clock Source 6 7 TIMER_PP_CHAIN Chain with Other Timers 4 5 TIMER_PP_SIZE Count Size 0 4 TIMER_PP_SIZE_16 Timer A and Timer B counters are 16 bits each with an 8-bit prescale counter 0x0 TIMER_PP_SIZE_32 Timer A and Timer B counters are 32 bits each with a 16-bit prescale counter 0x1 TIMER_PP_SYNCCNT Synchronize Start 5 6 TIMER0RIS GPTM Raw Interrupt Status 0x1C read-write n 0x0 0x0 TIMER_RIS_CAERIS GPTM Timer A Capture Mode Event Raw Interrupt 2 3 TIMER_RIS_CAMRIS GPTM Timer A Capture Mode Match Raw Interrupt 1 2 TIMER_RIS_CBERIS GPTM Timer B Capture Mode Event Raw Interrupt 10 11 TIMER_RIS_CBMRIS GPTM Timer B Capture Mode Match Raw Interrupt 9 10 TIMER_RIS_DMAARIS GPTM Timer A DMA Done Raw Interrupt Status 5 6 TIMER_RIS_DMABRIS GPTM Timer B DMA Done Raw Interrupt Status 13 14 TIMER_RIS_RTCRIS GPTM RTC Raw Interrupt 3 4 TIMER_RIS_TAMRIS GPTM Timer A Match Raw Interrupt 4 5 TIMER_RIS_TATORIS GPTM Timer A Time-Out Raw Interrupt 0 1 TIMER_RIS_TBMRIS GPTM Timer B Match Raw Interrupt 11 12 TIMER_RIS_TBTORIS GPTM Timer B Time-Out Raw Interrupt 8 9 TIMER0RTCPD GPTM RTC Predivide 0x58 read-write n 0x0 0x0 TIMER_RTCPD_RTCPD RTC Predivide Counter Value 0 16 TIMER0SYNC GPTM Synchronize 0x10 read-write n 0x0 0x0 TIMER_SYNC_SYNCT0 Synchronize GPTM Timer 0 0 2 TIMER_SYNC_SYNCT0_NONE GPTM0 is not affected 0x0 TIMER_SYNC_SYNCT0_TA A timeout event for Timer A of GPTM0 is triggered 0x1 TIMER_SYNC_SYNCT0_TB A timeout event for Timer B of GPTM0 is triggered 0x2 TIMER_SYNC_SYNCT0_TATB A timeout event for both Timer A and Timer B of GPTM0 is triggered 0x3 TIMER_SYNC_SYNCT1 Synchronize GPTM Timer 1 2 4 TIMER_SYNC_SYNCT1_NONE GPTM1 is not affected 0x0 TIMER_SYNC_SYNCT1_TA A timeout event for Timer A of GPTM1 is triggered 0x1 TIMER_SYNC_SYNCT1_TB A timeout event for Timer B of GPTM1 is triggered 0x2 TIMER_SYNC_SYNCT1_TATB A timeout event for both Timer A and Timer B of GPTM1 is triggered 0x3 TIMER_SYNC_SYNCT2 Synchronize GPTM Timer 2 4 6 TIMER_SYNC_SYNCT2_NONE GPTM2 is not affected 0x0 TIMER_SYNC_SYNCT2_TA A timeout event for Timer A of GPTM2 is triggered 0x1 TIMER_SYNC_SYNCT2_TB A timeout event for Timer B of GPTM2 is triggered 0x2 TIMER_SYNC_SYNCT2_TATB A timeout event for both Timer A and Timer B of GPTM2 is triggered 0x3 TIMER_SYNC_SYNCT3 Synchronize GPTM Timer 3 6 8 TIMER_SYNC_SYNCT3_NONE GPTM3 is not affected 0x0 TIMER_SYNC_SYNCT3_TA A timeout event for Timer A of GPTM3 is triggered 0x1 TIMER_SYNC_SYNCT3_TB A timeout event for Timer B of GPTM3 is triggered 0x2 TIMER_SYNC_SYNCT3_TATB A timeout event for both Timer A and Timer B of GPTM3 is triggered 0x3 TIMER_SYNC_SYNCT4 Synchronize GPTM Timer 4 8 10 TIMER_SYNC_SYNCT4_NONE GPTM4 is not affected 0x0 TIMER_SYNC_SYNCT4_TA A timeout event for Timer A of GPTM4 is triggered 0x1 TIMER_SYNC_SYNCT4_TB A timeout event for Timer B of GPTM4 is triggered 0x2 TIMER_SYNC_SYNCT4_TATB A timeout event for both Timer A and Timer B of GPTM4 is triggered 0x3 TIMER_SYNC_SYNCT5 Synchronize GPTM Timer 5 10 12 TIMER_SYNC_SYNCT5_NONE GPTM5 is not affected 0x0 TIMER_SYNC_SYNCT5_TA A timeout event for Timer A of GPTM5 is triggered 0x1 TIMER_SYNC_SYNCT5_TB A timeout event for Timer B of GPTM5 is triggered 0x2 TIMER_SYNC_SYNCT5_TATB A timeout event for both Timer A and Timer B of GPTM5 is triggered 0x3 TIMER_SYNC_SYNCT6 Synchronize GPTM Timer 6 12 14 TIMER_SYNC_SYNCT6_NONE GPTM6 is not affected 0x0 TIMER_SYNC_SYNCT6_TA A timeout event for Timer A of GPTM6 is triggered 0x1 TIMER_SYNC_SYNCT6_TB A timeout event for Timer B of GPTM6 is triggered 0x2 TIMER_SYNC_SYNCT6_TATB A timeout event for both Timer A and Timer B of GPTM6 is triggered 0x3 TIMER_SYNC_SYNCT7 Synchronize GPTM Timer 7 14 16 TIMER_SYNC_SYNCT7_NONE GPT7 is not affected 0x0 TIMER_SYNC_SYNCT7_TA A timeout event for Timer A of GPTM7 is triggered 0x1 TIMER_SYNC_SYNCT7_TB A timeout event for Timer B of GPTM7 is triggered 0x2 TIMER_SYNC_SYNCT7_TATB A timeout event for both Timer A and Timer B of GPTM7 is triggered 0x3 TIMER0TAILR GPTM Timer A Interval Load 0x28 read-write n 0x0 0x0 TIMER0TAMATCHR GPTM Timer A Match 0x30 read-write n 0x0 0x0 TIMER0TAMR GPTM Timer A Mode 0x4 read-write n 0x0 0x0 TIMER_TAMR_TAAMS GPTM Timer A Alternate Mode Select 3 4 TIMER_TAMR_TACDIR GPTM Timer A Count Direction 4 5 TIMER_TAMR_TACINTD One-shot/Periodic Interrupt Disable 12 13 TIMER_TAMR_TACMR GPTM Timer A Capture Mode 2 3 TIMER_TAMR_TAILD GPTM Timer A Interval Load Write 8 9 TIMER_TAMR_TAMIE GPTM Timer A Match Interrupt Enable 5 6 TIMER_TAMR_TAMR GPTM Timer A Mode 0 2 TIMER_TAMR_TAMR_1_SHOT One-Shot Timer mode 0x1 TIMER_TAMR_TAMR_PERIOD Periodic Timer mode 0x2 TIMER_TAMR_TAMR_CAP Capture mode 0x3 TIMER_TAMR_TAMRSU GPTM Timer A Match Register Update 10 11 TIMER_TAMR_TAPLO GPTM Timer A PWM Legacy Operation 11 12 TIMER_TAMR_TAPWMIE GPTM Timer A PWM Interrupt Enable 9 10 TIMER_TAMR_TASNAPS GPTM Timer A Snap-Shot Mode 7 8 TIMER_TAMR_TAWOT GPTM Timer A Wait-on-Trigger 6 7 TIMER_TAMR_TCACT Timer Compare Action Select 13 16 TIMER_TAMR_TCACT_NONE Disable compare operations 0x0 TIMER_TAMR_TCACT_TOGGLE Toggle State on Time-Out 0x1 TIMER_TAMR_TCACT_CLRTO Clear CCP on Time-Out 0x2 TIMER_TAMR_TCACT_SETTO Set CCP on Time-Out 0x3 TIMER_TAMR_TCACT_SETTOGTO Set CCP immediately and toggle on Time-Out 0x4 TIMER_TAMR_TCACT_CLRTOGTO Clear CCP immediately and toggle on Time-Out 0x5 TIMER_TAMR_TCACT_SETCLRTO Set CCP immediately and clear on Time-Out 0x6 TIMER_TAMR_TCACT_CLRSETTO Clear CCP immediately and set on Time-Out 0x7 TIMER0TAPMR GPTM TimerA Prescale Match 0x40 read-write n 0x0 0x0 TIMER_TAPMR_TAPSMR GPTM TimerA Prescale Match 0 8 TIMER0TAPR GPTM Timer A Prescale 0x38 read-write n 0x0 0x0 TIMER_TAPR_TAPSR GPTM Timer A Prescale 0 8 TIMER0TAPS GPTM Timer A Prescale Snapshot 0x5C read-write n 0x0 0x0 TIMER_TAPS_PSS GPTM Timer A Prescaler Snapshot 0 16 TIMER0TAR GPTM Timer A 0x48 read-write n 0x0 0x0 TIMER0TAV GPTM Timer A Value 0x50 read-write n 0x0 0x0 TIMER0TBILR GPTM Timer B Interval Load 0x2C read-write n 0x0 0x0 TIMER0TBMATCHR GPTM Timer B Match 0x34 read-write n 0x0 0x0 TIMER0TBMR GPTM Timer B Mode 0x8 read-write n 0x0 0x0 TIMER_TBMR_TBAMS GPTM Timer B Alternate Mode Select 3 4 TIMER_TBMR_TBCDIR GPTM Timer B Count Direction 4 5 TIMER_TBMR_TBCINTD One-Shot/Periodic Interrupt Disable 12 13 TIMER_TBMR_TBCMR GPTM Timer B Capture Mode 2 3 TIMER_TBMR_TBILD GPTM Timer B Interval Load Write 8 9 TIMER_TBMR_TBMIE GPTM Timer B Match Interrupt Enable 5 6 TIMER_TBMR_TBMR GPTM Timer B Mode 0 2 TIMER_TBMR_TBMR_1_SHOT One-Shot Timer mode 0x1 TIMER_TBMR_TBMR_PERIOD Periodic Timer mode 0x2 TIMER_TBMR_TBMR_CAP Capture mode 0x3 TIMER_TBMR_TBMRSU GPTM Timer B Match Register Update 10 11 TIMER_TBMR_TBPLO GPTM Timer B PWM Legacy Operation 11 12 TIMER_TBMR_TBPWMIE GPTM Timer B PWM Interrupt Enable 9 10 TIMER_TBMR_TBSNAPS GPTM Timer B Snap-Shot Mode 7 8 TIMER_TBMR_TBWOT GPTM Timer B Wait-on-Trigger 6 7 TIMER_TBMR_TCACT Timer Compare Action Select 13 16 TIMER_TBMR_TCACT_NONE Disable compare operations 0x0 TIMER_TBMR_TCACT_TOGGLE Toggle State on Time-Out 0x1 TIMER_TBMR_TCACT_CLRTO Clear CCP on Time-Out 0x2 TIMER_TBMR_TCACT_SETTO Set CCP on Time-Out 0x3 TIMER_TBMR_TCACT_SETTOGTO Set CCP immediately and toggle on Time-Out 0x4 TIMER_TBMR_TCACT_CLRTOGTO Clear CCP immediately and toggle on Time-Out 0x5 TIMER_TBMR_TCACT_SETCLRTO Set CCP immediately and clear on Time-Out 0x6 TIMER_TBMR_TCACT_CLRSETTO Clear CCP immediately and set on Time-Out 0x7 TIMER0TBPMR GPTM TimerB Prescale Match 0x44 read-write n 0x0 0x0 TIMER_TBPMR_TBPSMR GPTM TimerB Prescale Match 0 8 TIMER0TBPR GPTM Timer B Prescale 0x3C read-write n 0x0 0x0 TIMER_TBPR_TBPSR GPTM Timer B Prescale 0 8 TIMER0TBPS GPTM Timer B Prescale Snapshot 0x60 read-write n 0x0 0x0 TIMER_TBPS_PSS GPTM Timer A Prescaler Value 0 16 TIMER0TBR GPTM Timer B 0x4C read-write n 0x0 0x0 TIMER0TBV GPTM Timer B Value 0x54 read-write n 0x0 0x0 TIMER1 Register map for TIMER0 peripheral TIMER 0x0 0x0 0x1000 registers n TIMER1A 21 TIMER1B 22 ADCEV GPTM ADC Event 0x70 -1 read-write n 0x0 0x0 TIMER_ADCEV_CAEADCEN GPTM A Capture Event ADC Trigger Enable 2 3 TIMER_ADCEV_CAMADCEN GPTM A Capture Match Event ADC Trigger Enable 1 2 TIMER_ADCEV_CBEADCEN GPTM B Capture Event ADC Trigger Enable 10 11 TIMER_ADCEV_CBMADCEN GPTM B Capture Match Event ADC Trigger Enable 9 10 TIMER_ADCEV_RTCADCEN GPTM RTC Match Event ADC Trigger Enable 3 4 TIMER_ADCEV_TAMADCEN GPTM A Mode Match Event ADC Trigger Enable 4 5 TIMER_ADCEV_TATOADCEN GPTM A Time-Out Event ADC Trigger Enable 0 1 TIMER_ADCEV_TBMADCEN GPTM B Mode Match Event ADC Trigger Enable 11 12 TIMER_ADCEV_TBTOADCEN GPTM B Time-Out Event ADC Trigger Enable 8 9 CC GPTM Clock Configuration 0xFC8 -1 read-write n 0x0 0x0 TIMER_CC_ALTCLK Alternate Clock Source 0 1 CFG GPTM Configuration 0x0 -1 read-write n 0x0 0x0 TIMER_CFG GPTM Configuration 0 3 TIMER_CFG_32_BIT_TIMER For a 16/32-bit timer, this value selects the 32-bit timer configuration 0x0 TIMER_CFG_32_BIT_RTC For a 16/32-bit timer, this value selects the 32-bit real-time clock (RTC) counter configuration 0x1 TIMER_CFG_16_BIT For a 16/32-bit timer, this value selects the 16-bit timer configuration 0x4 CTL GPTM Control 0xC -1 read-write n 0x0 0x0 TIMER_CTL_RTCEN GPTM RTC Stall Enable 4 5 TIMER_CTL_TAEN GPTM Timer A Enable 0 1 TIMER_CTL_TAEVENT GPTM Timer A Event Mode 2 4 TIMER_CTL_TAEVENT_POS Positive edge 0x0 TIMER_CTL_TAEVENT_NEG Negative edge 0x1 TIMER_CTL_TAEVENT_BOTH Both edges 0x3 TIMER_CTL_TAOTE GPTM Timer A Output Trigger Enable 5 6 TIMER_CTL_TAPWML GPTM Timer A PWM Output Level 6 7 TIMER_CTL_TASTALL GPTM Timer A Stall Enable 1 2 TIMER_CTL_TBEN GPTM Timer B Enable 8 9 TIMER_CTL_TBEVENT GPTM Timer B Event Mode 10 12 TIMER_CTL_TBEVENT_POS Positive edge 0x0 TIMER_CTL_TBEVENT_NEG Negative edge 0x1 TIMER_CTL_TBEVENT_BOTH Both edges 0x3 TIMER_CTL_TBOTE GPTM Timer B Output Trigger Enable 13 14 TIMER_CTL_TBPWML GPTM Timer B PWM Output Level 14 15 TIMER_CTL_TBSTALL GPTM Timer B Stall Enable 9 10 DMAEV GPTM DMA Event 0x6C -1 read-write n 0x0 0x0 TIMER_DMAEV_CAEDMAEN GPTM A Capture Event DMA Trigger Enable 2 3 TIMER_DMAEV_CAMDMAEN GPTM A Capture Match Event DMA Trigger Enable 1 2 TIMER_DMAEV_CBEDMAEN GPTM B Capture Event DMA Trigger Enable 10 11 TIMER_DMAEV_CBMDMAEN GPTM B Capture Match Event DMA Trigger Enable 9 10 TIMER_DMAEV_RTCDMAEN GPTM A RTC Match Event DMA Trigger Enable 3 4 TIMER_DMAEV_TAMDMAEN GPTM A Mode Match Event DMA Trigger Enable 4 5 TIMER_DMAEV_TATODMAEN GPTM A Time-Out Event DMA Trigger Enable 0 1 TIMER_DMAEV_TBMDMAEN GPTM B Mode Match Event DMA Trigger Enable 11 12 TIMER_DMAEV_TBTODMAEN GPTM B Time-Out Event DMA Trigger Enable 8 9 ICR GPTM Interrupt Clear 0x24 -1 write-only n 0x0 0x0 TIMER_ICR_CAECINT GPTM Timer A Capture Mode Event Interrupt Clear 2 3 write-only TIMER_ICR_CAMCINT GPTM Timer A Capture Mode Match Interrupt Clear 1 2 write-only TIMER_ICR_CBECINT GPTM Timer B Capture Mode Event Interrupt Clear 10 11 write-only TIMER_ICR_CBMCINT GPTM Timer B Capture Mode Match Interrupt Clear 9 10 write-only TIMER_ICR_DMAAINT GPTM Timer A DMA Done Interrupt Clear 5 6 write-only TIMER_ICR_DMABINT GPTM Timer B DMA Done Interrupt Clear 13 14 write-only TIMER_ICR_RTCCINT GPTM RTC Interrupt Clear 3 4 write-only TIMER_ICR_TAMCINT GPTM Timer A Match Interrupt Clear 4 5 write-only TIMER_ICR_TATOCINT GPTM Timer A Time-Out Raw Interrupt 0 1 write-only TIMER_ICR_TBMCINT GPTM Timer B Match Interrupt Clear 11 12 write-only TIMER_ICR_TBTOCINT GPTM Timer B Time-Out Interrupt Clear 8 9 write-only IMR GPTM Interrupt Mask 0x18 -1 read-write n 0x0 0x0 TIMER_IMR_CAEIM GPTM Timer A Capture Mode Event Interrupt Mask 2 3 TIMER_IMR_CAMIM GPTM Timer A Capture Mode Match Interrupt Mask 1 2 TIMER_IMR_CBEIM GPTM Timer B Capture Mode Event Interrupt Mask 10 11 TIMER_IMR_CBMIM GPTM Timer B Capture Mode Match Interrupt Mask 9 10 TIMER_IMR_DMAAIM GPTM Timer A DMA Done Interrupt Mask 5 6 TIMER_IMR_DMABIM GPTM Timer B DMA Done Interrupt Mask 13 14 TIMER_IMR_RTCIM GPTM RTC Interrupt Mask 3 4 TIMER_IMR_TAMIM GPTM Timer A Match Interrupt Mask 4 5 TIMER_IMR_TATOIM GPTM Timer A Time-Out Interrupt Mask 0 1 TIMER_IMR_TBMIM GPTM Timer B Match Interrupt Mask 11 12 TIMER_IMR_TBTOIM GPTM Timer B Time-Out Interrupt Mask 8 9 MIS GPTM Masked Interrupt Status 0x20 -1 read-write n 0x0 0x0 TIMER_MIS_CAEMIS GPTM Timer A Capture Mode Event Masked Interrupt 2 3 TIMER_MIS_CAMMIS GPTM Timer A Capture Mode Match Masked Interrupt 1 2 TIMER_MIS_CBEMIS GPTM Timer B Capture Mode Event Masked Interrupt 10 11 TIMER_MIS_CBMMIS GPTM Timer B Capture Mode Match Masked Interrupt 9 10 TIMER_MIS_DMAAMIS GPTM Timer A DMA Done Masked Interrupt 5 6 TIMER_MIS_DMABMIS GPTM Timer B DMA Done Masked Interrupt 13 14 TIMER_MIS_RTCMIS GPTM RTC Masked Interrupt 3 4 TIMER_MIS_TAMMIS GPTM Timer A Match Masked Interrupt 4 5 TIMER_MIS_TATOMIS GPTM Timer A Time-Out Masked Interrupt 0 1 TIMER_MIS_TBMMIS GPTM Timer B Match Masked Interrupt 11 12 TIMER_MIS_TBTOMIS GPTM Timer B Time-Out Masked Interrupt 8 9 PP GPTM Peripheral Properties 0xFC0 -1 read-write n 0x0 0x0 TIMER_PP_ALTCLK Alternate Clock Source 6 7 TIMER_PP_CHAIN Chain with Other Timers 4 5 TIMER_PP_SIZE Count Size 0 4 TIMER_PP_SIZE_16 Timer A and Timer B counters are 16 bits each with an 8-bit prescale counter 0x0 TIMER_PP_SIZE_32 Timer A and Timer B counters are 32 bits each with a 16-bit prescale counter 0x1 TIMER_PP_SYNCCNT Synchronize Start 5 6 RIS GPTM Raw Interrupt Status 0x1C -1 read-write n 0x0 0x0 TIMER_RIS_CAERIS GPTM Timer A Capture Mode Event Raw Interrupt 2 3 TIMER_RIS_CAMRIS GPTM Timer A Capture Mode Match Raw Interrupt 1 2 TIMER_RIS_CBERIS GPTM Timer B Capture Mode Event Raw Interrupt 10 11 TIMER_RIS_CBMRIS GPTM Timer B Capture Mode Match Raw Interrupt 9 10 TIMER_RIS_DMAARIS GPTM Timer A DMA Done Raw Interrupt Status 5 6 TIMER_RIS_DMABRIS GPTM Timer B DMA Done Raw Interrupt Status 13 14 TIMER_RIS_RTCRIS GPTM RTC Raw Interrupt 3 4 TIMER_RIS_TAMRIS GPTM Timer A Match Raw Interrupt 4 5 TIMER_RIS_TATORIS GPTM Timer A Time-Out Raw Interrupt 0 1 TIMER_RIS_TBMRIS GPTM Timer B Match Raw Interrupt 11 12 TIMER_RIS_TBTORIS GPTM Timer B Time-Out Raw Interrupt 8 9 RTCPD GPTM RTC Predivide 0x58 -1 read-write n 0x0 0x0 TIMER_RTCPD_RTCPD RTC Predivide Counter Value 0 16 SYNC GPTM Synchronize 0x10 -1 read-write n 0x0 0x0 TIMER_SYNC_SYNCT0 Synchronize GPTM Timer 0 0 2 TIMER_SYNC_SYNCT0_NONE GPTM0 is not affected 0x0 TIMER_SYNC_SYNCT0_TA A timeout event for Timer A of GPTM0 is triggered 0x1 TIMER_SYNC_SYNCT0_TB A timeout event for Timer B of GPTM0 is triggered 0x2 TIMER_SYNC_SYNCT0_TATB A timeout event for both Timer A and Timer B of GPTM0 is triggered 0x3 TIMER_SYNC_SYNCT1 Synchronize GPTM Timer 1 2 4 TIMER_SYNC_SYNCT1_NONE GPTM1 is not affected 0x0 TIMER_SYNC_SYNCT1_TA A timeout event for Timer A of GPTM1 is triggered 0x1 TIMER_SYNC_SYNCT1_TB A timeout event for Timer B of GPTM1 is triggered 0x2 TIMER_SYNC_SYNCT1_TATB A timeout event for both Timer A and Timer B of GPTM1 is triggered 0x3 TIMER_SYNC_SYNCT2 Synchronize GPTM Timer 2 4 6 TIMER_SYNC_SYNCT2_NONE GPTM2 is not affected 0x0 TIMER_SYNC_SYNCT2_TA A timeout event for Timer A of GPTM2 is triggered 0x1 TIMER_SYNC_SYNCT2_TB A timeout event for Timer B of GPTM2 is triggered 0x2 TIMER_SYNC_SYNCT2_TATB A timeout event for both Timer A and Timer B of GPTM2 is triggered 0x3 TIMER_SYNC_SYNCT3 Synchronize GPTM Timer 3 6 8 TIMER_SYNC_SYNCT3_NONE GPTM3 is not affected 0x0 TIMER_SYNC_SYNCT3_TA A timeout event for Timer A of GPTM3 is triggered 0x1 TIMER_SYNC_SYNCT3_TB A timeout event for Timer B of GPTM3 is triggered 0x2 TIMER_SYNC_SYNCT3_TATB A timeout event for both Timer A and Timer B of GPTM3 is triggered 0x3 TIMER_SYNC_SYNCT4 Synchronize GPTM Timer 4 8 10 TIMER_SYNC_SYNCT4_NONE GPTM4 is not affected 0x0 TIMER_SYNC_SYNCT4_TA A timeout event for Timer A of GPTM4 is triggered 0x1 TIMER_SYNC_SYNCT4_TB A timeout event for Timer B of GPTM4 is triggered 0x2 TIMER_SYNC_SYNCT4_TATB A timeout event for both Timer A and Timer B of GPTM4 is triggered 0x3 TIMER_SYNC_SYNCT5 Synchronize GPTM Timer 5 10 12 TIMER_SYNC_SYNCT5_NONE GPTM5 is not affected 0x0 TIMER_SYNC_SYNCT5_TA A timeout event for Timer A of GPTM5 is triggered 0x1 TIMER_SYNC_SYNCT5_TB A timeout event for Timer B of GPTM5 is triggered 0x2 TIMER_SYNC_SYNCT5_TATB A timeout event for both Timer A and Timer B of GPTM5 is triggered 0x3 TIMER_SYNC_SYNCT6 Synchronize GPTM Timer 6 12 14 TIMER_SYNC_SYNCT6_NONE GPTM6 is not affected 0x0 TIMER_SYNC_SYNCT6_TA A timeout event for Timer A of GPTM6 is triggered 0x1 TIMER_SYNC_SYNCT6_TB A timeout event for Timer B of GPTM6 is triggered 0x2 TIMER_SYNC_SYNCT6_TATB A timeout event for both Timer A and Timer B of GPTM6 is triggered 0x3 TIMER_SYNC_SYNCT7 Synchronize GPTM Timer 7 14 16 TIMER_SYNC_SYNCT7_NONE GPT7 is not affected 0x0 TIMER_SYNC_SYNCT7_TA A timeout event for Timer A of GPTM7 is triggered 0x1 TIMER_SYNC_SYNCT7_TB A timeout event for Timer B of GPTM7 is triggered 0x2 TIMER_SYNC_SYNCT7_TATB A timeout event for both Timer A and Timer B of GPTM7 is triggered 0x3 TAILR GPTM Timer A Interval Load 0x28 -1 read-write n 0x0 0x0 TAMATCHR GPTM Timer A Match 0x30 -1 read-write n 0x0 0x0 TAMR GPTM Timer A Mode 0x4 -1 read-write n 0x0 0x0 TIMER_TAMR_TAAMS GPTM Timer A Alternate Mode Select 3 4 TIMER_TAMR_TACDIR GPTM Timer A Count Direction 4 5 TIMER_TAMR_TACINTD One-shot/Periodic Interrupt Disable 12 13 TIMER_TAMR_TACMR GPTM Timer A Capture Mode 2 3 TIMER_TAMR_TAILD GPTM Timer A Interval Load Write 8 9 TIMER_TAMR_TAMIE GPTM Timer A Match Interrupt Enable 5 6 TIMER_TAMR_TAMR GPTM Timer A Mode 0 2 TIMER_TAMR_TAMR_1_SHOT One-Shot Timer mode 0x1 TIMER_TAMR_TAMR_PERIOD Periodic Timer mode 0x2 TIMER_TAMR_TAMR_CAP Capture mode 0x3 TIMER_TAMR_TAMRSU GPTM Timer A Match Register Update 10 11 TIMER_TAMR_TAPLO GPTM Timer A PWM Legacy Operation 11 12 TIMER_TAMR_TAPWMIE GPTM Timer A PWM Interrupt Enable 9 10 TIMER_TAMR_TASNAPS GPTM Timer A Snap-Shot Mode 7 8 TIMER_TAMR_TAWOT GPTM Timer A Wait-on-Trigger 6 7 TIMER_TAMR_TCACT Timer Compare Action Select 13 16 TIMER_TAMR_TCACT_NONE Disable compare operations 0x0 TIMER_TAMR_TCACT_TOGGLE Toggle State on Time-Out 0x1 TIMER_TAMR_TCACT_CLRTO Clear CCP on Time-Out 0x2 TIMER_TAMR_TCACT_SETTO Set CCP on Time-Out 0x3 TIMER_TAMR_TCACT_SETTOGTO Set CCP immediately and toggle on Time-Out 0x4 TIMER_TAMR_TCACT_CLRTOGTO Clear CCP immediately and toggle on Time-Out 0x5 TIMER_TAMR_TCACT_SETCLRTO Set CCP immediately and clear on Time-Out 0x6 TIMER_TAMR_TCACT_CLRSETTO Clear CCP immediately and set on Time-Out 0x7 TAPMR GPTM TimerA Prescale Match 0x40 -1 read-write n 0x0 0x0 TIMER_TAPMR_TAPSMR GPTM TimerA Prescale Match 0 8 TAPR GPTM Timer A Prescale 0x38 -1 read-write n 0x0 0x0 TIMER_TAPR_TAPSR GPTM Timer A Prescale 0 8 TAPS GPTM Timer A Prescale Snapshot 0x5C -1 read-write n 0x0 0x0 TIMER_TAPS_PSS GPTM Timer A Prescaler Snapshot 0 16 TAR GPTM Timer A 0x48 -1 read-write n 0x0 0x0 TAV GPTM Timer A Value 0x50 -1 read-write n 0x0 0x0 TBILR GPTM Timer B Interval Load 0x2C -1 read-write n 0x0 0x0 TBMATCHR GPTM Timer B Match 0x34 -1 read-write n 0x0 0x0 TBMR GPTM Timer B Mode 0x8 -1 read-write n 0x0 0x0 TIMER_TBMR_TBAMS GPTM Timer B Alternate Mode Select 3 4 TIMER_TBMR_TBCDIR GPTM Timer B Count Direction 4 5 TIMER_TBMR_TBCINTD One-Shot/Periodic Interrupt Disable 12 13 TIMER_TBMR_TBCMR GPTM Timer B Capture Mode 2 3 TIMER_TBMR_TBILD GPTM Timer B Interval Load Write 8 9 TIMER_TBMR_TBMIE GPTM Timer B Match Interrupt Enable 5 6 TIMER_TBMR_TBMR GPTM Timer B Mode 0 2 TIMER_TBMR_TBMR_1_SHOT One-Shot Timer mode 0x1 TIMER_TBMR_TBMR_PERIOD Periodic Timer mode 0x2 TIMER_TBMR_TBMR_CAP Capture mode 0x3 TIMER_TBMR_TBMRSU GPTM Timer B Match Register Update 10 11 TIMER_TBMR_TBPLO GPTM Timer B PWM Legacy Operation 11 12 TIMER_TBMR_TBPWMIE GPTM Timer B PWM Interrupt Enable 9 10 TIMER_TBMR_TBSNAPS GPTM Timer B Snap-Shot Mode 7 8 TIMER_TBMR_TBWOT GPTM Timer B Wait-on-Trigger 6 7 TIMER_TBMR_TCACT Timer Compare Action Select 13 16 TIMER_TBMR_TCACT_NONE Disable compare operations 0x0 TIMER_TBMR_TCACT_TOGGLE Toggle State on Time-Out 0x1 TIMER_TBMR_TCACT_CLRTO Clear CCP on Time-Out 0x2 TIMER_TBMR_TCACT_SETTO Set CCP on Time-Out 0x3 TIMER_TBMR_TCACT_SETTOGTO Set CCP immediately and toggle on Time-Out 0x4 TIMER_TBMR_TCACT_CLRTOGTO Clear CCP immediately and toggle on Time-Out 0x5 TIMER_TBMR_TCACT_SETCLRTO Set CCP immediately and clear on Time-Out 0x6 TIMER_TBMR_TCACT_CLRSETTO Clear CCP immediately and set on Time-Out 0x7 TBPMR GPTM TimerB Prescale Match 0x44 -1 read-write n 0x0 0x0 TIMER_TBPMR_TBPSMR GPTM TimerB Prescale Match 0 8 TBPR GPTM Timer B Prescale 0x3C -1 read-write n 0x0 0x0 TIMER_TBPR_TBPSR GPTM Timer B Prescale 0 8 TBPS GPTM Timer B Prescale Snapshot 0x60 -1 read-write n 0x0 0x0 TIMER_TBPS_PSS GPTM Timer A Prescaler Value 0 16 TBR GPTM Timer B 0x4C -1 read-write n 0x0 0x0 TBV GPTM Timer B Value 0x54 -1 read-write n 0x0 0x0 TIMER0ADCEV GPTM ADC Event 0x70 read-write n 0x0 0x0 TIMER_ADCEV_CAEADCEN GPTM A Capture Event ADC Trigger Enable 2 3 TIMER_ADCEV_CAMADCEN GPTM A Capture Match Event ADC Trigger Enable 1 2 TIMER_ADCEV_CBEADCEN GPTM B Capture Event ADC Trigger Enable 10 11 TIMER_ADCEV_CBMADCEN GPTM B Capture Match Event ADC Trigger Enable 9 10 TIMER_ADCEV_RTCADCEN GPTM RTC Match Event ADC Trigger Enable 3 4 TIMER_ADCEV_TAMADCEN GPTM A Mode Match Event ADC Trigger Enable 4 5 TIMER_ADCEV_TATOADCEN GPTM A Time-Out Event ADC Trigger Enable 0 1 TIMER_ADCEV_TBMADCEN GPTM B Mode Match Event ADC Trigger Enable 11 12 TIMER_ADCEV_TBTOADCEN GPTM B Time-Out Event ADC Trigger Enable 8 9 TIMER0CC GPTM Clock Configuration 0xFC8 read-write n 0x0 0x0 TIMER_CC_ALTCLK Alternate Clock Source 0 1 TIMER0CFG GPTM Configuration 0x0 read-write n 0x0 0x0 TIMER_CFG GPTM Configuration 0 3 TIMER_CFG_32_BIT_TIMER For a 16/32-bit timer, this value selects the 32-bit timer configuration 0x0 TIMER_CFG_32_BIT_RTC For a 16/32-bit timer, this value selects the 32-bit real-time clock (RTC) counter configuration 0x1 TIMER_CFG_16_BIT For a 16/32-bit timer, this value selects the 16-bit timer configuration 0x4 TIMER0CTL GPTM Control 0xC read-write n 0x0 0x0 TIMER_CTL_RTCEN GPTM RTC Stall Enable 4 5 TIMER_CTL_TAEN GPTM Timer A Enable 0 1 TIMER_CTL_TAEVENT GPTM Timer A Event Mode 2 4 TIMER_CTL_TAEVENT_POS Positive edge 0x0 TIMER_CTL_TAEVENT_NEG Negative edge 0x1 TIMER_CTL_TAEVENT_BOTH Both edges 0x3 TIMER_CTL_TAOTE GPTM Timer A Output Trigger Enable 5 6 TIMER_CTL_TAPWML GPTM Timer A PWM Output Level 6 7 TIMER_CTL_TASTALL GPTM Timer A Stall Enable 1 2 TIMER_CTL_TBEN GPTM Timer B Enable 8 9 TIMER_CTL_TBEVENT GPTM Timer B Event Mode 10 12 TIMER_CTL_TBEVENT_POS Positive edge 0x0 TIMER_CTL_TBEVENT_NEG Negative edge 0x1 TIMER_CTL_TBEVENT_BOTH Both edges 0x3 TIMER_CTL_TBOTE GPTM Timer B Output Trigger Enable 13 14 TIMER_CTL_TBPWML GPTM Timer B PWM Output Level 14 15 TIMER_CTL_TBSTALL GPTM Timer B Stall Enable 9 10 TIMER0DMAEV GPTM DMA Event 0x6C read-write n 0x0 0x0 TIMER_DMAEV_CAEDMAEN GPTM A Capture Event DMA Trigger Enable 2 3 TIMER_DMAEV_CAMDMAEN GPTM A Capture Match Event DMA Trigger Enable 1 2 TIMER_DMAEV_CBEDMAEN GPTM B Capture Event DMA Trigger Enable 10 11 TIMER_DMAEV_CBMDMAEN GPTM B Capture Match Event DMA Trigger Enable 9 10 TIMER_DMAEV_RTCDMAEN GPTM A RTC Match Event DMA Trigger Enable 3 4 TIMER_DMAEV_TAMDMAEN GPTM A Mode Match Event DMA Trigger Enable 4 5 TIMER_DMAEV_TATODMAEN GPTM A Time-Out Event DMA Trigger Enable 0 1 TIMER_DMAEV_TBMDMAEN GPTM B Mode Match Event DMA Trigger Enable 11 12 TIMER_DMAEV_TBTODMAEN GPTM B Time-Out Event DMA Trigger Enable 8 9 TIMER0ICR GPTM Interrupt Clear 0x24 write-only n 0x0 0x0 TIMER_ICR_CAECINT GPTM Timer A Capture Mode Event Interrupt Clear 2 3 write-only TIMER_ICR_CAMCINT GPTM Timer A Capture Mode Match Interrupt Clear 1 2 write-only TIMER_ICR_CBECINT GPTM Timer B Capture Mode Event Interrupt Clear 10 11 write-only TIMER_ICR_CBMCINT GPTM Timer B Capture Mode Match Interrupt Clear 9 10 write-only TIMER_ICR_DMAAINT GPTM Timer A DMA Done Interrupt Clear 5 6 write-only TIMER_ICR_DMABINT GPTM Timer B DMA Done Interrupt Clear 13 14 write-only TIMER_ICR_RTCCINT GPTM RTC Interrupt Clear 3 4 write-only TIMER_ICR_TAMCINT GPTM Timer A Match Interrupt Clear 4 5 write-only TIMER_ICR_TATOCINT GPTM Timer A Time-Out Raw Interrupt 0 1 write-only TIMER_ICR_TBMCINT GPTM Timer B Match Interrupt Clear 11 12 write-only TIMER_ICR_TBTOCINT GPTM Timer B Time-Out Interrupt Clear 8 9 write-only TIMER0IMR GPTM Interrupt Mask 0x18 read-write n 0x0 0x0 TIMER_IMR_CAEIM GPTM Timer A Capture Mode Event Interrupt Mask 2 3 TIMER_IMR_CAMIM GPTM Timer A Capture Mode Match Interrupt Mask 1 2 TIMER_IMR_CBEIM GPTM Timer B Capture Mode Event Interrupt Mask 10 11 TIMER_IMR_CBMIM GPTM Timer B Capture Mode Match Interrupt Mask 9 10 TIMER_IMR_DMAAIM GPTM Timer A DMA Done Interrupt Mask 5 6 TIMER_IMR_DMABIM GPTM Timer B DMA Done Interrupt Mask 13 14 TIMER_IMR_RTCIM GPTM RTC Interrupt Mask 3 4 TIMER_IMR_TAMIM GPTM Timer A Match Interrupt Mask 4 5 TIMER_IMR_TATOIM GPTM Timer A Time-Out Interrupt Mask 0 1 TIMER_IMR_TBMIM GPTM Timer B Match Interrupt Mask 11 12 TIMER_IMR_TBTOIM GPTM Timer B Time-Out Interrupt Mask 8 9 TIMER0MIS GPTM Masked Interrupt Status 0x20 read-write n 0x0 0x0 TIMER_MIS_CAEMIS GPTM Timer A Capture Mode Event Masked Interrupt 2 3 TIMER_MIS_CAMMIS GPTM Timer A Capture Mode Match Masked Interrupt 1 2 TIMER_MIS_CBEMIS GPTM Timer B Capture Mode Event Masked Interrupt 10 11 TIMER_MIS_CBMMIS GPTM Timer B Capture Mode Match Masked Interrupt 9 10 TIMER_MIS_DMAAMIS GPTM Timer A DMA Done Masked Interrupt 5 6 TIMER_MIS_DMABMIS GPTM Timer B DMA Done Masked Interrupt 13 14 TIMER_MIS_RTCMIS GPTM RTC Masked Interrupt 3 4 TIMER_MIS_TAMMIS GPTM Timer A Match Masked Interrupt 4 5 TIMER_MIS_TATOMIS GPTM Timer A Time-Out Masked Interrupt 0 1 TIMER_MIS_TBMMIS GPTM Timer B Match Masked Interrupt 11 12 TIMER_MIS_TBTOMIS GPTM Timer B Time-Out Masked Interrupt 8 9 TIMER0PP GPTM Peripheral Properties 0xFC0 read-write n 0x0 0x0 TIMER_PP_ALTCLK Alternate Clock Source 6 7 TIMER_PP_CHAIN Chain with Other Timers 4 5 TIMER_PP_SIZE Count Size 0 4 TIMER_PP_SIZE_16 Timer A and Timer B counters are 16 bits each with an 8-bit prescale counter 0x0 TIMER_PP_SIZE_32 Timer A and Timer B counters are 32 bits each with a 16-bit prescale counter 0x1 TIMER_PP_SYNCCNT Synchronize Start 5 6 TIMER0RIS GPTM Raw Interrupt Status 0x1C read-write n 0x0 0x0 TIMER_RIS_CAERIS GPTM Timer A Capture Mode Event Raw Interrupt 2 3 TIMER_RIS_CAMRIS GPTM Timer A Capture Mode Match Raw Interrupt 1 2 TIMER_RIS_CBERIS GPTM Timer B Capture Mode Event Raw Interrupt 10 11 TIMER_RIS_CBMRIS GPTM Timer B Capture Mode Match Raw Interrupt 9 10 TIMER_RIS_DMAARIS GPTM Timer A DMA Done Raw Interrupt Status 5 6 TIMER_RIS_DMABRIS GPTM Timer B DMA Done Raw Interrupt Status 13 14 TIMER_RIS_RTCRIS GPTM RTC Raw Interrupt 3 4 TIMER_RIS_TAMRIS GPTM Timer A Match Raw Interrupt 4 5 TIMER_RIS_TATORIS GPTM Timer A Time-Out Raw Interrupt 0 1 TIMER_RIS_TBMRIS GPTM Timer B Match Raw Interrupt 11 12 TIMER_RIS_TBTORIS GPTM Timer B Time-Out Raw Interrupt 8 9 TIMER0RTCPD GPTM RTC Predivide 0x58 read-write n 0x0 0x0 TIMER_RTCPD_RTCPD RTC Predivide Counter Value 0 16 TIMER0SYNC GPTM Synchronize 0x10 read-write n 0x0 0x0 TIMER_SYNC_SYNCT0 Synchronize GPTM Timer 0 0 2 TIMER_SYNC_SYNCT0_NONE GPTM0 is not affected 0x0 TIMER_SYNC_SYNCT0_TA A timeout event for Timer A of GPTM0 is triggered 0x1 TIMER_SYNC_SYNCT0_TB A timeout event for Timer B of GPTM0 is triggered 0x2 TIMER_SYNC_SYNCT0_TATB A timeout event for both Timer A and Timer B of GPTM0 is triggered 0x3 TIMER_SYNC_SYNCT1 Synchronize GPTM Timer 1 2 4 TIMER_SYNC_SYNCT1_NONE GPTM1 is not affected 0x0 TIMER_SYNC_SYNCT1_TA A timeout event for Timer A of GPTM1 is triggered 0x1 TIMER_SYNC_SYNCT1_TB A timeout event for Timer B of GPTM1 is triggered 0x2 TIMER_SYNC_SYNCT1_TATB A timeout event for both Timer A and Timer B of GPTM1 is triggered 0x3 TIMER_SYNC_SYNCT2 Synchronize GPTM Timer 2 4 6 TIMER_SYNC_SYNCT2_NONE GPTM2 is not affected 0x0 TIMER_SYNC_SYNCT2_TA A timeout event for Timer A of GPTM2 is triggered 0x1 TIMER_SYNC_SYNCT2_TB A timeout event for Timer B of GPTM2 is triggered 0x2 TIMER_SYNC_SYNCT2_TATB A timeout event for both Timer A and Timer B of GPTM2 is triggered 0x3 TIMER_SYNC_SYNCT3 Synchronize GPTM Timer 3 6 8 TIMER_SYNC_SYNCT3_NONE GPTM3 is not affected 0x0 TIMER_SYNC_SYNCT3_TA A timeout event for Timer A of GPTM3 is triggered 0x1 TIMER_SYNC_SYNCT3_TB A timeout event for Timer B of GPTM3 is triggered 0x2 TIMER_SYNC_SYNCT3_TATB A timeout event for both Timer A and Timer B of GPTM3 is triggered 0x3 TIMER_SYNC_SYNCT4 Synchronize GPTM Timer 4 8 10 TIMER_SYNC_SYNCT4_NONE GPTM4 is not affected 0x0 TIMER_SYNC_SYNCT4_TA A timeout event for Timer A of GPTM4 is triggered 0x1 TIMER_SYNC_SYNCT4_TB A timeout event for Timer B of GPTM4 is triggered 0x2 TIMER_SYNC_SYNCT4_TATB A timeout event for both Timer A and Timer B of GPTM4 is triggered 0x3 TIMER_SYNC_SYNCT5 Synchronize GPTM Timer 5 10 12 TIMER_SYNC_SYNCT5_NONE GPTM5 is not affected 0x0 TIMER_SYNC_SYNCT5_TA A timeout event for Timer A of GPTM5 is triggered 0x1 TIMER_SYNC_SYNCT5_TB A timeout event for Timer B of GPTM5 is triggered 0x2 TIMER_SYNC_SYNCT5_TATB A timeout event for both Timer A and Timer B of GPTM5 is triggered 0x3 TIMER_SYNC_SYNCT6 Synchronize GPTM Timer 6 12 14 TIMER_SYNC_SYNCT6_NONE GPTM6 is not affected 0x0 TIMER_SYNC_SYNCT6_TA A timeout event for Timer A of GPTM6 is triggered 0x1 TIMER_SYNC_SYNCT6_TB A timeout event for Timer B of GPTM6 is triggered 0x2 TIMER_SYNC_SYNCT6_TATB A timeout event for both Timer A and Timer B of GPTM6 is triggered 0x3 TIMER_SYNC_SYNCT7 Synchronize GPTM Timer 7 14 16 TIMER_SYNC_SYNCT7_NONE GPT7 is not affected 0x0 TIMER_SYNC_SYNCT7_TA A timeout event for Timer A of GPTM7 is triggered 0x1 TIMER_SYNC_SYNCT7_TB A timeout event for Timer B of GPTM7 is triggered 0x2 TIMER_SYNC_SYNCT7_TATB A timeout event for both Timer A and Timer B of GPTM7 is triggered 0x3 TIMER0TAILR GPTM Timer A Interval Load 0x28 read-write n 0x0 0x0 TIMER0TAMATCHR GPTM Timer A Match 0x30 read-write n 0x0 0x0 TIMER0TAMR GPTM Timer A Mode 0x4 read-write n 0x0 0x0 TIMER_TAMR_TAAMS GPTM Timer A Alternate Mode Select 3 4 TIMER_TAMR_TACDIR GPTM Timer A Count Direction 4 5 TIMER_TAMR_TACINTD One-shot/Periodic Interrupt Disable 12 13 TIMER_TAMR_TACMR GPTM Timer A Capture Mode 2 3 TIMER_TAMR_TAILD GPTM Timer A Interval Load Write 8 9 TIMER_TAMR_TAMIE GPTM Timer A Match Interrupt Enable 5 6 TIMER_TAMR_TAMR GPTM Timer A Mode 0 2 TIMER_TAMR_TAMR_1_SHOT One-Shot Timer mode 0x1 TIMER_TAMR_TAMR_PERIOD Periodic Timer mode 0x2 TIMER_TAMR_TAMR_CAP Capture mode 0x3 TIMER_TAMR_TAMRSU GPTM Timer A Match Register Update 10 11 TIMER_TAMR_TAPLO GPTM Timer A PWM Legacy Operation 11 12 TIMER_TAMR_TAPWMIE GPTM Timer A PWM Interrupt Enable 9 10 TIMER_TAMR_TASNAPS GPTM Timer A Snap-Shot Mode 7 8 TIMER_TAMR_TAWOT GPTM Timer A Wait-on-Trigger 6 7 TIMER_TAMR_TCACT Timer Compare Action Select 13 16 TIMER_TAMR_TCACT_NONE Disable compare operations 0x0 TIMER_TAMR_TCACT_TOGGLE Toggle State on Time-Out 0x1 TIMER_TAMR_TCACT_CLRTO Clear CCP on Time-Out 0x2 TIMER_TAMR_TCACT_SETTO Set CCP on Time-Out 0x3 TIMER_TAMR_TCACT_SETTOGTO Set CCP immediately and toggle on Time-Out 0x4 TIMER_TAMR_TCACT_CLRTOGTO Clear CCP immediately and toggle on Time-Out 0x5 TIMER_TAMR_TCACT_SETCLRTO Set CCP immediately and clear on Time-Out 0x6 TIMER_TAMR_TCACT_CLRSETTO Clear CCP immediately and set on Time-Out 0x7 TIMER0TAPMR GPTM TimerA Prescale Match 0x40 read-write n 0x0 0x0 TIMER_TAPMR_TAPSMR GPTM TimerA Prescale Match 0 8 TIMER0TAPR GPTM Timer A Prescale 0x38 read-write n 0x0 0x0 TIMER_TAPR_TAPSR GPTM Timer A Prescale 0 8 TIMER0TAPS GPTM Timer A Prescale Snapshot 0x5C read-write n 0x0 0x0 TIMER_TAPS_PSS GPTM Timer A Prescaler Snapshot 0 16 TIMER0TAR GPTM Timer A 0x48 read-write n 0x0 0x0 TIMER0TAV GPTM Timer A Value 0x50 read-write n 0x0 0x0 TIMER0TBILR GPTM Timer B Interval Load 0x2C read-write n 0x0 0x0 TIMER0TBMATCHR GPTM Timer B Match 0x34 read-write n 0x0 0x0 TIMER0TBMR GPTM Timer B Mode 0x8 read-write n 0x0 0x0 TIMER_TBMR_TBAMS GPTM Timer B Alternate Mode Select 3 4 TIMER_TBMR_TBCDIR GPTM Timer B Count Direction 4 5 TIMER_TBMR_TBCINTD One-Shot/Periodic Interrupt Disable 12 13 TIMER_TBMR_TBCMR GPTM Timer B Capture Mode 2 3 TIMER_TBMR_TBILD GPTM Timer B Interval Load Write 8 9 TIMER_TBMR_TBMIE GPTM Timer B Match Interrupt Enable 5 6 TIMER_TBMR_TBMR GPTM Timer B Mode 0 2 TIMER_TBMR_TBMR_1_SHOT One-Shot Timer mode 0x1 TIMER_TBMR_TBMR_PERIOD Periodic Timer mode 0x2 TIMER_TBMR_TBMR_CAP Capture mode 0x3 TIMER_TBMR_TBMRSU GPTM Timer B Match Register Update 10 11 TIMER_TBMR_TBPLO GPTM Timer B PWM Legacy Operation 11 12 TIMER_TBMR_TBPWMIE GPTM Timer B PWM Interrupt Enable 9 10 TIMER_TBMR_TBSNAPS GPTM Timer B Snap-Shot Mode 7 8 TIMER_TBMR_TBWOT GPTM Timer B Wait-on-Trigger 6 7 TIMER_TBMR_TCACT Timer Compare Action Select 13 16 TIMER_TBMR_TCACT_NONE Disable compare operations 0x0 TIMER_TBMR_TCACT_TOGGLE Toggle State on Time-Out 0x1 TIMER_TBMR_TCACT_CLRTO Clear CCP on Time-Out 0x2 TIMER_TBMR_TCACT_SETTO Set CCP on Time-Out 0x3 TIMER_TBMR_TCACT_SETTOGTO Set CCP immediately and toggle on Time-Out 0x4 TIMER_TBMR_TCACT_CLRTOGTO Clear CCP immediately and toggle on Time-Out 0x5 TIMER_TBMR_TCACT_SETCLRTO Set CCP immediately and clear on Time-Out 0x6 TIMER_TBMR_TCACT_CLRSETTO Clear CCP immediately and set on Time-Out 0x7 TIMER0TBPMR GPTM TimerB Prescale Match 0x44 read-write n 0x0 0x0 TIMER_TBPMR_TBPSMR GPTM TimerB Prescale Match 0 8 TIMER0TBPR GPTM Timer B Prescale 0x3C read-write n 0x0 0x0 TIMER_TBPR_TBPSR GPTM Timer B Prescale 0 8 TIMER0TBPS GPTM Timer B Prescale Snapshot 0x60 read-write n 0x0 0x0 TIMER_TBPS_PSS GPTM Timer A Prescaler Value 0 16 TIMER0TBR GPTM Timer B 0x4C read-write n 0x0 0x0 TIMER0TBV GPTM Timer B Value 0x54 read-write n 0x0 0x0 TIMER2 Register map for TIMER0 peripheral TIMER 0x0 0x0 0x1000 registers n TIMER2A 23 TIMER2B 24 ADCEV GPTM ADC Event 0x70 -1 read-write n 0x0 0x0 TIMER_ADCEV_CAEADCEN GPTM A Capture Event ADC Trigger Enable 2 3 TIMER_ADCEV_CAMADCEN GPTM A Capture Match Event ADC Trigger Enable 1 2 TIMER_ADCEV_CBEADCEN GPTM B Capture Event ADC Trigger Enable 10 11 TIMER_ADCEV_CBMADCEN GPTM B Capture Match Event ADC Trigger Enable 9 10 TIMER_ADCEV_RTCADCEN GPTM RTC Match Event ADC Trigger Enable 3 4 TIMER_ADCEV_TAMADCEN GPTM A Mode Match Event ADC Trigger Enable 4 5 TIMER_ADCEV_TATOADCEN GPTM A Time-Out Event ADC Trigger Enable 0 1 TIMER_ADCEV_TBMADCEN GPTM B Mode Match Event ADC Trigger Enable 11 12 TIMER_ADCEV_TBTOADCEN GPTM B Time-Out Event ADC Trigger Enable 8 9 CC GPTM Clock Configuration 0xFC8 -1 read-write n 0x0 0x0 TIMER_CC_ALTCLK Alternate Clock Source 0 1 CFG GPTM Configuration 0x0 -1 read-write n 0x0 0x0 TIMER_CFG GPTM Configuration 0 3 TIMER_CFG_32_BIT_TIMER For a 16/32-bit timer, this value selects the 32-bit timer configuration 0x0 TIMER_CFG_32_BIT_RTC For a 16/32-bit timer, this value selects the 32-bit real-time clock (RTC) counter configuration 0x1 TIMER_CFG_16_BIT For a 16/32-bit timer, this value selects the 16-bit timer configuration 0x4 CTL GPTM Control 0xC -1 read-write n 0x0 0x0 TIMER_CTL_RTCEN GPTM RTC Stall Enable 4 5 TIMER_CTL_TAEN GPTM Timer A Enable 0 1 TIMER_CTL_TAEVENT GPTM Timer A Event Mode 2 4 TIMER_CTL_TAEVENT_POS Positive edge 0x0 TIMER_CTL_TAEVENT_NEG Negative edge 0x1 TIMER_CTL_TAEVENT_BOTH Both edges 0x3 TIMER_CTL_TAOTE GPTM Timer A Output Trigger Enable 5 6 TIMER_CTL_TAPWML GPTM Timer A PWM Output Level 6 7 TIMER_CTL_TASTALL GPTM Timer A Stall Enable 1 2 TIMER_CTL_TBEN GPTM Timer B Enable 8 9 TIMER_CTL_TBEVENT GPTM Timer B Event Mode 10 12 TIMER_CTL_TBEVENT_POS Positive edge 0x0 TIMER_CTL_TBEVENT_NEG Negative edge 0x1 TIMER_CTL_TBEVENT_BOTH Both edges 0x3 TIMER_CTL_TBOTE GPTM Timer B Output Trigger Enable 13 14 TIMER_CTL_TBPWML GPTM Timer B PWM Output Level 14 15 TIMER_CTL_TBSTALL GPTM Timer B Stall Enable 9 10 DMAEV GPTM DMA Event 0x6C -1 read-write n 0x0 0x0 TIMER_DMAEV_CAEDMAEN GPTM A Capture Event DMA Trigger Enable 2 3 TIMER_DMAEV_CAMDMAEN GPTM A Capture Match Event DMA Trigger Enable 1 2 TIMER_DMAEV_CBEDMAEN GPTM B Capture Event DMA Trigger Enable 10 11 TIMER_DMAEV_CBMDMAEN GPTM B Capture Match Event DMA Trigger Enable 9 10 TIMER_DMAEV_RTCDMAEN GPTM A RTC Match Event DMA Trigger Enable 3 4 TIMER_DMAEV_TAMDMAEN GPTM A Mode Match Event DMA Trigger Enable 4 5 TIMER_DMAEV_TATODMAEN GPTM A Time-Out Event DMA Trigger Enable 0 1 TIMER_DMAEV_TBMDMAEN GPTM B Mode Match Event DMA Trigger Enable 11 12 TIMER_DMAEV_TBTODMAEN GPTM B Time-Out Event DMA Trigger Enable 8 9 ICR GPTM Interrupt Clear 0x24 -1 write-only n 0x0 0x0 TIMER_ICR_CAECINT GPTM Timer A Capture Mode Event Interrupt Clear 2 3 write-only TIMER_ICR_CAMCINT GPTM Timer A Capture Mode Match Interrupt Clear 1 2 write-only TIMER_ICR_CBECINT GPTM Timer B Capture Mode Event Interrupt Clear 10 11 write-only TIMER_ICR_CBMCINT GPTM Timer B Capture Mode Match Interrupt Clear 9 10 write-only TIMER_ICR_DMAAINT GPTM Timer A DMA Done Interrupt Clear 5 6 write-only TIMER_ICR_DMABINT GPTM Timer B DMA Done Interrupt Clear 13 14 write-only TIMER_ICR_RTCCINT GPTM RTC Interrupt Clear 3 4 write-only TIMER_ICR_TAMCINT GPTM Timer A Match Interrupt Clear 4 5 write-only TIMER_ICR_TATOCINT GPTM Timer A Time-Out Raw Interrupt 0 1 write-only TIMER_ICR_TBMCINT GPTM Timer B Match Interrupt Clear 11 12 write-only TIMER_ICR_TBTOCINT GPTM Timer B Time-Out Interrupt Clear 8 9 write-only IMR GPTM Interrupt Mask 0x18 -1 read-write n 0x0 0x0 TIMER_IMR_CAEIM GPTM Timer A Capture Mode Event Interrupt Mask 2 3 TIMER_IMR_CAMIM GPTM Timer A Capture Mode Match Interrupt Mask 1 2 TIMER_IMR_CBEIM GPTM Timer B Capture Mode Event Interrupt Mask 10 11 TIMER_IMR_CBMIM GPTM Timer B Capture Mode Match Interrupt Mask 9 10 TIMER_IMR_DMAAIM GPTM Timer A DMA Done Interrupt Mask 5 6 TIMER_IMR_DMABIM GPTM Timer B DMA Done Interrupt Mask 13 14 TIMER_IMR_RTCIM GPTM RTC Interrupt Mask 3 4 TIMER_IMR_TAMIM GPTM Timer A Match Interrupt Mask 4 5 TIMER_IMR_TATOIM GPTM Timer A Time-Out Interrupt Mask 0 1 TIMER_IMR_TBMIM GPTM Timer B Match Interrupt Mask 11 12 TIMER_IMR_TBTOIM GPTM Timer B Time-Out Interrupt Mask 8 9 MIS GPTM Masked Interrupt Status 0x20 -1 read-write n 0x0 0x0 TIMER_MIS_CAEMIS GPTM Timer A Capture Mode Event Masked Interrupt 2 3 TIMER_MIS_CAMMIS GPTM Timer A Capture Mode Match Masked Interrupt 1 2 TIMER_MIS_CBEMIS GPTM Timer B Capture Mode Event Masked Interrupt 10 11 TIMER_MIS_CBMMIS GPTM Timer B Capture Mode Match Masked Interrupt 9 10 TIMER_MIS_DMAAMIS GPTM Timer A DMA Done Masked Interrupt 5 6 TIMER_MIS_DMABMIS GPTM Timer B DMA Done Masked Interrupt 13 14 TIMER_MIS_RTCMIS GPTM RTC Masked Interrupt 3 4 TIMER_MIS_TAMMIS GPTM Timer A Match Masked Interrupt 4 5 TIMER_MIS_TATOMIS GPTM Timer A Time-Out Masked Interrupt 0 1 TIMER_MIS_TBMMIS GPTM Timer B Match Masked Interrupt 11 12 TIMER_MIS_TBTOMIS GPTM Timer B Time-Out Masked Interrupt 8 9 PP GPTM Peripheral Properties 0xFC0 -1 read-write n 0x0 0x0 TIMER_PP_ALTCLK Alternate Clock Source 6 7 TIMER_PP_CHAIN Chain with Other Timers 4 5 TIMER_PP_SIZE Count Size 0 4 TIMER_PP_SIZE_16 Timer A and Timer B counters are 16 bits each with an 8-bit prescale counter 0x0 TIMER_PP_SIZE_32 Timer A and Timer B counters are 32 bits each with a 16-bit prescale counter 0x1 TIMER_PP_SYNCCNT Synchronize Start 5 6 RIS GPTM Raw Interrupt Status 0x1C -1 read-write n 0x0 0x0 TIMER_RIS_CAERIS GPTM Timer A Capture Mode Event Raw Interrupt 2 3 TIMER_RIS_CAMRIS GPTM Timer A Capture Mode Match Raw Interrupt 1 2 TIMER_RIS_CBERIS GPTM Timer B Capture Mode Event Raw Interrupt 10 11 TIMER_RIS_CBMRIS GPTM Timer B Capture Mode Match Raw Interrupt 9 10 TIMER_RIS_DMAARIS GPTM Timer A DMA Done Raw Interrupt Status 5 6 TIMER_RIS_DMABRIS GPTM Timer B DMA Done Raw Interrupt Status 13 14 TIMER_RIS_RTCRIS GPTM RTC Raw Interrupt 3 4 TIMER_RIS_TAMRIS GPTM Timer A Match Raw Interrupt 4 5 TIMER_RIS_TATORIS GPTM Timer A Time-Out Raw Interrupt 0 1 TIMER_RIS_TBMRIS GPTM Timer B Match Raw Interrupt 11 12 TIMER_RIS_TBTORIS GPTM Timer B Time-Out Raw Interrupt 8 9 RTCPD GPTM RTC Predivide 0x58 -1 read-write n 0x0 0x0 TIMER_RTCPD_RTCPD RTC Predivide Counter Value 0 16 SYNC GPTM Synchronize 0x10 -1 read-write n 0x0 0x0 TIMER_SYNC_SYNCT0 Synchronize GPTM Timer 0 0 2 TIMER_SYNC_SYNCT0_NONE GPTM0 is not affected 0x0 TIMER_SYNC_SYNCT0_TA A timeout event for Timer A of GPTM0 is triggered 0x1 TIMER_SYNC_SYNCT0_TB A timeout event for Timer B of GPTM0 is triggered 0x2 TIMER_SYNC_SYNCT0_TATB A timeout event for both Timer A and Timer B of GPTM0 is triggered 0x3 TIMER_SYNC_SYNCT1 Synchronize GPTM Timer 1 2 4 TIMER_SYNC_SYNCT1_NONE GPTM1 is not affected 0x0 TIMER_SYNC_SYNCT1_TA A timeout event for Timer A of GPTM1 is triggered 0x1 TIMER_SYNC_SYNCT1_TB A timeout event for Timer B of GPTM1 is triggered 0x2 TIMER_SYNC_SYNCT1_TATB A timeout event for both Timer A and Timer B of GPTM1 is triggered 0x3 TIMER_SYNC_SYNCT2 Synchronize GPTM Timer 2 4 6 TIMER_SYNC_SYNCT2_NONE GPTM2 is not affected 0x0 TIMER_SYNC_SYNCT2_TA A timeout event for Timer A of GPTM2 is triggered 0x1 TIMER_SYNC_SYNCT2_TB A timeout event for Timer B of GPTM2 is triggered 0x2 TIMER_SYNC_SYNCT2_TATB A timeout event for both Timer A and Timer B of GPTM2 is triggered 0x3 TIMER_SYNC_SYNCT3 Synchronize GPTM Timer 3 6 8 TIMER_SYNC_SYNCT3_NONE GPTM3 is not affected 0x0 TIMER_SYNC_SYNCT3_TA A timeout event for Timer A of GPTM3 is triggered 0x1 TIMER_SYNC_SYNCT3_TB A timeout event for Timer B of GPTM3 is triggered 0x2 TIMER_SYNC_SYNCT3_TATB A timeout event for both Timer A and Timer B of GPTM3 is triggered 0x3 TIMER_SYNC_SYNCT4 Synchronize GPTM Timer 4 8 10 TIMER_SYNC_SYNCT4_NONE GPTM4 is not affected 0x0 TIMER_SYNC_SYNCT4_TA A timeout event for Timer A of GPTM4 is triggered 0x1 TIMER_SYNC_SYNCT4_TB A timeout event for Timer B of GPTM4 is triggered 0x2 TIMER_SYNC_SYNCT4_TATB A timeout event for both Timer A and Timer B of GPTM4 is triggered 0x3 TIMER_SYNC_SYNCT5 Synchronize GPTM Timer 5 10 12 TIMER_SYNC_SYNCT5_NONE GPTM5 is not affected 0x0 TIMER_SYNC_SYNCT5_TA A timeout event for Timer A of GPTM5 is triggered 0x1 TIMER_SYNC_SYNCT5_TB A timeout event for Timer B of GPTM5 is triggered 0x2 TIMER_SYNC_SYNCT5_TATB A timeout event for both Timer A and Timer B of GPTM5 is triggered 0x3 TIMER_SYNC_SYNCT6 Synchronize GPTM Timer 6 12 14 TIMER_SYNC_SYNCT6_NONE GPTM6 is not affected 0x0 TIMER_SYNC_SYNCT6_TA A timeout event for Timer A of GPTM6 is triggered 0x1 TIMER_SYNC_SYNCT6_TB A timeout event for Timer B of GPTM6 is triggered 0x2 TIMER_SYNC_SYNCT6_TATB A timeout event for both Timer A and Timer B of GPTM6 is triggered 0x3 TIMER_SYNC_SYNCT7 Synchronize GPTM Timer 7 14 16 TIMER_SYNC_SYNCT7_NONE GPT7 is not affected 0x0 TIMER_SYNC_SYNCT7_TA A timeout event for Timer A of GPTM7 is triggered 0x1 TIMER_SYNC_SYNCT7_TB A timeout event for Timer B of GPTM7 is triggered 0x2 TIMER_SYNC_SYNCT7_TATB A timeout event for both Timer A and Timer B of GPTM7 is triggered 0x3 TAILR GPTM Timer A Interval Load 0x28 -1 read-write n 0x0 0x0 TAMATCHR GPTM Timer A Match 0x30 -1 read-write n 0x0 0x0 TAMR GPTM Timer A Mode 0x4 -1 read-write n 0x0 0x0 TIMER_TAMR_TAAMS GPTM Timer A Alternate Mode Select 3 4 TIMER_TAMR_TACDIR GPTM Timer A Count Direction 4 5 TIMER_TAMR_TACINTD One-shot/Periodic Interrupt Disable 12 13 TIMER_TAMR_TACMR GPTM Timer A Capture Mode 2 3 TIMER_TAMR_TAILD GPTM Timer A Interval Load Write 8 9 TIMER_TAMR_TAMIE GPTM Timer A Match Interrupt Enable 5 6 TIMER_TAMR_TAMR GPTM Timer A Mode 0 2 TIMER_TAMR_TAMR_1_SHOT One-Shot Timer mode 0x1 TIMER_TAMR_TAMR_PERIOD Periodic Timer mode 0x2 TIMER_TAMR_TAMR_CAP Capture mode 0x3 TIMER_TAMR_TAMRSU GPTM Timer A Match Register Update 10 11 TIMER_TAMR_TAPLO GPTM Timer A PWM Legacy Operation 11 12 TIMER_TAMR_TAPWMIE GPTM Timer A PWM Interrupt Enable 9 10 TIMER_TAMR_TASNAPS GPTM Timer A Snap-Shot Mode 7 8 TIMER_TAMR_TAWOT GPTM Timer A Wait-on-Trigger 6 7 TIMER_TAMR_TCACT Timer Compare Action Select 13 16 TIMER_TAMR_TCACT_NONE Disable compare operations 0x0 TIMER_TAMR_TCACT_TOGGLE Toggle State on Time-Out 0x1 TIMER_TAMR_TCACT_CLRTO Clear CCP on Time-Out 0x2 TIMER_TAMR_TCACT_SETTO Set CCP on Time-Out 0x3 TIMER_TAMR_TCACT_SETTOGTO Set CCP immediately and toggle on Time-Out 0x4 TIMER_TAMR_TCACT_CLRTOGTO Clear CCP immediately and toggle on Time-Out 0x5 TIMER_TAMR_TCACT_SETCLRTO Set CCP immediately and clear on Time-Out 0x6 TIMER_TAMR_TCACT_CLRSETTO Clear CCP immediately and set on Time-Out 0x7 TAPMR GPTM TimerA Prescale Match 0x40 -1 read-write n 0x0 0x0 TIMER_TAPMR_TAPSMR GPTM TimerA Prescale Match 0 8 TAPR GPTM Timer A Prescale 0x38 -1 read-write n 0x0 0x0 TIMER_TAPR_TAPSR GPTM Timer A Prescale 0 8 TAPS GPTM Timer A Prescale Snapshot 0x5C -1 read-write n 0x0 0x0 TIMER_TAPS_PSS GPTM Timer A Prescaler Snapshot 0 16 TAR GPTM Timer A 0x48 -1 read-write n 0x0 0x0 TAV GPTM Timer A Value 0x50 -1 read-write n 0x0 0x0 TBILR GPTM Timer B Interval Load 0x2C -1 read-write n 0x0 0x0 TBMATCHR GPTM Timer B Match 0x34 -1 read-write n 0x0 0x0 TBMR GPTM Timer B Mode 0x8 -1 read-write n 0x0 0x0 TIMER_TBMR_TBAMS GPTM Timer B Alternate Mode Select 3 4 TIMER_TBMR_TBCDIR GPTM Timer B Count Direction 4 5 TIMER_TBMR_TBCINTD One-Shot/Periodic Interrupt Disable 12 13 TIMER_TBMR_TBCMR GPTM Timer B Capture Mode 2 3 TIMER_TBMR_TBILD GPTM Timer B Interval Load Write 8 9 TIMER_TBMR_TBMIE GPTM Timer B Match Interrupt Enable 5 6 TIMER_TBMR_TBMR GPTM Timer B Mode 0 2 TIMER_TBMR_TBMR_1_SHOT One-Shot Timer mode 0x1 TIMER_TBMR_TBMR_PERIOD Periodic Timer mode 0x2 TIMER_TBMR_TBMR_CAP Capture mode 0x3 TIMER_TBMR_TBMRSU GPTM Timer B Match Register Update 10 11 TIMER_TBMR_TBPLO GPTM Timer B PWM Legacy Operation 11 12 TIMER_TBMR_TBPWMIE GPTM Timer B PWM Interrupt Enable 9 10 TIMER_TBMR_TBSNAPS GPTM Timer B Snap-Shot Mode 7 8 TIMER_TBMR_TBWOT GPTM Timer B Wait-on-Trigger 6 7 TIMER_TBMR_TCACT Timer Compare Action Select 13 16 TIMER_TBMR_TCACT_NONE Disable compare operations 0x0 TIMER_TBMR_TCACT_TOGGLE Toggle State on Time-Out 0x1 TIMER_TBMR_TCACT_CLRTO Clear CCP on Time-Out 0x2 TIMER_TBMR_TCACT_SETTO Set CCP on Time-Out 0x3 TIMER_TBMR_TCACT_SETTOGTO Set CCP immediately and toggle on Time-Out 0x4 TIMER_TBMR_TCACT_CLRTOGTO Clear CCP immediately and toggle on Time-Out 0x5 TIMER_TBMR_TCACT_SETCLRTO Set CCP immediately and clear on Time-Out 0x6 TIMER_TBMR_TCACT_CLRSETTO Clear CCP immediately and set on Time-Out 0x7 TBPMR GPTM TimerB Prescale Match 0x44 -1 read-write n 0x0 0x0 TIMER_TBPMR_TBPSMR GPTM TimerB Prescale Match 0 8 TBPR GPTM Timer B Prescale 0x3C -1 read-write n 0x0 0x0 TIMER_TBPR_TBPSR GPTM Timer B Prescale 0 8 TBPS GPTM Timer B Prescale Snapshot 0x60 -1 read-write n 0x0 0x0 TIMER_TBPS_PSS GPTM Timer A Prescaler Value 0 16 TBR GPTM Timer B 0x4C -1 read-write n 0x0 0x0 TBV GPTM Timer B Value 0x54 -1 read-write n 0x0 0x0 TIMER0ADCEV GPTM ADC Event 0x70 read-write n 0x0 0x0 TIMER_ADCEV_CAEADCEN GPTM A Capture Event ADC Trigger Enable 2 3 TIMER_ADCEV_CAMADCEN GPTM A Capture Match Event ADC Trigger Enable 1 2 TIMER_ADCEV_CBEADCEN GPTM B Capture Event ADC Trigger Enable 10 11 TIMER_ADCEV_CBMADCEN GPTM B Capture Match Event ADC Trigger Enable 9 10 TIMER_ADCEV_RTCADCEN GPTM RTC Match Event ADC Trigger Enable 3 4 TIMER_ADCEV_TAMADCEN GPTM A Mode Match Event ADC Trigger Enable 4 5 TIMER_ADCEV_TATOADCEN GPTM A Time-Out Event ADC Trigger Enable 0 1 TIMER_ADCEV_TBMADCEN GPTM B Mode Match Event ADC Trigger Enable 11 12 TIMER_ADCEV_TBTOADCEN GPTM B Time-Out Event ADC Trigger Enable 8 9 TIMER0CC GPTM Clock Configuration 0xFC8 read-write n 0x0 0x0 TIMER_CC_ALTCLK Alternate Clock Source 0 1 TIMER0CFG GPTM Configuration 0x0 read-write n 0x0 0x0 TIMER_CFG GPTM Configuration 0 3 TIMER_CFG_32_BIT_TIMER For a 16/32-bit timer, this value selects the 32-bit timer configuration 0x0 TIMER_CFG_32_BIT_RTC For a 16/32-bit timer, this value selects the 32-bit real-time clock (RTC) counter configuration 0x1 TIMER_CFG_16_BIT For a 16/32-bit timer, this value selects the 16-bit timer configuration 0x4 TIMER0CTL GPTM Control 0xC read-write n 0x0 0x0 TIMER_CTL_RTCEN GPTM RTC Stall Enable 4 5 TIMER_CTL_TAEN GPTM Timer A Enable 0 1 TIMER_CTL_TAEVENT GPTM Timer A Event Mode 2 4 TIMER_CTL_TAEVENT_POS Positive edge 0x0 TIMER_CTL_TAEVENT_NEG Negative edge 0x1 TIMER_CTL_TAEVENT_BOTH Both edges 0x3 TIMER_CTL_TAOTE GPTM Timer A Output Trigger Enable 5 6 TIMER_CTL_TAPWML GPTM Timer A PWM Output Level 6 7 TIMER_CTL_TASTALL GPTM Timer A Stall Enable 1 2 TIMER_CTL_TBEN GPTM Timer B Enable 8 9 TIMER_CTL_TBEVENT GPTM Timer B Event Mode 10 12 TIMER_CTL_TBEVENT_POS Positive edge 0x0 TIMER_CTL_TBEVENT_NEG Negative edge 0x1 TIMER_CTL_TBEVENT_BOTH Both edges 0x3 TIMER_CTL_TBOTE GPTM Timer B Output Trigger Enable 13 14 TIMER_CTL_TBPWML GPTM Timer B PWM Output Level 14 15 TIMER_CTL_TBSTALL GPTM Timer B Stall Enable 9 10 TIMER0DMAEV GPTM DMA Event 0x6C read-write n 0x0 0x0 TIMER_DMAEV_CAEDMAEN GPTM A Capture Event DMA Trigger Enable 2 3 TIMER_DMAEV_CAMDMAEN GPTM A Capture Match Event DMA Trigger Enable 1 2 TIMER_DMAEV_CBEDMAEN GPTM B Capture Event DMA Trigger Enable 10 11 TIMER_DMAEV_CBMDMAEN GPTM B Capture Match Event DMA Trigger Enable 9 10 TIMER_DMAEV_RTCDMAEN GPTM A RTC Match Event DMA Trigger Enable 3 4 TIMER_DMAEV_TAMDMAEN GPTM A Mode Match Event DMA Trigger Enable 4 5 TIMER_DMAEV_TATODMAEN GPTM A Time-Out Event DMA Trigger Enable 0 1 TIMER_DMAEV_TBMDMAEN GPTM B Mode Match Event DMA Trigger Enable 11 12 TIMER_DMAEV_TBTODMAEN GPTM B Time-Out Event DMA Trigger Enable 8 9 TIMER0ICR GPTM Interrupt Clear 0x24 write-only n 0x0 0x0 TIMER_ICR_CAECINT GPTM Timer A Capture Mode Event Interrupt Clear 2 3 write-only TIMER_ICR_CAMCINT GPTM Timer A Capture Mode Match Interrupt Clear 1 2 write-only TIMER_ICR_CBECINT GPTM Timer B Capture Mode Event Interrupt Clear 10 11 write-only TIMER_ICR_CBMCINT GPTM Timer B Capture Mode Match Interrupt Clear 9 10 write-only TIMER_ICR_DMAAINT GPTM Timer A DMA Done Interrupt Clear 5 6 write-only TIMER_ICR_DMABINT GPTM Timer B DMA Done Interrupt Clear 13 14 write-only TIMER_ICR_RTCCINT GPTM RTC Interrupt Clear 3 4 write-only TIMER_ICR_TAMCINT GPTM Timer A Match Interrupt Clear 4 5 write-only TIMER_ICR_TATOCINT GPTM Timer A Time-Out Raw Interrupt 0 1 write-only TIMER_ICR_TBMCINT GPTM Timer B Match Interrupt Clear 11 12 write-only TIMER_ICR_TBTOCINT GPTM Timer B Time-Out Interrupt Clear 8 9 write-only TIMER0IMR GPTM Interrupt Mask 0x18 read-write n 0x0 0x0 TIMER_IMR_CAEIM GPTM Timer A Capture Mode Event Interrupt Mask 2 3 TIMER_IMR_CAMIM GPTM Timer A Capture Mode Match Interrupt Mask 1 2 TIMER_IMR_CBEIM GPTM Timer B Capture Mode Event Interrupt Mask 10 11 TIMER_IMR_CBMIM GPTM Timer B Capture Mode Match Interrupt Mask 9 10 TIMER_IMR_DMAAIM GPTM Timer A DMA Done Interrupt Mask 5 6 TIMER_IMR_DMABIM GPTM Timer B DMA Done Interrupt Mask 13 14 TIMER_IMR_RTCIM GPTM RTC Interrupt Mask 3 4 TIMER_IMR_TAMIM GPTM Timer A Match Interrupt Mask 4 5 TIMER_IMR_TATOIM GPTM Timer A Time-Out Interrupt Mask 0 1 TIMER_IMR_TBMIM GPTM Timer B Match Interrupt Mask 11 12 TIMER_IMR_TBTOIM GPTM Timer B Time-Out Interrupt Mask 8 9 TIMER0MIS GPTM Masked Interrupt Status 0x20 read-write n 0x0 0x0 TIMER_MIS_CAEMIS GPTM Timer A Capture Mode Event Masked Interrupt 2 3 TIMER_MIS_CAMMIS GPTM Timer A Capture Mode Match Masked Interrupt 1 2 TIMER_MIS_CBEMIS GPTM Timer B Capture Mode Event Masked Interrupt 10 11 TIMER_MIS_CBMMIS GPTM Timer B Capture Mode Match Masked Interrupt 9 10 TIMER_MIS_DMAAMIS GPTM Timer A DMA Done Masked Interrupt 5 6 TIMER_MIS_DMABMIS GPTM Timer B DMA Done Masked Interrupt 13 14 TIMER_MIS_RTCMIS GPTM RTC Masked Interrupt 3 4 TIMER_MIS_TAMMIS GPTM Timer A Match Masked Interrupt 4 5 TIMER_MIS_TATOMIS GPTM Timer A Time-Out Masked Interrupt 0 1 TIMER_MIS_TBMMIS GPTM Timer B Match Masked Interrupt 11 12 TIMER_MIS_TBTOMIS GPTM Timer B Time-Out Masked Interrupt 8 9 TIMER0PP GPTM Peripheral Properties 0xFC0 read-write n 0x0 0x0 TIMER_PP_ALTCLK Alternate Clock Source 6 7 TIMER_PP_CHAIN Chain with Other Timers 4 5 TIMER_PP_SIZE Count Size 0 4 TIMER_PP_SIZE_16 Timer A and Timer B counters are 16 bits each with an 8-bit prescale counter 0x0 TIMER_PP_SIZE_32 Timer A and Timer B counters are 32 bits each with a 16-bit prescale counter 0x1 TIMER_PP_SYNCCNT Synchronize Start 5 6 TIMER0RIS GPTM Raw Interrupt Status 0x1C read-write n 0x0 0x0 TIMER_RIS_CAERIS GPTM Timer A Capture Mode Event Raw Interrupt 2 3 TIMER_RIS_CAMRIS GPTM Timer A Capture Mode Match Raw Interrupt 1 2 TIMER_RIS_CBERIS GPTM Timer B Capture Mode Event Raw Interrupt 10 11 TIMER_RIS_CBMRIS GPTM Timer B Capture Mode Match Raw Interrupt 9 10 TIMER_RIS_DMAARIS GPTM Timer A DMA Done Raw Interrupt Status 5 6 TIMER_RIS_DMABRIS GPTM Timer B DMA Done Raw Interrupt Status 13 14 TIMER_RIS_RTCRIS GPTM RTC Raw Interrupt 3 4 TIMER_RIS_TAMRIS GPTM Timer A Match Raw Interrupt 4 5 TIMER_RIS_TATORIS GPTM Timer A Time-Out Raw Interrupt 0 1 TIMER_RIS_TBMRIS GPTM Timer B Match Raw Interrupt 11 12 TIMER_RIS_TBTORIS GPTM Timer B Time-Out Raw Interrupt 8 9 TIMER0RTCPD GPTM RTC Predivide 0x58 read-write n 0x0 0x0 TIMER_RTCPD_RTCPD RTC Predivide Counter Value 0 16 TIMER0SYNC GPTM Synchronize 0x10 read-write n 0x0 0x0 TIMER_SYNC_SYNCT0 Synchronize GPTM Timer 0 0 2 TIMER_SYNC_SYNCT0_NONE GPTM0 is not affected 0x0 TIMER_SYNC_SYNCT0_TA A timeout event for Timer A of GPTM0 is triggered 0x1 TIMER_SYNC_SYNCT0_TB A timeout event for Timer B of GPTM0 is triggered 0x2 TIMER_SYNC_SYNCT0_TATB A timeout event for both Timer A and Timer B of GPTM0 is triggered 0x3 TIMER_SYNC_SYNCT1 Synchronize GPTM Timer 1 2 4 TIMER_SYNC_SYNCT1_NONE GPTM1 is not affected 0x0 TIMER_SYNC_SYNCT1_TA A timeout event for Timer A of GPTM1 is triggered 0x1 TIMER_SYNC_SYNCT1_TB A timeout event for Timer B of GPTM1 is triggered 0x2 TIMER_SYNC_SYNCT1_TATB A timeout event for both Timer A and Timer B of GPTM1 is triggered 0x3 TIMER_SYNC_SYNCT2 Synchronize GPTM Timer 2 4 6 TIMER_SYNC_SYNCT2_NONE GPTM2 is not affected 0x0 TIMER_SYNC_SYNCT2_TA A timeout event for Timer A of GPTM2 is triggered 0x1 TIMER_SYNC_SYNCT2_TB A timeout event for Timer B of GPTM2 is triggered 0x2 TIMER_SYNC_SYNCT2_TATB A timeout event for both Timer A and Timer B of GPTM2 is triggered 0x3 TIMER_SYNC_SYNCT3 Synchronize GPTM Timer 3 6 8 TIMER_SYNC_SYNCT3_NONE GPTM3 is not affected 0x0 TIMER_SYNC_SYNCT3_TA A timeout event for Timer A of GPTM3 is triggered 0x1 TIMER_SYNC_SYNCT3_TB A timeout event for Timer B of GPTM3 is triggered 0x2 TIMER_SYNC_SYNCT3_TATB A timeout event for both Timer A and Timer B of GPTM3 is triggered 0x3 TIMER_SYNC_SYNCT4 Synchronize GPTM Timer 4 8 10 TIMER_SYNC_SYNCT4_NONE GPTM4 is not affected 0x0 TIMER_SYNC_SYNCT4_TA A timeout event for Timer A of GPTM4 is triggered 0x1 TIMER_SYNC_SYNCT4_TB A timeout event for Timer B of GPTM4 is triggered 0x2 TIMER_SYNC_SYNCT4_TATB A timeout event for both Timer A and Timer B of GPTM4 is triggered 0x3 TIMER_SYNC_SYNCT5 Synchronize GPTM Timer 5 10 12 TIMER_SYNC_SYNCT5_NONE GPTM5 is not affected 0x0 TIMER_SYNC_SYNCT5_TA A timeout event for Timer A of GPTM5 is triggered 0x1 TIMER_SYNC_SYNCT5_TB A timeout event for Timer B of GPTM5 is triggered 0x2 TIMER_SYNC_SYNCT5_TATB A timeout event for both Timer A and Timer B of GPTM5 is triggered 0x3 TIMER_SYNC_SYNCT6 Synchronize GPTM Timer 6 12 14 TIMER_SYNC_SYNCT6_NONE GPTM6 is not affected 0x0 TIMER_SYNC_SYNCT6_TA A timeout event for Timer A of GPTM6 is triggered 0x1 TIMER_SYNC_SYNCT6_TB A timeout event for Timer B of GPTM6 is triggered 0x2 TIMER_SYNC_SYNCT6_TATB A timeout event for both Timer A and Timer B of GPTM6 is triggered 0x3 TIMER_SYNC_SYNCT7 Synchronize GPTM Timer 7 14 16 TIMER_SYNC_SYNCT7_NONE GPT7 is not affected 0x0 TIMER_SYNC_SYNCT7_TA A timeout event for Timer A of GPTM7 is triggered 0x1 TIMER_SYNC_SYNCT7_TB A timeout event for Timer B of GPTM7 is triggered 0x2 TIMER_SYNC_SYNCT7_TATB A timeout event for both Timer A and Timer B of GPTM7 is triggered 0x3 TIMER0TAILR GPTM Timer A Interval Load 0x28 read-write n 0x0 0x0 TIMER0TAMATCHR GPTM Timer A Match 0x30 read-write n 0x0 0x0 TIMER0TAMR GPTM Timer A Mode 0x4 read-write n 0x0 0x0 TIMER_TAMR_TAAMS GPTM Timer A Alternate Mode Select 3 4 TIMER_TAMR_TACDIR GPTM Timer A Count Direction 4 5 TIMER_TAMR_TACINTD One-shot/Periodic Interrupt Disable 12 13 TIMER_TAMR_TACMR GPTM Timer A Capture Mode 2 3 TIMER_TAMR_TAILD GPTM Timer A Interval Load Write 8 9 TIMER_TAMR_TAMIE GPTM Timer A Match Interrupt Enable 5 6 TIMER_TAMR_TAMR GPTM Timer A Mode 0 2 TIMER_TAMR_TAMR_1_SHOT One-Shot Timer mode 0x1 TIMER_TAMR_TAMR_PERIOD Periodic Timer mode 0x2 TIMER_TAMR_TAMR_CAP Capture mode 0x3 TIMER_TAMR_TAMRSU GPTM Timer A Match Register Update 10 11 TIMER_TAMR_TAPLO GPTM Timer A PWM Legacy Operation 11 12 TIMER_TAMR_TAPWMIE GPTM Timer A PWM Interrupt Enable 9 10 TIMER_TAMR_TASNAPS GPTM Timer A Snap-Shot Mode 7 8 TIMER_TAMR_TAWOT GPTM Timer A Wait-on-Trigger 6 7 TIMER_TAMR_TCACT Timer Compare Action Select 13 16 TIMER_TAMR_TCACT_NONE Disable compare operations 0x0 TIMER_TAMR_TCACT_TOGGLE Toggle State on Time-Out 0x1 TIMER_TAMR_TCACT_CLRTO Clear CCP on Time-Out 0x2 TIMER_TAMR_TCACT_SETTO Set CCP on Time-Out 0x3 TIMER_TAMR_TCACT_SETTOGTO Set CCP immediately and toggle on Time-Out 0x4 TIMER_TAMR_TCACT_CLRTOGTO Clear CCP immediately and toggle on Time-Out 0x5 TIMER_TAMR_TCACT_SETCLRTO Set CCP immediately and clear on Time-Out 0x6 TIMER_TAMR_TCACT_CLRSETTO Clear CCP immediately and set on Time-Out 0x7 TIMER0TAPMR GPTM TimerA Prescale Match 0x40 read-write n 0x0 0x0 TIMER_TAPMR_TAPSMR GPTM TimerA Prescale Match 0 8 TIMER0TAPR GPTM Timer A Prescale 0x38 read-write n 0x0 0x0 TIMER_TAPR_TAPSR GPTM Timer A Prescale 0 8 TIMER0TAPS GPTM Timer A Prescale Snapshot 0x5C read-write n 0x0 0x0 TIMER_TAPS_PSS GPTM Timer A Prescaler Snapshot 0 16 TIMER0TAR GPTM Timer A 0x48 read-write n 0x0 0x0 TIMER0TAV GPTM Timer A Value 0x50 read-write n 0x0 0x0 TIMER0TBILR GPTM Timer B Interval Load 0x2C read-write n 0x0 0x0 TIMER0TBMATCHR GPTM Timer B Match 0x34 read-write n 0x0 0x0 TIMER0TBMR GPTM Timer B Mode 0x8 read-write n 0x0 0x0 TIMER_TBMR_TBAMS GPTM Timer B Alternate Mode Select 3 4 TIMER_TBMR_TBCDIR GPTM Timer B Count Direction 4 5 TIMER_TBMR_TBCINTD One-Shot/Periodic Interrupt Disable 12 13 TIMER_TBMR_TBCMR GPTM Timer B Capture Mode 2 3 TIMER_TBMR_TBILD GPTM Timer B Interval Load Write 8 9 TIMER_TBMR_TBMIE GPTM Timer B Match Interrupt Enable 5 6 TIMER_TBMR_TBMR GPTM Timer B Mode 0 2 TIMER_TBMR_TBMR_1_SHOT One-Shot Timer mode 0x1 TIMER_TBMR_TBMR_PERIOD Periodic Timer mode 0x2 TIMER_TBMR_TBMR_CAP Capture mode 0x3 TIMER_TBMR_TBMRSU GPTM Timer B Match Register Update 10 11 TIMER_TBMR_TBPLO GPTM Timer B PWM Legacy Operation 11 12 TIMER_TBMR_TBPWMIE GPTM Timer B PWM Interrupt Enable 9 10 TIMER_TBMR_TBSNAPS GPTM Timer B Snap-Shot Mode 7 8 TIMER_TBMR_TBWOT GPTM Timer B Wait-on-Trigger 6 7 TIMER_TBMR_TCACT Timer Compare Action Select 13 16 TIMER_TBMR_TCACT_NONE Disable compare operations 0x0 TIMER_TBMR_TCACT_TOGGLE Toggle State on Time-Out 0x1 TIMER_TBMR_TCACT_CLRTO Clear CCP on Time-Out 0x2 TIMER_TBMR_TCACT_SETTO Set CCP on Time-Out 0x3 TIMER_TBMR_TCACT_SETTOGTO Set CCP immediately and toggle on Time-Out 0x4 TIMER_TBMR_TCACT_CLRTOGTO Clear CCP immediately and toggle on Time-Out 0x5 TIMER_TBMR_TCACT_SETCLRTO Set CCP immediately and clear on Time-Out 0x6 TIMER_TBMR_TCACT_CLRSETTO Clear CCP immediately and set on Time-Out 0x7 TIMER0TBPMR GPTM TimerB Prescale Match 0x44 read-write n 0x0 0x0 TIMER_TBPMR_TBPSMR GPTM TimerB Prescale Match 0 8 TIMER0TBPR GPTM Timer B Prescale 0x3C read-write n 0x0 0x0 TIMER_TBPR_TBPSR GPTM Timer B Prescale 0 8 TIMER0TBPS GPTM Timer B Prescale Snapshot 0x60 read-write n 0x0 0x0 TIMER_TBPS_PSS GPTM Timer A Prescaler Value 0 16 TIMER0TBR GPTM Timer B 0x4C read-write n 0x0 0x0 TIMER0TBV GPTM Timer B Value 0x54 read-write n 0x0 0x0 TIMER3 Register map for TIMER0 peripheral TIMER 0x0 0x0 0x1000 registers n TIMER3A 35 TIMER3B 36 ADCEV GPTM ADC Event 0x70 -1 read-write n 0x0 0x0 TIMER_ADCEV_CAEADCEN GPTM A Capture Event ADC Trigger Enable 2 3 TIMER_ADCEV_CAMADCEN GPTM A Capture Match Event ADC Trigger Enable 1 2 TIMER_ADCEV_CBEADCEN GPTM B Capture Event ADC Trigger Enable 10 11 TIMER_ADCEV_CBMADCEN GPTM B Capture Match Event ADC Trigger Enable 9 10 TIMER_ADCEV_RTCADCEN GPTM RTC Match Event ADC Trigger Enable 3 4 TIMER_ADCEV_TAMADCEN GPTM A Mode Match Event ADC Trigger Enable 4 5 TIMER_ADCEV_TATOADCEN GPTM A Time-Out Event ADC Trigger Enable 0 1 TIMER_ADCEV_TBMADCEN GPTM B Mode Match Event ADC Trigger Enable 11 12 TIMER_ADCEV_TBTOADCEN GPTM B Time-Out Event ADC Trigger Enable 8 9 CC GPTM Clock Configuration 0xFC8 -1 read-write n 0x0 0x0 TIMER_CC_ALTCLK Alternate Clock Source 0 1 CFG GPTM Configuration 0x0 -1 read-write n 0x0 0x0 TIMER_CFG GPTM Configuration 0 3 TIMER_CFG_32_BIT_TIMER For a 16/32-bit timer, this value selects the 32-bit timer configuration 0x0 TIMER_CFG_32_BIT_RTC For a 16/32-bit timer, this value selects the 32-bit real-time clock (RTC) counter configuration 0x1 TIMER_CFG_16_BIT For a 16/32-bit timer, this value selects the 16-bit timer configuration 0x4 CTL GPTM Control 0xC -1 read-write n 0x0 0x0 TIMER_CTL_RTCEN GPTM RTC Stall Enable 4 5 TIMER_CTL_TAEN GPTM Timer A Enable 0 1 TIMER_CTL_TAEVENT GPTM Timer A Event Mode 2 4 TIMER_CTL_TAEVENT_POS Positive edge 0x0 TIMER_CTL_TAEVENT_NEG Negative edge 0x1 TIMER_CTL_TAEVENT_BOTH Both edges 0x3 TIMER_CTL_TAOTE GPTM Timer A Output Trigger Enable 5 6 TIMER_CTL_TAPWML GPTM Timer A PWM Output Level 6 7 TIMER_CTL_TASTALL GPTM Timer A Stall Enable 1 2 TIMER_CTL_TBEN GPTM Timer B Enable 8 9 TIMER_CTL_TBEVENT GPTM Timer B Event Mode 10 12 TIMER_CTL_TBEVENT_POS Positive edge 0x0 TIMER_CTL_TBEVENT_NEG Negative edge 0x1 TIMER_CTL_TBEVENT_BOTH Both edges 0x3 TIMER_CTL_TBOTE GPTM Timer B Output Trigger Enable 13 14 TIMER_CTL_TBPWML GPTM Timer B PWM Output Level 14 15 TIMER_CTL_TBSTALL GPTM Timer B Stall Enable 9 10 DMAEV GPTM DMA Event 0x6C -1 read-write n 0x0 0x0 TIMER_DMAEV_CAEDMAEN GPTM A Capture Event DMA Trigger Enable 2 3 TIMER_DMAEV_CAMDMAEN GPTM A Capture Match Event DMA Trigger Enable 1 2 TIMER_DMAEV_CBEDMAEN GPTM B Capture Event DMA Trigger Enable 10 11 TIMER_DMAEV_CBMDMAEN GPTM B Capture Match Event DMA Trigger Enable 9 10 TIMER_DMAEV_RTCDMAEN GPTM A RTC Match Event DMA Trigger Enable 3 4 TIMER_DMAEV_TAMDMAEN GPTM A Mode Match Event DMA Trigger Enable 4 5 TIMER_DMAEV_TATODMAEN GPTM A Time-Out Event DMA Trigger Enable 0 1 TIMER_DMAEV_TBMDMAEN GPTM B Mode Match Event DMA Trigger Enable 11 12 TIMER_DMAEV_TBTODMAEN GPTM B Time-Out Event DMA Trigger Enable 8 9 ICR GPTM Interrupt Clear 0x24 -1 write-only n 0x0 0x0 TIMER_ICR_CAECINT GPTM Timer A Capture Mode Event Interrupt Clear 2 3 write-only TIMER_ICR_CAMCINT GPTM Timer A Capture Mode Match Interrupt Clear 1 2 write-only TIMER_ICR_CBECINT GPTM Timer B Capture Mode Event Interrupt Clear 10 11 write-only TIMER_ICR_CBMCINT GPTM Timer B Capture Mode Match Interrupt Clear 9 10 write-only TIMER_ICR_DMAAINT GPTM Timer A DMA Done Interrupt Clear 5 6 write-only TIMER_ICR_DMABINT GPTM Timer B DMA Done Interrupt Clear 13 14 write-only TIMER_ICR_RTCCINT GPTM RTC Interrupt Clear 3 4 write-only TIMER_ICR_TAMCINT GPTM Timer A Match Interrupt Clear 4 5 write-only TIMER_ICR_TATOCINT GPTM Timer A Time-Out Raw Interrupt 0 1 write-only TIMER_ICR_TBMCINT GPTM Timer B Match Interrupt Clear 11 12 write-only TIMER_ICR_TBTOCINT GPTM Timer B Time-Out Interrupt Clear 8 9 write-only IMR GPTM Interrupt Mask 0x18 -1 read-write n 0x0 0x0 TIMER_IMR_CAEIM GPTM Timer A Capture Mode Event Interrupt Mask 2 3 TIMER_IMR_CAMIM GPTM Timer A Capture Mode Match Interrupt Mask 1 2 TIMER_IMR_CBEIM GPTM Timer B Capture Mode Event Interrupt Mask 10 11 TIMER_IMR_CBMIM GPTM Timer B Capture Mode Match Interrupt Mask 9 10 TIMER_IMR_DMAAIM GPTM Timer A DMA Done Interrupt Mask 5 6 TIMER_IMR_DMABIM GPTM Timer B DMA Done Interrupt Mask 13 14 TIMER_IMR_RTCIM GPTM RTC Interrupt Mask 3 4 TIMER_IMR_TAMIM GPTM Timer A Match Interrupt Mask 4 5 TIMER_IMR_TATOIM GPTM Timer A Time-Out Interrupt Mask 0 1 TIMER_IMR_TBMIM GPTM Timer B Match Interrupt Mask 11 12 TIMER_IMR_TBTOIM GPTM Timer B Time-Out Interrupt Mask 8 9 MIS GPTM Masked Interrupt Status 0x20 -1 read-write n 0x0 0x0 TIMER_MIS_CAEMIS GPTM Timer A Capture Mode Event Masked Interrupt 2 3 TIMER_MIS_CAMMIS GPTM Timer A Capture Mode Match Masked Interrupt 1 2 TIMER_MIS_CBEMIS GPTM Timer B Capture Mode Event Masked Interrupt 10 11 TIMER_MIS_CBMMIS GPTM Timer B Capture Mode Match Masked Interrupt 9 10 TIMER_MIS_DMAAMIS GPTM Timer A DMA Done Masked Interrupt 5 6 TIMER_MIS_DMABMIS GPTM Timer B DMA Done Masked Interrupt 13 14 TIMER_MIS_RTCMIS GPTM RTC Masked Interrupt 3 4 TIMER_MIS_TAMMIS GPTM Timer A Match Masked Interrupt 4 5 TIMER_MIS_TATOMIS GPTM Timer A Time-Out Masked Interrupt 0 1 TIMER_MIS_TBMMIS GPTM Timer B Match Masked Interrupt 11 12 TIMER_MIS_TBTOMIS GPTM Timer B Time-Out Masked Interrupt 8 9 PP GPTM Peripheral Properties 0xFC0 -1 read-write n 0x0 0x0 TIMER_PP_ALTCLK Alternate Clock Source 6 7 TIMER_PP_CHAIN Chain with Other Timers 4 5 TIMER_PP_SIZE Count Size 0 4 TIMER_PP_SIZE_16 Timer A and Timer B counters are 16 bits each with an 8-bit prescale counter 0x0 TIMER_PP_SIZE_32 Timer A and Timer B counters are 32 bits each with a 16-bit prescale counter 0x1 TIMER_PP_SYNCCNT Synchronize Start 5 6 RIS GPTM Raw Interrupt Status 0x1C -1 read-write n 0x0 0x0 TIMER_RIS_CAERIS GPTM Timer A Capture Mode Event Raw Interrupt 2 3 TIMER_RIS_CAMRIS GPTM Timer A Capture Mode Match Raw Interrupt 1 2 TIMER_RIS_CBERIS GPTM Timer B Capture Mode Event Raw Interrupt 10 11 TIMER_RIS_CBMRIS GPTM Timer B Capture Mode Match Raw Interrupt 9 10 TIMER_RIS_DMAARIS GPTM Timer A DMA Done Raw Interrupt Status 5 6 TIMER_RIS_DMABRIS GPTM Timer B DMA Done Raw Interrupt Status 13 14 TIMER_RIS_RTCRIS GPTM RTC Raw Interrupt 3 4 TIMER_RIS_TAMRIS GPTM Timer A Match Raw Interrupt 4 5 TIMER_RIS_TATORIS GPTM Timer A Time-Out Raw Interrupt 0 1 TIMER_RIS_TBMRIS GPTM Timer B Match Raw Interrupt 11 12 TIMER_RIS_TBTORIS GPTM Timer B Time-Out Raw Interrupt 8 9 RTCPD GPTM RTC Predivide 0x58 -1 read-write n 0x0 0x0 TIMER_RTCPD_RTCPD RTC Predivide Counter Value 0 16 SYNC GPTM Synchronize 0x10 -1 read-write n 0x0 0x0 TIMER_SYNC_SYNCT0 Synchronize GPTM Timer 0 0 2 TIMER_SYNC_SYNCT0_NONE GPTM0 is not affected 0x0 TIMER_SYNC_SYNCT0_TA A timeout event for Timer A of GPTM0 is triggered 0x1 TIMER_SYNC_SYNCT0_TB A timeout event for Timer B of GPTM0 is triggered 0x2 TIMER_SYNC_SYNCT0_TATB A timeout event for both Timer A and Timer B of GPTM0 is triggered 0x3 TIMER_SYNC_SYNCT1 Synchronize GPTM Timer 1 2 4 TIMER_SYNC_SYNCT1_NONE GPTM1 is not affected 0x0 TIMER_SYNC_SYNCT1_TA A timeout event for Timer A of GPTM1 is triggered 0x1 TIMER_SYNC_SYNCT1_TB A timeout event for Timer B of GPTM1 is triggered 0x2 TIMER_SYNC_SYNCT1_TATB A timeout event for both Timer A and Timer B of GPTM1 is triggered 0x3 TIMER_SYNC_SYNCT2 Synchronize GPTM Timer 2 4 6 TIMER_SYNC_SYNCT2_NONE GPTM2 is not affected 0x0 TIMER_SYNC_SYNCT2_TA A timeout event for Timer A of GPTM2 is triggered 0x1 TIMER_SYNC_SYNCT2_TB A timeout event for Timer B of GPTM2 is triggered 0x2 TIMER_SYNC_SYNCT2_TATB A timeout event for both Timer A and Timer B of GPTM2 is triggered 0x3 TIMER_SYNC_SYNCT3 Synchronize GPTM Timer 3 6 8 TIMER_SYNC_SYNCT3_NONE GPTM3 is not affected 0x0 TIMER_SYNC_SYNCT3_TA A timeout event for Timer A of GPTM3 is triggered 0x1 TIMER_SYNC_SYNCT3_TB A timeout event for Timer B of GPTM3 is triggered 0x2 TIMER_SYNC_SYNCT3_TATB A timeout event for both Timer A and Timer B of GPTM3 is triggered 0x3 TIMER_SYNC_SYNCT4 Synchronize GPTM Timer 4 8 10 TIMER_SYNC_SYNCT4_NONE GPTM4 is not affected 0x0 TIMER_SYNC_SYNCT4_TA A timeout event for Timer A of GPTM4 is triggered 0x1 TIMER_SYNC_SYNCT4_TB A timeout event for Timer B of GPTM4 is triggered 0x2 TIMER_SYNC_SYNCT4_TATB A timeout event for both Timer A and Timer B of GPTM4 is triggered 0x3 TIMER_SYNC_SYNCT5 Synchronize GPTM Timer 5 10 12 TIMER_SYNC_SYNCT5_NONE GPTM5 is not affected 0x0 TIMER_SYNC_SYNCT5_TA A timeout event for Timer A of GPTM5 is triggered 0x1 TIMER_SYNC_SYNCT5_TB A timeout event for Timer B of GPTM5 is triggered 0x2 TIMER_SYNC_SYNCT5_TATB A timeout event for both Timer A and Timer B of GPTM5 is triggered 0x3 TIMER_SYNC_SYNCT6 Synchronize GPTM Timer 6 12 14 TIMER_SYNC_SYNCT6_NONE GPTM6 is not affected 0x0 TIMER_SYNC_SYNCT6_TA A timeout event for Timer A of GPTM6 is triggered 0x1 TIMER_SYNC_SYNCT6_TB A timeout event for Timer B of GPTM6 is triggered 0x2 TIMER_SYNC_SYNCT6_TATB A timeout event for both Timer A and Timer B of GPTM6 is triggered 0x3 TIMER_SYNC_SYNCT7 Synchronize GPTM Timer 7 14 16 TIMER_SYNC_SYNCT7_NONE GPT7 is not affected 0x0 TIMER_SYNC_SYNCT7_TA A timeout event for Timer A of GPTM7 is triggered 0x1 TIMER_SYNC_SYNCT7_TB A timeout event for Timer B of GPTM7 is triggered 0x2 TIMER_SYNC_SYNCT7_TATB A timeout event for both Timer A and Timer B of GPTM7 is triggered 0x3 TAILR GPTM Timer A Interval Load 0x28 -1 read-write n 0x0 0x0 TAMATCHR GPTM Timer A Match 0x30 -1 read-write n 0x0 0x0 TAMR GPTM Timer A Mode 0x4 -1 read-write n 0x0 0x0 TIMER_TAMR_TAAMS GPTM Timer A Alternate Mode Select 3 4 TIMER_TAMR_TACDIR GPTM Timer A Count Direction 4 5 TIMER_TAMR_TACINTD One-shot/Periodic Interrupt Disable 12 13 TIMER_TAMR_TACMR GPTM Timer A Capture Mode 2 3 TIMER_TAMR_TAILD GPTM Timer A Interval Load Write 8 9 TIMER_TAMR_TAMIE GPTM Timer A Match Interrupt Enable 5 6 TIMER_TAMR_TAMR GPTM Timer A Mode 0 2 TIMER_TAMR_TAMR_1_SHOT One-Shot Timer mode 0x1 TIMER_TAMR_TAMR_PERIOD Periodic Timer mode 0x2 TIMER_TAMR_TAMR_CAP Capture mode 0x3 TIMER_TAMR_TAMRSU GPTM Timer A Match Register Update 10 11 TIMER_TAMR_TAPLO GPTM Timer A PWM Legacy Operation 11 12 TIMER_TAMR_TAPWMIE GPTM Timer A PWM Interrupt Enable 9 10 TIMER_TAMR_TASNAPS GPTM Timer A Snap-Shot Mode 7 8 TIMER_TAMR_TAWOT GPTM Timer A Wait-on-Trigger 6 7 TIMER_TAMR_TCACT Timer Compare Action Select 13 16 TIMER_TAMR_TCACT_NONE Disable compare operations 0x0 TIMER_TAMR_TCACT_TOGGLE Toggle State on Time-Out 0x1 TIMER_TAMR_TCACT_CLRTO Clear CCP on Time-Out 0x2 TIMER_TAMR_TCACT_SETTO Set CCP on Time-Out 0x3 TIMER_TAMR_TCACT_SETTOGTO Set CCP immediately and toggle on Time-Out 0x4 TIMER_TAMR_TCACT_CLRTOGTO Clear CCP immediately and toggle on Time-Out 0x5 TIMER_TAMR_TCACT_SETCLRTO Set CCP immediately and clear on Time-Out 0x6 TIMER_TAMR_TCACT_CLRSETTO Clear CCP immediately and set on Time-Out 0x7 TAPMR GPTM TimerA Prescale Match 0x40 -1 read-write n 0x0 0x0 TIMER_TAPMR_TAPSMR GPTM TimerA Prescale Match 0 8 TAPR GPTM Timer A Prescale 0x38 -1 read-write n 0x0 0x0 TIMER_TAPR_TAPSR GPTM Timer A Prescale 0 8 TAPS GPTM Timer A Prescale Snapshot 0x5C -1 read-write n 0x0 0x0 TIMER_TAPS_PSS GPTM Timer A Prescaler Snapshot 0 16 TAR GPTM Timer A 0x48 -1 read-write n 0x0 0x0 TAV GPTM Timer A Value 0x50 -1 read-write n 0x0 0x0 TBILR GPTM Timer B Interval Load 0x2C -1 read-write n 0x0 0x0 TBMATCHR GPTM Timer B Match 0x34 -1 read-write n 0x0 0x0 TBMR GPTM Timer B Mode 0x8 -1 read-write n 0x0 0x0 TIMER_TBMR_TBAMS GPTM Timer B Alternate Mode Select 3 4 TIMER_TBMR_TBCDIR GPTM Timer B Count Direction 4 5 TIMER_TBMR_TBCINTD One-Shot/Periodic Interrupt Disable 12 13 TIMER_TBMR_TBCMR GPTM Timer B Capture Mode 2 3 TIMER_TBMR_TBILD GPTM Timer B Interval Load Write 8 9 TIMER_TBMR_TBMIE GPTM Timer B Match Interrupt Enable 5 6 TIMER_TBMR_TBMR GPTM Timer B Mode 0 2 TIMER_TBMR_TBMR_1_SHOT One-Shot Timer mode 0x1 TIMER_TBMR_TBMR_PERIOD Periodic Timer mode 0x2 TIMER_TBMR_TBMR_CAP Capture mode 0x3 TIMER_TBMR_TBMRSU GPTM Timer B Match Register Update 10 11 TIMER_TBMR_TBPLO GPTM Timer B PWM Legacy Operation 11 12 TIMER_TBMR_TBPWMIE GPTM Timer B PWM Interrupt Enable 9 10 TIMER_TBMR_TBSNAPS GPTM Timer B Snap-Shot Mode 7 8 TIMER_TBMR_TBWOT GPTM Timer B Wait-on-Trigger 6 7 TIMER_TBMR_TCACT Timer Compare Action Select 13 16 TIMER_TBMR_TCACT_NONE Disable compare operations 0x0 TIMER_TBMR_TCACT_TOGGLE Toggle State on Time-Out 0x1 TIMER_TBMR_TCACT_CLRTO Clear CCP on Time-Out 0x2 TIMER_TBMR_TCACT_SETTO Set CCP on Time-Out 0x3 TIMER_TBMR_TCACT_SETTOGTO Set CCP immediately and toggle on Time-Out 0x4 TIMER_TBMR_TCACT_CLRTOGTO Clear CCP immediately and toggle on Time-Out 0x5 TIMER_TBMR_TCACT_SETCLRTO Set CCP immediately and clear on Time-Out 0x6 TIMER_TBMR_TCACT_CLRSETTO Clear CCP immediately and set on Time-Out 0x7 TBPMR GPTM TimerB Prescale Match 0x44 -1 read-write n 0x0 0x0 TIMER_TBPMR_TBPSMR GPTM TimerB Prescale Match 0 8 TBPR GPTM Timer B Prescale 0x3C -1 read-write n 0x0 0x0 TIMER_TBPR_TBPSR GPTM Timer B Prescale 0 8 TBPS GPTM Timer B Prescale Snapshot 0x60 -1 read-write n 0x0 0x0 TIMER_TBPS_PSS GPTM Timer A Prescaler Value 0 16 TBR GPTM Timer B 0x4C -1 read-write n 0x0 0x0 TBV GPTM Timer B Value 0x54 -1 read-write n 0x0 0x0 TIMER0ADCEV GPTM ADC Event 0x70 read-write n 0x0 0x0 TIMER_ADCEV_CAEADCEN GPTM A Capture Event ADC Trigger Enable 2 3 TIMER_ADCEV_CAMADCEN GPTM A Capture Match Event ADC Trigger Enable 1 2 TIMER_ADCEV_CBEADCEN GPTM B Capture Event ADC Trigger Enable 10 11 TIMER_ADCEV_CBMADCEN GPTM B Capture Match Event ADC Trigger Enable 9 10 TIMER_ADCEV_RTCADCEN GPTM RTC Match Event ADC Trigger Enable 3 4 TIMER_ADCEV_TAMADCEN GPTM A Mode Match Event ADC Trigger Enable 4 5 TIMER_ADCEV_TATOADCEN GPTM A Time-Out Event ADC Trigger Enable 0 1 TIMER_ADCEV_TBMADCEN GPTM B Mode Match Event ADC Trigger Enable 11 12 TIMER_ADCEV_TBTOADCEN GPTM B Time-Out Event ADC Trigger Enable 8 9 TIMER0CC GPTM Clock Configuration 0xFC8 read-write n 0x0 0x0 TIMER_CC_ALTCLK Alternate Clock Source 0 1 TIMER0CFG GPTM Configuration 0x0 read-write n 0x0 0x0 TIMER_CFG GPTM Configuration 0 3 TIMER_CFG_32_BIT_TIMER For a 16/32-bit timer, this value selects the 32-bit timer configuration 0x0 TIMER_CFG_32_BIT_RTC For a 16/32-bit timer, this value selects the 32-bit real-time clock (RTC) counter configuration 0x1 TIMER_CFG_16_BIT For a 16/32-bit timer, this value selects the 16-bit timer configuration 0x4 TIMER0CTL GPTM Control 0xC read-write n 0x0 0x0 TIMER_CTL_RTCEN GPTM RTC Stall Enable 4 5 TIMER_CTL_TAEN GPTM Timer A Enable 0 1 TIMER_CTL_TAEVENT GPTM Timer A Event Mode 2 4 TIMER_CTL_TAEVENT_POS Positive edge 0x0 TIMER_CTL_TAEVENT_NEG Negative edge 0x1 TIMER_CTL_TAEVENT_BOTH Both edges 0x3 TIMER_CTL_TAOTE GPTM Timer A Output Trigger Enable 5 6 TIMER_CTL_TAPWML GPTM Timer A PWM Output Level 6 7 TIMER_CTL_TASTALL GPTM Timer A Stall Enable 1 2 TIMER_CTL_TBEN GPTM Timer B Enable 8 9 TIMER_CTL_TBEVENT GPTM Timer B Event Mode 10 12 TIMER_CTL_TBEVENT_POS Positive edge 0x0 TIMER_CTL_TBEVENT_NEG Negative edge 0x1 TIMER_CTL_TBEVENT_BOTH Both edges 0x3 TIMER_CTL_TBOTE GPTM Timer B Output Trigger Enable 13 14 TIMER_CTL_TBPWML GPTM Timer B PWM Output Level 14 15 TIMER_CTL_TBSTALL GPTM Timer B Stall Enable 9 10 TIMER0DMAEV GPTM DMA Event 0x6C read-write n 0x0 0x0 TIMER_DMAEV_CAEDMAEN GPTM A Capture Event DMA Trigger Enable 2 3 TIMER_DMAEV_CAMDMAEN GPTM A Capture Match Event DMA Trigger Enable 1 2 TIMER_DMAEV_CBEDMAEN GPTM B Capture Event DMA Trigger Enable 10 11 TIMER_DMAEV_CBMDMAEN GPTM B Capture Match Event DMA Trigger Enable 9 10 TIMER_DMAEV_RTCDMAEN GPTM A RTC Match Event DMA Trigger Enable 3 4 TIMER_DMAEV_TAMDMAEN GPTM A Mode Match Event DMA Trigger Enable 4 5 TIMER_DMAEV_TATODMAEN GPTM A Time-Out Event DMA Trigger Enable 0 1 TIMER_DMAEV_TBMDMAEN GPTM B Mode Match Event DMA Trigger Enable 11 12 TIMER_DMAEV_TBTODMAEN GPTM B Time-Out Event DMA Trigger Enable 8 9 TIMER0ICR GPTM Interrupt Clear 0x24 write-only n 0x0 0x0 TIMER_ICR_CAECINT GPTM Timer A Capture Mode Event Interrupt Clear 2 3 write-only TIMER_ICR_CAMCINT GPTM Timer A Capture Mode Match Interrupt Clear 1 2 write-only TIMER_ICR_CBECINT GPTM Timer B Capture Mode Event Interrupt Clear 10 11 write-only TIMER_ICR_CBMCINT GPTM Timer B Capture Mode Match Interrupt Clear 9 10 write-only TIMER_ICR_DMAAINT GPTM Timer A DMA Done Interrupt Clear 5 6 write-only TIMER_ICR_DMABINT GPTM Timer B DMA Done Interrupt Clear 13 14 write-only TIMER_ICR_RTCCINT GPTM RTC Interrupt Clear 3 4 write-only TIMER_ICR_TAMCINT GPTM Timer A Match Interrupt Clear 4 5 write-only TIMER_ICR_TATOCINT GPTM Timer A Time-Out Raw Interrupt 0 1 write-only TIMER_ICR_TBMCINT GPTM Timer B Match Interrupt Clear 11 12 write-only TIMER_ICR_TBTOCINT GPTM Timer B Time-Out Interrupt Clear 8 9 write-only TIMER0IMR GPTM Interrupt Mask 0x18 read-write n 0x0 0x0 TIMER_IMR_CAEIM GPTM Timer A Capture Mode Event Interrupt Mask 2 3 TIMER_IMR_CAMIM GPTM Timer A Capture Mode Match Interrupt Mask 1 2 TIMER_IMR_CBEIM GPTM Timer B Capture Mode Event Interrupt Mask 10 11 TIMER_IMR_CBMIM GPTM Timer B Capture Mode Match Interrupt Mask 9 10 TIMER_IMR_DMAAIM GPTM Timer A DMA Done Interrupt Mask 5 6 TIMER_IMR_DMABIM GPTM Timer B DMA Done Interrupt Mask 13 14 TIMER_IMR_RTCIM GPTM RTC Interrupt Mask 3 4 TIMER_IMR_TAMIM GPTM Timer A Match Interrupt Mask 4 5 TIMER_IMR_TATOIM GPTM Timer A Time-Out Interrupt Mask 0 1 TIMER_IMR_TBMIM GPTM Timer B Match Interrupt Mask 11 12 TIMER_IMR_TBTOIM GPTM Timer B Time-Out Interrupt Mask 8 9 TIMER0MIS GPTM Masked Interrupt Status 0x20 read-write n 0x0 0x0 TIMER_MIS_CAEMIS GPTM Timer A Capture Mode Event Masked Interrupt 2 3 TIMER_MIS_CAMMIS GPTM Timer A Capture Mode Match Masked Interrupt 1 2 TIMER_MIS_CBEMIS GPTM Timer B Capture Mode Event Masked Interrupt 10 11 TIMER_MIS_CBMMIS GPTM Timer B Capture Mode Match Masked Interrupt 9 10 TIMER_MIS_DMAAMIS GPTM Timer A DMA Done Masked Interrupt 5 6 TIMER_MIS_DMABMIS GPTM Timer B DMA Done Masked Interrupt 13 14 TIMER_MIS_RTCMIS GPTM RTC Masked Interrupt 3 4 TIMER_MIS_TAMMIS GPTM Timer A Match Masked Interrupt 4 5 TIMER_MIS_TATOMIS GPTM Timer A Time-Out Masked Interrupt 0 1 TIMER_MIS_TBMMIS GPTM Timer B Match Masked Interrupt 11 12 TIMER_MIS_TBTOMIS GPTM Timer B Time-Out Masked Interrupt 8 9 TIMER0PP GPTM Peripheral Properties 0xFC0 read-write n 0x0 0x0 TIMER_PP_ALTCLK Alternate Clock Source 6 7 TIMER_PP_CHAIN Chain with Other Timers 4 5 TIMER_PP_SIZE Count Size 0 4 TIMER_PP_SIZE_16 Timer A and Timer B counters are 16 bits each with an 8-bit prescale counter 0x0 TIMER_PP_SIZE_32 Timer A and Timer B counters are 32 bits each with a 16-bit prescale counter 0x1 TIMER_PP_SYNCCNT Synchronize Start 5 6 TIMER0RIS GPTM Raw Interrupt Status 0x1C read-write n 0x0 0x0 TIMER_RIS_CAERIS GPTM Timer A Capture Mode Event Raw Interrupt 2 3 TIMER_RIS_CAMRIS GPTM Timer A Capture Mode Match Raw Interrupt 1 2 TIMER_RIS_CBERIS GPTM Timer B Capture Mode Event Raw Interrupt 10 11 TIMER_RIS_CBMRIS GPTM Timer B Capture Mode Match Raw Interrupt 9 10 TIMER_RIS_DMAARIS GPTM Timer A DMA Done Raw Interrupt Status 5 6 TIMER_RIS_DMABRIS GPTM Timer B DMA Done Raw Interrupt Status 13 14 TIMER_RIS_RTCRIS GPTM RTC Raw Interrupt 3 4 TIMER_RIS_TAMRIS GPTM Timer A Match Raw Interrupt 4 5 TIMER_RIS_TATORIS GPTM Timer A Time-Out Raw Interrupt 0 1 TIMER_RIS_TBMRIS GPTM Timer B Match Raw Interrupt 11 12 TIMER_RIS_TBTORIS GPTM Timer B Time-Out Raw Interrupt 8 9 TIMER0RTCPD GPTM RTC Predivide 0x58 read-write n 0x0 0x0 TIMER_RTCPD_RTCPD RTC Predivide Counter Value 0 16 TIMER0SYNC GPTM Synchronize 0x10 read-write n 0x0 0x0 TIMER_SYNC_SYNCT0 Synchronize GPTM Timer 0 0 2 TIMER_SYNC_SYNCT0_NONE GPTM0 is not affected 0x0 TIMER_SYNC_SYNCT0_TA A timeout event for Timer A of GPTM0 is triggered 0x1 TIMER_SYNC_SYNCT0_TB A timeout event for Timer B of GPTM0 is triggered 0x2 TIMER_SYNC_SYNCT0_TATB A timeout event for both Timer A and Timer B of GPTM0 is triggered 0x3 TIMER_SYNC_SYNCT1 Synchronize GPTM Timer 1 2 4 TIMER_SYNC_SYNCT1_NONE GPTM1 is not affected 0x0 TIMER_SYNC_SYNCT1_TA A timeout event for Timer A of GPTM1 is triggered 0x1 TIMER_SYNC_SYNCT1_TB A timeout event for Timer B of GPTM1 is triggered 0x2 TIMER_SYNC_SYNCT1_TATB A timeout event for both Timer A and Timer B of GPTM1 is triggered 0x3 TIMER_SYNC_SYNCT2 Synchronize GPTM Timer 2 4 6 TIMER_SYNC_SYNCT2_NONE GPTM2 is not affected 0x0 TIMER_SYNC_SYNCT2_TA A timeout event for Timer A of GPTM2 is triggered 0x1 TIMER_SYNC_SYNCT2_TB A timeout event for Timer B of GPTM2 is triggered 0x2 TIMER_SYNC_SYNCT2_TATB A timeout event for both Timer A and Timer B of GPTM2 is triggered 0x3 TIMER_SYNC_SYNCT3 Synchronize GPTM Timer 3 6 8 TIMER_SYNC_SYNCT3_NONE GPTM3 is not affected 0x0 TIMER_SYNC_SYNCT3_TA A timeout event for Timer A of GPTM3 is triggered 0x1 TIMER_SYNC_SYNCT3_TB A timeout event for Timer B of GPTM3 is triggered 0x2 TIMER_SYNC_SYNCT3_TATB A timeout event for both Timer A and Timer B of GPTM3 is triggered 0x3 TIMER_SYNC_SYNCT4 Synchronize GPTM Timer 4 8 10 TIMER_SYNC_SYNCT4_NONE GPTM4 is not affected 0x0 TIMER_SYNC_SYNCT4_TA A timeout event for Timer A of GPTM4 is triggered 0x1 TIMER_SYNC_SYNCT4_TB A timeout event for Timer B of GPTM4 is triggered 0x2 TIMER_SYNC_SYNCT4_TATB A timeout event for both Timer A and Timer B of GPTM4 is triggered 0x3 TIMER_SYNC_SYNCT5 Synchronize GPTM Timer 5 10 12 TIMER_SYNC_SYNCT5_NONE GPTM5 is not affected 0x0 TIMER_SYNC_SYNCT5_TA A timeout event for Timer A of GPTM5 is triggered 0x1 TIMER_SYNC_SYNCT5_TB A timeout event for Timer B of GPTM5 is triggered 0x2 TIMER_SYNC_SYNCT5_TATB A timeout event for both Timer A and Timer B of GPTM5 is triggered 0x3 TIMER_SYNC_SYNCT6 Synchronize GPTM Timer 6 12 14 TIMER_SYNC_SYNCT6_NONE GPTM6 is not affected 0x0 TIMER_SYNC_SYNCT6_TA A timeout event for Timer A of GPTM6 is triggered 0x1 TIMER_SYNC_SYNCT6_TB A timeout event for Timer B of GPTM6 is triggered 0x2 TIMER_SYNC_SYNCT6_TATB A timeout event for both Timer A and Timer B of GPTM6 is triggered 0x3 TIMER_SYNC_SYNCT7 Synchronize GPTM Timer 7 14 16 TIMER_SYNC_SYNCT7_NONE GPT7 is not affected 0x0 TIMER_SYNC_SYNCT7_TA A timeout event for Timer A of GPTM7 is triggered 0x1 TIMER_SYNC_SYNCT7_TB A timeout event for Timer B of GPTM7 is triggered 0x2 TIMER_SYNC_SYNCT7_TATB A timeout event for both Timer A and Timer B of GPTM7 is triggered 0x3 TIMER0TAILR GPTM Timer A Interval Load 0x28 read-write n 0x0 0x0 TIMER0TAMATCHR GPTM Timer A Match 0x30 read-write n 0x0 0x0 TIMER0TAMR GPTM Timer A Mode 0x4 read-write n 0x0 0x0 TIMER_TAMR_TAAMS GPTM Timer A Alternate Mode Select 3 4 TIMER_TAMR_TACDIR GPTM Timer A Count Direction 4 5 TIMER_TAMR_TACINTD One-shot/Periodic Interrupt Disable 12 13 TIMER_TAMR_TACMR GPTM Timer A Capture Mode 2 3 TIMER_TAMR_TAILD GPTM Timer A Interval Load Write 8 9 TIMER_TAMR_TAMIE GPTM Timer A Match Interrupt Enable 5 6 TIMER_TAMR_TAMR GPTM Timer A Mode 0 2 TIMER_TAMR_TAMR_1_SHOT One-Shot Timer mode 0x1 TIMER_TAMR_TAMR_PERIOD Periodic Timer mode 0x2 TIMER_TAMR_TAMR_CAP Capture mode 0x3 TIMER_TAMR_TAMRSU GPTM Timer A Match Register Update 10 11 TIMER_TAMR_TAPLO GPTM Timer A PWM Legacy Operation 11 12 TIMER_TAMR_TAPWMIE GPTM Timer A PWM Interrupt Enable 9 10 TIMER_TAMR_TASNAPS GPTM Timer A Snap-Shot Mode 7 8 TIMER_TAMR_TAWOT GPTM Timer A Wait-on-Trigger 6 7 TIMER_TAMR_TCACT Timer Compare Action Select 13 16 TIMER_TAMR_TCACT_NONE Disable compare operations 0x0 TIMER_TAMR_TCACT_TOGGLE Toggle State on Time-Out 0x1 TIMER_TAMR_TCACT_CLRTO Clear CCP on Time-Out 0x2 TIMER_TAMR_TCACT_SETTO Set CCP on Time-Out 0x3 TIMER_TAMR_TCACT_SETTOGTO Set CCP immediately and toggle on Time-Out 0x4 TIMER_TAMR_TCACT_CLRTOGTO Clear CCP immediately and toggle on Time-Out 0x5 TIMER_TAMR_TCACT_SETCLRTO Set CCP immediately and clear on Time-Out 0x6 TIMER_TAMR_TCACT_CLRSETTO Clear CCP immediately and set on Time-Out 0x7 TIMER0TAPMR GPTM TimerA Prescale Match 0x40 read-write n 0x0 0x0 TIMER_TAPMR_TAPSMR GPTM TimerA Prescale Match 0 8 TIMER0TAPR GPTM Timer A Prescale 0x38 read-write n 0x0 0x0 TIMER_TAPR_TAPSR GPTM Timer A Prescale 0 8 TIMER0TAPS GPTM Timer A Prescale Snapshot 0x5C read-write n 0x0 0x0 TIMER_TAPS_PSS GPTM Timer A Prescaler Snapshot 0 16 TIMER0TAR GPTM Timer A 0x48 read-write n 0x0 0x0 TIMER0TAV GPTM Timer A Value 0x50 read-write n 0x0 0x0 TIMER0TBILR GPTM Timer B Interval Load 0x2C read-write n 0x0 0x0 TIMER0TBMATCHR GPTM Timer B Match 0x34 read-write n 0x0 0x0 TIMER0TBMR GPTM Timer B Mode 0x8 read-write n 0x0 0x0 TIMER_TBMR_TBAMS GPTM Timer B Alternate Mode Select 3 4 TIMER_TBMR_TBCDIR GPTM Timer B Count Direction 4 5 TIMER_TBMR_TBCINTD One-Shot/Periodic Interrupt Disable 12 13 TIMER_TBMR_TBCMR GPTM Timer B Capture Mode 2 3 TIMER_TBMR_TBILD GPTM Timer B Interval Load Write 8 9 TIMER_TBMR_TBMIE GPTM Timer B Match Interrupt Enable 5 6 TIMER_TBMR_TBMR GPTM Timer B Mode 0 2 TIMER_TBMR_TBMR_1_SHOT One-Shot Timer mode 0x1 TIMER_TBMR_TBMR_PERIOD Periodic Timer mode 0x2 TIMER_TBMR_TBMR_CAP Capture mode 0x3 TIMER_TBMR_TBMRSU GPTM Timer B Match Register Update 10 11 TIMER_TBMR_TBPLO GPTM Timer B PWM Legacy Operation 11 12 TIMER_TBMR_TBPWMIE GPTM Timer B PWM Interrupt Enable 9 10 TIMER_TBMR_TBSNAPS GPTM Timer B Snap-Shot Mode 7 8 TIMER_TBMR_TBWOT GPTM Timer B Wait-on-Trigger 6 7 TIMER_TBMR_TCACT Timer Compare Action Select 13 16 TIMER_TBMR_TCACT_NONE Disable compare operations 0x0 TIMER_TBMR_TCACT_TOGGLE Toggle State on Time-Out 0x1 TIMER_TBMR_TCACT_CLRTO Clear CCP on Time-Out 0x2 TIMER_TBMR_TCACT_SETTO Set CCP on Time-Out 0x3 TIMER_TBMR_TCACT_SETTOGTO Set CCP immediately and toggle on Time-Out 0x4 TIMER_TBMR_TCACT_CLRTOGTO Clear CCP immediately and toggle on Time-Out 0x5 TIMER_TBMR_TCACT_SETCLRTO Set CCP immediately and clear on Time-Out 0x6 TIMER_TBMR_TCACT_CLRSETTO Clear CCP immediately and set on Time-Out 0x7 TIMER0TBPMR GPTM TimerB Prescale Match 0x44 read-write n 0x0 0x0 TIMER_TBPMR_TBPSMR GPTM TimerB Prescale Match 0 8 TIMER0TBPR GPTM Timer B Prescale 0x3C read-write n 0x0 0x0 TIMER_TBPR_TBPSR GPTM Timer B Prescale 0 8 TIMER0TBPS GPTM Timer B Prescale Snapshot 0x60 read-write n 0x0 0x0 TIMER_TBPS_PSS GPTM Timer A Prescaler Value 0 16 TIMER0TBR GPTM Timer B 0x4C read-write n 0x0 0x0 TIMER0TBV GPTM Timer B Value 0x54 read-write n 0x0 0x0 TIMER4 Register map for TIMER0 peripheral TIMER 0x0 0x0 0x1000 registers n TIMER4A 63 TIMER4B 64 ADCEV GPTM ADC Event 0x70 -1 read-write n 0x0 0x0 TIMER_ADCEV_CAEADCEN GPTM A Capture Event ADC Trigger Enable 2 3 TIMER_ADCEV_CAMADCEN GPTM A Capture Match Event ADC Trigger Enable 1 2 TIMER_ADCEV_CBEADCEN GPTM B Capture Event ADC Trigger Enable 10 11 TIMER_ADCEV_CBMADCEN GPTM B Capture Match Event ADC Trigger Enable 9 10 TIMER_ADCEV_RTCADCEN GPTM RTC Match Event ADC Trigger Enable 3 4 TIMER_ADCEV_TAMADCEN GPTM A Mode Match Event ADC Trigger Enable 4 5 TIMER_ADCEV_TATOADCEN GPTM A Time-Out Event ADC Trigger Enable 0 1 TIMER_ADCEV_TBMADCEN GPTM B Mode Match Event ADC Trigger Enable 11 12 TIMER_ADCEV_TBTOADCEN GPTM B Time-Out Event ADC Trigger Enable 8 9 CC GPTM Clock Configuration 0xFC8 -1 read-write n 0x0 0x0 TIMER_CC_ALTCLK Alternate Clock Source 0 1 CFG GPTM Configuration 0x0 -1 read-write n 0x0 0x0 TIMER_CFG GPTM Configuration 0 3 TIMER_CFG_32_BIT_TIMER For a 16/32-bit timer, this value selects the 32-bit timer configuration 0x0 TIMER_CFG_32_BIT_RTC For a 16/32-bit timer, this value selects the 32-bit real-time clock (RTC) counter configuration 0x1 TIMER_CFG_16_BIT For a 16/32-bit timer, this value selects the 16-bit timer configuration 0x4 CTL GPTM Control 0xC -1 read-write n 0x0 0x0 TIMER_CTL_RTCEN GPTM RTC Stall Enable 4 5 TIMER_CTL_TAEN GPTM Timer A Enable 0 1 TIMER_CTL_TAEVENT GPTM Timer A Event Mode 2 4 TIMER_CTL_TAEVENT_POS Positive edge 0x0 TIMER_CTL_TAEVENT_NEG Negative edge 0x1 TIMER_CTL_TAEVENT_BOTH Both edges 0x3 TIMER_CTL_TAOTE GPTM Timer A Output Trigger Enable 5 6 TIMER_CTL_TAPWML GPTM Timer A PWM Output Level 6 7 TIMER_CTL_TASTALL GPTM Timer A Stall Enable 1 2 TIMER_CTL_TBEN GPTM Timer B Enable 8 9 TIMER_CTL_TBEVENT GPTM Timer B Event Mode 10 12 TIMER_CTL_TBEVENT_POS Positive edge 0x0 TIMER_CTL_TBEVENT_NEG Negative edge 0x1 TIMER_CTL_TBEVENT_BOTH Both edges 0x3 TIMER_CTL_TBOTE GPTM Timer B Output Trigger Enable 13 14 TIMER_CTL_TBPWML GPTM Timer B PWM Output Level 14 15 TIMER_CTL_TBSTALL GPTM Timer B Stall Enable 9 10 DMAEV GPTM DMA Event 0x6C -1 read-write n 0x0 0x0 TIMER_DMAEV_CAEDMAEN GPTM A Capture Event DMA Trigger Enable 2 3 TIMER_DMAEV_CAMDMAEN GPTM A Capture Match Event DMA Trigger Enable 1 2 TIMER_DMAEV_CBEDMAEN GPTM B Capture Event DMA Trigger Enable 10 11 TIMER_DMAEV_CBMDMAEN GPTM B Capture Match Event DMA Trigger Enable 9 10 TIMER_DMAEV_RTCDMAEN GPTM A RTC Match Event DMA Trigger Enable 3 4 TIMER_DMAEV_TAMDMAEN GPTM A Mode Match Event DMA Trigger Enable 4 5 TIMER_DMAEV_TATODMAEN GPTM A Time-Out Event DMA Trigger Enable 0 1 TIMER_DMAEV_TBMDMAEN GPTM B Mode Match Event DMA Trigger Enable 11 12 TIMER_DMAEV_TBTODMAEN GPTM B Time-Out Event DMA Trigger Enable 8 9 ICR GPTM Interrupt Clear 0x24 -1 write-only n 0x0 0x0 TIMER_ICR_CAECINT GPTM Timer A Capture Mode Event Interrupt Clear 2 3 write-only TIMER_ICR_CAMCINT GPTM Timer A Capture Mode Match Interrupt Clear 1 2 write-only TIMER_ICR_CBECINT GPTM Timer B Capture Mode Event Interrupt Clear 10 11 write-only TIMER_ICR_CBMCINT GPTM Timer B Capture Mode Match Interrupt Clear 9 10 write-only TIMER_ICR_DMAAINT GPTM Timer A DMA Done Interrupt Clear 5 6 write-only TIMER_ICR_DMABINT GPTM Timer B DMA Done Interrupt Clear 13 14 write-only TIMER_ICR_RTCCINT GPTM RTC Interrupt Clear 3 4 write-only TIMER_ICR_TAMCINT GPTM Timer A Match Interrupt Clear 4 5 write-only TIMER_ICR_TATOCINT GPTM Timer A Time-Out Raw Interrupt 0 1 write-only TIMER_ICR_TBMCINT GPTM Timer B Match Interrupt Clear 11 12 write-only TIMER_ICR_TBTOCINT GPTM Timer B Time-Out Interrupt Clear 8 9 write-only IMR GPTM Interrupt Mask 0x18 -1 read-write n 0x0 0x0 TIMER_IMR_CAEIM GPTM Timer A Capture Mode Event Interrupt Mask 2 3 TIMER_IMR_CAMIM GPTM Timer A Capture Mode Match Interrupt Mask 1 2 TIMER_IMR_CBEIM GPTM Timer B Capture Mode Event Interrupt Mask 10 11 TIMER_IMR_CBMIM GPTM Timer B Capture Mode Match Interrupt Mask 9 10 TIMER_IMR_DMAAIM GPTM Timer A DMA Done Interrupt Mask 5 6 TIMER_IMR_DMABIM GPTM Timer B DMA Done Interrupt Mask 13 14 TIMER_IMR_RTCIM GPTM RTC Interrupt Mask 3 4 TIMER_IMR_TAMIM GPTM Timer A Match Interrupt Mask 4 5 TIMER_IMR_TATOIM GPTM Timer A Time-Out Interrupt Mask 0 1 TIMER_IMR_TBMIM GPTM Timer B Match Interrupt Mask 11 12 TIMER_IMR_TBTOIM GPTM Timer B Time-Out Interrupt Mask 8 9 MIS GPTM Masked Interrupt Status 0x20 -1 read-write n 0x0 0x0 TIMER_MIS_CAEMIS GPTM Timer A Capture Mode Event Masked Interrupt 2 3 TIMER_MIS_CAMMIS GPTM Timer A Capture Mode Match Masked Interrupt 1 2 TIMER_MIS_CBEMIS GPTM Timer B Capture Mode Event Masked Interrupt 10 11 TIMER_MIS_CBMMIS GPTM Timer B Capture Mode Match Masked Interrupt 9 10 TIMER_MIS_DMAAMIS GPTM Timer A DMA Done Masked Interrupt 5 6 TIMER_MIS_DMABMIS GPTM Timer B DMA Done Masked Interrupt 13 14 TIMER_MIS_RTCMIS GPTM RTC Masked Interrupt 3 4 TIMER_MIS_TAMMIS GPTM Timer A Match Masked Interrupt 4 5 TIMER_MIS_TATOMIS GPTM Timer A Time-Out Masked Interrupt 0 1 TIMER_MIS_TBMMIS GPTM Timer B Match Masked Interrupt 11 12 TIMER_MIS_TBTOMIS GPTM Timer B Time-Out Masked Interrupt 8 9 PP GPTM Peripheral Properties 0xFC0 -1 read-write n 0x0 0x0 TIMER_PP_ALTCLK Alternate Clock Source 6 7 TIMER_PP_CHAIN Chain with Other Timers 4 5 TIMER_PP_SIZE Count Size 0 4 TIMER_PP_SIZE_16 Timer A and Timer B counters are 16 bits each with an 8-bit prescale counter 0x0 TIMER_PP_SIZE_32 Timer A and Timer B counters are 32 bits each with a 16-bit prescale counter 0x1 TIMER_PP_SYNCCNT Synchronize Start 5 6 RIS GPTM Raw Interrupt Status 0x1C -1 read-write n 0x0 0x0 TIMER_RIS_CAERIS GPTM Timer A Capture Mode Event Raw Interrupt 2 3 TIMER_RIS_CAMRIS GPTM Timer A Capture Mode Match Raw Interrupt 1 2 TIMER_RIS_CBERIS GPTM Timer B Capture Mode Event Raw Interrupt 10 11 TIMER_RIS_CBMRIS GPTM Timer B Capture Mode Match Raw Interrupt 9 10 TIMER_RIS_DMAARIS GPTM Timer A DMA Done Raw Interrupt Status 5 6 TIMER_RIS_DMABRIS GPTM Timer B DMA Done Raw Interrupt Status 13 14 TIMER_RIS_RTCRIS GPTM RTC Raw Interrupt 3 4 TIMER_RIS_TAMRIS GPTM Timer A Match Raw Interrupt 4 5 TIMER_RIS_TATORIS GPTM Timer A Time-Out Raw Interrupt 0 1 TIMER_RIS_TBMRIS GPTM Timer B Match Raw Interrupt 11 12 TIMER_RIS_TBTORIS GPTM Timer B Time-Out Raw Interrupt 8 9 RTCPD GPTM RTC Predivide 0x58 -1 read-write n 0x0 0x0 TIMER_RTCPD_RTCPD RTC Predivide Counter Value 0 16 SYNC GPTM Synchronize 0x10 -1 read-write n 0x0 0x0 TIMER_SYNC_SYNCT0 Synchronize GPTM Timer 0 0 2 TIMER_SYNC_SYNCT0_NONE GPTM0 is not affected 0x0 TIMER_SYNC_SYNCT0_TA A timeout event for Timer A of GPTM0 is triggered 0x1 TIMER_SYNC_SYNCT0_TB A timeout event for Timer B of GPTM0 is triggered 0x2 TIMER_SYNC_SYNCT0_TATB A timeout event for both Timer A and Timer B of GPTM0 is triggered 0x3 TIMER_SYNC_SYNCT1 Synchronize GPTM Timer 1 2 4 TIMER_SYNC_SYNCT1_NONE GPTM1 is not affected 0x0 TIMER_SYNC_SYNCT1_TA A timeout event for Timer A of GPTM1 is triggered 0x1 TIMER_SYNC_SYNCT1_TB A timeout event for Timer B of GPTM1 is triggered 0x2 TIMER_SYNC_SYNCT1_TATB A timeout event for both Timer A and Timer B of GPTM1 is triggered 0x3 TIMER_SYNC_SYNCT2 Synchronize GPTM Timer 2 4 6 TIMER_SYNC_SYNCT2_NONE GPTM2 is not affected 0x0 TIMER_SYNC_SYNCT2_TA A timeout event for Timer A of GPTM2 is triggered 0x1 TIMER_SYNC_SYNCT2_TB A timeout event for Timer B of GPTM2 is triggered 0x2 TIMER_SYNC_SYNCT2_TATB A timeout event for both Timer A and Timer B of GPTM2 is triggered 0x3 TIMER_SYNC_SYNCT3 Synchronize GPTM Timer 3 6 8 TIMER_SYNC_SYNCT3_NONE GPTM3 is not affected 0x0 TIMER_SYNC_SYNCT3_TA A timeout event for Timer A of GPTM3 is triggered 0x1 TIMER_SYNC_SYNCT3_TB A timeout event for Timer B of GPTM3 is triggered 0x2 TIMER_SYNC_SYNCT3_TATB A timeout event for both Timer A and Timer B of GPTM3 is triggered 0x3 TIMER_SYNC_SYNCT4 Synchronize GPTM Timer 4 8 10 TIMER_SYNC_SYNCT4_NONE GPTM4 is not affected 0x0 TIMER_SYNC_SYNCT4_TA A timeout event for Timer A of GPTM4 is triggered 0x1 TIMER_SYNC_SYNCT4_TB A timeout event for Timer B of GPTM4 is triggered 0x2 TIMER_SYNC_SYNCT4_TATB A timeout event for both Timer A and Timer B of GPTM4 is triggered 0x3 TIMER_SYNC_SYNCT5 Synchronize GPTM Timer 5 10 12 TIMER_SYNC_SYNCT5_NONE GPTM5 is not affected 0x0 TIMER_SYNC_SYNCT5_TA A timeout event for Timer A of GPTM5 is triggered 0x1 TIMER_SYNC_SYNCT5_TB A timeout event for Timer B of GPTM5 is triggered 0x2 TIMER_SYNC_SYNCT5_TATB A timeout event for both Timer A and Timer B of GPTM5 is triggered 0x3 TIMER_SYNC_SYNCT6 Synchronize GPTM Timer 6 12 14 TIMER_SYNC_SYNCT6_NONE GPTM6 is not affected 0x0 TIMER_SYNC_SYNCT6_TA A timeout event for Timer A of GPTM6 is triggered 0x1 TIMER_SYNC_SYNCT6_TB A timeout event for Timer B of GPTM6 is triggered 0x2 TIMER_SYNC_SYNCT6_TATB A timeout event for both Timer A and Timer B of GPTM6 is triggered 0x3 TIMER_SYNC_SYNCT7 Synchronize GPTM Timer 7 14 16 TIMER_SYNC_SYNCT7_NONE GPT7 is not affected 0x0 TIMER_SYNC_SYNCT7_TA A timeout event for Timer A of GPTM7 is triggered 0x1 TIMER_SYNC_SYNCT7_TB A timeout event for Timer B of GPTM7 is triggered 0x2 TIMER_SYNC_SYNCT7_TATB A timeout event for both Timer A and Timer B of GPTM7 is triggered 0x3 TAILR GPTM Timer A Interval Load 0x28 -1 read-write n 0x0 0x0 TAMATCHR GPTM Timer A Match 0x30 -1 read-write n 0x0 0x0 TAMR GPTM Timer A Mode 0x4 -1 read-write n 0x0 0x0 TIMER_TAMR_TAAMS GPTM Timer A Alternate Mode Select 3 4 TIMER_TAMR_TACDIR GPTM Timer A Count Direction 4 5 TIMER_TAMR_TACINTD One-shot/Periodic Interrupt Disable 12 13 TIMER_TAMR_TACMR GPTM Timer A Capture Mode 2 3 TIMER_TAMR_TAILD GPTM Timer A Interval Load Write 8 9 TIMER_TAMR_TAMIE GPTM Timer A Match Interrupt Enable 5 6 TIMER_TAMR_TAMR GPTM Timer A Mode 0 2 TIMER_TAMR_TAMR_1_SHOT One-Shot Timer mode 0x1 TIMER_TAMR_TAMR_PERIOD Periodic Timer mode 0x2 TIMER_TAMR_TAMR_CAP Capture mode 0x3 TIMER_TAMR_TAMRSU GPTM Timer A Match Register Update 10 11 TIMER_TAMR_TAPLO GPTM Timer A PWM Legacy Operation 11 12 TIMER_TAMR_TAPWMIE GPTM Timer A PWM Interrupt Enable 9 10 TIMER_TAMR_TASNAPS GPTM Timer A Snap-Shot Mode 7 8 TIMER_TAMR_TAWOT GPTM Timer A Wait-on-Trigger 6 7 TIMER_TAMR_TCACT Timer Compare Action Select 13 16 TIMER_TAMR_TCACT_NONE Disable compare operations 0x0 TIMER_TAMR_TCACT_TOGGLE Toggle State on Time-Out 0x1 TIMER_TAMR_TCACT_CLRTO Clear CCP on Time-Out 0x2 TIMER_TAMR_TCACT_SETTO Set CCP on Time-Out 0x3 TIMER_TAMR_TCACT_SETTOGTO Set CCP immediately and toggle on Time-Out 0x4 TIMER_TAMR_TCACT_CLRTOGTO Clear CCP immediately and toggle on Time-Out 0x5 TIMER_TAMR_TCACT_SETCLRTO Set CCP immediately and clear on Time-Out 0x6 TIMER_TAMR_TCACT_CLRSETTO Clear CCP immediately and set on Time-Out 0x7 TAPMR GPTM TimerA Prescale Match 0x40 -1 read-write n 0x0 0x0 TIMER_TAPMR_TAPSMR GPTM TimerA Prescale Match 0 8 TAPR GPTM Timer A Prescale 0x38 -1 read-write n 0x0 0x0 TIMER_TAPR_TAPSR GPTM Timer A Prescale 0 8 TAPS GPTM Timer A Prescale Snapshot 0x5C -1 read-write n 0x0 0x0 TIMER_TAPS_PSS GPTM Timer A Prescaler Snapshot 0 16 TAR GPTM Timer A 0x48 -1 read-write n 0x0 0x0 TAV GPTM Timer A Value 0x50 -1 read-write n 0x0 0x0 TBILR GPTM Timer B Interval Load 0x2C -1 read-write n 0x0 0x0 TBMATCHR GPTM Timer B Match 0x34 -1 read-write n 0x0 0x0 TBMR GPTM Timer B Mode 0x8 -1 read-write n 0x0 0x0 TIMER_TBMR_TBAMS GPTM Timer B Alternate Mode Select 3 4 TIMER_TBMR_TBCDIR GPTM Timer B Count Direction 4 5 TIMER_TBMR_TBCINTD One-Shot/Periodic Interrupt Disable 12 13 TIMER_TBMR_TBCMR GPTM Timer B Capture Mode 2 3 TIMER_TBMR_TBILD GPTM Timer B Interval Load Write 8 9 TIMER_TBMR_TBMIE GPTM Timer B Match Interrupt Enable 5 6 TIMER_TBMR_TBMR GPTM Timer B Mode 0 2 TIMER_TBMR_TBMR_1_SHOT One-Shot Timer mode 0x1 TIMER_TBMR_TBMR_PERIOD Periodic Timer mode 0x2 TIMER_TBMR_TBMR_CAP Capture mode 0x3 TIMER_TBMR_TBMRSU GPTM Timer B Match Register Update 10 11 TIMER_TBMR_TBPLO GPTM Timer B PWM Legacy Operation 11 12 TIMER_TBMR_TBPWMIE GPTM Timer B PWM Interrupt Enable 9 10 TIMER_TBMR_TBSNAPS GPTM Timer B Snap-Shot Mode 7 8 TIMER_TBMR_TBWOT GPTM Timer B Wait-on-Trigger 6 7 TIMER_TBMR_TCACT Timer Compare Action Select 13 16 TIMER_TBMR_TCACT_NONE Disable compare operations 0x0 TIMER_TBMR_TCACT_TOGGLE Toggle State on Time-Out 0x1 TIMER_TBMR_TCACT_CLRTO Clear CCP on Time-Out 0x2 TIMER_TBMR_TCACT_SETTO Set CCP on Time-Out 0x3 TIMER_TBMR_TCACT_SETTOGTO Set CCP immediately and toggle on Time-Out 0x4 TIMER_TBMR_TCACT_CLRTOGTO Clear CCP immediately and toggle on Time-Out 0x5 TIMER_TBMR_TCACT_SETCLRTO Set CCP immediately and clear on Time-Out 0x6 TIMER_TBMR_TCACT_CLRSETTO Clear CCP immediately and set on Time-Out 0x7 TBPMR GPTM TimerB Prescale Match 0x44 -1 read-write n 0x0 0x0 TIMER_TBPMR_TBPSMR GPTM TimerB Prescale Match 0 8 TBPR GPTM Timer B Prescale 0x3C -1 read-write n 0x0 0x0 TIMER_TBPR_TBPSR GPTM Timer B Prescale 0 8 TBPS GPTM Timer B Prescale Snapshot 0x60 -1 read-write n 0x0 0x0 TIMER_TBPS_PSS GPTM Timer A Prescaler Value 0 16 TBR GPTM Timer B 0x4C -1 read-write n 0x0 0x0 TBV GPTM Timer B Value 0x54 -1 read-write n 0x0 0x0 TIMER0ADCEV GPTM ADC Event 0x70 read-write n 0x0 0x0 TIMER_ADCEV_CAEADCEN GPTM A Capture Event ADC Trigger Enable 2 3 TIMER_ADCEV_CAMADCEN GPTM A Capture Match Event ADC Trigger Enable 1 2 TIMER_ADCEV_CBEADCEN GPTM B Capture Event ADC Trigger Enable 10 11 TIMER_ADCEV_CBMADCEN GPTM B Capture Match Event ADC Trigger Enable 9 10 TIMER_ADCEV_RTCADCEN GPTM RTC Match Event ADC Trigger Enable 3 4 TIMER_ADCEV_TAMADCEN GPTM A Mode Match Event ADC Trigger Enable 4 5 TIMER_ADCEV_TATOADCEN GPTM A Time-Out Event ADC Trigger Enable 0 1 TIMER_ADCEV_TBMADCEN GPTM B Mode Match Event ADC Trigger Enable 11 12 TIMER_ADCEV_TBTOADCEN GPTM B Time-Out Event ADC Trigger Enable 8 9 TIMER0CC GPTM Clock Configuration 0xFC8 read-write n 0x0 0x0 TIMER_CC_ALTCLK Alternate Clock Source 0 1 TIMER0CFG GPTM Configuration 0x0 read-write n 0x0 0x0 TIMER_CFG GPTM Configuration 0 3 TIMER_CFG_32_BIT_TIMER For a 16/32-bit timer, this value selects the 32-bit timer configuration 0x0 TIMER_CFG_32_BIT_RTC For a 16/32-bit timer, this value selects the 32-bit real-time clock (RTC) counter configuration 0x1 TIMER_CFG_16_BIT For a 16/32-bit timer, this value selects the 16-bit timer configuration 0x4 TIMER0CTL GPTM Control 0xC read-write n 0x0 0x0 TIMER_CTL_RTCEN GPTM RTC Stall Enable 4 5 TIMER_CTL_TAEN GPTM Timer A Enable 0 1 TIMER_CTL_TAEVENT GPTM Timer A Event Mode 2 4 TIMER_CTL_TAEVENT_POS Positive edge 0x0 TIMER_CTL_TAEVENT_NEG Negative edge 0x1 TIMER_CTL_TAEVENT_BOTH Both edges 0x3 TIMER_CTL_TAOTE GPTM Timer A Output Trigger Enable 5 6 TIMER_CTL_TAPWML GPTM Timer A PWM Output Level 6 7 TIMER_CTL_TASTALL GPTM Timer A Stall Enable 1 2 TIMER_CTL_TBEN GPTM Timer B Enable 8 9 TIMER_CTL_TBEVENT GPTM Timer B Event Mode 10 12 TIMER_CTL_TBEVENT_POS Positive edge 0x0 TIMER_CTL_TBEVENT_NEG Negative edge 0x1 TIMER_CTL_TBEVENT_BOTH Both edges 0x3 TIMER_CTL_TBOTE GPTM Timer B Output Trigger Enable 13 14 TIMER_CTL_TBPWML GPTM Timer B PWM Output Level 14 15 TIMER_CTL_TBSTALL GPTM Timer B Stall Enable 9 10 TIMER0DMAEV GPTM DMA Event 0x6C read-write n 0x0 0x0 TIMER_DMAEV_CAEDMAEN GPTM A Capture Event DMA Trigger Enable 2 3 TIMER_DMAEV_CAMDMAEN GPTM A Capture Match Event DMA Trigger Enable 1 2 TIMER_DMAEV_CBEDMAEN GPTM B Capture Event DMA Trigger Enable 10 11 TIMER_DMAEV_CBMDMAEN GPTM B Capture Match Event DMA Trigger Enable 9 10 TIMER_DMAEV_RTCDMAEN GPTM A RTC Match Event DMA Trigger Enable 3 4 TIMER_DMAEV_TAMDMAEN GPTM A Mode Match Event DMA Trigger Enable 4 5 TIMER_DMAEV_TATODMAEN GPTM A Time-Out Event DMA Trigger Enable 0 1 TIMER_DMAEV_TBMDMAEN GPTM B Mode Match Event DMA Trigger Enable 11 12 TIMER_DMAEV_TBTODMAEN GPTM B Time-Out Event DMA Trigger Enable 8 9 TIMER0ICR GPTM Interrupt Clear 0x24 write-only n 0x0 0x0 TIMER_ICR_CAECINT GPTM Timer A Capture Mode Event Interrupt Clear 2 3 write-only TIMER_ICR_CAMCINT GPTM Timer A Capture Mode Match Interrupt Clear 1 2 write-only TIMER_ICR_CBECINT GPTM Timer B Capture Mode Event Interrupt Clear 10 11 write-only TIMER_ICR_CBMCINT GPTM Timer B Capture Mode Match Interrupt Clear 9 10 write-only TIMER_ICR_DMAAINT GPTM Timer A DMA Done Interrupt Clear 5 6 write-only TIMER_ICR_DMABINT GPTM Timer B DMA Done Interrupt Clear 13 14 write-only TIMER_ICR_RTCCINT GPTM RTC Interrupt Clear 3 4 write-only TIMER_ICR_TAMCINT GPTM Timer A Match Interrupt Clear 4 5 write-only TIMER_ICR_TATOCINT GPTM Timer A Time-Out Raw Interrupt 0 1 write-only TIMER_ICR_TBMCINT GPTM Timer B Match Interrupt Clear 11 12 write-only TIMER_ICR_TBTOCINT GPTM Timer B Time-Out Interrupt Clear 8 9 write-only TIMER0IMR GPTM Interrupt Mask 0x18 read-write n 0x0 0x0 TIMER_IMR_CAEIM GPTM Timer A Capture Mode Event Interrupt Mask 2 3 TIMER_IMR_CAMIM GPTM Timer A Capture Mode Match Interrupt Mask 1 2 TIMER_IMR_CBEIM GPTM Timer B Capture Mode Event Interrupt Mask 10 11 TIMER_IMR_CBMIM GPTM Timer B Capture Mode Match Interrupt Mask 9 10 TIMER_IMR_DMAAIM GPTM Timer A DMA Done Interrupt Mask 5 6 TIMER_IMR_DMABIM GPTM Timer B DMA Done Interrupt Mask 13 14 TIMER_IMR_RTCIM GPTM RTC Interrupt Mask 3 4 TIMER_IMR_TAMIM GPTM Timer A Match Interrupt Mask 4 5 TIMER_IMR_TATOIM GPTM Timer A Time-Out Interrupt Mask 0 1 TIMER_IMR_TBMIM GPTM Timer B Match Interrupt Mask 11 12 TIMER_IMR_TBTOIM GPTM Timer B Time-Out Interrupt Mask 8 9 TIMER0MIS GPTM Masked Interrupt Status 0x20 read-write n 0x0 0x0 TIMER_MIS_CAEMIS GPTM Timer A Capture Mode Event Masked Interrupt 2 3 TIMER_MIS_CAMMIS GPTM Timer A Capture Mode Match Masked Interrupt 1 2 TIMER_MIS_CBEMIS GPTM Timer B Capture Mode Event Masked Interrupt 10 11 TIMER_MIS_CBMMIS GPTM Timer B Capture Mode Match Masked Interrupt 9 10 TIMER_MIS_DMAAMIS GPTM Timer A DMA Done Masked Interrupt 5 6 TIMER_MIS_DMABMIS GPTM Timer B DMA Done Masked Interrupt 13 14 TIMER_MIS_RTCMIS GPTM RTC Masked Interrupt 3 4 TIMER_MIS_TAMMIS GPTM Timer A Match Masked Interrupt 4 5 TIMER_MIS_TATOMIS GPTM Timer A Time-Out Masked Interrupt 0 1 TIMER_MIS_TBMMIS GPTM Timer B Match Masked Interrupt 11 12 TIMER_MIS_TBTOMIS GPTM Timer B Time-Out Masked Interrupt 8 9 TIMER0PP GPTM Peripheral Properties 0xFC0 read-write n 0x0 0x0 TIMER_PP_ALTCLK Alternate Clock Source 6 7 TIMER_PP_CHAIN Chain with Other Timers 4 5 TIMER_PP_SIZE Count Size 0 4 TIMER_PP_SIZE_16 Timer A and Timer B counters are 16 bits each with an 8-bit prescale counter 0x0 TIMER_PP_SIZE_32 Timer A and Timer B counters are 32 bits each with a 16-bit prescale counter 0x1 TIMER_PP_SYNCCNT Synchronize Start 5 6 TIMER0RIS GPTM Raw Interrupt Status 0x1C read-write n 0x0 0x0 TIMER_RIS_CAERIS GPTM Timer A Capture Mode Event Raw Interrupt 2 3 TIMER_RIS_CAMRIS GPTM Timer A Capture Mode Match Raw Interrupt 1 2 TIMER_RIS_CBERIS GPTM Timer B Capture Mode Event Raw Interrupt 10 11 TIMER_RIS_CBMRIS GPTM Timer B Capture Mode Match Raw Interrupt 9 10 TIMER_RIS_DMAARIS GPTM Timer A DMA Done Raw Interrupt Status 5 6 TIMER_RIS_DMABRIS GPTM Timer B DMA Done Raw Interrupt Status 13 14 TIMER_RIS_RTCRIS GPTM RTC Raw Interrupt 3 4 TIMER_RIS_TAMRIS GPTM Timer A Match Raw Interrupt 4 5 TIMER_RIS_TATORIS GPTM Timer A Time-Out Raw Interrupt 0 1 TIMER_RIS_TBMRIS GPTM Timer B Match Raw Interrupt 11 12 TIMER_RIS_TBTORIS GPTM Timer B Time-Out Raw Interrupt 8 9 TIMER0RTCPD GPTM RTC Predivide 0x58 read-write n 0x0 0x0 TIMER_RTCPD_RTCPD RTC Predivide Counter Value 0 16 TIMER0SYNC GPTM Synchronize 0x10 read-write n 0x0 0x0 TIMER_SYNC_SYNCT0 Synchronize GPTM Timer 0 0 2 TIMER_SYNC_SYNCT0_NONE GPTM0 is not affected 0x0 TIMER_SYNC_SYNCT0_TA A timeout event for Timer A of GPTM0 is triggered 0x1 TIMER_SYNC_SYNCT0_TB A timeout event for Timer B of GPTM0 is triggered 0x2 TIMER_SYNC_SYNCT0_TATB A timeout event for both Timer A and Timer B of GPTM0 is triggered 0x3 TIMER_SYNC_SYNCT1 Synchronize GPTM Timer 1 2 4 TIMER_SYNC_SYNCT1_NONE GPTM1 is not affected 0x0 TIMER_SYNC_SYNCT1_TA A timeout event for Timer A of GPTM1 is triggered 0x1 TIMER_SYNC_SYNCT1_TB A timeout event for Timer B of GPTM1 is triggered 0x2 TIMER_SYNC_SYNCT1_TATB A timeout event for both Timer A and Timer B of GPTM1 is triggered 0x3 TIMER_SYNC_SYNCT2 Synchronize GPTM Timer 2 4 6 TIMER_SYNC_SYNCT2_NONE GPTM2 is not affected 0x0 TIMER_SYNC_SYNCT2_TA A timeout event for Timer A of GPTM2 is triggered 0x1 TIMER_SYNC_SYNCT2_TB A timeout event for Timer B of GPTM2 is triggered 0x2 TIMER_SYNC_SYNCT2_TATB A timeout event for both Timer A and Timer B of GPTM2 is triggered 0x3 TIMER_SYNC_SYNCT3 Synchronize GPTM Timer 3 6 8 TIMER_SYNC_SYNCT3_NONE GPTM3 is not affected 0x0 TIMER_SYNC_SYNCT3_TA A timeout event for Timer A of GPTM3 is triggered 0x1 TIMER_SYNC_SYNCT3_TB A timeout event for Timer B of GPTM3 is triggered 0x2 TIMER_SYNC_SYNCT3_TATB A timeout event for both Timer A and Timer B of GPTM3 is triggered 0x3 TIMER_SYNC_SYNCT4 Synchronize GPTM Timer 4 8 10 TIMER_SYNC_SYNCT4_NONE GPTM4 is not affected 0x0 TIMER_SYNC_SYNCT4_TA A timeout event for Timer A of GPTM4 is triggered 0x1 TIMER_SYNC_SYNCT4_TB A timeout event for Timer B of GPTM4 is triggered 0x2 TIMER_SYNC_SYNCT4_TATB A timeout event for both Timer A and Timer B of GPTM4 is triggered 0x3 TIMER_SYNC_SYNCT5 Synchronize GPTM Timer 5 10 12 TIMER_SYNC_SYNCT5_NONE GPTM5 is not affected 0x0 TIMER_SYNC_SYNCT5_TA A timeout event for Timer A of GPTM5 is triggered 0x1 TIMER_SYNC_SYNCT5_TB A timeout event for Timer B of GPTM5 is triggered 0x2 TIMER_SYNC_SYNCT5_TATB A timeout event for both Timer A and Timer B of GPTM5 is triggered 0x3 TIMER_SYNC_SYNCT6 Synchronize GPTM Timer 6 12 14 TIMER_SYNC_SYNCT6_NONE GPTM6 is not affected 0x0 TIMER_SYNC_SYNCT6_TA A timeout event for Timer A of GPTM6 is triggered 0x1 TIMER_SYNC_SYNCT6_TB A timeout event for Timer B of GPTM6 is triggered 0x2 TIMER_SYNC_SYNCT6_TATB A timeout event for both Timer A and Timer B of GPTM6 is triggered 0x3 TIMER_SYNC_SYNCT7 Synchronize GPTM Timer 7 14 16 TIMER_SYNC_SYNCT7_NONE GPT7 is not affected 0x0 TIMER_SYNC_SYNCT7_TA A timeout event for Timer A of GPTM7 is triggered 0x1 TIMER_SYNC_SYNCT7_TB A timeout event for Timer B of GPTM7 is triggered 0x2 TIMER_SYNC_SYNCT7_TATB A timeout event for both Timer A and Timer B of GPTM7 is triggered 0x3 TIMER0TAILR GPTM Timer A Interval Load 0x28 read-write n 0x0 0x0 TIMER0TAMATCHR GPTM Timer A Match 0x30 read-write n 0x0 0x0 TIMER0TAMR GPTM Timer A Mode 0x4 read-write n 0x0 0x0 TIMER_TAMR_TAAMS GPTM Timer A Alternate Mode Select 3 4 TIMER_TAMR_TACDIR GPTM Timer A Count Direction 4 5 TIMER_TAMR_TACINTD One-shot/Periodic Interrupt Disable 12 13 TIMER_TAMR_TACMR GPTM Timer A Capture Mode 2 3 TIMER_TAMR_TAILD GPTM Timer A Interval Load Write 8 9 TIMER_TAMR_TAMIE GPTM Timer A Match Interrupt Enable 5 6 TIMER_TAMR_TAMR GPTM Timer A Mode 0 2 TIMER_TAMR_TAMR_1_SHOT One-Shot Timer mode 0x1 TIMER_TAMR_TAMR_PERIOD Periodic Timer mode 0x2 TIMER_TAMR_TAMR_CAP Capture mode 0x3 TIMER_TAMR_TAMRSU GPTM Timer A Match Register Update 10 11 TIMER_TAMR_TAPLO GPTM Timer A PWM Legacy Operation 11 12 TIMER_TAMR_TAPWMIE GPTM Timer A PWM Interrupt Enable 9 10 TIMER_TAMR_TASNAPS GPTM Timer A Snap-Shot Mode 7 8 TIMER_TAMR_TAWOT GPTM Timer A Wait-on-Trigger 6 7 TIMER_TAMR_TCACT Timer Compare Action Select 13 16 TIMER_TAMR_TCACT_NONE Disable compare operations 0x0 TIMER_TAMR_TCACT_TOGGLE Toggle State on Time-Out 0x1 TIMER_TAMR_TCACT_CLRTO Clear CCP on Time-Out 0x2 TIMER_TAMR_TCACT_SETTO Set CCP on Time-Out 0x3 TIMER_TAMR_TCACT_SETTOGTO Set CCP immediately and toggle on Time-Out 0x4 TIMER_TAMR_TCACT_CLRTOGTO Clear CCP immediately and toggle on Time-Out 0x5 TIMER_TAMR_TCACT_SETCLRTO Set CCP immediately and clear on Time-Out 0x6 TIMER_TAMR_TCACT_CLRSETTO Clear CCP immediately and set on Time-Out 0x7 TIMER0TAPMR GPTM TimerA Prescale Match 0x40 read-write n 0x0 0x0 TIMER_TAPMR_TAPSMR GPTM TimerA Prescale Match 0 8 TIMER0TAPR GPTM Timer A Prescale 0x38 read-write n 0x0 0x0 TIMER_TAPR_TAPSR GPTM Timer A Prescale 0 8 TIMER0TAPS GPTM Timer A Prescale Snapshot 0x5C read-write n 0x0 0x0 TIMER_TAPS_PSS GPTM Timer A Prescaler Snapshot 0 16 TIMER0TAR GPTM Timer A 0x48 read-write n 0x0 0x0 TIMER0TAV GPTM Timer A Value 0x50 read-write n 0x0 0x0 TIMER0TBILR GPTM Timer B Interval Load 0x2C read-write n 0x0 0x0 TIMER0TBMATCHR GPTM Timer B Match 0x34 read-write n 0x0 0x0 TIMER0TBMR GPTM Timer B Mode 0x8 read-write n 0x0 0x0 TIMER_TBMR_TBAMS GPTM Timer B Alternate Mode Select 3 4 TIMER_TBMR_TBCDIR GPTM Timer B Count Direction 4 5 TIMER_TBMR_TBCINTD One-Shot/Periodic Interrupt Disable 12 13 TIMER_TBMR_TBCMR GPTM Timer B Capture Mode 2 3 TIMER_TBMR_TBILD GPTM Timer B Interval Load Write 8 9 TIMER_TBMR_TBMIE GPTM Timer B Match Interrupt Enable 5 6 TIMER_TBMR_TBMR GPTM Timer B Mode 0 2 TIMER_TBMR_TBMR_1_SHOT One-Shot Timer mode 0x1 TIMER_TBMR_TBMR_PERIOD Periodic Timer mode 0x2 TIMER_TBMR_TBMR_CAP Capture mode 0x3 TIMER_TBMR_TBMRSU GPTM Timer B Match Register Update 10 11 TIMER_TBMR_TBPLO GPTM Timer B PWM Legacy Operation 11 12 TIMER_TBMR_TBPWMIE GPTM Timer B PWM Interrupt Enable 9 10 TIMER_TBMR_TBSNAPS GPTM Timer B Snap-Shot Mode 7 8 TIMER_TBMR_TBWOT GPTM Timer B Wait-on-Trigger 6 7 TIMER_TBMR_TCACT Timer Compare Action Select 13 16 TIMER_TBMR_TCACT_NONE Disable compare operations 0x0 TIMER_TBMR_TCACT_TOGGLE Toggle State on Time-Out 0x1 TIMER_TBMR_TCACT_CLRTO Clear CCP on Time-Out 0x2 TIMER_TBMR_TCACT_SETTO Set CCP on Time-Out 0x3 TIMER_TBMR_TCACT_SETTOGTO Set CCP immediately and toggle on Time-Out 0x4 TIMER_TBMR_TCACT_CLRTOGTO Clear CCP immediately and toggle on Time-Out 0x5 TIMER_TBMR_TCACT_SETCLRTO Set CCP immediately and clear on Time-Out 0x6 TIMER_TBMR_TCACT_CLRSETTO Clear CCP immediately and set on Time-Out 0x7 TIMER0TBPMR GPTM TimerB Prescale Match 0x44 read-write n 0x0 0x0 TIMER_TBPMR_TBPSMR GPTM TimerB Prescale Match 0 8 TIMER0TBPR GPTM Timer B Prescale 0x3C read-write n 0x0 0x0 TIMER_TBPR_TBPSR GPTM Timer B Prescale 0 8 TIMER0TBPS GPTM Timer B Prescale Snapshot 0x60 read-write n 0x0 0x0 TIMER_TBPS_PSS GPTM Timer A Prescaler Value 0 16 TIMER0TBR GPTM Timer B 0x4C read-write n 0x0 0x0 TIMER0TBV GPTM Timer B Value 0x54 read-write n 0x0 0x0 TIMER5 Register map for TIMER0 peripheral TIMER 0x0 0x0 0x1000 registers n TIMER5A 65 TIMER5B 66 ADCEV GPTM ADC Event 0x70 -1 read-write n 0x0 0x0 TIMER_ADCEV_CAEADCEN GPTM A Capture Event ADC Trigger Enable 2 3 TIMER_ADCEV_CAMADCEN GPTM A Capture Match Event ADC Trigger Enable 1 2 TIMER_ADCEV_CBEADCEN GPTM B Capture Event ADC Trigger Enable 10 11 TIMER_ADCEV_CBMADCEN GPTM B Capture Match Event ADC Trigger Enable 9 10 TIMER_ADCEV_RTCADCEN GPTM RTC Match Event ADC Trigger Enable 3 4 TIMER_ADCEV_TAMADCEN GPTM A Mode Match Event ADC Trigger Enable 4 5 TIMER_ADCEV_TATOADCEN GPTM A Time-Out Event ADC Trigger Enable 0 1 TIMER_ADCEV_TBMADCEN GPTM B Mode Match Event ADC Trigger Enable 11 12 TIMER_ADCEV_TBTOADCEN GPTM B Time-Out Event ADC Trigger Enable 8 9 CC GPTM Clock Configuration 0xFC8 -1 read-write n 0x0 0x0 TIMER_CC_ALTCLK Alternate Clock Source 0 1 CFG GPTM Configuration 0x0 -1 read-write n 0x0 0x0 TIMER_CFG GPTM Configuration 0 3 TIMER_CFG_32_BIT_TIMER For a 16/32-bit timer, this value selects the 32-bit timer configuration 0x0 TIMER_CFG_32_BIT_RTC For a 16/32-bit timer, this value selects the 32-bit real-time clock (RTC) counter configuration 0x1 TIMER_CFG_16_BIT For a 16/32-bit timer, this value selects the 16-bit timer configuration 0x4 CTL GPTM Control 0xC -1 read-write n 0x0 0x0 TIMER_CTL_RTCEN GPTM RTC Stall Enable 4 5 TIMER_CTL_TAEN GPTM Timer A Enable 0 1 TIMER_CTL_TAEVENT GPTM Timer A Event Mode 2 4 TIMER_CTL_TAEVENT_POS Positive edge 0x0 TIMER_CTL_TAEVENT_NEG Negative edge 0x1 TIMER_CTL_TAEVENT_BOTH Both edges 0x3 TIMER_CTL_TAOTE GPTM Timer A Output Trigger Enable 5 6 TIMER_CTL_TAPWML GPTM Timer A PWM Output Level 6 7 TIMER_CTL_TASTALL GPTM Timer A Stall Enable 1 2 TIMER_CTL_TBEN GPTM Timer B Enable 8 9 TIMER_CTL_TBEVENT GPTM Timer B Event Mode 10 12 TIMER_CTL_TBEVENT_POS Positive edge 0x0 TIMER_CTL_TBEVENT_NEG Negative edge 0x1 TIMER_CTL_TBEVENT_BOTH Both edges 0x3 TIMER_CTL_TBOTE GPTM Timer B Output Trigger Enable 13 14 TIMER_CTL_TBPWML GPTM Timer B PWM Output Level 14 15 TIMER_CTL_TBSTALL GPTM Timer B Stall Enable 9 10 DMAEV GPTM DMA Event 0x6C -1 read-write n 0x0 0x0 TIMER_DMAEV_CAEDMAEN GPTM A Capture Event DMA Trigger Enable 2 3 TIMER_DMAEV_CAMDMAEN GPTM A Capture Match Event DMA Trigger Enable 1 2 TIMER_DMAEV_CBEDMAEN GPTM B Capture Event DMA Trigger Enable 10 11 TIMER_DMAEV_CBMDMAEN GPTM B Capture Match Event DMA Trigger Enable 9 10 TIMER_DMAEV_RTCDMAEN GPTM A RTC Match Event DMA Trigger Enable 3 4 TIMER_DMAEV_TAMDMAEN GPTM A Mode Match Event DMA Trigger Enable 4 5 TIMER_DMAEV_TATODMAEN GPTM A Time-Out Event DMA Trigger Enable 0 1 TIMER_DMAEV_TBMDMAEN GPTM B Mode Match Event DMA Trigger Enable 11 12 TIMER_DMAEV_TBTODMAEN GPTM B Time-Out Event DMA Trigger Enable 8 9 ICR GPTM Interrupt Clear 0x24 -1 write-only n 0x0 0x0 TIMER_ICR_CAECINT GPTM Timer A Capture Mode Event Interrupt Clear 2 3 write-only TIMER_ICR_CAMCINT GPTM Timer A Capture Mode Match Interrupt Clear 1 2 write-only TIMER_ICR_CBECINT GPTM Timer B Capture Mode Event Interrupt Clear 10 11 write-only TIMER_ICR_CBMCINT GPTM Timer B Capture Mode Match Interrupt Clear 9 10 write-only TIMER_ICR_DMAAINT GPTM Timer A DMA Done Interrupt Clear 5 6 write-only TIMER_ICR_DMABINT GPTM Timer B DMA Done Interrupt Clear 13 14 write-only TIMER_ICR_RTCCINT GPTM RTC Interrupt Clear 3 4 write-only TIMER_ICR_TAMCINT GPTM Timer A Match Interrupt Clear 4 5 write-only TIMER_ICR_TATOCINT GPTM Timer A Time-Out Raw Interrupt 0 1 write-only TIMER_ICR_TBMCINT GPTM Timer B Match Interrupt Clear 11 12 write-only TIMER_ICR_TBTOCINT GPTM Timer B Time-Out Interrupt Clear 8 9 write-only IMR GPTM Interrupt Mask 0x18 -1 read-write n 0x0 0x0 TIMER_IMR_CAEIM GPTM Timer A Capture Mode Event Interrupt Mask 2 3 TIMER_IMR_CAMIM GPTM Timer A Capture Mode Match Interrupt Mask 1 2 TIMER_IMR_CBEIM GPTM Timer B Capture Mode Event Interrupt Mask 10 11 TIMER_IMR_CBMIM GPTM Timer B Capture Mode Match Interrupt Mask 9 10 TIMER_IMR_DMAAIM GPTM Timer A DMA Done Interrupt Mask 5 6 TIMER_IMR_DMABIM GPTM Timer B DMA Done Interrupt Mask 13 14 TIMER_IMR_RTCIM GPTM RTC Interrupt Mask 3 4 TIMER_IMR_TAMIM GPTM Timer A Match Interrupt Mask 4 5 TIMER_IMR_TATOIM GPTM Timer A Time-Out Interrupt Mask 0 1 TIMER_IMR_TBMIM GPTM Timer B Match Interrupt Mask 11 12 TIMER_IMR_TBTOIM GPTM Timer B Time-Out Interrupt Mask 8 9 MIS GPTM Masked Interrupt Status 0x20 -1 read-write n 0x0 0x0 TIMER_MIS_CAEMIS GPTM Timer A Capture Mode Event Masked Interrupt 2 3 TIMER_MIS_CAMMIS GPTM Timer A Capture Mode Match Masked Interrupt 1 2 TIMER_MIS_CBEMIS GPTM Timer B Capture Mode Event Masked Interrupt 10 11 TIMER_MIS_CBMMIS GPTM Timer B Capture Mode Match Masked Interrupt 9 10 TIMER_MIS_DMAAMIS GPTM Timer A DMA Done Masked Interrupt 5 6 TIMER_MIS_DMABMIS GPTM Timer B DMA Done Masked Interrupt 13 14 TIMER_MIS_RTCMIS GPTM RTC Masked Interrupt 3 4 TIMER_MIS_TAMMIS GPTM Timer A Match Masked Interrupt 4 5 TIMER_MIS_TATOMIS GPTM Timer A Time-Out Masked Interrupt 0 1 TIMER_MIS_TBMMIS GPTM Timer B Match Masked Interrupt 11 12 TIMER_MIS_TBTOMIS GPTM Timer B Time-Out Masked Interrupt 8 9 PP GPTM Peripheral Properties 0xFC0 -1 read-write n 0x0 0x0 TIMER_PP_ALTCLK Alternate Clock Source 6 7 TIMER_PP_CHAIN Chain with Other Timers 4 5 TIMER_PP_SIZE Count Size 0 4 TIMER_PP_SIZE_16 Timer A and Timer B counters are 16 bits each with an 8-bit prescale counter 0x0 TIMER_PP_SIZE_32 Timer A and Timer B counters are 32 bits each with a 16-bit prescale counter 0x1 TIMER_PP_SYNCCNT Synchronize Start 5 6 RIS GPTM Raw Interrupt Status 0x1C -1 read-write n 0x0 0x0 TIMER_RIS_CAERIS GPTM Timer A Capture Mode Event Raw Interrupt 2 3 TIMER_RIS_CAMRIS GPTM Timer A Capture Mode Match Raw Interrupt 1 2 TIMER_RIS_CBERIS GPTM Timer B Capture Mode Event Raw Interrupt 10 11 TIMER_RIS_CBMRIS GPTM Timer B Capture Mode Match Raw Interrupt 9 10 TIMER_RIS_DMAARIS GPTM Timer A DMA Done Raw Interrupt Status 5 6 TIMER_RIS_DMABRIS GPTM Timer B DMA Done Raw Interrupt Status 13 14 TIMER_RIS_RTCRIS GPTM RTC Raw Interrupt 3 4 TIMER_RIS_TAMRIS GPTM Timer A Match Raw Interrupt 4 5 TIMER_RIS_TATORIS GPTM Timer A Time-Out Raw Interrupt 0 1 TIMER_RIS_TBMRIS GPTM Timer B Match Raw Interrupt 11 12 TIMER_RIS_TBTORIS GPTM Timer B Time-Out Raw Interrupt 8 9 RTCPD GPTM RTC Predivide 0x58 -1 read-write n 0x0 0x0 TIMER_RTCPD_RTCPD RTC Predivide Counter Value 0 16 SYNC GPTM Synchronize 0x10 -1 read-write n 0x0 0x0 TIMER_SYNC_SYNCT0 Synchronize GPTM Timer 0 0 2 TIMER_SYNC_SYNCT0_NONE GPTM0 is not affected 0x0 TIMER_SYNC_SYNCT0_TA A timeout event for Timer A of GPTM0 is triggered 0x1 TIMER_SYNC_SYNCT0_TB A timeout event for Timer B of GPTM0 is triggered 0x2 TIMER_SYNC_SYNCT0_TATB A timeout event for both Timer A and Timer B of GPTM0 is triggered 0x3 TIMER_SYNC_SYNCT1 Synchronize GPTM Timer 1 2 4 TIMER_SYNC_SYNCT1_NONE GPTM1 is not affected 0x0 TIMER_SYNC_SYNCT1_TA A timeout event for Timer A of GPTM1 is triggered 0x1 TIMER_SYNC_SYNCT1_TB A timeout event for Timer B of GPTM1 is triggered 0x2 TIMER_SYNC_SYNCT1_TATB A timeout event for both Timer A and Timer B of GPTM1 is triggered 0x3 TIMER_SYNC_SYNCT2 Synchronize GPTM Timer 2 4 6 TIMER_SYNC_SYNCT2_NONE GPTM2 is not affected 0x0 TIMER_SYNC_SYNCT2_TA A timeout event for Timer A of GPTM2 is triggered 0x1 TIMER_SYNC_SYNCT2_TB A timeout event for Timer B of GPTM2 is triggered 0x2 TIMER_SYNC_SYNCT2_TATB A timeout event for both Timer A and Timer B of GPTM2 is triggered 0x3 TIMER_SYNC_SYNCT3 Synchronize GPTM Timer 3 6 8 TIMER_SYNC_SYNCT3_NONE GPTM3 is not affected 0x0 TIMER_SYNC_SYNCT3_TA A timeout event for Timer A of GPTM3 is triggered 0x1 TIMER_SYNC_SYNCT3_TB A timeout event for Timer B of GPTM3 is triggered 0x2 TIMER_SYNC_SYNCT3_TATB A timeout event for both Timer A and Timer B of GPTM3 is triggered 0x3 TIMER_SYNC_SYNCT4 Synchronize GPTM Timer 4 8 10 TIMER_SYNC_SYNCT4_NONE GPTM4 is not affected 0x0 TIMER_SYNC_SYNCT4_TA A timeout event for Timer A of GPTM4 is triggered 0x1 TIMER_SYNC_SYNCT4_TB A timeout event for Timer B of GPTM4 is triggered 0x2 TIMER_SYNC_SYNCT4_TATB A timeout event for both Timer A and Timer B of GPTM4 is triggered 0x3 TIMER_SYNC_SYNCT5 Synchronize GPTM Timer 5 10 12 TIMER_SYNC_SYNCT5_NONE GPTM5 is not affected 0x0 TIMER_SYNC_SYNCT5_TA A timeout event for Timer A of GPTM5 is triggered 0x1 TIMER_SYNC_SYNCT5_TB A timeout event for Timer B of GPTM5 is triggered 0x2 TIMER_SYNC_SYNCT5_TATB A timeout event for both Timer A and Timer B of GPTM5 is triggered 0x3 TIMER_SYNC_SYNCT6 Synchronize GPTM Timer 6 12 14 TIMER_SYNC_SYNCT6_NONE GPTM6 is not affected 0x0 TIMER_SYNC_SYNCT6_TA A timeout event for Timer A of GPTM6 is triggered 0x1 TIMER_SYNC_SYNCT6_TB A timeout event for Timer B of GPTM6 is triggered 0x2 TIMER_SYNC_SYNCT6_TATB A timeout event for both Timer A and Timer B of GPTM6 is triggered 0x3 TIMER_SYNC_SYNCT7 Synchronize GPTM Timer 7 14 16 TIMER_SYNC_SYNCT7_NONE GPT7 is not affected 0x0 TIMER_SYNC_SYNCT7_TA A timeout event for Timer A of GPTM7 is triggered 0x1 TIMER_SYNC_SYNCT7_TB A timeout event for Timer B of GPTM7 is triggered 0x2 TIMER_SYNC_SYNCT7_TATB A timeout event for both Timer A and Timer B of GPTM7 is triggered 0x3 TAILR GPTM Timer A Interval Load 0x28 -1 read-write n 0x0 0x0 TAMATCHR GPTM Timer A Match 0x30 -1 read-write n 0x0 0x0 TAMR GPTM Timer A Mode 0x4 -1 read-write n 0x0 0x0 TIMER_TAMR_TAAMS GPTM Timer A Alternate Mode Select 3 4 TIMER_TAMR_TACDIR GPTM Timer A Count Direction 4 5 TIMER_TAMR_TACINTD One-shot/Periodic Interrupt Disable 12 13 TIMER_TAMR_TACMR GPTM Timer A Capture Mode 2 3 TIMER_TAMR_TAILD GPTM Timer A Interval Load Write 8 9 TIMER_TAMR_TAMIE GPTM Timer A Match Interrupt Enable 5 6 TIMER_TAMR_TAMR GPTM Timer A Mode 0 2 TIMER_TAMR_TAMR_1_SHOT One-Shot Timer mode 0x1 TIMER_TAMR_TAMR_PERIOD Periodic Timer mode 0x2 TIMER_TAMR_TAMR_CAP Capture mode 0x3 TIMER_TAMR_TAMRSU GPTM Timer A Match Register Update 10 11 TIMER_TAMR_TAPLO GPTM Timer A PWM Legacy Operation 11 12 TIMER_TAMR_TAPWMIE GPTM Timer A PWM Interrupt Enable 9 10 TIMER_TAMR_TASNAPS GPTM Timer A Snap-Shot Mode 7 8 TIMER_TAMR_TAWOT GPTM Timer A Wait-on-Trigger 6 7 TIMER_TAMR_TCACT Timer Compare Action Select 13 16 TIMER_TAMR_TCACT_NONE Disable compare operations 0x0 TIMER_TAMR_TCACT_TOGGLE Toggle State on Time-Out 0x1 TIMER_TAMR_TCACT_CLRTO Clear CCP on Time-Out 0x2 TIMER_TAMR_TCACT_SETTO Set CCP on Time-Out 0x3 TIMER_TAMR_TCACT_SETTOGTO Set CCP immediately and toggle on Time-Out 0x4 TIMER_TAMR_TCACT_CLRTOGTO Clear CCP immediately and toggle on Time-Out 0x5 TIMER_TAMR_TCACT_SETCLRTO Set CCP immediately and clear on Time-Out 0x6 TIMER_TAMR_TCACT_CLRSETTO Clear CCP immediately and set on Time-Out 0x7 TAPMR GPTM TimerA Prescale Match 0x40 -1 read-write n 0x0 0x0 TIMER_TAPMR_TAPSMR GPTM TimerA Prescale Match 0 8 TAPR GPTM Timer A Prescale 0x38 -1 read-write n 0x0 0x0 TIMER_TAPR_TAPSR GPTM Timer A Prescale 0 8 TAPS GPTM Timer A Prescale Snapshot 0x5C -1 read-write n 0x0 0x0 TIMER_TAPS_PSS GPTM Timer A Prescaler Snapshot 0 16 TAR GPTM Timer A 0x48 -1 read-write n 0x0 0x0 TAV GPTM Timer A Value 0x50 -1 read-write n 0x0 0x0 TBILR GPTM Timer B Interval Load 0x2C -1 read-write n 0x0 0x0 TBMATCHR GPTM Timer B Match 0x34 -1 read-write n 0x0 0x0 TBMR GPTM Timer B Mode 0x8 -1 read-write n 0x0 0x0 TIMER_TBMR_TBAMS GPTM Timer B Alternate Mode Select 3 4 TIMER_TBMR_TBCDIR GPTM Timer B Count Direction 4 5 TIMER_TBMR_TBCINTD One-Shot/Periodic Interrupt Disable 12 13 TIMER_TBMR_TBCMR GPTM Timer B Capture Mode 2 3 TIMER_TBMR_TBILD GPTM Timer B Interval Load Write 8 9 TIMER_TBMR_TBMIE GPTM Timer B Match Interrupt Enable 5 6 TIMER_TBMR_TBMR GPTM Timer B Mode 0 2 TIMER_TBMR_TBMR_1_SHOT One-Shot Timer mode 0x1 TIMER_TBMR_TBMR_PERIOD Periodic Timer mode 0x2 TIMER_TBMR_TBMR_CAP Capture mode 0x3 TIMER_TBMR_TBMRSU GPTM Timer B Match Register Update 10 11 TIMER_TBMR_TBPLO GPTM Timer B PWM Legacy Operation 11 12 TIMER_TBMR_TBPWMIE GPTM Timer B PWM Interrupt Enable 9 10 TIMER_TBMR_TBSNAPS GPTM Timer B Snap-Shot Mode 7 8 TIMER_TBMR_TBWOT GPTM Timer B Wait-on-Trigger 6 7 TIMER_TBMR_TCACT Timer Compare Action Select 13 16 TIMER_TBMR_TCACT_NONE Disable compare operations 0x0 TIMER_TBMR_TCACT_TOGGLE Toggle State on Time-Out 0x1 TIMER_TBMR_TCACT_CLRTO Clear CCP on Time-Out 0x2 TIMER_TBMR_TCACT_SETTO Set CCP on Time-Out 0x3 TIMER_TBMR_TCACT_SETTOGTO Set CCP immediately and toggle on Time-Out 0x4 TIMER_TBMR_TCACT_CLRTOGTO Clear CCP immediately and toggle on Time-Out 0x5 TIMER_TBMR_TCACT_SETCLRTO Set CCP immediately and clear on Time-Out 0x6 TIMER_TBMR_TCACT_CLRSETTO Clear CCP immediately and set on Time-Out 0x7 TBPMR GPTM TimerB Prescale Match 0x44 -1 read-write n 0x0 0x0 TIMER_TBPMR_TBPSMR GPTM TimerB Prescale Match 0 8 TBPR GPTM Timer B Prescale 0x3C -1 read-write n 0x0 0x0 TIMER_TBPR_TBPSR GPTM Timer B Prescale 0 8 TBPS GPTM Timer B Prescale Snapshot 0x60 -1 read-write n 0x0 0x0 TIMER_TBPS_PSS GPTM Timer A Prescaler Value 0 16 TBR GPTM Timer B 0x4C -1 read-write n 0x0 0x0 TBV GPTM Timer B Value 0x54 -1 read-write n 0x0 0x0 TIMER0ADCEV GPTM ADC Event 0x70 read-write n 0x0 0x0 TIMER_ADCEV_CAEADCEN GPTM A Capture Event ADC Trigger Enable 2 3 TIMER_ADCEV_CAMADCEN GPTM A Capture Match Event ADC Trigger Enable 1 2 TIMER_ADCEV_CBEADCEN GPTM B Capture Event ADC Trigger Enable 10 11 TIMER_ADCEV_CBMADCEN GPTM B Capture Match Event ADC Trigger Enable 9 10 TIMER_ADCEV_RTCADCEN GPTM RTC Match Event ADC Trigger Enable 3 4 TIMER_ADCEV_TAMADCEN GPTM A Mode Match Event ADC Trigger Enable 4 5 TIMER_ADCEV_TATOADCEN GPTM A Time-Out Event ADC Trigger Enable 0 1 TIMER_ADCEV_TBMADCEN GPTM B Mode Match Event ADC Trigger Enable 11 12 TIMER_ADCEV_TBTOADCEN GPTM B Time-Out Event ADC Trigger Enable 8 9 TIMER0CC GPTM Clock Configuration 0xFC8 read-write n 0x0 0x0 TIMER_CC_ALTCLK Alternate Clock Source 0 1 TIMER0CFG GPTM Configuration 0x0 read-write n 0x0 0x0 TIMER_CFG GPTM Configuration 0 3 TIMER_CFG_32_BIT_TIMER For a 16/32-bit timer, this value selects the 32-bit timer configuration 0x0 TIMER_CFG_32_BIT_RTC For a 16/32-bit timer, this value selects the 32-bit real-time clock (RTC) counter configuration 0x1 TIMER_CFG_16_BIT For a 16/32-bit timer, this value selects the 16-bit timer configuration 0x4 TIMER0CTL GPTM Control 0xC read-write n 0x0 0x0 TIMER_CTL_RTCEN GPTM RTC Stall Enable 4 5 TIMER_CTL_TAEN GPTM Timer A Enable 0 1 TIMER_CTL_TAEVENT GPTM Timer A Event Mode 2 4 TIMER_CTL_TAEVENT_POS Positive edge 0x0 TIMER_CTL_TAEVENT_NEG Negative edge 0x1 TIMER_CTL_TAEVENT_BOTH Both edges 0x3 TIMER_CTL_TAOTE GPTM Timer A Output Trigger Enable 5 6 TIMER_CTL_TAPWML GPTM Timer A PWM Output Level 6 7 TIMER_CTL_TASTALL GPTM Timer A Stall Enable 1 2 TIMER_CTL_TBEN GPTM Timer B Enable 8 9 TIMER_CTL_TBEVENT GPTM Timer B Event Mode 10 12 TIMER_CTL_TBEVENT_POS Positive edge 0x0 TIMER_CTL_TBEVENT_NEG Negative edge 0x1 TIMER_CTL_TBEVENT_BOTH Both edges 0x3 TIMER_CTL_TBOTE GPTM Timer B Output Trigger Enable 13 14 TIMER_CTL_TBPWML GPTM Timer B PWM Output Level 14 15 TIMER_CTL_TBSTALL GPTM Timer B Stall Enable 9 10 TIMER0DMAEV GPTM DMA Event 0x6C read-write n 0x0 0x0 TIMER_DMAEV_CAEDMAEN GPTM A Capture Event DMA Trigger Enable 2 3 TIMER_DMAEV_CAMDMAEN GPTM A Capture Match Event DMA Trigger Enable 1 2 TIMER_DMAEV_CBEDMAEN GPTM B Capture Event DMA Trigger Enable 10 11 TIMER_DMAEV_CBMDMAEN GPTM B Capture Match Event DMA Trigger Enable 9 10 TIMER_DMAEV_RTCDMAEN GPTM A RTC Match Event DMA Trigger Enable 3 4 TIMER_DMAEV_TAMDMAEN GPTM A Mode Match Event DMA Trigger Enable 4 5 TIMER_DMAEV_TATODMAEN GPTM A Time-Out Event DMA Trigger Enable 0 1 TIMER_DMAEV_TBMDMAEN GPTM B Mode Match Event DMA Trigger Enable 11 12 TIMER_DMAEV_TBTODMAEN GPTM B Time-Out Event DMA Trigger Enable 8 9 TIMER0ICR GPTM Interrupt Clear 0x24 write-only n 0x0 0x0 TIMER_ICR_CAECINT GPTM Timer A Capture Mode Event Interrupt Clear 2 3 write-only TIMER_ICR_CAMCINT GPTM Timer A Capture Mode Match Interrupt Clear 1 2 write-only TIMER_ICR_CBECINT GPTM Timer B Capture Mode Event Interrupt Clear 10 11 write-only TIMER_ICR_CBMCINT GPTM Timer B Capture Mode Match Interrupt Clear 9 10 write-only TIMER_ICR_DMAAINT GPTM Timer A DMA Done Interrupt Clear 5 6 write-only TIMER_ICR_DMABINT GPTM Timer B DMA Done Interrupt Clear 13 14 write-only TIMER_ICR_RTCCINT GPTM RTC Interrupt Clear 3 4 write-only TIMER_ICR_TAMCINT GPTM Timer A Match Interrupt Clear 4 5 write-only TIMER_ICR_TATOCINT GPTM Timer A Time-Out Raw Interrupt 0 1 write-only TIMER_ICR_TBMCINT GPTM Timer B Match Interrupt Clear 11 12 write-only TIMER_ICR_TBTOCINT GPTM Timer B Time-Out Interrupt Clear 8 9 write-only TIMER0IMR GPTM Interrupt Mask 0x18 read-write n 0x0 0x0 TIMER_IMR_CAEIM GPTM Timer A Capture Mode Event Interrupt Mask 2 3 TIMER_IMR_CAMIM GPTM Timer A Capture Mode Match Interrupt Mask 1 2 TIMER_IMR_CBEIM GPTM Timer B Capture Mode Event Interrupt Mask 10 11 TIMER_IMR_CBMIM GPTM Timer B Capture Mode Match Interrupt Mask 9 10 TIMER_IMR_DMAAIM GPTM Timer A DMA Done Interrupt Mask 5 6 TIMER_IMR_DMABIM GPTM Timer B DMA Done Interrupt Mask 13 14 TIMER_IMR_RTCIM GPTM RTC Interrupt Mask 3 4 TIMER_IMR_TAMIM GPTM Timer A Match Interrupt Mask 4 5 TIMER_IMR_TATOIM GPTM Timer A Time-Out Interrupt Mask 0 1 TIMER_IMR_TBMIM GPTM Timer B Match Interrupt Mask 11 12 TIMER_IMR_TBTOIM GPTM Timer B Time-Out Interrupt Mask 8 9 TIMER0MIS GPTM Masked Interrupt Status 0x20 read-write n 0x0 0x0 TIMER_MIS_CAEMIS GPTM Timer A Capture Mode Event Masked Interrupt 2 3 TIMER_MIS_CAMMIS GPTM Timer A Capture Mode Match Masked Interrupt 1 2 TIMER_MIS_CBEMIS GPTM Timer B Capture Mode Event Masked Interrupt 10 11 TIMER_MIS_CBMMIS GPTM Timer B Capture Mode Match Masked Interrupt 9 10 TIMER_MIS_DMAAMIS GPTM Timer A DMA Done Masked Interrupt 5 6 TIMER_MIS_DMABMIS GPTM Timer B DMA Done Masked Interrupt 13 14 TIMER_MIS_RTCMIS GPTM RTC Masked Interrupt 3 4 TIMER_MIS_TAMMIS GPTM Timer A Match Masked Interrupt 4 5 TIMER_MIS_TATOMIS GPTM Timer A Time-Out Masked Interrupt 0 1 TIMER_MIS_TBMMIS GPTM Timer B Match Masked Interrupt 11 12 TIMER_MIS_TBTOMIS GPTM Timer B Time-Out Masked Interrupt 8 9 TIMER0PP GPTM Peripheral Properties 0xFC0 read-write n 0x0 0x0 TIMER_PP_ALTCLK Alternate Clock Source 6 7 TIMER_PP_CHAIN Chain with Other Timers 4 5 TIMER_PP_SIZE Count Size 0 4 TIMER_PP_SIZE_16 Timer A and Timer B counters are 16 bits each with an 8-bit prescale counter 0x0 TIMER_PP_SIZE_32 Timer A and Timer B counters are 32 bits each with a 16-bit prescale counter 0x1 TIMER_PP_SYNCCNT Synchronize Start 5 6 TIMER0RIS GPTM Raw Interrupt Status 0x1C read-write n 0x0 0x0 TIMER_RIS_CAERIS GPTM Timer A Capture Mode Event Raw Interrupt 2 3 TIMER_RIS_CAMRIS GPTM Timer A Capture Mode Match Raw Interrupt 1 2 TIMER_RIS_CBERIS GPTM Timer B Capture Mode Event Raw Interrupt 10 11 TIMER_RIS_CBMRIS GPTM Timer B Capture Mode Match Raw Interrupt 9 10 TIMER_RIS_DMAARIS GPTM Timer A DMA Done Raw Interrupt Status 5 6 TIMER_RIS_DMABRIS GPTM Timer B DMA Done Raw Interrupt Status 13 14 TIMER_RIS_RTCRIS GPTM RTC Raw Interrupt 3 4 TIMER_RIS_TAMRIS GPTM Timer A Match Raw Interrupt 4 5 TIMER_RIS_TATORIS GPTM Timer A Time-Out Raw Interrupt 0 1 TIMER_RIS_TBMRIS GPTM Timer B Match Raw Interrupt 11 12 TIMER_RIS_TBTORIS GPTM Timer B Time-Out Raw Interrupt 8 9 TIMER0RTCPD GPTM RTC Predivide 0x58 read-write n 0x0 0x0 TIMER_RTCPD_RTCPD RTC Predivide Counter Value 0 16 TIMER0SYNC GPTM Synchronize 0x10 read-write n 0x0 0x0 TIMER_SYNC_SYNCT0 Synchronize GPTM Timer 0 0 2 TIMER_SYNC_SYNCT0_NONE GPTM0 is not affected 0x0 TIMER_SYNC_SYNCT0_TA A timeout event for Timer A of GPTM0 is triggered 0x1 TIMER_SYNC_SYNCT0_TB A timeout event for Timer B of GPTM0 is triggered 0x2 TIMER_SYNC_SYNCT0_TATB A timeout event for both Timer A and Timer B of GPTM0 is triggered 0x3 TIMER_SYNC_SYNCT1 Synchronize GPTM Timer 1 2 4 TIMER_SYNC_SYNCT1_NONE GPTM1 is not affected 0x0 TIMER_SYNC_SYNCT1_TA A timeout event for Timer A of GPTM1 is triggered 0x1 TIMER_SYNC_SYNCT1_TB A timeout event for Timer B of GPTM1 is triggered 0x2 TIMER_SYNC_SYNCT1_TATB A timeout event for both Timer A and Timer B of GPTM1 is triggered 0x3 TIMER_SYNC_SYNCT2 Synchronize GPTM Timer 2 4 6 TIMER_SYNC_SYNCT2_NONE GPTM2 is not affected 0x0 TIMER_SYNC_SYNCT2_TA A timeout event for Timer A of GPTM2 is triggered 0x1 TIMER_SYNC_SYNCT2_TB A timeout event for Timer B of GPTM2 is triggered 0x2 TIMER_SYNC_SYNCT2_TATB A timeout event for both Timer A and Timer B of GPTM2 is triggered 0x3 TIMER_SYNC_SYNCT3 Synchronize GPTM Timer 3 6 8 TIMER_SYNC_SYNCT3_NONE GPTM3 is not affected 0x0 TIMER_SYNC_SYNCT3_TA A timeout event for Timer A of GPTM3 is triggered 0x1 TIMER_SYNC_SYNCT3_TB A timeout event for Timer B of GPTM3 is triggered 0x2 TIMER_SYNC_SYNCT3_TATB A timeout event for both Timer A and Timer B of GPTM3 is triggered 0x3 TIMER_SYNC_SYNCT4 Synchronize GPTM Timer 4 8 10 TIMER_SYNC_SYNCT4_NONE GPTM4 is not affected 0x0 TIMER_SYNC_SYNCT4_TA A timeout event for Timer A of GPTM4 is triggered 0x1 TIMER_SYNC_SYNCT4_TB A timeout event for Timer B of GPTM4 is triggered 0x2 TIMER_SYNC_SYNCT4_TATB A timeout event for both Timer A and Timer B of GPTM4 is triggered 0x3 TIMER_SYNC_SYNCT5 Synchronize GPTM Timer 5 10 12 TIMER_SYNC_SYNCT5_NONE GPTM5 is not affected 0x0 TIMER_SYNC_SYNCT5_TA A timeout event for Timer A of GPTM5 is triggered 0x1 TIMER_SYNC_SYNCT5_TB A timeout event for Timer B of GPTM5 is triggered 0x2 TIMER_SYNC_SYNCT5_TATB A timeout event for both Timer A and Timer B of GPTM5 is triggered 0x3 TIMER_SYNC_SYNCT6 Synchronize GPTM Timer 6 12 14 TIMER_SYNC_SYNCT6_NONE GPTM6 is not affected 0x0 TIMER_SYNC_SYNCT6_TA A timeout event for Timer A of GPTM6 is triggered 0x1 TIMER_SYNC_SYNCT6_TB A timeout event for Timer B of GPTM6 is triggered 0x2 TIMER_SYNC_SYNCT6_TATB A timeout event for both Timer A and Timer B of GPTM6 is triggered 0x3 TIMER_SYNC_SYNCT7 Synchronize GPTM Timer 7 14 16 TIMER_SYNC_SYNCT7_NONE GPT7 is not affected 0x0 TIMER_SYNC_SYNCT7_TA A timeout event for Timer A of GPTM7 is triggered 0x1 TIMER_SYNC_SYNCT7_TB A timeout event for Timer B of GPTM7 is triggered 0x2 TIMER_SYNC_SYNCT7_TATB A timeout event for both Timer A and Timer B of GPTM7 is triggered 0x3 TIMER0TAILR GPTM Timer A Interval Load 0x28 read-write n 0x0 0x0 TIMER0TAMATCHR GPTM Timer A Match 0x30 read-write n 0x0 0x0 TIMER0TAMR GPTM Timer A Mode 0x4 read-write n 0x0 0x0 TIMER_TAMR_TAAMS GPTM Timer A Alternate Mode Select 3 4 TIMER_TAMR_TACDIR GPTM Timer A Count Direction 4 5 TIMER_TAMR_TACINTD One-shot/Periodic Interrupt Disable 12 13 TIMER_TAMR_TACMR GPTM Timer A Capture Mode 2 3 TIMER_TAMR_TAILD GPTM Timer A Interval Load Write 8 9 TIMER_TAMR_TAMIE GPTM Timer A Match Interrupt Enable 5 6 TIMER_TAMR_TAMR GPTM Timer A Mode 0 2 TIMER_TAMR_TAMR_1_SHOT One-Shot Timer mode 0x1 TIMER_TAMR_TAMR_PERIOD Periodic Timer mode 0x2 TIMER_TAMR_TAMR_CAP Capture mode 0x3 TIMER_TAMR_TAMRSU GPTM Timer A Match Register Update 10 11 TIMER_TAMR_TAPLO GPTM Timer A PWM Legacy Operation 11 12 TIMER_TAMR_TAPWMIE GPTM Timer A PWM Interrupt Enable 9 10 TIMER_TAMR_TASNAPS GPTM Timer A Snap-Shot Mode 7 8 TIMER_TAMR_TAWOT GPTM Timer A Wait-on-Trigger 6 7 TIMER_TAMR_TCACT Timer Compare Action Select 13 16 TIMER_TAMR_TCACT_NONE Disable compare operations 0x0 TIMER_TAMR_TCACT_TOGGLE Toggle State on Time-Out 0x1 TIMER_TAMR_TCACT_CLRTO Clear CCP on Time-Out 0x2 TIMER_TAMR_TCACT_SETTO Set CCP on Time-Out 0x3 TIMER_TAMR_TCACT_SETTOGTO Set CCP immediately and toggle on Time-Out 0x4 TIMER_TAMR_TCACT_CLRTOGTO Clear CCP immediately and toggle on Time-Out 0x5 TIMER_TAMR_TCACT_SETCLRTO Set CCP immediately and clear on Time-Out 0x6 TIMER_TAMR_TCACT_CLRSETTO Clear CCP immediately and set on Time-Out 0x7 TIMER0TAPMR GPTM TimerA Prescale Match 0x40 read-write n 0x0 0x0 TIMER_TAPMR_TAPSMR GPTM TimerA Prescale Match 0 8 TIMER0TAPR GPTM Timer A Prescale 0x38 read-write n 0x0 0x0 TIMER_TAPR_TAPSR GPTM Timer A Prescale 0 8 TIMER0TAPS GPTM Timer A Prescale Snapshot 0x5C read-write n 0x0 0x0 TIMER_TAPS_PSS GPTM Timer A Prescaler Snapshot 0 16 TIMER0TAR GPTM Timer A 0x48 read-write n 0x0 0x0 TIMER0TAV GPTM Timer A Value 0x50 read-write n 0x0 0x0 TIMER0TBILR GPTM Timer B Interval Load 0x2C read-write n 0x0 0x0 TIMER0TBMATCHR GPTM Timer B Match 0x34 read-write n 0x0 0x0 TIMER0TBMR GPTM Timer B Mode 0x8 read-write n 0x0 0x0 TIMER_TBMR_TBAMS GPTM Timer B Alternate Mode Select 3 4 TIMER_TBMR_TBCDIR GPTM Timer B Count Direction 4 5 TIMER_TBMR_TBCINTD One-Shot/Periodic Interrupt Disable 12 13 TIMER_TBMR_TBCMR GPTM Timer B Capture Mode 2 3 TIMER_TBMR_TBILD GPTM Timer B Interval Load Write 8 9 TIMER_TBMR_TBMIE GPTM Timer B Match Interrupt Enable 5 6 TIMER_TBMR_TBMR GPTM Timer B Mode 0 2 TIMER_TBMR_TBMR_1_SHOT One-Shot Timer mode 0x1 TIMER_TBMR_TBMR_PERIOD Periodic Timer mode 0x2 TIMER_TBMR_TBMR_CAP Capture mode 0x3 TIMER_TBMR_TBMRSU GPTM Timer B Match Register Update 10 11 TIMER_TBMR_TBPLO GPTM Timer B PWM Legacy Operation 11 12 TIMER_TBMR_TBPWMIE GPTM Timer B PWM Interrupt Enable 9 10 TIMER_TBMR_TBSNAPS GPTM Timer B Snap-Shot Mode 7 8 TIMER_TBMR_TBWOT GPTM Timer B Wait-on-Trigger 6 7 TIMER_TBMR_TCACT Timer Compare Action Select 13 16 TIMER_TBMR_TCACT_NONE Disable compare operations 0x0 TIMER_TBMR_TCACT_TOGGLE Toggle State on Time-Out 0x1 TIMER_TBMR_TCACT_CLRTO Clear CCP on Time-Out 0x2 TIMER_TBMR_TCACT_SETTO Set CCP on Time-Out 0x3 TIMER_TBMR_TCACT_SETTOGTO Set CCP immediately and toggle on Time-Out 0x4 TIMER_TBMR_TCACT_CLRTOGTO Clear CCP immediately and toggle on Time-Out 0x5 TIMER_TBMR_TCACT_SETCLRTO Set CCP immediately and clear on Time-Out 0x6 TIMER_TBMR_TCACT_CLRSETTO Clear CCP immediately and set on Time-Out 0x7 TIMER0TBPMR GPTM TimerB Prescale Match 0x44 read-write n 0x0 0x0 TIMER_TBPMR_TBPSMR GPTM TimerB Prescale Match 0 8 TIMER0TBPR GPTM Timer B Prescale 0x3C read-write n 0x0 0x0 TIMER_TBPR_TBPSR GPTM Timer B Prescale 0 8 TIMER0TBPS GPTM Timer B Prescale Snapshot 0x60 read-write n 0x0 0x0 TIMER_TBPS_PSS GPTM Timer A Prescaler Value 0 16 TIMER0TBR GPTM Timer B 0x4C read-write n 0x0 0x0 TIMER0TBV GPTM Timer B Value 0x54 read-write n 0x0 0x0 TIMER6 Register map for TIMER0 peripheral TIMER 0x0 0x0 0x1000 registers n TIMER6A 98 TIMER6B 99 ADCEV GPTM ADC Event 0x70 -1 read-write n 0x0 0x0 TIMER_ADCEV_CAEADCEN GPTM A Capture Event ADC Trigger Enable 2 3 TIMER_ADCEV_CAMADCEN GPTM A Capture Match Event ADC Trigger Enable 1 2 TIMER_ADCEV_CBEADCEN GPTM B Capture Event ADC Trigger Enable 10 11 TIMER_ADCEV_CBMADCEN GPTM B Capture Match Event ADC Trigger Enable 9 10 TIMER_ADCEV_RTCADCEN GPTM RTC Match Event ADC Trigger Enable 3 4 TIMER_ADCEV_TAMADCEN GPTM A Mode Match Event ADC Trigger Enable 4 5 TIMER_ADCEV_TATOADCEN GPTM A Time-Out Event ADC Trigger Enable 0 1 TIMER_ADCEV_TBMADCEN GPTM B Mode Match Event ADC Trigger Enable 11 12 TIMER_ADCEV_TBTOADCEN GPTM B Time-Out Event ADC Trigger Enable 8 9 CC GPTM Clock Configuration 0xFC8 -1 read-write n 0x0 0x0 TIMER_CC_ALTCLK Alternate Clock Source 0 1 CFG GPTM Configuration 0x0 -1 read-write n 0x0 0x0 TIMER_CFG GPTM Configuration 0 3 TIMER_CFG_32_BIT_TIMER For a 16/32-bit timer, this value selects the 32-bit timer configuration 0x0 TIMER_CFG_32_BIT_RTC For a 16/32-bit timer, this value selects the 32-bit real-time clock (RTC) counter configuration 0x1 TIMER_CFG_16_BIT For a 16/32-bit timer, this value selects the 16-bit timer configuration 0x4 CTL GPTM Control 0xC -1 read-write n 0x0 0x0 TIMER_CTL_RTCEN GPTM RTC Stall Enable 4 5 TIMER_CTL_TAEN GPTM Timer A Enable 0 1 TIMER_CTL_TAEVENT GPTM Timer A Event Mode 2 4 TIMER_CTL_TAEVENT_POS Positive edge 0x0 TIMER_CTL_TAEVENT_NEG Negative edge 0x1 TIMER_CTL_TAEVENT_BOTH Both edges 0x3 TIMER_CTL_TAOTE GPTM Timer A Output Trigger Enable 5 6 TIMER_CTL_TAPWML GPTM Timer A PWM Output Level 6 7 TIMER_CTL_TASTALL GPTM Timer A Stall Enable 1 2 TIMER_CTL_TBEN GPTM Timer B Enable 8 9 TIMER_CTL_TBEVENT GPTM Timer B Event Mode 10 12 TIMER_CTL_TBEVENT_POS Positive edge 0x0 TIMER_CTL_TBEVENT_NEG Negative edge 0x1 TIMER_CTL_TBEVENT_BOTH Both edges 0x3 TIMER_CTL_TBOTE GPTM Timer B Output Trigger Enable 13 14 TIMER_CTL_TBPWML GPTM Timer B PWM Output Level 14 15 TIMER_CTL_TBSTALL GPTM Timer B Stall Enable 9 10 DMAEV GPTM DMA Event 0x6C -1 read-write n 0x0 0x0 TIMER_DMAEV_CAEDMAEN GPTM A Capture Event DMA Trigger Enable 2 3 TIMER_DMAEV_CAMDMAEN GPTM A Capture Match Event DMA Trigger Enable 1 2 TIMER_DMAEV_CBEDMAEN GPTM B Capture Event DMA Trigger Enable 10 11 TIMER_DMAEV_CBMDMAEN GPTM B Capture Match Event DMA Trigger Enable 9 10 TIMER_DMAEV_RTCDMAEN GPTM A RTC Match Event DMA Trigger Enable 3 4 TIMER_DMAEV_TAMDMAEN GPTM A Mode Match Event DMA Trigger Enable 4 5 TIMER_DMAEV_TATODMAEN GPTM A Time-Out Event DMA Trigger Enable 0 1 TIMER_DMAEV_TBMDMAEN GPTM B Mode Match Event DMA Trigger Enable 11 12 TIMER_DMAEV_TBTODMAEN GPTM B Time-Out Event DMA Trigger Enable 8 9 ICR GPTM Interrupt Clear 0x24 -1 write-only n 0x0 0x0 TIMER_ICR_CAECINT GPTM Timer A Capture Mode Event Interrupt Clear 2 3 write-only TIMER_ICR_CAMCINT GPTM Timer A Capture Mode Match Interrupt Clear 1 2 write-only TIMER_ICR_CBECINT GPTM Timer B Capture Mode Event Interrupt Clear 10 11 write-only TIMER_ICR_CBMCINT GPTM Timer B Capture Mode Match Interrupt Clear 9 10 write-only TIMER_ICR_DMAAINT GPTM Timer A DMA Done Interrupt Clear 5 6 write-only TIMER_ICR_DMABINT GPTM Timer B DMA Done Interrupt Clear 13 14 write-only TIMER_ICR_RTCCINT GPTM RTC Interrupt Clear 3 4 write-only TIMER_ICR_TAMCINT GPTM Timer A Match Interrupt Clear 4 5 write-only TIMER_ICR_TATOCINT GPTM Timer A Time-Out Raw Interrupt 0 1 write-only TIMER_ICR_TBMCINT GPTM Timer B Match Interrupt Clear 11 12 write-only TIMER_ICR_TBTOCINT GPTM Timer B Time-Out Interrupt Clear 8 9 write-only IMR GPTM Interrupt Mask 0x18 -1 read-write n 0x0 0x0 TIMER_IMR_CAEIM GPTM Timer A Capture Mode Event Interrupt Mask 2 3 TIMER_IMR_CAMIM GPTM Timer A Capture Mode Match Interrupt Mask 1 2 TIMER_IMR_CBEIM GPTM Timer B Capture Mode Event Interrupt Mask 10 11 TIMER_IMR_CBMIM GPTM Timer B Capture Mode Match Interrupt Mask 9 10 TIMER_IMR_DMAAIM GPTM Timer A DMA Done Interrupt Mask 5 6 TIMER_IMR_DMABIM GPTM Timer B DMA Done Interrupt Mask 13 14 TIMER_IMR_RTCIM GPTM RTC Interrupt Mask 3 4 TIMER_IMR_TAMIM GPTM Timer A Match Interrupt Mask 4 5 TIMER_IMR_TATOIM GPTM Timer A Time-Out Interrupt Mask 0 1 TIMER_IMR_TBMIM GPTM Timer B Match Interrupt Mask 11 12 TIMER_IMR_TBTOIM GPTM Timer B Time-Out Interrupt Mask 8 9 MIS GPTM Masked Interrupt Status 0x20 -1 read-write n 0x0 0x0 TIMER_MIS_CAEMIS GPTM Timer A Capture Mode Event Masked Interrupt 2 3 TIMER_MIS_CAMMIS GPTM Timer A Capture Mode Match Masked Interrupt 1 2 TIMER_MIS_CBEMIS GPTM Timer B Capture Mode Event Masked Interrupt 10 11 TIMER_MIS_CBMMIS GPTM Timer B Capture Mode Match Masked Interrupt 9 10 TIMER_MIS_DMAAMIS GPTM Timer A DMA Done Masked Interrupt 5 6 TIMER_MIS_DMABMIS GPTM Timer B DMA Done Masked Interrupt 13 14 TIMER_MIS_RTCMIS GPTM RTC Masked Interrupt 3 4 TIMER_MIS_TAMMIS GPTM Timer A Match Masked Interrupt 4 5 TIMER_MIS_TATOMIS GPTM Timer A Time-Out Masked Interrupt 0 1 TIMER_MIS_TBMMIS GPTM Timer B Match Masked Interrupt 11 12 TIMER_MIS_TBTOMIS GPTM Timer B Time-Out Masked Interrupt 8 9 PP GPTM Peripheral Properties 0xFC0 -1 read-write n 0x0 0x0 TIMER_PP_ALTCLK Alternate Clock Source 6 7 TIMER_PP_CHAIN Chain with Other Timers 4 5 TIMER_PP_SIZE Count Size 0 4 TIMER_PP_SIZE_16 Timer A and Timer B counters are 16 bits each with an 8-bit prescale counter 0x0 TIMER_PP_SIZE_32 Timer A and Timer B counters are 32 bits each with a 16-bit prescale counter 0x1 TIMER_PP_SYNCCNT Synchronize Start 5 6 RIS GPTM Raw Interrupt Status 0x1C -1 read-write n 0x0 0x0 TIMER_RIS_CAERIS GPTM Timer A Capture Mode Event Raw Interrupt 2 3 TIMER_RIS_CAMRIS GPTM Timer A Capture Mode Match Raw Interrupt 1 2 TIMER_RIS_CBERIS GPTM Timer B Capture Mode Event Raw Interrupt 10 11 TIMER_RIS_CBMRIS GPTM Timer B Capture Mode Match Raw Interrupt 9 10 TIMER_RIS_DMAARIS GPTM Timer A DMA Done Raw Interrupt Status 5 6 TIMER_RIS_DMABRIS GPTM Timer B DMA Done Raw Interrupt Status 13 14 TIMER_RIS_RTCRIS GPTM RTC Raw Interrupt 3 4 TIMER_RIS_TAMRIS GPTM Timer A Match Raw Interrupt 4 5 TIMER_RIS_TATORIS GPTM Timer A Time-Out Raw Interrupt 0 1 TIMER_RIS_TBMRIS GPTM Timer B Match Raw Interrupt 11 12 TIMER_RIS_TBTORIS GPTM Timer B Time-Out Raw Interrupt 8 9 RTCPD GPTM RTC Predivide 0x58 -1 read-write n 0x0 0x0 TIMER_RTCPD_RTCPD RTC Predivide Counter Value 0 16 SYNC GPTM Synchronize 0x10 -1 read-write n 0x0 0x0 TIMER_SYNC_SYNCT0 Synchronize GPTM Timer 0 0 2 TIMER_SYNC_SYNCT0_NONE GPTM0 is not affected 0x0 TIMER_SYNC_SYNCT0_TA A timeout event for Timer A of GPTM0 is triggered 0x1 TIMER_SYNC_SYNCT0_TB A timeout event for Timer B of GPTM0 is triggered 0x2 TIMER_SYNC_SYNCT0_TATB A timeout event for both Timer A and Timer B of GPTM0 is triggered 0x3 TIMER_SYNC_SYNCT1 Synchronize GPTM Timer 1 2 4 TIMER_SYNC_SYNCT1_NONE GPTM1 is not affected 0x0 TIMER_SYNC_SYNCT1_TA A timeout event for Timer A of GPTM1 is triggered 0x1 TIMER_SYNC_SYNCT1_TB A timeout event for Timer B of GPTM1 is triggered 0x2 TIMER_SYNC_SYNCT1_TATB A timeout event for both Timer A and Timer B of GPTM1 is triggered 0x3 TIMER_SYNC_SYNCT2 Synchronize GPTM Timer 2 4 6 TIMER_SYNC_SYNCT2_NONE GPTM2 is not affected 0x0 TIMER_SYNC_SYNCT2_TA A timeout event for Timer A of GPTM2 is triggered 0x1 TIMER_SYNC_SYNCT2_TB A timeout event for Timer B of GPTM2 is triggered 0x2 TIMER_SYNC_SYNCT2_TATB A timeout event for both Timer A and Timer B of GPTM2 is triggered 0x3 TIMER_SYNC_SYNCT3 Synchronize GPTM Timer 3 6 8 TIMER_SYNC_SYNCT3_NONE GPTM3 is not affected 0x0 TIMER_SYNC_SYNCT3_TA A timeout event for Timer A of GPTM3 is triggered 0x1 TIMER_SYNC_SYNCT3_TB A timeout event for Timer B of GPTM3 is triggered 0x2 TIMER_SYNC_SYNCT3_TATB A timeout event for both Timer A and Timer B of GPTM3 is triggered 0x3 TIMER_SYNC_SYNCT4 Synchronize GPTM Timer 4 8 10 TIMER_SYNC_SYNCT4_NONE GPTM4 is not affected 0x0 TIMER_SYNC_SYNCT4_TA A timeout event for Timer A of GPTM4 is triggered 0x1 TIMER_SYNC_SYNCT4_TB A timeout event for Timer B of GPTM4 is triggered 0x2 TIMER_SYNC_SYNCT4_TATB A timeout event for both Timer A and Timer B of GPTM4 is triggered 0x3 TIMER_SYNC_SYNCT5 Synchronize GPTM Timer 5 10 12 TIMER_SYNC_SYNCT5_NONE GPTM5 is not affected 0x0 TIMER_SYNC_SYNCT5_TA A timeout event for Timer A of GPTM5 is triggered 0x1 TIMER_SYNC_SYNCT5_TB A timeout event for Timer B of GPTM5 is triggered 0x2 TIMER_SYNC_SYNCT5_TATB A timeout event for both Timer A and Timer B of GPTM5 is triggered 0x3 TIMER_SYNC_SYNCT6 Synchronize GPTM Timer 6 12 14 TIMER_SYNC_SYNCT6_NONE GPTM6 is not affected 0x0 TIMER_SYNC_SYNCT6_TA A timeout event for Timer A of GPTM6 is triggered 0x1 TIMER_SYNC_SYNCT6_TB A timeout event for Timer B of GPTM6 is triggered 0x2 TIMER_SYNC_SYNCT6_TATB A timeout event for both Timer A and Timer B of GPTM6 is triggered 0x3 TIMER_SYNC_SYNCT7 Synchronize GPTM Timer 7 14 16 TIMER_SYNC_SYNCT7_NONE GPT7 is not affected 0x0 TIMER_SYNC_SYNCT7_TA A timeout event for Timer A of GPTM7 is triggered 0x1 TIMER_SYNC_SYNCT7_TB A timeout event for Timer B of GPTM7 is triggered 0x2 TIMER_SYNC_SYNCT7_TATB A timeout event for both Timer A and Timer B of GPTM7 is triggered 0x3 TAILR GPTM Timer A Interval Load 0x28 -1 read-write n 0x0 0x0 TAMATCHR GPTM Timer A Match 0x30 -1 read-write n 0x0 0x0 TAMR GPTM Timer A Mode 0x4 -1 read-write n 0x0 0x0 TIMER_TAMR_TAAMS GPTM Timer A Alternate Mode Select 3 4 TIMER_TAMR_TACDIR GPTM Timer A Count Direction 4 5 TIMER_TAMR_TACINTD One-shot/Periodic Interrupt Disable 12 13 TIMER_TAMR_TACMR GPTM Timer A Capture Mode 2 3 TIMER_TAMR_TAILD GPTM Timer A Interval Load Write 8 9 TIMER_TAMR_TAMIE GPTM Timer A Match Interrupt Enable 5 6 TIMER_TAMR_TAMR GPTM Timer A Mode 0 2 TIMER_TAMR_TAMR_1_SHOT One-Shot Timer mode 0x1 TIMER_TAMR_TAMR_PERIOD Periodic Timer mode 0x2 TIMER_TAMR_TAMR_CAP Capture mode 0x3 TIMER_TAMR_TAMRSU GPTM Timer A Match Register Update 10 11 TIMER_TAMR_TAPLO GPTM Timer A PWM Legacy Operation 11 12 TIMER_TAMR_TAPWMIE GPTM Timer A PWM Interrupt Enable 9 10 TIMER_TAMR_TASNAPS GPTM Timer A Snap-Shot Mode 7 8 TIMER_TAMR_TAWOT GPTM Timer A Wait-on-Trigger 6 7 TIMER_TAMR_TCACT Timer Compare Action Select 13 16 TIMER_TAMR_TCACT_NONE Disable compare operations 0x0 TIMER_TAMR_TCACT_TOGGLE Toggle State on Time-Out 0x1 TIMER_TAMR_TCACT_CLRTO Clear CCP on Time-Out 0x2 TIMER_TAMR_TCACT_SETTO Set CCP on Time-Out 0x3 TIMER_TAMR_TCACT_SETTOGTO Set CCP immediately and toggle on Time-Out 0x4 TIMER_TAMR_TCACT_CLRTOGTO Clear CCP immediately and toggle on Time-Out 0x5 TIMER_TAMR_TCACT_SETCLRTO Set CCP immediately and clear on Time-Out 0x6 TIMER_TAMR_TCACT_CLRSETTO Clear CCP immediately and set on Time-Out 0x7 TAPMR GPTM TimerA Prescale Match 0x40 -1 read-write n 0x0 0x0 TIMER_TAPMR_TAPSMR GPTM TimerA Prescale Match 0 8 TAPR GPTM Timer A Prescale 0x38 -1 read-write n 0x0 0x0 TIMER_TAPR_TAPSR GPTM Timer A Prescale 0 8 TAPS GPTM Timer A Prescale Snapshot 0x5C -1 read-write n 0x0 0x0 TIMER_TAPS_PSS GPTM Timer A Prescaler Snapshot 0 16 TAR GPTM Timer A 0x48 -1 read-write n 0x0 0x0 TAV GPTM Timer A Value 0x50 -1 read-write n 0x0 0x0 TBILR GPTM Timer B Interval Load 0x2C -1 read-write n 0x0 0x0 TBMATCHR GPTM Timer B Match 0x34 -1 read-write n 0x0 0x0 TBMR GPTM Timer B Mode 0x8 -1 read-write n 0x0 0x0 TIMER_TBMR_TBAMS GPTM Timer B Alternate Mode Select 3 4 TIMER_TBMR_TBCDIR GPTM Timer B Count Direction 4 5 TIMER_TBMR_TBCINTD One-Shot/Periodic Interrupt Disable 12 13 TIMER_TBMR_TBCMR GPTM Timer B Capture Mode 2 3 TIMER_TBMR_TBILD GPTM Timer B Interval Load Write 8 9 TIMER_TBMR_TBMIE GPTM Timer B Match Interrupt Enable 5 6 TIMER_TBMR_TBMR GPTM Timer B Mode 0 2 TIMER_TBMR_TBMR_1_SHOT One-Shot Timer mode 0x1 TIMER_TBMR_TBMR_PERIOD Periodic Timer mode 0x2 TIMER_TBMR_TBMR_CAP Capture mode 0x3 TIMER_TBMR_TBMRSU GPTM Timer B Match Register Update 10 11 TIMER_TBMR_TBPLO GPTM Timer B PWM Legacy Operation 11 12 TIMER_TBMR_TBPWMIE GPTM Timer B PWM Interrupt Enable 9 10 TIMER_TBMR_TBSNAPS GPTM Timer B Snap-Shot Mode 7 8 TIMER_TBMR_TBWOT GPTM Timer B Wait-on-Trigger 6 7 TIMER_TBMR_TCACT Timer Compare Action Select 13 16 TIMER_TBMR_TCACT_NONE Disable compare operations 0x0 TIMER_TBMR_TCACT_TOGGLE Toggle State on Time-Out 0x1 TIMER_TBMR_TCACT_CLRTO Clear CCP on Time-Out 0x2 TIMER_TBMR_TCACT_SETTO Set CCP on Time-Out 0x3 TIMER_TBMR_TCACT_SETTOGTO Set CCP immediately and toggle on Time-Out 0x4 TIMER_TBMR_TCACT_CLRTOGTO Clear CCP immediately and toggle on Time-Out 0x5 TIMER_TBMR_TCACT_SETCLRTO Set CCP immediately and clear on Time-Out 0x6 TIMER_TBMR_TCACT_CLRSETTO Clear CCP immediately and set on Time-Out 0x7 TBPMR GPTM TimerB Prescale Match 0x44 -1 read-write n 0x0 0x0 TIMER_TBPMR_TBPSMR GPTM TimerB Prescale Match 0 8 TBPR GPTM Timer B Prescale 0x3C -1 read-write n 0x0 0x0 TIMER_TBPR_TBPSR GPTM Timer B Prescale 0 8 TBPS GPTM Timer B Prescale Snapshot 0x60 -1 read-write n 0x0 0x0 TIMER_TBPS_PSS GPTM Timer A Prescaler Value 0 16 TBR GPTM Timer B 0x4C -1 read-write n 0x0 0x0 TBV GPTM Timer B Value 0x54 -1 read-write n 0x0 0x0 TIMER0ADCEV GPTM ADC Event 0x70 read-write n 0x0 0x0 TIMER_ADCEV_CAEADCEN GPTM A Capture Event ADC Trigger Enable 2 3 TIMER_ADCEV_CAMADCEN GPTM A Capture Match Event ADC Trigger Enable 1 2 TIMER_ADCEV_CBEADCEN GPTM B Capture Event ADC Trigger Enable 10 11 TIMER_ADCEV_CBMADCEN GPTM B Capture Match Event ADC Trigger Enable 9 10 TIMER_ADCEV_RTCADCEN GPTM RTC Match Event ADC Trigger Enable 3 4 TIMER_ADCEV_TAMADCEN GPTM A Mode Match Event ADC Trigger Enable 4 5 TIMER_ADCEV_TATOADCEN GPTM A Time-Out Event ADC Trigger Enable 0 1 TIMER_ADCEV_TBMADCEN GPTM B Mode Match Event ADC Trigger Enable 11 12 TIMER_ADCEV_TBTOADCEN GPTM B Time-Out Event ADC Trigger Enable 8 9 TIMER0CC GPTM Clock Configuration 0xFC8 read-write n 0x0 0x0 TIMER_CC_ALTCLK Alternate Clock Source 0 1 TIMER0CFG GPTM Configuration 0x0 read-write n 0x0 0x0 TIMER_CFG GPTM Configuration 0 3 TIMER_CFG_32_BIT_TIMER For a 16/32-bit timer, this value selects the 32-bit timer configuration 0x0 TIMER_CFG_32_BIT_RTC For a 16/32-bit timer, this value selects the 32-bit real-time clock (RTC) counter configuration 0x1 TIMER_CFG_16_BIT For a 16/32-bit timer, this value selects the 16-bit timer configuration 0x4 TIMER0CTL GPTM Control 0xC read-write n 0x0 0x0 TIMER_CTL_RTCEN GPTM RTC Stall Enable 4 5 TIMER_CTL_TAEN GPTM Timer A Enable 0 1 TIMER_CTL_TAEVENT GPTM Timer A Event Mode 2 4 TIMER_CTL_TAEVENT_POS Positive edge 0x0 TIMER_CTL_TAEVENT_NEG Negative edge 0x1 TIMER_CTL_TAEVENT_BOTH Both edges 0x3 TIMER_CTL_TAOTE GPTM Timer A Output Trigger Enable 5 6 TIMER_CTL_TAPWML GPTM Timer A PWM Output Level 6 7 TIMER_CTL_TASTALL GPTM Timer A Stall Enable 1 2 TIMER_CTL_TBEN GPTM Timer B Enable 8 9 TIMER_CTL_TBEVENT GPTM Timer B Event Mode 10 12 TIMER_CTL_TBEVENT_POS Positive edge 0x0 TIMER_CTL_TBEVENT_NEG Negative edge 0x1 TIMER_CTL_TBEVENT_BOTH Both edges 0x3 TIMER_CTL_TBOTE GPTM Timer B Output Trigger Enable 13 14 TIMER_CTL_TBPWML GPTM Timer B PWM Output Level 14 15 TIMER_CTL_TBSTALL GPTM Timer B Stall Enable 9 10 TIMER0DMAEV GPTM DMA Event 0x6C read-write n 0x0 0x0 TIMER_DMAEV_CAEDMAEN GPTM A Capture Event DMA Trigger Enable 2 3 TIMER_DMAEV_CAMDMAEN GPTM A Capture Match Event DMA Trigger Enable 1 2 TIMER_DMAEV_CBEDMAEN GPTM B Capture Event DMA Trigger Enable 10 11 TIMER_DMAEV_CBMDMAEN GPTM B Capture Match Event DMA Trigger Enable 9 10 TIMER_DMAEV_RTCDMAEN GPTM A RTC Match Event DMA Trigger Enable 3 4 TIMER_DMAEV_TAMDMAEN GPTM A Mode Match Event DMA Trigger Enable 4 5 TIMER_DMAEV_TATODMAEN GPTM A Time-Out Event DMA Trigger Enable 0 1 TIMER_DMAEV_TBMDMAEN GPTM B Mode Match Event DMA Trigger Enable 11 12 TIMER_DMAEV_TBTODMAEN GPTM B Time-Out Event DMA Trigger Enable 8 9 TIMER0ICR GPTM Interrupt Clear 0x24 write-only n 0x0 0x0 TIMER_ICR_CAECINT GPTM Timer A Capture Mode Event Interrupt Clear 2 3 write-only TIMER_ICR_CAMCINT GPTM Timer A Capture Mode Match Interrupt Clear 1 2 write-only TIMER_ICR_CBECINT GPTM Timer B Capture Mode Event Interrupt Clear 10 11 write-only TIMER_ICR_CBMCINT GPTM Timer B Capture Mode Match Interrupt Clear 9 10 write-only TIMER_ICR_DMAAINT GPTM Timer A DMA Done Interrupt Clear 5 6 write-only TIMER_ICR_DMABINT GPTM Timer B DMA Done Interrupt Clear 13 14 write-only TIMER_ICR_RTCCINT GPTM RTC Interrupt Clear 3 4 write-only TIMER_ICR_TAMCINT GPTM Timer A Match Interrupt Clear 4 5 write-only TIMER_ICR_TATOCINT GPTM Timer A Time-Out Raw Interrupt 0 1 write-only TIMER_ICR_TBMCINT GPTM Timer B Match Interrupt Clear 11 12 write-only TIMER_ICR_TBTOCINT GPTM Timer B Time-Out Interrupt Clear 8 9 write-only TIMER0IMR GPTM Interrupt Mask 0x18 read-write n 0x0 0x0 TIMER_IMR_CAEIM GPTM Timer A Capture Mode Event Interrupt Mask 2 3 TIMER_IMR_CAMIM GPTM Timer A Capture Mode Match Interrupt Mask 1 2 TIMER_IMR_CBEIM GPTM Timer B Capture Mode Event Interrupt Mask 10 11 TIMER_IMR_CBMIM GPTM Timer B Capture Mode Match Interrupt Mask 9 10 TIMER_IMR_DMAAIM GPTM Timer A DMA Done Interrupt Mask 5 6 TIMER_IMR_DMABIM GPTM Timer B DMA Done Interrupt Mask 13 14 TIMER_IMR_RTCIM GPTM RTC Interrupt Mask 3 4 TIMER_IMR_TAMIM GPTM Timer A Match Interrupt Mask 4 5 TIMER_IMR_TATOIM GPTM Timer A Time-Out Interrupt Mask 0 1 TIMER_IMR_TBMIM GPTM Timer B Match Interrupt Mask 11 12 TIMER_IMR_TBTOIM GPTM Timer B Time-Out Interrupt Mask 8 9 TIMER0MIS GPTM Masked Interrupt Status 0x20 read-write n 0x0 0x0 TIMER_MIS_CAEMIS GPTM Timer A Capture Mode Event Masked Interrupt 2 3 TIMER_MIS_CAMMIS GPTM Timer A Capture Mode Match Masked Interrupt 1 2 TIMER_MIS_CBEMIS GPTM Timer B Capture Mode Event Masked Interrupt 10 11 TIMER_MIS_CBMMIS GPTM Timer B Capture Mode Match Masked Interrupt 9 10 TIMER_MIS_DMAAMIS GPTM Timer A DMA Done Masked Interrupt 5 6 TIMER_MIS_DMABMIS GPTM Timer B DMA Done Masked Interrupt 13 14 TIMER_MIS_RTCMIS GPTM RTC Masked Interrupt 3 4 TIMER_MIS_TAMMIS GPTM Timer A Match Masked Interrupt 4 5 TIMER_MIS_TATOMIS GPTM Timer A Time-Out Masked Interrupt 0 1 TIMER_MIS_TBMMIS GPTM Timer B Match Masked Interrupt 11 12 TIMER_MIS_TBTOMIS GPTM Timer B Time-Out Masked Interrupt 8 9 TIMER0PP GPTM Peripheral Properties 0xFC0 read-write n 0x0 0x0 TIMER_PP_ALTCLK Alternate Clock Source 6 7 TIMER_PP_CHAIN Chain with Other Timers 4 5 TIMER_PP_SIZE Count Size 0 4 TIMER_PP_SIZE_16 Timer A and Timer B counters are 16 bits each with an 8-bit prescale counter 0x0 TIMER_PP_SIZE_32 Timer A and Timer B counters are 32 bits each with a 16-bit prescale counter 0x1 TIMER_PP_SYNCCNT Synchronize Start 5 6 TIMER0RIS GPTM Raw Interrupt Status 0x1C read-write n 0x0 0x0 TIMER_RIS_CAERIS GPTM Timer A Capture Mode Event Raw Interrupt 2 3 TIMER_RIS_CAMRIS GPTM Timer A Capture Mode Match Raw Interrupt 1 2 TIMER_RIS_CBERIS GPTM Timer B Capture Mode Event Raw Interrupt 10 11 TIMER_RIS_CBMRIS GPTM Timer B Capture Mode Match Raw Interrupt 9 10 TIMER_RIS_DMAARIS GPTM Timer A DMA Done Raw Interrupt Status 5 6 TIMER_RIS_DMABRIS GPTM Timer B DMA Done Raw Interrupt Status 13 14 TIMER_RIS_RTCRIS GPTM RTC Raw Interrupt 3 4 TIMER_RIS_TAMRIS GPTM Timer A Match Raw Interrupt 4 5 TIMER_RIS_TATORIS GPTM Timer A Time-Out Raw Interrupt 0 1 TIMER_RIS_TBMRIS GPTM Timer B Match Raw Interrupt 11 12 TIMER_RIS_TBTORIS GPTM Timer B Time-Out Raw Interrupt 8 9 TIMER0RTCPD GPTM RTC Predivide 0x58 read-write n 0x0 0x0 TIMER_RTCPD_RTCPD RTC Predivide Counter Value 0 16 TIMER0SYNC GPTM Synchronize 0x10 read-write n 0x0 0x0 TIMER_SYNC_SYNCT0 Synchronize GPTM Timer 0 0 2 TIMER_SYNC_SYNCT0_NONE GPTM0 is not affected 0x0 TIMER_SYNC_SYNCT0_TA A timeout event for Timer A of GPTM0 is triggered 0x1 TIMER_SYNC_SYNCT0_TB A timeout event for Timer B of GPTM0 is triggered 0x2 TIMER_SYNC_SYNCT0_TATB A timeout event for both Timer A and Timer B of GPTM0 is triggered 0x3 TIMER_SYNC_SYNCT1 Synchronize GPTM Timer 1 2 4 TIMER_SYNC_SYNCT1_NONE GPTM1 is not affected 0x0 TIMER_SYNC_SYNCT1_TA A timeout event for Timer A of GPTM1 is triggered 0x1 TIMER_SYNC_SYNCT1_TB A timeout event for Timer B of GPTM1 is triggered 0x2 TIMER_SYNC_SYNCT1_TATB A timeout event for both Timer A and Timer B of GPTM1 is triggered 0x3 TIMER_SYNC_SYNCT2 Synchronize GPTM Timer 2 4 6 TIMER_SYNC_SYNCT2_NONE GPTM2 is not affected 0x0 TIMER_SYNC_SYNCT2_TA A timeout event for Timer A of GPTM2 is triggered 0x1 TIMER_SYNC_SYNCT2_TB A timeout event for Timer B of GPTM2 is triggered 0x2 TIMER_SYNC_SYNCT2_TATB A timeout event for both Timer A and Timer B of GPTM2 is triggered 0x3 TIMER_SYNC_SYNCT3 Synchronize GPTM Timer 3 6 8 TIMER_SYNC_SYNCT3_NONE GPTM3 is not affected 0x0 TIMER_SYNC_SYNCT3_TA A timeout event for Timer A of GPTM3 is triggered 0x1 TIMER_SYNC_SYNCT3_TB A timeout event for Timer B of GPTM3 is triggered 0x2 TIMER_SYNC_SYNCT3_TATB A timeout event for both Timer A and Timer B of GPTM3 is triggered 0x3 TIMER_SYNC_SYNCT4 Synchronize GPTM Timer 4 8 10 TIMER_SYNC_SYNCT4_NONE GPTM4 is not affected 0x0 TIMER_SYNC_SYNCT4_TA A timeout event for Timer A of GPTM4 is triggered 0x1 TIMER_SYNC_SYNCT4_TB A timeout event for Timer B of GPTM4 is triggered 0x2 TIMER_SYNC_SYNCT4_TATB A timeout event for both Timer A and Timer B of GPTM4 is triggered 0x3 TIMER_SYNC_SYNCT5 Synchronize GPTM Timer 5 10 12 TIMER_SYNC_SYNCT5_NONE GPTM5 is not affected 0x0 TIMER_SYNC_SYNCT5_TA A timeout event for Timer A of GPTM5 is triggered 0x1 TIMER_SYNC_SYNCT5_TB A timeout event for Timer B of GPTM5 is triggered 0x2 TIMER_SYNC_SYNCT5_TATB A timeout event for both Timer A and Timer B of GPTM5 is triggered 0x3 TIMER_SYNC_SYNCT6 Synchronize GPTM Timer 6 12 14 TIMER_SYNC_SYNCT6_NONE GPTM6 is not affected 0x0 TIMER_SYNC_SYNCT6_TA A timeout event for Timer A of GPTM6 is triggered 0x1 TIMER_SYNC_SYNCT6_TB A timeout event for Timer B of GPTM6 is triggered 0x2 TIMER_SYNC_SYNCT6_TATB A timeout event for both Timer A and Timer B of GPTM6 is triggered 0x3 TIMER_SYNC_SYNCT7 Synchronize GPTM Timer 7 14 16 TIMER_SYNC_SYNCT7_NONE GPT7 is not affected 0x0 TIMER_SYNC_SYNCT7_TA A timeout event for Timer A of GPTM7 is triggered 0x1 TIMER_SYNC_SYNCT7_TB A timeout event for Timer B of GPTM7 is triggered 0x2 TIMER_SYNC_SYNCT7_TATB A timeout event for both Timer A and Timer B of GPTM7 is triggered 0x3 TIMER0TAILR GPTM Timer A Interval Load 0x28 read-write n 0x0 0x0 TIMER0TAMATCHR GPTM Timer A Match 0x30 read-write n 0x0 0x0 TIMER0TAMR GPTM Timer A Mode 0x4 read-write n 0x0 0x0 TIMER_TAMR_TAAMS GPTM Timer A Alternate Mode Select 3 4 TIMER_TAMR_TACDIR GPTM Timer A Count Direction 4 5 TIMER_TAMR_TACINTD One-shot/Periodic Interrupt Disable 12 13 TIMER_TAMR_TACMR GPTM Timer A Capture Mode 2 3 TIMER_TAMR_TAILD GPTM Timer A Interval Load Write 8 9 TIMER_TAMR_TAMIE GPTM Timer A Match Interrupt Enable 5 6 TIMER_TAMR_TAMR GPTM Timer A Mode 0 2 TIMER_TAMR_TAMR_1_SHOT One-Shot Timer mode 0x1 TIMER_TAMR_TAMR_PERIOD Periodic Timer mode 0x2 TIMER_TAMR_TAMR_CAP Capture mode 0x3 TIMER_TAMR_TAMRSU GPTM Timer A Match Register Update 10 11 TIMER_TAMR_TAPLO GPTM Timer A PWM Legacy Operation 11 12 TIMER_TAMR_TAPWMIE GPTM Timer A PWM Interrupt Enable 9 10 TIMER_TAMR_TASNAPS GPTM Timer A Snap-Shot Mode 7 8 TIMER_TAMR_TAWOT GPTM Timer A Wait-on-Trigger 6 7 TIMER_TAMR_TCACT Timer Compare Action Select 13 16 TIMER_TAMR_TCACT_NONE Disable compare operations 0x0 TIMER_TAMR_TCACT_TOGGLE Toggle State on Time-Out 0x1 TIMER_TAMR_TCACT_CLRTO Clear CCP on Time-Out 0x2 TIMER_TAMR_TCACT_SETTO Set CCP on Time-Out 0x3 TIMER_TAMR_TCACT_SETTOGTO Set CCP immediately and toggle on Time-Out 0x4 TIMER_TAMR_TCACT_CLRTOGTO Clear CCP immediately and toggle on Time-Out 0x5 TIMER_TAMR_TCACT_SETCLRTO Set CCP immediately and clear on Time-Out 0x6 TIMER_TAMR_TCACT_CLRSETTO Clear CCP immediately and set on Time-Out 0x7 TIMER0TAPMR GPTM TimerA Prescale Match 0x40 read-write n 0x0 0x0 TIMER_TAPMR_TAPSMR GPTM TimerA Prescale Match 0 8 TIMER0TAPR GPTM Timer A Prescale 0x38 read-write n 0x0 0x0 TIMER_TAPR_TAPSR GPTM Timer A Prescale 0 8 TIMER0TAPS GPTM Timer A Prescale Snapshot 0x5C read-write n 0x0 0x0 TIMER_TAPS_PSS GPTM Timer A Prescaler Snapshot 0 16 TIMER0TAR GPTM Timer A 0x48 read-write n 0x0 0x0 TIMER0TAV GPTM Timer A Value 0x50 read-write n 0x0 0x0 TIMER0TBILR GPTM Timer B Interval Load 0x2C read-write n 0x0 0x0 TIMER0TBMATCHR GPTM Timer B Match 0x34 read-write n 0x0 0x0 TIMER0TBMR GPTM Timer B Mode 0x8 read-write n 0x0 0x0 TIMER_TBMR_TBAMS GPTM Timer B Alternate Mode Select 3 4 TIMER_TBMR_TBCDIR GPTM Timer B Count Direction 4 5 TIMER_TBMR_TBCINTD One-Shot/Periodic Interrupt Disable 12 13 TIMER_TBMR_TBCMR GPTM Timer B Capture Mode 2 3 TIMER_TBMR_TBILD GPTM Timer B Interval Load Write 8 9 TIMER_TBMR_TBMIE GPTM Timer B Match Interrupt Enable 5 6 TIMER_TBMR_TBMR GPTM Timer B Mode 0 2 TIMER_TBMR_TBMR_1_SHOT One-Shot Timer mode 0x1 TIMER_TBMR_TBMR_PERIOD Periodic Timer mode 0x2 TIMER_TBMR_TBMR_CAP Capture mode 0x3 TIMER_TBMR_TBMRSU GPTM Timer B Match Register Update 10 11 TIMER_TBMR_TBPLO GPTM Timer B PWM Legacy Operation 11 12 TIMER_TBMR_TBPWMIE GPTM Timer B PWM Interrupt Enable 9 10 TIMER_TBMR_TBSNAPS GPTM Timer B Snap-Shot Mode 7 8 TIMER_TBMR_TBWOT GPTM Timer B Wait-on-Trigger 6 7 TIMER_TBMR_TCACT Timer Compare Action Select 13 16 TIMER_TBMR_TCACT_NONE Disable compare operations 0x0 TIMER_TBMR_TCACT_TOGGLE Toggle State on Time-Out 0x1 TIMER_TBMR_TCACT_CLRTO Clear CCP on Time-Out 0x2 TIMER_TBMR_TCACT_SETTO Set CCP on Time-Out 0x3 TIMER_TBMR_TCACT_SETTOGTO Set CCP immediately and toggle on Time-Out 0x4 TIMER_TBMR_TCACT_CLRTOGTO Clear CCP immediately and toggle on Time-Out 0x5 TIMER_TBMR_TCACT_SETCLRTO Set CCP immediately and clear on Time-Out 0x6 TIMER_TBMR_TCACT_CLRSETTO Clear CCP immediately and set on Time-Out 0x7 TIMER0TBPMR GPTM TimerB Prescale Match 0x44 read-write n 0x0 0x0 TIMER_TBPMR_TBPSMR GPTM TimerB Prescale Match 0 8 TIMER0TBPR GPTM Timer B Prescale 0x3C read-write n 0x0 0x0 TIMER_TBPR_TBPSR GPTM Timer B Prescale 0 8 TIMER0TBPS GPTM Timer B Prescale Snapshot 0x60 read-write n 0x0 0x0 TIMER_TBPS_PSS GPTM Timer A Prescaler Value 0 16 TIMER0TBR GPTM Timer B 0x4C read-write n 0x0 0x0 TIMER0TBV GPTM Timer B Value 0x54 read-write n 0x0 0x0 TIMER7 Register map for TIMER0 peripheral TIMER 0x0 0x0 0x1000 registers n TIMER7A 100 TIMER7B 101 ADCEV GPTM ADC Event 0x70 -1 read-write n 0x0 0x0 TIMER_ADCEV_CAEADCEN GPTM A Capture Event ADC Trigger Enable 2 3 TIMER_ADCEV_CAMADCEN GPTM A Capture Match Event ADC Trigger Enable 1 2 TIMER_ADCEV_CBEADCEN GPTM B Capture Event ADC Trigger Enable 10 11 TIMER_ADCEV_CBMADCEN GPTM B Capture Match Event ADC Trigger Enable 9 10 TIMER_ADCEV_RTCADCEN GPTM RTC Match Event ADC Trigger Enable 3 4 TIMER_ADCEV_TAMADCEN GPTM A Mode Match Event ADC Trigger Enable 4 5 TIMER_ADCEV_TATOADCEN GPTM A Time-Out Event ADC Trigger Enable 0 1 TIMER_ADCEV_TBMADCEN GPTM B Mode Match Event ADC Trigger Enable 11 12 TIMER_ADCEV_TBTOADCEN GPTM B Time-Out Event ADC Trigger Enable 8 9 CC GPTM Clock Configuration 0xFC8 -1 read-write n 0x0 0x0 TIMER_CC_ALTCLK Alternate Clock Source 0 1 CFG GPTM Configuration 0x0 -1 read-write n 0x0 0x0 TIMER_CFG GPTM Configuration 0 3 TIMER_CFG_32_BIT_TIMER For a 16/32-bit timer, this value selects the 32-bit timer configuration 0x0 TIMER_CFG_32_BIT_RTC For a 16/32-bit timer, this value selects the 32-bit real-time clock (RTC) counter configuration 0x1 TIMER_CFG_16_BIT For a 16/32-bit timer, this value selects the 16-bit timer configuration 0x4 CTL GPTM Control 0xC -1 read-write n 0x0 0x0 TIMER_CTL_RTCEN GPTM RTC Stall Enable 4 5 TIMER_CTL_TAEN GPTM Timer A Enable 0 1 TIMER_CTL_TAEVENT GPTM Timer A Event Mode 2 4 TIMER_CTL_TAEVENT_POS Positive edge 0x0 TIMER_CTL_TAEVENT_NEG Negative edge 0x1 TIMER_CTL_TAEVENT_BOTH Both edges 0x3 TIMER_CTL_TAOTE GPTM Timer A Output Trigger Enable 5 6 TIMER_CTL_TAPWML GPTM Timer A PWM Output Level 6 7 TIMER_CTL_TASTALL GPTM Timer A Stall Enable 1 2 TIMER_CTL_TBEN GPTM Timer B Enable 8 9 TIMER_CTL_TBEVENT GPTM Timer B Event Mode 10 12 TIMER_CTL_TBEVENT_POS Positive edge 0x0 TIMER_CTL_TBEVENT_NEG Negative edge 0x1 TIMER_CTL_TBEVENT_BOTH Both edges 0x3 TIMER_CTL_TBOTE GPTM Timer B Output Trigger Enable 13 14 TIMER_CTL_TBPWML GPTM Timer B PWM Output Level 14 15 TIMER_CTL_TBSTALL GPTM Timer B Stall Enable 9 10 DMAEV GPTM DMA Event 0x6C -1 read-write n 0x0 0x0 TIMER_DMAEV_CAEDMAEN GPTM A Capture Event DMA Trigger Enable 2 3 TIMER_DMAEV_CAMDMAEN GPTM A Capture Match Event DMA Trigger Enable 1 2 TIMER_DMAEV_CBEDMAEN GPTM B Capture Event DMA Trigger Enable 10 11 TIMER_DMAEV_CBMDMAEN GPTM B Capture Match Event DMA Trigger Enable 9 10 TIMER_DMAEV_RTCDMAEN GPTM A RTC Match Event DMA Trigger Enable 3 4 TIMER_DMAEV_TAMDMAEN GPTM A Mode Match Event DMA Trigger Enable 4 5 TIMER_DMAEV_TATODMAEN GPTM A Time-Out Event DMA Trigger Enable 0 1 TIMER_DMAEV_TBMDMAEN GPTM B Mode Match Event DMA Trigger Enable 11 12 TIMER_DMAEV_TBTODMAEN GPTM B Time-Out Event DMA Trigger Enable 8 9 ICR GPTM Interrupt Clear 0x24 -1 write-only n 0x0 0x0 TIMER_ICR_CAECINT GPTM Timer A Capture Mode Event Interrupt Clear 2 3 write-only TIMER_ICR_CAMCINT GPTM Timer A Capture Mode Match Interrupt Clear 1 2 write-only TIMER_ICR_CBECINT GPTM Timer B Capture Mode Event Interrupt Clear 10 11 write-only TIMER_ICR_CBMCINT GPTM Timer B Capture Mode Match Interrupt Clear 9 10 write-only TIMER_ICR_DMAAINT GPTM Timer A DMA Done Interrupt Clear 5 6 write-only TIMER_ICR_DMABINT GPTM Timer B DMA Done Interrupt Clear 13 14 write-only TIMER_ICR_RTCCINT GPTM RTC Interrupt Clear 3 4 write-only TIMER_ICR_TAMCINT GPTM Timer A Match Interrupt Clear 4 5 write-only TIMER_ICR_TATOCINT GPTM Timer A Time-Out Raw Interrupt 0 1 write-only TIMER_ICR_TBMCINT GPTM Timer B Match Interrupt Clear 11 12 write-only TIMER_ICR_TBTOCINT GPTM Timer B Time-Out Interrupt Clear 8 9 write-only IMR GPTM Interrupt Mask 0x18 -1 read-write n 0x0 0x0 TIMER_IMR_CAEIM GPTM Timer A Capture Mode Event Interrupt Mask 2 3 TIMER_IMR_CAMIM GPTM Timer A Capture Mode Match Interrupt Mask 1 2 TIMER_IMR_CBEIM GPTM Timer B Capture Mode Event Interrupt Mask 10 11 TIMER_IMR_CBMIM GPTM Timer B Capture Mode Match Interrupt Mask 9 10 TIMER_IMR_DMAAIM GPTM Timer A DMA Done Interrupt Mask 5 6 TIMER_IMR_DMABIM GPTM Timer B DMA Done Interrupt Mask 13 14 TIMER_IMR_RTCIM GPTM RTC Interrupt Mask 3 4 TIMER_IMR_TAMIM GPTM Timer A Match Interrupt Mask 4 5 TIMER_IMR_TATOIM GPTM Timer A Time-Out Interrupt Mask 0 1 TIMER_IMR_TBMIM GPTM Timer B Match Interrupt Mask 11 12 TIMER_IMR_TBTOIM GPTM Timer B Time-Out Interrupt Mask 8 9 MIS GPTM Masked Interrupt Status 0x20 -1 read-write n 0x0 0x0 TIMER_MIS_CAEMIS GPTM Timer A Capture Mode Event Masked Interrupt 2 3 TIMER_MIS_CAMMIS GPTM Timer A Capture Mode Match Masked Interrupt 1 2 TIMER_MIS_CBEMIS GPTM Timer B Capture Mode Event Masked Interrupt 10 11 TIMER_MIS_CBMMIS GPTM Timer B Capture Mode Match Masked Interrupt 9 10 TIMER_MIS_DMAAMIS GPTM Timer A DMA Done Masked Interrupt 5 6 TIMER_MIS_DMABMIS GPTM Timer B DMA Done Masked Interrupt 13 14 TIMER_MIS_RTCMIS GPTM RTC Masked Interrupt 3 4 TIMER_MIS_TAMMIS GPTM Timer A Match Masked Interrupt 4 5 TIMER_MIS_TATOMIS GPTM Timer A Time-Out Masked Interrupt 0 1 TIMER_MIS_TBMMIS GPTM Timer B Match Masked Interrupt 11 12 TIMER_MIS_TBTOMIS GPTM Timer B Time-Out Masked Interrupt 8 9 PP GPTM Peripheral Properties 0xFC0 -1 read-write n 0x0 0x0 TIMER_PP_ALTCLK Alternate Clock Source 6 7 TIMER_PP_CHAIN Chain with Other Timers 4 5 TIMER_PP_SIZE Count Size 0 4 TIMER_PP_SIZE_16 Timer A and Timer B counters are 16 bits each with an 8-bit prescale counter 0x0 TIMER_PP_SIZE_32 Timer A and Timer B counters are 32 bits each with a 16-bit prescale counter 0x1 TIMER_PP_SYNCCNT Synchronize Start 5 6 RIS GPTM Raw Interrupt Status 0x1C -1 read-write n 0x0 0x0 TIMER_RIS_CAERIS GPTM Timer A Capture Mode Event Raw Interrupt 2 3 TIMER_RIS_CAMRIS GPTM Timer A Capture Mode Match Raw Interrupt 1 2 TIMER_RIS_CBERIS GPTM Timer B Capture Mode Event Raw Interrupt 10 11 TIMER_RIS_CBMRIS GPTM Timer B Capture Mode Match Raw Interrupt 9 10 TIMER_RIS_DMAARIS GPTM Timer A DMA Done Raw Interrupt Status 5 6 TIMER_RIS_DMABRIS GPTM Timer B DMA Done Raw Interrupt Status 13 14 TIMER_RIS_RTCRIS GPTM RTC Raw Interrupt 3 4 TIMER_RIS_TAMRIS GPTM Timer A Match Raw Interrupt 4 5 TIMER_RIS_TATORIS GPTM Timer A Time-Out Raw Interrupt 0 1 TIMER_RIS_TBMRIS GPTM Timer B Match Raw Interrupt 11 12 TIMER_RIS_TBTORIS GPTM Timer B Time-Out Raw Interrupt 8 9 RTCPD GPTM RTC Predivide 0x58 -1 read-write n 0x0 0x0 TIMER_RTCPD_RTCPD RTC Predivide Counter Value 0 16 SYNC GPTM Synchronize 0x10 -1 read-write n 0x0 0x0 TIMER_SYNC_SYNCT0 Synchronize GPTM Timer 0 0 2 TIMER_SYNC_SYNCT0_NONE GPTM0 is not affected 0x0 TIMER_SYNC_SYNCT0_TA A timeout event for Timer A of GPTM0 is triggered 0x1 TIMER_SYNC_SYNCT0_TB A timeout event for Timer B of GPTM0 is triggered 0x2 TIMER_SYNC_SYNCT0_TATB A timeout event for both Timer A and Timer B of GPTM0 is triggered 0x3 TIMER_SYNC_SYNCT1 Synchronize GPTM Timer 1 2 4 TIMER_SYNC_SYNCT1_NONE GPTM1 is not affected 0x0 TIMER_SYNC_SYNCT1_TA A timeout event for Timer A of GPTM1 is triggered 0x1 TIMER_SYNC_SYNCT1_TB A timeout event for Timer B of GPTM1 is triggered 0x2 TIMER_SYNC_SYNCT1_TATB A timeout event for both Timer A and Timer B of GPTM1 is triggered 0x3 TIMER_SYNC_SYNCT2 Synchronize GPTM Timer 2 4 6 TIMER_SYNC_SYNCT2_NONE GPTM2 is not affected 0x0 TIMER_SYNC_SYNCT2_TA A timeout event for Timer A of GPTM2 is triggered 0x1 TIMER_SYNC_SYNCT2_TB A timeout event for Timer B of GPTM2 is triggered 0x2 TIMER_SYNC_SYNCT2_TATB A timeout event for both Timer A and Timer B of GPTM2 is triggered 0x3 TIMER_SYNC_SYNCT3 Synchronize GPTM Timer 3 6 8 TIMER_SYNC_SYNCT3_NONE GPTM3 is not affected 0x0 TIMER_SYNC_SYNCT3_TA A timeout event for Timer A of GPTM3 is triggered 0x1 TIMER_SYNC_SYNCT3_TB A timeout event for Timer B of GPTM3 is triggered 0x2 TIMER_SYNC_SYNCT3_TATB A timeout event for both Timer A and Timer B of GPTM3 is triggered 0x3 TIMER_SYNC_SYNCT4 Synchronize GPTM Timer 4 8 10 TIMER_SYNC_SYNCT4_NONE GPTM4 is not affected 0x0 TIMER_SYNC_SYNCT4_TA A timeout event for Timer A of GPTM4 is triggered 0x1 TIMER_SYNC_SYNCT4_TB A timeout event for Timer B of GPTM4 is triggered 0x2 TIMER_SYNC_SYNCT4_TATB A timeout event for both Timer A and Timer B of GPTM4 is triggered 0x3 TIMER_SYNC_SYNCT5 Synchronize GPTM Timer 5 10 12 TIMER_SYNC_SYNCT5_NONE GPTM5 is not affected 0x0 TIMER_SYNC_SYNCT5_TA A timeout event for Timer A of GPTM5 is triggered 0x1 TIMER_SYNC_SYNCT5_TB A timeout event for Timer B of GPTM5 is triggered 0x2 TIMER_SYNC_SYNCT5_TATB A timeout event for both Timer A and Timer B of GPTM5 is triggered 0x3 TIMER_SYNC_SYNCT6 Synchronize GPTM Timer 6 12 14 TIMER_SYNC_SYNCT6_NONE GPTM6 is not affected 0x0 TIMER_SYNC_SYNCT6_TA A timeout event for Timer A of GPTM6 is triggered 0x1 TIMER_SYNC_SYNCT6_TB A timeout event for Timer B of GPTM6 is triggered 0x2 TIMER_SYNC_SYNCT6_TATB A timeout event for both Timer A and Timer B of GPTM6 is triggered 0x3 TIMER_SYNC_SYNCT7 Synchronize GPTM Timer 7 14 16 TIMER_SYNC_SYNCT7_NONE GPT7 is not affected 0x0 TIMER_SYNC_SYNCT7_TA A timeout event for Timer A of GPTM7 is triggered 0x1 TIMER_SYNC_SYNCT7_TB A timeout event for Timer B of GPTM7 is triggered 0x2 TIMER_SYNC_SYNCT7_TATB A timeout event for both Timer A and Timer B of GPTM7 is triggered 0x3 TAILR GPTM Timer A Interval Load 0x28 -1 read-write n 0x0 0x0 TAMATCHR GPTM Timer A Match 0x30 -1 read-write n 0x0 0x0 TAMR GPTM Timer A Mode 0x4 -1 read-write n 0x0 0x0 TIMER_TAMR_TAAMS GPTM Timer A Alternate Mode Select 3 4 TIMER_TAMR_TACDIR GPTM Timer A Count Direction 4 5 TIMER_TAMR_TACINTD One-shot/Periodic Interrupt Disable 12 13 TIMER_TAMR_TACMR GPTM Timer A Capture Mode 2 3 TIMER_TAMR_TAILD GPTM Timer A Interval Load Write 8 9 TIMER_TAMR_TAMIE GPTM Timer A Match Interrupt Enable 5 6 TIMER_TAMR_TAMR GPTM Timer A Mode 0 2 TIMER_TAMR_TAMR_1_SHOT One-Shot Timer mode 0x1 TIMER_TAMR_TAMR_PERIOD Periodic Timer mode 0x2 TIMER_TAMR_TAMR_CAP Capture mode 0x3 TIMER_TAMR_TAMRSU GPTM Timer A Match Register Update 10 11 TIMER_TAMR_TAPLO GPTM Timer A PWM Legacy Operation 11 12 TIMER_TAMR_TAPWMIE GPTM Timer A PWM Interrupt Enable 9 10 TIMER_TAMR_TASNAPS GPTM Timer A Snap-Shot Mode 7 8 TIMER_TAMR_TAWOT GPTM Timer A Wait-on-Trigger 6 7 TIMER_TAMR_TCACT Timer Compare Action Select 13 16 TIMER_TAMR_TCACT_NONE Disable compare operations 0x0 TIMER_TAMR_TCACT_TOGGLE Toggle State on Time-Out 0x1 TIMER_TAMR_TCACT_CLRTO Clear CCP on Time-Out 0x2 TIMER_TAMR_TCACT_SETTO Set CCP on Time-Out 0x3 TIMER_TAMR_TCACT_SETTOGTO Set CCP immediately and toggle on Time-Out 0x4 TIMER_TAMR_TCACT_CLRTOGTO Clear CCP immediately and toggle on Time-Out 0x5 TIMER_TAMR_TCACT_SETCLRTO Set CCP immediately and clear on Time-Out 0x6 TIMER_TAMR_TCACT_CLRSETTO Clear CCP immediately and set on Time-Out 0x7 TAPMR GPTM TimerA Prescale Match 0x40 -1 read-write n 0x0 0x0 TIMER_TAPMR_TAPSMR GPTM TimerA Prescale Match 0 8 TAPR GPTM Timer A Prescale 0x38 -1 read-write n 0x0 0x0 TIMER_TAPR_TAPSR GPTM Timer A Prescale 0 8 TAPS GPTM Timer A Prescale Snapshot 0x5C -1 read-write n 0x0 0x0 TIMER_TAPS_PSS GPTM Timer A Prescaler Snapshot 0 16 TAR GPTM Timer A 0x48 -1 read-write n 0x0 0x0 TAV GPTM Timer A Value 0x50 -1 read-write n 0x0 0x0 TBILR GPTM Timer B Interval Load 0x2C -1 read-write n 0x0 0x0 TBMATCHR GPTM Timer B Match 0x34 -1 read-write n 0x0 0x0 TBMR GPTM Timer B Mode 0x8 -1 read-write n 0x0 0x0 TIMER_TBMR_TBAMS GPTM Timer B Alternate Mode Select 3 4 TIMER_TBMR_TBCDIR GPTM Timer B Count Direction 4 5 TIMER_TBMR_TBCINTD One-Shot/Periodic Interrupt Disable 12 13 TIMER_TBMR_TBCMR GPTM Timer B Capture Mode 2 3 TIMER_TBMR_TBILD GPTM Timer B Interval Load Write 8 9 TIMER_TBMR_TBMIE GPTM Timer B Match Interrupt Enable 5 6 TIMER_TBMR_TBMR GPTM Timer B Mode 0 2 TIMER_TBMR_TBMR_1_SHOT One-Shot Timer mode 0x1 TIMER_TBMR_TBMR_PERIOD Periodic Timer mode 0x2 TIMER_TBMR_TBMR_CAP Capture mode 0x3 TIMER_TBMR_TBMRSU GPTM Timer B Match Register Update 10 11 TIMER_TBMR_TBPLO GPTM Timer B PWM Legacy Operation 11 12 TIMER_TBMR_TBPWMIE GPTM Timer B PWM Interrupt Enable 9 10 TIMER_TBMR_TBSNAPS GPTM Timer B Snap-Shot Mode 7 8 TIMER_TBMR_TBWOT GPTM Timer B Wait-on-Trigger 6 7 TIMER_TBMR_TCACT Timer Compare Action Select 13 16 TIMER_TBMR_TCACT_NONE Disable compare operations 0x0 TIMER_TBMR_TCACT_TOGGLE Toggle State on Time-Out 0x1 TIMER_TBMR_TCACT_CLRTO Clear CCP on Time-Out 0x2 TIMER_TBMR_TCACT_SETTO Set CCP on Time-Out 0x3 TIMER_TBMR_TCACT_SETTOGTO Set CCP immediately and toggle on Time-Out 0x4 TIMER_TBMR_TCACT_CLRTOGTO Clear CCP immediately and toggle on Time-Out 0x5 TIMER_TBMR_TCACT_SETCLRTO Set CCP immediately and clear on Time-Out 0x6 TIMER_TBMR_TCACT_CLRSETTO Clear CCP immediately and set on Time-Out 0x7 TBPMR GPTM TimerB Prescale Match 0x44 -1 read-write n 0x0 0x0 TIMER_TBPMR_TBPSMR GPTM TimerB Prescale Match 0 8 TBPR GPTM Timer B Prescale 0x3C -1 read-write n 0x0 0x0 TIMER_TBPR_TBPSR GPTM Timer B Prescale 0 8 TBPS GPTM Timer B Prescale Snapshot 0x60 -1 read-write n 0x0 0x0 TIMER_TBPS_PSS GPTM Timer A Prescaler Value 0 16 TBR GPTM Timer B 0x4C -1 read-write n 0x0 0x0 TBV GPTM Timer B Value 0x54 -1 read-write n 0x0 0x0 TIMER0ADCEV GPTM ADC Event 0x70 read-write n 0x0 0x0 TIMER_ADCEV_CAEADCEN GPTM A Capture Event ADC Trigger Enable 2 3 TIMER_ADCEV_CAMADCEN GPTM A Capture Match Event ADC Trigger Enable 1 2 TIMER_ADCEV_CBEADCEN GPTM B Capture Event ADC Trigger Enable 10 11 TIMER_ADCEV_CBMADCEN GPTM B Capture Match Event ADC Trigger Enable 9 10 TIMER_ADCEV_RTCADCEN GPTM RTC Match Event ADC Trigger Enable 3 4 TIMER_ADCEV_TAMADCEN GPTM A Mode Match Event ADC Trigger Enable 4 5 TIMER_ADCEV_TATOADCEN GPTM A Time-Out Event ADC Trigger Enable 0 1 TIMER_ADCEV_TBMADCEN GPTM B Mode Match Event ADC Trigger Enable 11 12 TIMER_ADCEV_TBTOADCEN GPTM B Time-Out Event ADC Trigger Enable 8 9 TIMER0CC GPTM Clock Configuration 0xFC8 read-write n 0x0 0x0 TIMER_CC_ALTCLK Alternate Clock Source 0 1 TIMER0CFG GPTM Configuration 0x0 read-write n 0x0 0x0 TIMER_CFG GPTM Configuration 0 3 TIMER_CFG_32_BIT_TIMER For a 16/32-bit timer, this value selects the 32-bit timer configuration 0x0 TIMER_CFG_32_BIT_RTC For a 16/32-bit timer, this value selects the 32-bit real-time clock (RTC) counter configuration 0x1 TIMER_CFG_16_BIT For a 16/32-bit timer, this value selects the 16-bit timer configuration 0x4 TIMER0CTL GPTM Control 0xC read-write n 0x0 0x0 TIMER_CTL_RTCEN GPTM RTC Stall Enable 4 5 TIMER_CTL_TAEN GPTM Timer A Enable 0 1 TIMER_CTL_TAEVENT GPTM Timer A Event Mode 2 4 TIMER_CTL_TAEVENT_POS Positive edge 0x0 TIMER_CTL_TAEVENT_NEG Negative edge 0x1 TIMER_CTL_TAEVENT_BOTH Both edges 0x3 TIMER_CTL_TAOTE GPTM Timer A Output Trigger Enable 5 6 TIMER_CTL_TAPWML GPTM Timer A PWM Output Level 6 7 TIMER_CTL_TASTALL GPTM Timer A Stall Enable 1 2 TIMER_CTL_TBEN GPTM Timer B Enable 8 9 TIMER_CTL_TBEVENT GPTM Timer B Event Mode 10 12 TIMER_CTL_TBEVENT_POS Positive edge 0x0 TIMER_CTL_TBEVENT_NEG Negative edge 0x1 TIMER_CTL_TBEVENT_BOTH Both edges 0x3 TIMER_CTL_TBOTE GPTM Timer B Output Trigger Enable 13 14 TIMER_CTL_TBPWML GPTM Timer B PWM Output Level 14 15 TIMER_CTL_TBSTALL GPTM Timer B Stall Enable 9 10 TIMER0DMAEV GPTM DMA Event 0x6C read-write n 0x0 0x0 TIMER_DMAEV_CAEDMAEN GPTM A Capture Event DMA Trigger Enable 2 3 TIMER_DMAEV_CAMDMAEN GPTM A Capture Match Event DMA Trigger Enable 1 2 TIMER_DMAEV_CBEDMAEN GPTM B Capture Event DMA Trigger Enable 10 11 TIMER_DMAEV_CBMDMAEN GPTM B Capture Match Event DMA Trigger Enable 9 10 TIMER_DMAEV_RTCDMAEN GPTM A RTC Match Event DMA Trigger Enable 3 4 TIMER_DMAEV_TAMDMAEN GPTM A Mode Match Event DMA Trigger Enable 4 5 TIMER_DMAEV_TATODMAEN GPTM A Time-Out Event DMA Trigger Enable 0 1 TIMER_DMAEV_TBMDMAEN GPTM B Mode Match Event DMA Trigger Enable 11 12 TIMER_DMAEV_TBTODMAEN GPTM B Time-Out Event DMA Trigger Enable 8 9 TIMER0ICR GPTM Interrupt Clear 0x24 write-only n 0x0 0x0 TIMER_ICR_CAECINT GPTM Timer A Capture Mode Event Interrupt Clear 2 3 write-only TIMER_ICR_CAMCINT GPTM Timer A Capture Mode Match Interrupt Clear 1 2 write-only TIMER_ICR_CBECINT GPTM Timer B Capture Mode Event Interrupt Clear 10 11 write-only TIMER_ICR_CBMCINT GPTM Timer B Capture Mode Match Interrupt Clear 9 10 write-only TIMER_ICR_DMAAINT GPTM Timer A DMA Done Interrupt Clear 5 6 write-only TIMER_ICR_DMABINT GPTM Timer B DMA Done Interrupt Clear 13 14 write-only TIMER_ICR_RTCCINT GPTM RTC Interrupt Clear 3 4 write-only TIMER_ICR_TAMCINT GPTM Timer A Match Interrupt Clear 4 5 write-only TIMER_ICR_TATOCINT GPTM Timer A Time-Out Raw Interrupt 0 1 write-only TIMER_ICR_TBMCINT GPTM Timer B Match Interrupt Clear 11 12 write-only TIMER_ICR_TBTOCINT GPTM Timer B Time-Out Interrupt Clear 8 9 write-only TIMER0IMR GPTM Interrupt Mask 0x18 read-write n 0x0 0x0 TIMER_IMR_CAEIM GPTM Timer A Capture Mode Event Interrupt Mask 2 3 TIMER_IMR_CAMIM GPTM Timer A Capture Mode Match Interrupt Mask 1 2 TIMER_IMR_CBEIM GPTM Timer B Capture Mode Event Interrupt Mask 10 11 TIMER_IMR_CBMIM GPTM Timer B Capture Mode Match Interrupt Mask 9 10 TIMER_IMR_DMAAIM GPTM Timer A DMA Done Interrupt Mask 5 6 TIMER_IMR_DMABIM GPTM Timer B DMA Done Interrupt Mask 13 14 TIMER_IMR_RTCIM GPTM RTC Interrupt Mask 3 4 TIMER_IMR_TAMIM GPTM Timer A Match Interrupt Mask 4 5 TIMER_IMR_TATOIM GPTM Timer A Time-Out Interrupt Mask 0 1 TIMER_IMR_TBMIM GPTM Timer B Match Interrupt Mask 11 12 TIMER_IMR_TBTOIM GPTM Timer B Time-Out Interrupt Mask 8 9 TIMER0MIS GPTM Masked Interrupt Status 0x20 read-write n 0x0 0x0 TIMER_MIS_CAEMIS GPTM Timer A Capture Mode Event Masked Interrupt 2 3 TIMER_MIS_CAMMIS GPTM Timer A Capture Mode Match Masked Interrupt 1 2 TIMER_MIS_CBEMIS GPTM Timer B Capture Mode Event Masked Interrupt 10 11 TIMER_MIS_CBMMIS GPTM Timer B Capture Mode Match Masked Interrupt 9 10 TIMER_MIS_DMAAMIS GPTM Timer A DMA Done Masked Interrupt 5 6 TIMER_MIS_DMABMIS GPTM Timer B DMA Done Masked Interrupt 13 14 TIMER_MIS_RTCMIS GPTM RTC Masked Interrupt 3 4 TIMER_MIS_TAMMIS GPTM Timer A Match Masked Interrupt 4 5 TIMER_MIS_TATOMIS GPTM Timer A Time-Out Masked Interrupt 0 1 TIMER_MIS_TBMMIS GPTM Timer B Match Masked Interrupt 11 12 TIMER_MIS_TBTOMIS GPTM Timer B Time-Out Masked Interrupt 8 9 TIMER0PP GPTM Peripheral Properties 0xFC0 read-write n 0x0 0x0 TIMER_PP_ALTCLK Alternate Clock Source 6 7 TIMER_PP_CHAIN Chain with Other Timers 4 5 TIMER_PP_SIZE Count Size 0 4 TIMER_PP_SIZE_16 Timer A and Timer B counters are 16 bits each with an 8-bit prescale counter 0x0 TIMER_PP_SIZE_32 Timer A and Timer B counters are 32 bits each with a 16-bit prescale counter 0x1 TIMER_PP_SYNCCNT Synchronize Start 5 6 TIMER0RIS GPTM Raw Interrupt Status 0x1C read-write n 0x0 0x0 TIMER_RIS_CAERIS GPTM Timer A Capture Mode Event Raw Interrupt 2 3 TIMER_RIS_CAMRIS GPTM Timer A Capture Mode Match Raw Interrupt 1 2 TIMER_RIS_CBERIS GPTM Timer B Capture Mode Event Raw Interrupt 10 11 TIMER_RIS_CBMRIS GPTM Timer B Capture Mode Match Raw Interrupt 9 10 TIMER_RIS_DMAARIS GPTM Timer A DMA Done Raw Interrupt Status 5 6 TIMER_RIS_DMABRIS GPTM Timer B DMA Done Raw Interrupt Status 13 14 TIMER_RIS_RTCRIS GPTM RTC Raw Interrupt 3 4 TIMER_RIS_TAMRIS GPTM Timer A Match Raw Interrupt 4 5 TIMER_RIS_TATORIS GPTM Timer A Time-Out Raw Interrupt 0 1 TIMER_RIS_TBMRIS GPTM Timer B Match Raw Interrupt 11 12 TIMER_RIS_TBTORIS GPTM Timer B Time-Out Raw Interrupt 8 9 TIMER0RTCPD GPTM RTC Predivide 0x58 read-write n 0x0 0x0 TIMER_RTCPD_RTCPD RTC Predivide Counter Value 0 16 TIMER0SYNC GPTM Synchronize 0x10 read-write n 0x0 0x0 TIMER_SYNC_SYNCT0 Synchronize GPTM Timer 0 0 2 TIMER_SYNC_SYNCT0_NONE GPTM0 is not affected 0x0 TIMER_SYNC_SYNCT0_TA A timeout event for Timer A of GPTM0 is triggered 0x1 TIMER_SYNC_SYNCT0_TB A timeout event for Timer B of GPTM0 is triggered 0x2 TIMER_SYNC_SYNCT0_TATB A timeout event for both Timer A and Timer B of GPTM0 is triggered 0x3 TIMER_SYNC_SYNCT1 Synchronize GPTM Timer 1 2 4 TIMER_SYNC_SYNCT1_NONE GPTM1 is not affected 0x0 TIMER_SYNC_SYNCT1_TA A timeout event for Timer A of GPTM1 is triggered 0x1 TIMER_SYNC_SYNCT1_TB A timeout event for Timer B of GPTM1 is triggered 0x2 TIMER_SYNC_SYNCT1_TATB A timeout event for both Timer A and Timer B of GPTM1 is triggered 0x3 TIMER_SYNC_SYNCT2 Synchronize GPTM Timer 2 4 6 TIMER_SYNC_SYNCT2_NONE GPTM2 is not affected 0x0 TIMER_SYNC_SYNCT2_TA A timeout event for Timer A of GPTM2 is triggered 0x1 TIMER_SYNC_SYNCT2_TB A timeout event for Timer B of GPTM2 is triggered 0x2 TIMER_SYNC_SYNCT2_TATB A timeout event for both Timer A and Timer B of GPTM2 is triggered 0x3 TIMER_SYNC_SYNCT3 Synchronize GPTM Timer 3 6 8 TIMER_SYNC_SYNCT3_NONE GPTM3 is not affected 0x0 TIMER_SYNC_SYNCT3_TA A timeout event for Timer A of GPTM3 is triggered 0x1 TIMER_SYNC_SYNCT3_TB A timeout event for Timer B of GPTM3 is triggered 0x2 TIMER_SYNC_SYNCT3_TATB A timeout event for both Timer A and Timer B of GPTM3 is triggered 0x3 TIMER_SYNC_SYNCT4 Synchronize GPTM Timer 4 8 10 TIMER_SYNC_SYNCT4_NONE GPTM4 is not affected 0x0 TIMER_SYNC_SYNCT4_TA A timeout event for Timer A of GPTM4 is triggered 0x1 TIMER_SYNC_SYNCT4_TB A timeout event for Timer B of GPTM4 is triggered 0x2 TIMER_SYNC_SYNCT4_TATB A timeout event for both Timer A and Timer B of GPTM4 is triggered 0x3 TIMER_SYNC_SYNCT5 Synchronize GPTM Timer 5 10 12 TIMER_SYNC_SYNCT5_NONE GPTM5 is not affected 0x0 TIMER_SYNC_SYNCT5_TA A timeout event for Timer A of GPTM5 is triggered 0x1 TIMER_SYNC_SYNCT5_TB A timeout event for Timer B of GPTM5 is triggered 0x2 TIMER_SYNC_SYNCT5_TATB A timeout event for both Timer A and Timer B of GPTM5 is triggered 0x3 TIMER_SYNC_SYNCT6 Synchronize GPTM Timer 6 12 14 TIMER_SYNC_SYNCT6_NONE GPTM6 is not affected 0x0 TIMER_SYNC_SYNCT6_TA A timeout event for Timer A of GPTM6 is triggered 0x1 TIMER_SYNC_SYNCT6_TB A timeout event for Timer B of GPTM6 is triggered 0x2 TIMER_SYNC_SYNCT6_TATB A timeout event for both Timer A and Timer B of GPTM6 is triggered 0x3 TIMER_SYNC_SYNCT7 Synchronize GPTM Timer 7 14 16 TIMER_SYNC_SYNCT7_NONE GPT7 is not affected 0x0 TIMER_SYNC_SYNCT7_TA A timeout event for Timer A of GPTM7 is triggered 0x1 TIMER_SYNC_SYNCT7_TB A timeout event for Timer B of GPTM7 is triggered 0x2 TIMER_SYNC_SYNCT7_TATB A timeout event for both Timer A and Timer B of GPTM7 is triggered 0x3 TIMER0TAILR GPTM Timer A Interval Load 0x28 read-write n 0x0 0x0 TIMER0TAMATCHR GPTM Timer A Match 0x30 read-write n 0x0 0x0 TIMER0TAMR GPTM Timer A Mode 0x4 read-write n 0x0 0x0 TIMER_TAMR_TAAMS GPTM Timer A Alternate Mode Select 3 4 TIMER_TAMR_TACDIR GPTM Timer A Count Direction 4 5 TIMER_TAMR_TACINTD One-shot/Periodic Interrupt Disable 12 13 TIMER_TAMR_TACMR GPTM Timer A Capture Mode 2 3 TIMER_TAMR_TAILD GPTM Timer A Interval Load Write 8 9 TIMER_TAMR_TAMIE GPTM Timer A Match Interrupt Enable 5 6 TIMER_TAMR_TAMR GPTM Timer A Mode 0 2 TIMER_TAMR_TAMR_1_SHOT One-Shot Timer mode 0x1 TIMER_TAMR_TAMR_PERIOD Periodic Timer mode 0x2 TIMER_TAMR_TAMR_CAP Capture mode 0x3 TIMER_TAMR_TAMRSU GPTM Timer A Match Register Update 10 11 TIMER_TAMR_TAPLO GPTM Timer A PWM Legacy Operation 11 12 TIMER_TAMR_TAPWMIE GPTM Timer A PWM Interrupt Enable 9 10 TIMER_TAMR_TASNAPS GPTM Timer A Snap-Shot Mode 7 8 TIMER_TAMR_TAWOT GPTM Timer A Wait-on-Trigger 6 7 TIMER_TAMR_TCACT Timer Compare Action Select 13 16 TIMER_TAMR_TCACT_NONE Disable compare operations 0x0 TIMER_TAMR_TCACT_TOGGLE Toggle State on Time-Out 0x1 TIMER_TAMR_TCACT_CLRTO Clear CCP on Time-Out 0x2 TIMER_TAMR_TCACT_SETTO Set CCP on Time-Out 0x3 TIMER_TAMR_TCACT_SETTOGTO Set CCP immediately and toggle on Time-Out 0x4 TIMER_TAMR_TCACT_CLRTOGTO Clear CCP immediately and toggle on Time-Out 0x5 TIMER_TAMR_TCACT_SETCLRTO Set CCP immediately and clear on Time-Out 0x6 TIMER_TAMR_TCACT_CLRSETTO Clear CCP immediately and set on Time-Out 0x7 TIMER0TAPMR GPTM TimerA Prescale Match 0x40 read-write n 0x0 0x0 TIMER_TAPMR_TAPSMR GPTM TimerA Prescale Match 0 8 TIMER0TAPR GPTM Timer A Prescale 0x38 read-write n 0x0 0x0 TIMER_TAPR_TAPSR GPTM Timer A Prescale 0 8 TIMER0TAPS GPTM Timer A Prescale Snapshot 0x5C read-write n 0x0 0x0 TIMER_TAPS_PSS GPTM Timer A Prescaler Snapshot 0 16 TIMER0TAR GPTM Timer A 0x48 read-write n 0x0 0x0 TIMER0TAV GPTM Timer A Value 0x50 read-write n 0x0 0x0 TIMER0TBILR GPTM Timer B Interval Load 0x2C read-write n 0x0 0x0 TIMER0TBMATCHR GPTM Timer B Match 0x34 read-write n 0x0 0x0 TIMER0TBMR GPTM Timer B Mode 0x8 read-write n 0x0 0x0 TIMER_TBMR_TBAMS GPTM Timer B Alternate Mode Select 3 4 TIMER_TBMR_TBCDIR GPTM Timer B Count Direction 4 5 TIMER_TBMR_TBCINTD One-Shot/Periodic Interrupt Disable 12 13 TIMER_TBMR_TBCMR GPTM Timer B Capture Mode 2 3 TIMER_TBMR_TBILD GPTM Timer B Interval Load Write 8 9 TIMER_TBMR_TBMIE GPTM Timer B Match Interrupt Enable 5 6 TIMER_TBMR_TBMR GPTM Timer B Mode 0 2 TIMER_TBMR_TBMR_1_SHOT One-Shot Timer mode 0x1 TIMER_TBMR_TBMR_PERIOD Periodic Timer mode 0x2 TIMER_TBMR_TBMR_CAP Capture mode 0x3 TIMER_TBMR_TBMRSU GPTM Timer B Match Register Update 10 11 TIMER_TBMR_TBPLO GPTM Timer B PWM Legacy Operation 11 12 TIMER_TBMR_TBPWMIE GPTM Timer B PWM Interrupt Enable 9 10 TIMER_TBMR_TBSNAPS GPTM Timer B Snap-Shot Mode 7 8 TIMER_TBMR_TBWOT GPTM Timer B Wait-on-Trigger 6 7 TIMER_TBMR_TCACT Timer Compare Action Select 13 16 TIMER_TBMR_TCACT_NONE Disable compare operations 0x0 TIMER_TBMR_TCACT_TOGGLE Toggle State on Time-Out 0x1 TIMER_TBMR_TCACT_CLRTO Clear CCP on Time-Out 0x2 TIMER_TBMR_TCACT_SETTO Set CCP on Time-Out 0x3 TIMER_TBMR_TCACT_SETTOGTO Set CCP immediately and toggle on Time-Out 0x4 TIMER_TBMR_TCACT_CLRTOGTO Clear CCP immediately and toggle on Time-Out 0x5 TIMER_TBMR_TCACT_SETCLRTO Set CCP immediately and clear on Time-Out 0x6 TIMER_TBMR_TCACT_CLRSETTO Clear CCP immediately and set on Time-Out 0x7 TIMER0TBPMR GPTM TimerB Prescale Match 0x44 read-write n 0x0 0x0 TIMER_TBPMR_TBPSMR GPTM TimerB Prescale Match 0 8 TIMER0TBPR GPTM Timer B Prescale 0x3C read-write n 0x0 0x0 TIMER_TBPR_TBPSR GPTM Timer B Prescale 0 8 TIMER0TBPS GPTM Timer B Prescale Snapshot 0x60 read-write n 0x0 0x0 TIMER_TBPS_PSS GPTM Timer A Prescaler Value 0 16 TIMER0TBR GPTM Timer B 0x4C read-write n 0x0 0x0 TIMER0TBV GPTM Timer B Value 0x54 read-write n 0x0 0x0 UART0 Register map for UART0 peripheral UART 0x0 0x0 0x1000 registers n UART0 5 9BITADDR UART 9-Bit Self Address 0xA4 read-write n 0x0 0x0 UART_9BITADDR_9BITEN Enable 9-Bit Mode 15 16 UART_9BITADDR_ADDR Self Address for 9-Bit Mode 0 8 9BITAMASK UART 9-Bit Self Address Mask 0xA8 read-write n 0x0 0x0 UART_9BITAMASK_MASK Self Address Mask for 9-Bit Mode 0 8 CC UART Clock Configuration 0xFC8 -1 read-write n 0x0 0x0 UART_CC_CS UART Baud Clock Source 0 4 UART_CC_CS_SYSCLK System clock (based on clock source and divisor factor) 0x0 UART_CC_CS_PIOSC PIOSC 0x5 CTL UART Control 0x30 -1 read-write n 0x0 0x0 UART_CTL_CTSEN Enable Clear To Send 15 16 UART_CTL_DTR Data Terminal Ready 10 11 UART_CTL_EOT End of Transmission 4 5 UART_CTL_HSE High-Speed Enable 5 6 UART_CTL_LBE UART Loop Back Enable 7 8 UART_CTL_RTS Request to Send 11 12 UART_CTL_RTSEN Enable Request to Send 14 15 UART_CTL_RXE UART Receive Enable 9 10 UART_CTL_SIREN UART SIR Enable 1 2 UART_CTL_SIRLP UART SIR Low-Power Mode 2 3 UART_CTL_SMART ISO 7816 Smart Card Support 3 4 UART_CTL_TXE UART Transmit Enable 8 9 UART_CTL_UARTEN UART Enable 0 1 DMACTL UART DMA Control 0x48 -1 read-write n 0x0 0x0 UART_DMACTL_DMAERR DMA on Error 2 3 UART_DMACTL_RXDMAE Receive DMA Enable 0 1 UART_DMACTL_TXDMAE Transmit DMA Enable 1 2 DR UART Data 0x0 -1 read-write n 0x0 0x0 UART_DR_BE UART Break Error 10 11 UART_DR_DATA Data Transmitted or Received 0 8 UART_DR_FE UART Framing Error 8 9 UART_DR_OE UART Overrun Error 11 12 UART_DR_PE UART Parity Error 9 10 ECR UART Receive Status/Error Clear 0x4 -1 read-write n 0x0 0x0 UART_ECR_DATA Error Clear 0 8 FBRD UART Fractional Baud-Rate Divisor 0x28 -1 read-write n 0x0 0x0 UART_FBRD_DIVFRAC Fractional Baud-Rate Divisor 0 6 FR UART Flag 0x18 -1 read-write n 0x0 0x0 UART_FR_BUSY UART Busy 3 4 UART_FR_CTS Clear To Send 0 1 UART_FR_DCD Data Carrier Detect 2 3 UART_FR_DSR Data Set Ready 1 2 UART_FR_RI Ring Indicator 8 9 UART_FR_RXFE UART Receive FIFO Empty 4 5 UART_FR_RXFF UART Receive FIFO Full 6 7 UART_FR_TXFE UART Transmit FIFO Empty 7 8 UART_FR_TXFF UART Transmit FIFO Full 5 6 IBRD UART Integer Baud-Rate Divisor 0x24 -1 read-write n 0x0 0x0 UART_IBRD_DIVINT Integer Baud-Rate Divisor 0 16 ICR UART Interrupt Clear 0x44 -1 write-only n 0x0 0x0 UART_ICR_9BITIC 9-Bit Mode Interrupt Clear 12 13 write-only UART_ICR_BEIC Break Error Interrupt Clear 9 10 write-only UART_ICR_CTSMIC UART Clear to Send Modem Interrupt Clear 1 2 write-only UART_ICR_DCDMIC UART Data Carrier Detect Modem Interrupt Clear 2 3 write-only UART_ICR_DMARXIC Receive DMA Interrupt Clear 16 17 write-only UART_ICR_DMATXIC Transmit DMA Interrupt Clear 17 18 write-only UART_ICR_DSRMIC UART Data Set Ready Modem Interrupt Clear 3 4 write-only UART_ICR_EOTIC End of Transmission Interrupt Clear 11 12 write-only UART_ICR_FEIC Framing Error Interrupt Clear 7 8 write-only UART_ICR_OEIC Overrun Error Interrupt Clear 10 11 write-only UART_ICR_PEIC Parity Error Interrupt Clear 8 9 write-only UART_ICR_RIMIC UART Ring Indicator Modem Interrupt Clear 0 1 write-only UART_ICR_RTIC Receive Time-Out Interrupt Clear 6 7 write-only UART_ICR_RXIC Receive Interrupt Clear 4 5 write-only UART_ICR_TXIC Transmit Interrupt Clear 5 6 write-only IFLS UART Interrupt FIFO Level Select 0x34 -1 read-write n 0x0 0x0 UART_IFLS_RX UART Receive Interrupt FIFO Level Select 3 6 UART_IFLS_RX1_8 RX FIFO >= 1/8 full 0x0 UART_IFLS_RX2_8 RX FIFO >= 1/4 full 0x1 UART_IFLS_RX4_8 RX FIFO >= 1/2 full (default) 0x2 UART_IFLS_RX6_8 RX FIFO >= 3/4 full 0x3 UART_IFLS_RX7_8 RX FIFO >= 7/8 full 0x4 UART_IFLS_TX UART Transmit Interrupt FIFO Level Select 0 3 UART_IFLS_TX1_8 TX FIFO and lt = 1/8 full 0x0 UART_IFLS_TX2_8 TX FIFO and lt = 1/4 full 0x1 UART_IFLS_TX4_8 TX FIFO and lt = 1/2 full (default) 0x2 UART_IFLS_TX6_8 TX FIFO and lt = 3/4 full 0x3 UART_IFLS_TX7_8 TX FIFO and lt = 7/8 full 0x4 ILPR UART IrDA Low-Power Register 0x20 -1 read-write n 0x0 0x0 UART_ILPR_ILPDVSR IrDA Low-Power Divisor 0 8 IM UART Interrupt Mask 0x38 -1 read-write n 0x0 0x0 UART_IM_9BITIM 9-Bit Mode Interrupt Mask 12 13 UART_IM_BEIM UART Break Error Interrupt Mask 9 10 UART_IM_CTSMIM UART Clear to Send Modem Interrupt Mask 1 2 UART_IM_DCDMIM UART Data Carrier Detect Modem Interrupt Mask 2 3 UART_IM_DMARXIM Receive DMA Interrupt Mask 16 17 UART_IM_DMATXIM Transmit DMA Interrupt Mask 17 18 UART_IM_DSRMIM UART Data Set Ready Modem Interrupt Mask 3 4 UART_IM_EOTIM End of Transmission Interrupt Mask 11 12 UART_IM_FEIM UART Framing Error Interrupt Mask 7 8 UART_IM_OEIM UART Overrun Error Interrupt Mask 10 11 UART_IM_PEIM UART Parity Error Interrupt Mask 8 9 UART_IM_RIMIM UART Ring Indicator Modem Interrupt Mask 0 1 UART_IM_RTIM UART Receive Time-Out Interrupt Mask 6 7 UART_IM_RXIM UART Receive Interrupt Mask 4 5 UART_IM_TXIM UART Transmit Interrupt Mask 5 6 LCRH UART Line Control 0x2C -1 read-write n 0x0 0x0 UART_LCRH_BRK UART Send Break 0 1 UART_LCRH_EPS UART Even Parity Select 2 3 UART_LCRH_FEN UART Enable FIFOs 4 5 UART_LCRH_PEN UART Parity Enable 1 2 UART_LCRH_SPS UART Stick Parity Select 7 8 UART_LCRH_STP2 UART Two Stop Bits Select 3 4 UART_LCRH_WLEN UART Word Length 5 7 UART_LCRH_WLEN_5 5 bits (default) 0x0 UART_LCRH_WLEN_6 6 bits 0x1 UART_LCRH_WLEN_7 7 bits 0x2 UART_LCRH_WLEN_8 8 bits 0x3 MIS UART Masked Interrupt Status 0x40 -1 read-write n 0x0 0x0 UART_MIS_9BITMIS 9-Bit Mode Masked Interrupt Status 12 13 UART_MIS_BEMIS UART Break Error Masked Interrupt Status 9 10 UART_MIS_CTSMIS UART Clear to Send Modem Masked Interrupt Status 1 2 UART_MIS_DCDMIS UART Data Carrier Detect Modem Masked Interrupt Status 2 3 UART_MIS_DMARXMIS Receive DMA Masked Interrupt Status 16 17 UART_MIS_DMATXMIS Transmit DMA Masked Interrupt Status 17 18 UART_MIS_DSRMIS UART Data Set Ready Modem Masked Interrupt Status 3 4 UART_MIS_EOTMIS End of Transmission Masked Interrupt Status 11 12 UART_MIS_FEMIS UART Framing Error Masked Interrupt Status 7 8 UART_MIS_OEMIS UART Overrun Error Masked Interrupt Status 10 11 UART_MIS_PEMIS UART Parity Error Masked Interrupt Status 8 9 UART_MIS_RIMIS UART Ring Indicator Modem Masked Interrupt Status 0 1 UART_MIS_RTMIS UART Receive Time-Out Masked Interrupt Status 6 7 UART_MIS_RXMIS UART Receive Masked Interrupt Status 4 5 UART_MIS_TXMIS UART Transmit Masked Interrupt Status 5 6 PP UART Peripheral Properties 0xFC0 -1 read-write n 0x0 0x0 UART_PP_MS Modem Support 2 3 UART_PP_MSE Modem Support Extended 3 4 UART_PP_NB 9-Bit Support 1 2 UART_PP_SC Smart Card Support 0 1 RIS UART Raw Interrupt Status 0x3C -1 read-write n 0x0 0x0 UART_RIS_9BITRIS 9-Bit Mode Raw Interrupt Status 12 13 UART_RIS_BERIS UART Break Error Raw Interrupt Status 9 10 UART_RIS_CTSRIS UART Clear to Send Modem Raw Interrupt Status 1 2 UART_RIS_DCDRIS UART Data Carrier Detect Modem Raw Interrupt Status 2 3 UART_RIS_DMARXRIS Receive DMA Raw Interrupt Status 16 17 UART_RIS_DMATXRIS Transmit DMA Raw Interrupt Status 17 18 UART_RIS_DSRRIS UART Data Set Ready Modem Raw Interrupt Status 3 4 UART_RIS_EOTRIS End of Transmission Raw Interrupt Status 11 12 UART_RIS_FERIS UART Framing Error Raw Interrupt Status 7 8 UART_RIS_OERIS UART Overrun Error Raw Interrupt Status 10 11 UART_RIS_PERIS UART Parity Error Raw Interrupt Status 8 9 UART_RIS_RIRIS UART Ring Indicator Modem Raw Interrupt Status 0 1 UART_RIS_RTRIS UART Receive Time-Out Raw Interrupt Status 6 7 UART_RIS_RXRIS UART Receive Raw Interrupt Status 4 5 UART_RIS_TXRIS UART Transmit Raw Interrupt Status 5 6 RSR UART Receive Status/Error Clear 0x4 -1 read-write n 0x0 0x0 UART_RSR_BE UART Break Error 2 3 UART_RSR_FE UART Framing Error 0 1 UART_RSR_OE UART Overrun Error 3 4 UART_RSR_PE UART Parity Error 1 2 UART0CC UART Clock Configuration 0xFC8 read-write n 0x0 0x0 UART_CC_CS UART Baud Clock Source 0 4 UART_CC_CS_SYSCLK System clock (based on clock source and divisor factor) 0x0 UART_CC_CS_PIOSC PIOSC 0x5 UART0CTL UART Control 0x30 read-write n 0x0 0x0 UART_CTL_CTSEN Enable Clear To Send 15 16 UART_CTL_DTR Data Terminal Ready 10 11 UART_CTL_EOT End of Transmission 4 5 UART_CTL_HSE High-Speed Enable 5 6 UART_CTL_LBE UART Loop Back Enable 7 8 UART_CTL_RTS Request to Send 11 12 UART_CTL_RTSEN Enable Request to Send 14 15 UART_CTL_RXE UART Receive Enable 9 10 UART_CTL_SIREN UART SIR Enable 1 2 UART_CTL_SIRLP UART SIR Low-Power Mode 2 3 UART_CTL_SMART ISO 7816 Smart Card Support 3 4 UART_CTL_TXE UART Transmit Enable 8 9 UART_CTL_UARTEN UART Enable 0 1 UART0DMACTL UART DMA Control 0x48 read-write n 0x0 0x0 UART_DMACTL_DMAERR DMA on Error 2 3 UART_DMACTL_RXDMAE Receive DMA Enable 0 1 UART_DMACTL_TXDMAE Transmit DMA Enable 1 2 UART0DR UART Data 0x0 read-write n 0x0 0x0 UART_DR_BE UART Break Error 10 11 UART_DR_DATA Data Transmitted or Received 0 8 UART_DR_FE UART Framing Error 8 9 UART_DR_OE UART Overrun Error 11 12 UART_DR_PE UART Parity Error 9 10 UART0ECR UART Receive Status/Error Clear UART_ALT 0x4 read-write n 0x0 0x0 UART_ECR_DATA Error Clear 0 8 UART0FBRD UART Fractional Baud-Rate Divisor 0x28 read-write n 0x0 0x0 UART_FBRD_DIVFRAC Fractional Baud-Rate Divisor 0 6 UART0FR UART Flag 0x18 read-write n 0x0 0x0 UART_FR_BUSY UART Busy 3 4 UART_FR_CTS Clear To Send 0 1 UART_FR_DCD Data Carrier Detect 2 3 UART_FR_DSR Data Set Ready 1 2 UART_FR_RI Ring Indicator 8 9 UART_FR_RXFE UART Receive FIFO Empty 4 5 UART_FR_RXFF UART Receive FIFO Full 6 7 UART_FR_TXFE UART Transmit FIFO Empty 7 8 UART_FR_TXFF UART Transmit FIFO Full 5 6 UART0IBRD UART Integer Baud-Rate Divisor 0x24 read-write n 0x0 0x0 UART_IBRD_DIVINT Integer Baud-Rate Divisor 0 16 UART0ICR UART Interrupt Clear 0x44 write-only n 0x0 0x0 UART_ICR_9BITIC 9-Bit Mode Interrupt Clear 12 13 write-only UART_ICR_BEIC Break Error Interrupt Clear 9 10 write-only UART_ICR_CTSMIC UART Clear to Send Modem Interrupt Clear 1 2 write-only UART_ICR_DCDMIC UART Data Carrier Detect Modem Interrupt Clear 2 3 write-only UART_ICR_DMARXIC Receive DMA Interrupt Clear 16 17 write-only UART_ICR_DMATXIC Transmit DMA Interrupt Clear 17 18 write-only UART_ICR_DSRMIC UART Data Set Ready Modem Interrupt Clear 3 4 write-only UART_ICR_EOTIC End of Transmission Interrupt Clear 11 12 write-only UART_ICR_FEIC Framing Error Interrupt Clear 7 8 write-only UART_ICR_OEIC Overrun Error Interrupt Clear 10 11 write-only UART_ICR_PEIC Parity Error Interrupt Clear 8 9 write-only UART_ICR_RIMIC UART Ring Indicator Modem Interrupt Clear 0 1 write-only UART_ICR_RTIC Receive Time-Out Interrupt Clear 6 7 write-only UART_ICR_RXIC Receive Interrupt Clear 4 5 write-only UART_ICR_TXIC Transmit Interrupt Clear 5 6 write-only UART0IFLS UART Interrupt FIFO Level Select 0x34 read-write n 0x0 0x0 UART_IFLS_RX UART Receive Interrupt FIFO Level Select 3 6 UART_IFLS_RX1_8 RX FIFO >= 1/8 full 0x0 UART_IFLS_RX2_8 RX FIFO >= 1/4 full 0x1 UART_IFLS_RX4_8 RX FIFO >= 1/2 full (default) 0x2 UART_IFLS_RX6_8 RX FIFO >= 3/4 full 0x3 UART_IFLS_RX7_8 RX FIFO >= 7/8 full 0x4 UART_IFLS_TX UART Transmit Interrupt FIFO Level Select 0 3 UART_IFLS_TX1_8 TX FIFO <= 1/8 full 0x0 UART_IFLS_TX2_8 TX FIFO <= 1/4 full 0x1 UART_IFLS_TX4_8 TX FIFO <= 1/2 full (default) 0x2 UART_IFLS_TX6_8 TX FIFO <= 3/4 full 0x3 UART_IFLS_TX7_8 TX FIFO <= 7/8 full 0x4 UART0ILPR UART IrDA Low-Power Register 0x20 read-write n 0x0 0x0 UART_ILPR_ILPDVSR IrDA Low-Power Divisor 0 8 UART0IM UART Interrupt Mask 0x38 read-write n 0x0 0x0 UART_IM_9BITIM 9-Bit Mode Interrupt Mask 12 13 UART_IM_BEIM UART Break Error Interrupt Mask 9 10 UART_IM_CTSMIM UART Clear to Send Modem Interrupt Mask 1 2 UART_IM_DCDMIM UART Data Carrier Detect Modem Interrupt Mask 2 3 UART_IM_DMARXIM Receive DMA Interrupt Mask 16 17 UART_IM_DMATXIM Transmit DMA Interrupt Mask 17 18 UART_IM_DSRMIM UART Data Set Ready Modem Interrupt Mask 3 4 UART_IM_EOTIM End of Transmission Interrupt Mask 11 12 UART_IM_FEIM UART Framing Error Interrupt Mask 7 8 UART_IM_OEIM UART Overrun Error Interrupt Mask 10 11 UART_IM_PEIM UART Parity Error Interrupt Mask 8 9 UART_IM_RIMIM UART Ring Indicator Modem Interrupt Mask 0 1 UART_IM_RTIM UART Receive Time-Out Interrupt Mask 6 7 UART_IM_RXIM UART Receive Interrupt Mask 4 5 UART_IM_TXIM UART Transmit Interrupt Mask 5 6 UART0LCRH UART Line Control 0x2C read-write n 0x0 0x0 UART_LCRH_BRK UART Send Break 0 1 UART_LCRH_EPS UART Even Parity Select 2 3 UART_LCRH_FEN UART Enable FIFOs 4 5 UART_LCRH_PEN UART Parity Enable 1 2 UART_LCRH_SPS UART Stick Parity Select 7 8 UART_LCRH_STP2 UART Two Stop Bits Select 3 4 UART_LCRH_WLEN UART Word Length 5 7 UART_LCRH_WLEN_5 5 bits (default) 0x0 UART_LCRH_WLEN_6 6 bits 0x1 UART_LCRH_WLEN_7 7 bits 0x2 UART_LCRH_WLEN_8 8 bits 0x3 UART0MIS UART Masked Interrupt Status 0x40 read-write n 0x0 0x0 UART_MIS_9BITMIS 9-Bit Mode Masked Interrupt Status 12 13 UART_MIS_BEMIS UART Break Error Masked Interrupt Status 9 10 UART_MIS_CTSMIS UART Clear to Send Modem Masked Interrupt Status 1 2 UART_MIS_DCDMIS UART Data Carrier Detect Modem Masked Interrupt Status 2 3 UART_MIS_DMARXMIS Receive DMA Masked Interrupt Status 16 17 UART_MIS_DMATXMIS Transmit DMA Masked Interrupt Status 17 18 UART_MIS_DSRMIS UART Data Set Ready Modem Masked Interrupt Status 3 4 UART_MIS_EOTMIS End of Transmission Masked Interrupt Status 11 12 UART_MIS_FEMIS UART Framing Error Masked Interrupt Status 7 8 UART_MIS_OEMIS UART Overrun Error Masked Interrupt Status 10 11 UART_MIS_PEMIS UART Parity Error Masked Interrupt Status 8 9 UART_MIS_RIMIS UART Ring Indicator Modem Masked Interrupt Status 0 1 UART_MIS_RTMIS UART Receive Time-Out Masked Interrupt Status 6 7 UART_MIS_RXMIS UART Receive Masked Interrupt Status 4 5 UART_MIS_TXMIS UART Transmit Masked Interrupt Status 5 6 UART0PP UART Peripheral Properties 0xFC0 read-write n 0x0 0x0 UART_PP_MS Modem Support 2 3 UART_PP_MSE Modem Support Extended 3 4 UART_PP_NB 9-Bit Support 1 2 UART_PP_SC Smart Card Support 0 1 UART0RIS UART Raw Interrupt Status 0x3C read-write n 0x0 0x0 UART_RIS_9BITRIS 9-Bit Mode Raw Interrupt Status 12 13 UART_RIS_BERIS UART Break Error Raw Interrupt Status 9 10 UART_RIS_CTSRIS UART Clear to Send Modem Raw Interrupt Status 1 2 UART_RIS_DCDRIS UART Data Carrier Detect Modem Raw Interrupt Status 2 3 UART_RIS_DMARXRIS Receive DMA Raw Interrupt Status 16 17 UART_RIS_DMATXRIS Transmit DMA Raw Interrupt Status 17 18 UART_RIS_DSRRIS UART Data Set Ready Modem Raw Interrupt Status 3 4 UART_RIS_EOTRIS End of Transmission Raw Interrupt Status 11 12 UART_RIS_FERIS UART Framing Error Raw Interrupt Status 7 8 UART_RIS_OERIS UART Overrun Error Raw Interrupt Status 10 11 UART_RIS_PERIS UART Parity Error Raw Interrupt Status 8 9 UART_RIS_RIRIS UART Ring Indicator Modem Raw Interrupt Status 0 1 UART_RIS_RTRIS UART Receive Time-Out Raw Interrupt Status 6 7 UART_RIS_RXRIS UART Receive Raw Interrupt Status 4 5 UART_RIS_TXRIS UART Transmit Raw Interrupt Status 5 6 UART0RSR UART Receive Status/Error Clear 0x4 read-write n 0x0 0x0 UART_RSR_BE UART Break Error 2 3 UART_RSR_FE UART Framing Error 0 1 UART_RSR_OE UART Overrun Error 3 4 UART_RSR_PE UART Parity Error 1 2 _9BITADDR UART 9-Bit Self Address 0xA4 -1 read-write n 0x0 0x0 UART_9BITADDR_9BITEN Enable 9-Bit Mode 15 16 UART_9BITADDR_ADDR Self Address for 9-Bit Mode 0 8 _9BITAMASK UART 9-Bit Self Address Mask 0xA8 -1 read-write n 0x0 0x0 UART_9BITAMASK_MASK Self Address Mask for 9-Bit Mode 0 8 UART1 Register map for UART0 peripheral UART 0x0 0x0 0x1000 registers n UART1 6 9BITADDR UART 9-Bit Self Address 0xA4 read-write n 0x0 0x0 UART_9BITADDR_9BITEN Enable 9-Bit Mode 15 16 UART_9BITADDR_ADDR Self Address for 9-Bit Mode 0 8 9BITAMASK UART 9-Bit Self Address Mask 0xA8 read-write n 0x0 0x0 UART_9BITAMASK_MASK Self Address Mask for 9-Bit Mode 0 8 CC UART Clock Configuration 0xFC8 -1 read-write n 0x0 0x0 UART_CC_CS UART Baud Clock Source 0 4 UART_CC_CS_SYSCLK System clock (based on clock source and divisor factor) 0x0 UART_CC_CS_PIOSC PIOSC 0x5 CTL UART Control 0x30 -1 read-write n 0x0 0x0 UART_CTL_CTSEN Enable Clear To Send 15 16 UART_CTL_DTR Data Terminal Ready 10 11 UART_CTL_EOT End of Transmission 4 5 UART_CTL_HSE High-Speed Enable 5 6 UART_CTL_LBE UART Loop Back Enable 7 8 UART_CTL_RTS Request to Send 11 12 UART_CTL_RTSEN Enable Request to Send 14 15 UART_CTL_RXE UART Receive Enable 9 10 UART_CTL_SIREN UART SIR Enable 1 2 UART_CTL_SIRLP UART SIR Low-Power Mode 2 3 UART_CTL_SMART ISO 7816 Smart Card Support 3 4 UART_CTL_TXE UART Transmit Enable 8 9 UART_CTL_UARTEN UART Enable 0 1 DMACTL UART DMA Control 0x48 -1 read-write n 0x0 0x0 UART_DMACTL_DMAERR DMA on Error 2 3 UART_DMACTL_RXDMAE Receive DMA Enable 0 1 UART_DMACTL_TXDMAE Transmit DMA Enable 1 2 DR UART Data 0x0 -1 read-write n 0x0 0x0 UART_DR_BE UART Break Error 10 11 UART_DR_DATA Data Transmitted or Received 0 8 UART_DR_FE UART Framing Error 8 9 UART_DR_OE UART Overrun Error 11 12 UART_DR_PE UART Parity Error 9 10 ECR UART Receive Status/Error Clear 0x4 -1 read-write n 0x0 0x0 UART_ECR_DATA Error Clear 0 8 FBRD UART Fractional Baud-Rate Divisor 0x28 -1 read-write n 0x0 0x0 UART_FBRD_DIVFRAC Fractional Baud-Rate Divisor 0 6 FR UART Flag 0x18 -1 read-write n 0x0 0x0 UART_FR_BUSY UART Busy 3 4 UART_FR_CTS Clear To Send 0 1 UART_FR_DCD Data Carrier Detect 2 3 UART_FR_DSR Data Set Ready 1 2 UART_FR_RI Ring Indicator 8 9 UART_FR_RXFE UART Receive FIFO Empty 4 5 UART_FR_RXFF UART Receive FIFO Full 6 7 UART_FR_TXFE UART Transmit FIFO Empty 7 8 UART_FR_TXFF UART Transmit FIFO Full 5 6 IBRD UART Integer Baud-Rate Divisor 0x24 -1 read-write n 0x0 0x0 UART_IBRD_DIVINT Integer Baud-Rate Divisor 0 16 ICR UART Interrupt Clear 0x44 -1 write-only n 0x0 0x0 UART_ICR_9BITIC 9-Bit Mode Interrupt Clear 12 13 write-only UART_ICR_BEIC Break Error Interrupt Clear 9 10 write-only UART_ICR_CTSMIC UART Clear to Send Modem Interrupt Clear 1 2 write-only UART_ICR_DCDMIC UART Data Carrier Detect Modem Interrupt Clear 2 3 write-only UART_ICR_DMARXIC Receive DMA Interrupt Clear 16 17 write-only UART_ICR_DMATXIC Transmit DMA Interrupt Clear 17 18 write-only UART_ICR_DSRMIC UART Data Set Ready Modem Interrupt Clear 3 4 write-only UART_ICR_EOTIC End of Transmission Interrupt Clear 11 12 write-only UART_ICR_FEIC Framing Error Interrupt Clear 7 8 write-only UART_ICR_OEIC Overrun Error Interrupt Clear 10 11 write-only UART_ICR_PEIC Parity Error Interrupt Clear 8 9 write-only UART_ICR_RIMIC UART Ring Indicator Modem Interrupt Clear 0 1 write-only UART_ICR_RTIC Receive Time-Out Interrupt Clear 6 7 write-only UART_ICR_RXIC Receive Interrupt Clear 4 5 write-only UART_ICR_TXIC Transmit Interrupt Clear 5 6 write-only IFLS UART Interrupt FIFO Level Select 0x34 -1 read-write n 0x0 0x0 UART_IFLS_RX UART Receive Interrupt FIFO Level Select 3 6 UART_IFLS_RX1_8 RX FIFO >= 1/8 full 0x0 UART_IFLS_RX2_8 RX FIFO >= 1/4 full 0x1 UART_IFLS_RX4_8 RX FIFO >= 1/2 full (default) 0x2 UART_IFLS_RX6_8 RX FIFO >= 3/4 full 0x3 UART_IFLS_RX7_8 RX FIFO >= 7/8 full 0x4 UART_IFLS_TX UART Transmit Interrupt FIFO Level Select 0 3 UART_IFLS_TX1_8 TX FIFO and lt = 1/8 full 0x0 UART_IFLS_TX2_8 TX FIFO and lt = 1/4 full 0x1 UART_IFLS_TX4_8 TX FIFO and lt = 1/2 full (default) 0x2 UART_IFLS_TX6_8 TX FIFO and lt = 3/4 full 0x3 UART_IFLS_TX7_8 TX FIFO and lt = 7/8 full 0x4 ILPR UART IrDA Low-Power Register 0x20 -1 read-write n 0x0 0x0 UART_ILPR_ILPDVSR IrDA Low-Power Divisor 0 8 IM UART Interrupt Mask 0x38 -1 read-write n 0x0 0x0 UART_IM_9BITIM 9-Bit Mode Interrupt Mask 12 13 UART_IM_BEIM UART Break Error Interrupt Mask 9 10 UART_IM_CTSMIM UART Clear to Send Modem Interrupt Mask 1 2 UART_IM_DCDMIM UART Data Carrier Detect Modem Interrupt Mask 2 3 UART_IM_DMARXIM Receive DMA Interrupt Mask 16 17 UART_IM_DMATXIM Transmit DMA Interrupt Mask 17 18 UART_IM_DSRMIM UART Data Set Ready Modem Interrupt Mask 3 4 UART_IM_EOTIM End of Transmission Interrupt Mask 11 12 UART_IM_FEIM UART Framing Error Interrupt Mask 7 8 UART_IM_OEIM UART Overrun Error Interrupt Mask 10 11 UART_IM_PEIM UART Parity Error Interrupt Mask 8 9 UART_IM_RIMIM UART Ring Indicator Modem Interrupt Mask 0 1 UART_IM_RTIM UART Receive Time-Out Interrupt Mask 6 7 UART_IM_RXIM UART Receive Interrupt Mask 4 5 UART_IM_TXIM UART Transmit Interrupt Mask 5 6 LCRH UART Line Control 0x2C -1 read-write n 0x0 0x0 UART_LCRH_BRK UART Send Break 0 1 UART_LCRH_EPS UART Even Parity Select 2 3 UART_LCRH_FEN UART Enable FIFOs 4 5 UART_LCRH_PEN UART Parity Enable 1 2 UART_LCRH_SPS UART Stick Parity Select 7 8 UART_LCRH_STP2 UART Two Stop Bits Select 3 4 UART_LCRH_WLEN UART Word Length 5 7 UART_LCRH_WLEN_5 5 bits (default) 0x0 UART_LCRH_WLEN_6 6 bits 0x1 UART_LCRH_WLEN_7 7 bits 0x2 UART_LCRH_WLEN_8 8 bits 0x3 MIS UART Masked Interrupt Status 0x40 -1 read-write n 0x0 0x0 UART_MIS_9BITMIS 9-Bit Mode Masked Interrupt Status 12 13 UART_MIS_BEMIS UART Break Error Masked Interrupt Status 9 10 UART_MIS_CTSMIS UART Clear to Send Modem Masked Interrupt Status 1 2 UART_MIS_DCDMIS UART Data Carrier Detect Modem Masked Interrupt Status 2 3 UART_MIS_DMARXMIS Receive DMA Masked Interrupt Status 16 17 UART_MIS_DMATXMIS Transmit DMA Masked Interrupt Status 17 18 UART_MIS_DSRMIS UART Data Set Ready Modem Masked Interrupt Status 3 4 UART_MIS_EOTMIS End of Transmission Masked Interrupt Status 11 12 UART_MIS_FEMIS UART Framing Error Masked Interrupt Status 7 8 UART_MIS_OEMIS UART Overrun Error Masked Interrupt Status 10 11 UART_MIS_PEMIS UART Parity Error Masked Interrupt Status 8 9 UART_MIS_RIMIS UART Ring Indicator Modem Masked Interrupt Status 0 1 UART_MIS_RTMIS UART Receive Time-Out Masked Interrupt Status 6 7 UART_MIS_RXMIS UART Receive Masked Interrupt Status 4 5 UART_MIS_TXMIS UART Transmit Masked Interrupt Status 5 6 PP UART Peripheral Properties 0xFC0 -1 read-write n 0x0 0x0 UART_PP_MS Modem Support 2 3 UART_PP_MSE Modem Support Extended 3 4 UART_PP_NB 9-Bit Support 1 2 UART_PP_SC Smart Card Support 0 1 RIS UART Raw Interrupt Status 0x3C -1 read-write n 0x0 0x0 UART_RIS_9BITRIS 9-Bit Mode Raw Interrupt Status 12 13 UART_RIS_BERIS UART Break Error Raw Interrupt Status 9 10 UART_RIS_CTSRIS UART Clear to Send Modem Raw Interrupt Status 1 2 UART_RIS_DCDRIS UART Data Carrier Detect Modem Raw Interrupt Status 2 3 UART_RIS_DMARXRIS Receive DMA Raw Interrupt Status 16 17 UART_RIS_DMATXRIS Transmit DMA Raw Interrupt Status 17 18 UART_RIS_DSRRIS UART Data Set Ready Modem Raw Interrupt Status 3 4 UART_RIS_EOTRIS End of Transmission Raw Interrupt Status 11 12 UART_RIS_FERIS UART Framing Error Raw Interrupt Status 7 8 UART_RIS_OERIS UART Overrun Error Raw Interrupt Status 10 11 UART_RIS_PERIS UART Parity Error Raw Interrupt Status 8 9 UART_RIS_RIRIS UART Ring Indicator Modem Raw Interrupt Status 0 1 UART_RIS_RTRIS UART Receive Time-Out Raw Interrupt Status 6 7 UART_RIS_RXRIS UART Receive Raw Interrupt Status 4 5 UART_RIS_TXRIS UART Transmit Raw Interrupt Status 5 6 RSR UART Receive Status/Error Clear 0x4 -1 read-write n 0x0 0x0 UART_RSR_BE UART Break Error 2 3 UART_RSR_FE UART Framing Error 0 1 UART_RSR_OE UART Overrun Error 3 4 UART_RSR_PE UART Parity Error 1 2 UART0CC UART Clock Configuration 0xFC8 read-write n 0x0 0x0 UART_CC_CS UART Baud Clock Source 0 4 UART_CC_CS_SYSCLK System clock (based on clock source and divisor factor) 0x0 UART_CC_CS_PIOSC PIOSC 0x5 UART0CTL UART Control 0x30 read-write n 0x0 0x0 UART_CTL_CTSEN Enable Clear To Send 15 16 UART_CTL_DTR Data Terminal Ready 10 11 UART_CTL_EOT End of Transmission 4 5 UART_CTL_HSE High-Speed Enable 5 6 UART_CTL_LBE UART Loop Back Enable 7 8 UART_CTL_RTS Request to Send 11 12 UART_CTL_RTSEN Enable Request to Send 14 15 UART_CTL_RXE UART Receive Enable 9 10 UART_CTL_SIREN UART SIR Enable 1 2 UART_CTL_SIRLP UART SIR Low-Power Mode 2 3 UART_CTL_SMART ISO 7816 Smart Card Support 3 4 UART_CTL_TXE UART Transmit Enable 8 9 UART_CTL_UARTEN UART Enable 0 1 UART0DMACTL UART DMA Control 0x48 read-write n 0x0 0x0 UART_DMACTL_DMAERR DMA on Error 2 3 UART_DMACTL_RXDMAE Receive DMA Enable 0 1 UART_DMACTL_TXDMAE Transmit DMA Enable 1 2 UART0DR UART Data 0x0 read-write n 0x0 0x0 UART_DR_BE UART Break Error 10 11 UART_DR_DATA Data Transmitted or Received 0 8 UART_DR_FE UART Framing Error 8 9 UART_DR_OE UART Overrun Error 11 12 UART_DR_PE UART Parity Error 9 10 UART0ECR UART Receive Status/Error Clear UART_ALT 0x4 read-write n 0x0 0x0 UART_ECR_DATA Error Clear 0 8 UART0FBRD UART Fractional Baud-Rate Divisor 0x28 read-write n 0x0 0x0 UART_FBRD_DIVFRAC Fractional Baud-Rate Divisor 0 6 UART0FR UART Flag 0x18 read-write n 0x0 0x0 UART_FR_BUSY UART Busy 3 4 UART_FR_CTS Clear To Send 0 1 UART_FR_DCD Data Carrier Detect 2 3 UART_FR_DSR Data Set Ready 1 2 UART_FR_RI Ring Indicator 8 9 UART_FR_RXFE UART Receive FIFO Empty 4 5 UART_FR_RXFF UART Receive FIFO Full 6 7 UART_FR_TXFE UART Transmit FIFO Empty 7 8 UART_FR_TXFF UART Transmit FIFO Full 5 6 UART0IBRD UART Integer Baud-Rate Divisor 0x24 read-write n 0x0 0x0 UART_IBRD_DIVINT Integer Baud-Rate Divisor 0 16 UART0ICR UART Interrupt Clear 0x44 write-only n 0x0 0x0 UART_ICR_9BITIC 9-Bit Mode Interrupt Clear 12 13 write-only UART_ICR_BEIC Break Error Interrupt Clear 9 10 write-only UART_ICR_CTSMIC UART Clear to Send Modem Interrupt Clear 1 2 write-only UART_ICR_DCDMIC UART Data Carrier Detect Modem Interrupt Clear 2 3 write-only UART_ICR_DMARXIC Receive DMA Interrupt Clear 16 17 write-only UART_ICR_DMATXIC Transmit DMA Interrupt Clear 17 18 write-only UART_ICR_DSRMIC UART Data Set Ready Modem Interrupt Clear 3 4 write-only UART_ICR_EOTIC End of Transmission Interrupt Clear 11 12 write-only UART_ICR_FEIC Framing Error Interrupt Clear 7 8 write-only UART_ICR_OEIC Overrun Error Interrupt Clear 10 11 write-only UART_ICR_PEIC Parity Error Interrupt Clear 8 9 write-only UART_ICR_RIMIC UART Ring Indicator Modem Interrupt Clear 0 1 write-only UART_ICR_RTIC Receive Time-Out Interrupt Clear 6 7 write-only UART_ICR_RXIC Receive Interrupt Clear 4 5 write-only UART_ICR_TXIC Transmit Interrupt Clear 5 6 write-only UART0IFLS UART Interrupt FIFO Level Select 0x34 read-write n 0x0 0x0 UART_IFLS_RX UART Receive Interrupt FIFO Level Select 3 6 UART_IFLS_RX1_8 RX FIFO >= 1/8 full 0x0 UART_IFLS_RX2_8 RX FIFO >= 1/4 full 0x1 UART_IFLS_RX4_8 RX FIFO >= 1/2 full (default) 0x2 UART_IFLS_RX6_8 RX FIFO >= 3/4 full 0x3 UART_IFLS_RX7_8 RX FIFO >= 7/8 full 0x4 UART_IFLS_TX UART Transmit Interrupt FIFO Level Select 0 3 UART_IFLS_TX1_8 TX FIFO <= 1/8 full 0x0 UART_IFLS_TX2_8 TX FIFO <= 1/4 full 0x1 UART_IFLS_TX4_8 TX FIFO <= 1/2 full (default) 0x2 UART_IFLS_TX6_8 TX FIFO <= 3/4 full 0x3 UART_IFLS_TX7_8 TX FIFO <= 7/8 full 0x4 UART0ILPR UART IrDA Low-Power Register 0x20 read-write n 0x0 0x0 UART_ILPR_ILPDVSR IrDA Low-Power Divisor 0 8 UART0IM UART Interrupt Mask 0x38 read-write n 0x0 0x0 UART_IM_9BITIM 9-Bit Mode Interrupt Mask 12 13 UART_IM_BEIM UART Break Error Interrupt Mask 9 10 UART_IM_CTSMIM UART Clear to Send Modem Interrupt Mask 1 2 UART_IM_DCDMIM UART Data Carrier Detect Modem Interrupt Mask 2 3 UART_IM_DMARXIM Receive DMA Interrupt Mask 16 17 UART_IM_DMATXIM Transmit DMA Interrupt Mask 17 18 UART_IM_DSRMIM UART Data Set Ready Modem Interrupt Mask 3 4 UART_IM_EOTIM End of Transmission Interrupt Mask 11 12 UART_IM_FEIM UART Framing Error Interrupt Mask 7 8 UART_IM_OEIM UART Overrun Error Interrupt Mask 10 11 UART_IM_PEIM UART Parity Error Interrupt Mask 8 9 UART_IM_RIMIM UART Ring Indicator Modem Interrupt Mask 0 1 UART_IM_RTIM UART Receive Time-Out Interrupt Mask 6 7 UART_IM_RXIM UART Receive Interrupt Mask 4 5 UART_IM_TXIM UART Transmit Interrupt Mask 5 6 UART0LCRH UART Line Control 0x2C read-write n 0x0 0x0 UART_LCRH_BRK UART Send Break 0 1 UART_LCRH_EPS UART Even Parity Select 2 3 UART_LCRH_FEN UART Enable FIFOs 4 5 UART_LCRH_PEN UART Parity Enable 1 2 UART_LCRH_SPS UART Stick Parity Select 7 8 UART_LCRH_STP2 UART Two Stop Bits Select 3 4 UART_LCRH_WLEN UART Word Length 5 7 UART_LCRH_WLEN_5 5 bits (default) 0x0 UART_LCRH_WLEN_6 6 bits 0x1 UART_LCRH_WLEN_7 7 bits 0x2 UART_LCRH_WLEN_8 8 bits 0x3 UART0MIS UART Masked Interrupt Status 0x40 read-write n 0x0 0x0 UART_MIS_9BITMIS 9-Bit Mode Masked Interrupt Status 12 13 UART_MIS_BEMIS UART Break Error Masked Interrupt Status 9 10 UART_MIS_CTSMIS UART Clear to Send Modem Masked Interrupt Status 1 2 UART_MIS_DCDMIS UART Data Carrier Detect Modem Masked Interrupt Status 2 3 UART_MIS_DMARXMIS Receive DMA Masked Interrupt Status 16 17 UART_MIS_DMATXMIS Transmit DMA Masked Interrupt Status 17 18 UART_MIS_DSRMIS UART Data Set Ready Modem Masked Interrupt Status 3 4 UART_MIS_EOTMIS End of Transmission Masked Interrupt Status 11 12 UART_MIS_FEMIS UART Framing Error Masked Interrupt Status 7 8 UART_MIS_OEMIS UART Overrun Error Masked Interrupt Status 10 11 UART_MIS_PEMIS UART Parity Error Masked Interrupt Status 8 9 UART_MIS_RIMIS UART Ring Indicator Modem Masked Interrupt Status 0 1 UART_MIS_RTMIS UART Receive Time-Out Masked Interrupt Status 6 7 UART_MIS_RXMIS UART Receive Masked Interrupt Status 4 5 UART_MIS_TXMIS UART Transmit Masked Interrupt Status 5 6 UART0PP UART Peripheral Properties 0xFC0 read-write n 0x0 0x0 UART_PP_MS Modem Support 2 3 UART_PP_MSE Modem Support Extended 3 4 UART_PP_NB 9-Bit Support 1 2 UART_PP_SC Smart Card Support 0 1 UART0RIS UART Raw Interrupt Status 0x3C read-write n 0x0 0x0 UART_RIS_9BITRIS 9-Bit Mode Raw Interrupt Status 12 13 UART_RIS_BERIS UART Break Error Raw Interrupt Status 9 10 UART_RIS_CTSRIS UART Clear to Send Modem Raw Interrupt Status 1 2 UART_RIS_DCDRIS UART Data Carrier Detect Modem Raw Interrupt Status 2 3 UART_RIS_DMARXRIS Receive DMA Raw Interrupt Status 16 17 UART_RIS_DMATXRIS Transmit DMA Raw Interrupt Status 17 18 UART_RIS_DSRRIS UART Data Set Ready Modem Raw Interrupt Status 3 4 UART_RIS_EOTRIS End of Transmission Raw Interrupt Status 11 12 UART_RIS_FERIS UART Framing Error Raw Interrupt Status 7 8 UART_RIS_OERIS UART Overrun Error Raw Interrupt Status 10 11 UART_RIS_PERIS UART Parity Error Raw Interrupt Status 8 9 UART_RIS_RIRIS UART Ring Indicator Modem Raw Interrupt Status 0 1 UART_RIS_RTRIS UART Receive Time-Out Raw Interrupt Status 6 7 UART_RIS_RXRIS UART Receive Raw Interrupt Status 4 5 UART_RIS_TXRIS UART Transmit Raw Interrupt Status 5 6 UART0RSR UART Receive Status/Error Clear 0x4 read-write n 0x0 0x0 UART_RSR_BE UART Break Error 2 3 UART_RSR_FE UART Framing Error 0 1 UART_RSR_OE UART Overrun Error 3 4 UART_RSR_PE UART Parity Error 1 2 _9BITADDR UART 9-Bit Self Address 0xA4 -1 read-write n 0x0 0x0 UART_9BITADDR_9BITEN Enable 9-Bit Mode 15 16 UART_9BITADDR_ADDR Self Address for 9-Bit Mode 0 8 _9BITAMASK UART 9-Bit Self Address Mask 0xA8 -1 read-write n 0x0 0x0 UART_9BITAMASK_MASK Self Address Mask for 9-Bit Mode 0 8 UART2 Register map for UART0 peripheral UART 0x0 0x0 0x1000 registers n UART2 33 9BITADDR UART 9-Bit Self Address 0xA4 read-write n 0x0 0x0 UART_9BITADDR_9BITEN Enable 9-Bit Mode 15 16 UART_9BITADDR_ADDR Self Address for 9-Bit Mode 0 8 9BITAMASK UART 9-Bit Self Address Mask 0xA8 read-write n 0x0 0x0 UART_9BITAMASK_MASK Self Address Mask for 9-Bit Mode 0 8 CC UART Clock Configuration 0xFC8 -1 read-write n 0x0 0x0 UART_CC_CS UART Baud Clock Source 0 4 UART_CC_CS_SYSCLK System clock (based on clock source and divisor factor) 0x0 UART_CC_CS_PIOSC PIOSC 0x5 CTL UART Control 0x30 -1 read-write n 0x0 0x0 UART_CTL_CTSEN Enable Clear To Send 15 16 UART_CTL_DTR Data Terminal Ready 10 11 UART_CTL_EOT End of Transmission 4 5 UART_CTL_HSE High-Speed Enable 5 6 UART_CTL_LBE UART Loop Back Enable 7 8 UART_CTL_RTS Request to Send 11 12 UART_CTL_RTSEN Enable Request to Send 14 15 UART_CTL_RXE UART Receive Enable 9 10 UART_CTL_SIREN UART SIR Enable 1 2 UART_CTL_SIRLP UART SIR Low-Power Mode 2 3 UART_CTL_SMART ISO 7816 Smart Card Support 3 4 UART_CTL_TXE UART Transmit Enable 8 9 UART_CTL_UARTEN UART Enable 0 1 DMACTL UART DMA Control 0x48 -1 read-write n 0x0 0x0 UART_DMACTL_DMAERR DMA on Error 2 3 UART_DMACTL_RXDMAE Receive DMA Enable 0 1 UART_DMACTL_TXDMAE Transmit DMA Enable 1 2 DR UART Data 0x0 -1 read-write n 0x0 0x0 UART_DR_BE UART Break Error 10 11 UART_DR_DATA Data Transmitted or Received 0 8 UART_DR_FE UART Framing Error 8 9 UART_DR_OE UART Overrun Error 11 12 UART_DR_PE UART Parity Error 9 10 ECR UART Receive Status/Error Clear 0x4 -1 read-write n 0x0 0x0 UART_ECR_DATA Error Clear 0 8 FBRD UART Fractional Baud-Rate Divisor 0x28 -1 read-write n 0x0 0x0 UART_FBRD_DIVFRAC Fractional Baud-Rate Divisor 0 6 FR UART Flag 0x18 -1 read-write n 0x0 0x0 UART_FR_BUSY UART Busy 3 4 UART_FR_CTS Clear To Send 0 1 UART_FR_DCD Data Carrier Detect 2 3 UART_FR_DSR Data Set Ready 1 2 UART_FR_RI Ring Indicator 8 9 UART_FR_RXFE UART Receive FIFO Empty 4 5 UART_FR_RXFF UART Receive FIFO Full 6 7 UART_FR_TXFE UART Transmit FIFO Empty 7 8 UART_FR_TXFF UART Transmit FIFO Full 5 6 IBRD UART Integer Baud-Rate Divisor 0x24 -1 read-write n 0x0 0x0 UART_IBRD_DIVINT Integer Baud-Rate Divisor 0 16 ICR UART Interrupt Clear 0x44 -1 write-only n 0x0 0x0 UART_ICR_9BITIC 9-Bit Mode Interrupt Clear 12 13 write-only UART_ICR_BEIC Break Error Interrupt Clear 9 10 write-only UART_ICR_CTSMIC UART Clear to Send Modem Interrupt Clear 1 2 write-only UART_ICR_DCDMIC UART Data Carrier Detect Modem Interrupt Clear 2 3 write-only UART_ICR_DMARXIC Receive DMA Interrupt Clear 16 17 write-only UART_ICR_DMATXIC Transmit DMA Interrupt Clear 17 18 write-only UART_ICR_DSRMIC UART Data Set Ready Modem Interrupt Clear 3 4 write-only UART_ICR_EOTIC End of Transmission Interrupt Clear 11 12 write-only UART_ICR_FEIC Framing Error Interrupt Clear 7 8 write-only UART_ICR_OEIC Overrun Error Interrupt Clear 10 11 write-only UART_ICR_PEIC Parity Error Interrupt Clear 8 9 write-only UART_ICR_RIMIC UART Ring Indicator Modem Interrupt Clear 0 1 write-only UART_ICR_RTIC Receive Time-Out Interrupt Clear 6 7 write-only UART_ICR_RXIC Receive Interrupt Clear 4 5 write-only UART_ICR_TXIC Transmit Interrupt Clear 5 6 write-only IFLS UART Interrupt FIFO Level Select 0x34 -1 read-write n 0x0 0x0 UART_IFLS_RX UART Receive Interrupt FIFO Level Select 3 6 UART_IFLS_RX1_8 RX FIFO >= 1/8 full 0x0 UART_IFLS_RX2_8 RX FIFO >= 1/4 full 0x1 UART_IFLS_RX4_8 RX FIFO >= 1/2 full (default) 0x2 UART_IFLS_RX6_8 RX FIFO >= 3/4 full 0x3 UART_IFLS_RX7_8 RX FIFO >= 7/8 full 0x4 UART_IFLS_TX UART Transmit Interrupt FIFO Level Select 0 3 UART_IFLS_TX1_8 TX FIFO and lt = 1/8 full 0x0 UART_IFLS_TX2_8 TX FIFO and lt = 1/4 full 0x1 UART_IFLS_TX4_8 TX FIFO and lt = 1/2 full (default) 0x2 UART_IFLS_TX6_8 TX FIFO and lt = 3/4 full 0x3 UART_IFLS_TX7_8 TX FIFO and lt = 7/8 full 0x4 ILPR UART IrDA Low-Power Register 0x20 -1 read-write n 0x0 0x0 UART_ILPR_ILPDVSR IrDA Low-Power Divisor 0 8 IM UART Interrupt Mask 0x38 -1 read-write n 0x0 0x0 UART_IM_9BITIM 9-Bit Mode Interrupt Mask 12 13 UART_IM_BEIM UART Break Error Interrupt Mask 9 10 UART_IM_CTSMIM UART Clear to Send Modem Interrupt Mask 1 2 UART_IM_DCDMIM UART Data Carrier Detect Modem Interrupt Mask 2 3 UART_IM_DMARXIM Receive DMA Interrupt Mask 16 17 UART_IM_DMATXIM Transmit DMA Interrupt Mask 17 18 UART_IM_DSRMIM UART Data Set Ready Modem Interrupt Mask 3 4 UART_IM_EOTIM End of Transmission Interrupt Mask 11 12 UART_IM_FEIM UART Framing Error Interrupt Mask 7 8 UART_IM_OEIM UART Overrun Error Interrupt Mask 10 11 UART_IM_PEIM UART Parity Error Interrupt Mask 8 9 UART_IM_RIMIM UART Ring Indicator Modem Interrupt Mask 0 1 UART_IM_RTIM UART Receive Time-Out Interrupt Mask 6 7 UART_IM_RXIM UART Receive Interrupt Mask 4 5 UART_IM_TXIM UART Transmit Interrupt Mask 5 6 LCRH UART Line Control 0x2C -1 read-write n 0x0 0x0 UART_LCRH_BRK UART Send Break 0 1 UART_LCRH_EPS UART Even Parity Select 2 3 UART_LCRH_FEN UART Enable FIFOs 4 5 UART_LCRH_PEN UART Parity Enable 1 2 UART_LCRH_SPS UART Stick Parity Select 7 8 UART_LCRH_STP2 UART Two Stop Bits Select 3 4 UART_LCRH_WLEN UART Word Length 5 7 UART_LCRH_WLEN_5 5 bits (default) 0x0 UART_LCRH_WLEN_6 6 bits 0x1 UART_LCRH_WLEN_7 7 bits 0x2 UART_LCRH_WLEN_8 8 bits 0x3 MIS UART Masked Interrupt Status 0x40 -1 read-write n 0x0 0x0 UART_MIS_9BITMIS 9-Bit Mode Masked Interrupt Status 12 13 UART_MIS_BEMIS UART Break Error Masked Interrupt Status 9 10 UART_MIS_CTSMIS UART Clear to Send Modem Masked Interrupt Status 1 2 UART_MIS_DCDMIS UART Data Carrier Detect Modem Masked Interrupt Status 2 3 UART_MIS_DMARXMIS Receive DMA Masked Interrupt Status 16 17 UART_MIS_DMATXMIS Transmit DMA Masked Interrupt Status 17 18 UART_MIS_DSRMIS UART Data Set Ready Modem Masked Interrupt Status 3 4 UART_MIS_EOTMIS End of Transmission Masked Interrupt Status 11 12 UART_MIS_FEMIS UART Framing Error Masked Interrupt Status 7 8 UART_MIS_OEMIS UART Overrun Error Masked Interrupt Status 10 11 UART_MIS_PEMIS UART Parity Error Masked Interrupt Status 8 9 UART_MIS_RIMIS UART Ring Indicator Modem Masked Interrupt Status 0 1 UART_MIS_RTMIS UART Receive Time-Out Masked Interrupt Status 6 7 UART_MIS_RXMIS UART Receive Masked Interrupt Status 4 5 UART_MIS_TXMIS UART Transmit Masked Interrupt Status 5 6 PP UART Peripheral Properties 0xFC0 -1 read-write n 0x0 0x0 UART_PP_MS Modem Support 2 3 UART_PP_MSE Modem Support Extended 3 4 UART_PP_NB 9-Bit Support 1 2 UART_PP_SC Smart Card Support 0 1 RIS UART Raw Interrupt Status 0x3C -1 read-write n 0x0 0x0 UART_RIS_9BITRIS 9-Bit Mode Raw Interrupt Status 12 13 UART_RIS_BERIS UART Break Error Raw Interrupt Status 9 10 UART_RIS_CTSRIS UART Clear to Send Modem Raw Interrupt Status 1 2 UART_RIS_DCDRIS UART Data Carrier Detect Modem Raw Interrupt Status 2 3 UART_RIS_DMARXRIS Receive DMA Raw Interrupt Status 16 17 UART_RIS_DMATXRIS Transmit DMA Raw Interrupt Status 17 18 UART_RIS_DSRRIS UART Data Set Ready Modem Raw Interrupt Status 3 4 UART_RIS_EOTRIS End of Transmission Raw Interrupt Status 11 12 UART_RIS_FERIS UART Framing Error Raw Interrupt Status 7 8 UART_RIS_OERIS UART Overrun Error Raw Interrupt Status 10 11 UART_RIS_PERIS UART Parity Error Raw Interrupt Status 8 9 UART_RIS_RIRIS UART Ring Indicator Modem Raw Interrupt Status 0 1 UART_RIS_RTRIS UART Receive Time-Out Raw Interrupt Status 6 7 UART_RIS_RXRIS UART Receive Raw Interrupt Status 4 5 UART_RIS_TXRIS UART Transmit Raw Interrupt Status 5 6 RSR UART Receive Status/Error Clear 0x4 -1 read-write n 0x0 0x0 UART_RSR_BE UART Break Error 2 3 UART_RSR_FE UART Framing Error 0 1 UART_RSR_OE UART Overrun Error 3 4 UART_RSR_PE UART Parity Error 1 2 UART0CC UART Clock Configuration 0xFC8 read-write n 0x0 0x0 UART_CC_CS UART Baud Clock Source 0 4 UART_CC_CS_SYSCLK System clock (based on clock source and divisor factor) 0x0 UART_CC_CS_PIOSC PIOSC 0x5 UART0CTL UART Control 0x30 read-write n 0x0 0x0 UART_CTL_CTSEN Enable Clear To Send 15 16 UART_CTL_DTR Data Terminal Ready 10 11 UART_CTL_EOT End of Transmission 4 5 UART_CTL_HSE High-Speed Enable 5 6 UART_CTL_LBE UART Loop Back Enable 7 8 UART_CTL_RTS Request to Send 11 12 UART_CTL_RTSEN Enable Request to Send 14 15 UART_CTL_RXE UART Receive Enable 9 10 UART_CTL_SIREN UART SIR Enable 1 2 UART_CTL_SIRLP UART SIR Low-Power Mode 2 3 UART_CTL_SMART ISO 7816 Smart Card Support 3 4 UART_CTL_TXE UART Transmit Enable 8 9 UART_CTL_UARTEN UART Enable 0 1 UART0DMACTL UART DMA Control 0x48 read-write n 0x0 0x0 UART_DMACTL_DMAERR DMA on Error 2 3 UART_DMACTL_RXDMAE Receive DMA Enable 0 1 UART_DMACTL_TXDMAE Transmit DMA Enable 1 2 UART0DR UART Data 0x0 read-write n 0x0 0x0 UART_DR_BE UART Break Error 10 11 UART_DR_DATA Data Transmitted or Received 0 8 UART_DR_FE UART Framing Error 8 9 UART_DR_OE UART Overrun Error 11 12 UART_DR_PE UART Parity Error 9 10 UART0ECR UART Receive Status/Error Clear UART_ALT 0x4 read-write n 0x0 0x0 UART_ECR_DATA Error Clear 0 8 UART0FBRD UART Fractional Baud-Rate Divisor 0x28 read-write n 0x0 0x0 UART_FBRD_DIVFRAC Fractional Baud-Rate Divisor 0 6 UART0FR UART Flag 0x18 read-write n 0x0 0x0 UART_FR_BUSY UART Busy 3 4 UART_FR_CTS Clear To Send 0 1 UART_FR_DCD Data Carrier Detect 2 3 UART_FR_DSR Data Set Ready 1 2 UART_FR_RI Ring Indicator 8 9 UART_FR_RXFE UART Receive FIFO Empty 4 5 UART_FR_RXFF UART Receive FIFO Full 6 7 UART_FR_TXFE UART Transmit FIFO Empty 7 8 UART_FR_TXFF UART Transmit FIFO Full 5 6 UART0IBRD UART Integer Baud-Rate Divisor 0x24 read-write n 0x0 0x0 UART_IBRD_DIVINT Integer Baud-Rate Divisor 0 16 UART0ICR UART Interrupt Clear 0x44 write-only n 0x0 0x0 UART_ICR_9BITIC 9-Bit Mode Interrupt Clear 12 13 write-only UART_ICR_BEIC Break Error Interrupt Clear 9 10 write-only UART_ICR_CTSMIC UART Clear to Send Modem Interrupt Clear 1 2 write-only UART_ICR_DCDMIC UART Data Carrier Detect Modem Interrupt Clear 2 3 write-only UART_ICR_DMARXIC Receive DMA Interrupt Clear 16 17 write-only UART_ICR_DMATXIC Transmit DMA Interrupt Clear 17 18 write-only UART_ICR_DSRMIC UART Data Set Ready Modem Interrupt Clear 3 4 write-only UART_ICR_EOTIC End of Transmission Interrupt Clear 11 12 write-only UART_ICR_FEIC Framing Error Interrupt Clear 7 8 write-only UART_ICR_OEIC Overrun Error Interrupt Clear 10 11 write-only UART_ICR_PEIC Parity Error Interrupt Clear 8 9 write-only UART_ICR_RIMIC UART Ring Indicator Modem Interrupt Clear 0 1 write-only UART_ICR_RTIC Receive Time-Out Interrupt Clear 6 7 write-only UART_ICR_RXIC Receive Interrupt Clear 4 5 write-only UART_ICR_TXIC Transmit Interrupt Clear 5 6 write-only UART0IFLS UART Interrupt FIFO Level Select 0x34 read-write n 0x0 0x0 UART_IFLS_RX UART Receive Interrupt FIFO Level Select 3 6 UART_IFLS_RX1_8 RX FIFO >= 1/8 full 0x0 UART_IFLS_RX2_8 RX FIFO >= 1/4 full 0x1 UART_IFLS_RX4_8 RX FIFO >= 1/2 full (default) 0x2 UART_IFLS_RX6_8 RX FIFO >= 3/4 full 0x3 UART_IFLS_RX7_8 RX FIFO >= 7/8 full 0x4 UART_IFLS_TX UART Transmit Interrupt FIFO Level Select 0 3 UART_IFLS_TX1_8 TX FIFO <= 1/8 full 0x0 UART_IFLS_TX2_8 TX FIFO <= 1/4 full 0x1 UART_IFLS_TX4_8 TX FIFO <= 1/2 full (default) 0x2 UART_IFLS_TX6_8 TX FIFO <= 3/4 full 0x3 UART_IFLS_TX7_8 TX FIFO <= 7/8 full 0x4 UART0ILPR UART IrDA Low-Power Register 0x20 read-write n 0x0 0x0 UART_ILPR_ILPDVSR IrDA Low-Power Divisor 0 8 UART0IM UART Interrupt Mask 0x38 read-write n 0x0 0x0 UART_IM_9BITIM 9-Bit Mode Interrupt Mask 12 13 UART_IM_BEIM UART Break Error Interrupt Mask 9 10 UART_IM_CTSMIM UART Clear to Send Modem Interrupt Mask 1 2 UART_IM_DCDMIM UART Data Carrier Detect Modem Interrupt Mask 2 3 UART_IM_DMARXIM Receive DMA Interrupt Mask 16 17 UART_IM_DMATXIM Transmit DMA Interrupt Mask 17 18 UART_IM_DSRMIM UART Data Set Ready Modem Interrupt Mask 3 4 UART_IM_EOTIM End of Transmission Interrupt Mask 11 12 UART_IM_FEIM UART Framing Error Interrupt Mask 7 8 UART_IM_OEIM UART Overrun Error Interrupt Mask 10 11 UART_IM_PEIM UART Parity Error Interrupt Mask 8 9 UART_IM_RIMIM UART Ring Indicator Modem Interrupt Mask 0 1 UART_IM_RTIM UART Receive Time-Out Interrupt Mask 6 7 UART_IM_RXIM UART Receive Interrupt Mask 4 5 UART_IM_TXIM UART Transmit Interrupt Mask 5 6 UART0LCRH UART Line Control 0x2C read-write n 0x0 0x0 UART_LCRH_BRK UART Send Break 0 1 UART_LCRH_EPS UART Even Parity Select 2 3 UART_LCRH_FEN UART Enable FIFOs 4 5 UART_LCRH_PEN UART Parity Enable 1 2 UART_LCRH_SPS UART Stick Parity Select 7 8 UART_LCRH_STP2 UART Two Stop Bits Select 3 4 UART_LCRH_WLEN UART Word Length 5 7 UART_LCRH_WLEN_5 5 bits (default) 0x0 UART_LCRH_WLEN_6 6 bits 0x1 UART_LCRH_WLEN_7 7 bits 0x2 UART_LCRH_WLEN_8 8 bits 0x3 UART0MIS UART Masked Interrupt Status 0x40 read-write n 0x0 0x0 UART_MIS_9BITMIS 9-Bit Mode Masked Interrupt Status 12 13 UART_MIS_BEMIS UART Break Error Masked Interrupt Status 9 10 UART_MIS_CTSMIS UART Clear to Send Modem Masked Interrupt Status 1 2 UART_MIS_DCDMIS UART Data Carrier Detect Modem Masked Interrupt Status 2 3 UART_MIS_DMARXMIS Receive DMA Masked Interrupt Status 16 17 UART_MIS_DMATXMIS Transmit DMA Masked Interrupt Status 17 18 UART_MIS_DSRMIS UART Data Set Ready Modem Masked Interrupt Status 3 4 UART_MIS_EOTMIS End of Transmission Masked Interrupt Status 11 12 UART_MIS_FEMIS UART Framing Error Masked Interrupt Status 7 8 UART_MIS_OEMIS UART Overrun Error Masked Interrupt Status 10 11 UART_MIS_PEMIS UART Parity Error Masked Interrupt Status 8 9 UART_MIS_RIMIS UART Ring Indicator Modem Masked Interrupt Status 0 1 UART_MIS_RTMIS UART Receive Time-Out Masked Interrupt Status 6 7 UART_MIS_RXMIS UART Receive Masked Interrupt Status 4 5 UART_MIS_TXMIS UART Transmit Masked Interrupt Status 5 6 UART0PP UART Peripheral Properties 0xFC0 read-write n 0x0 0x0 UART_PP_MS Modem Support 2 3 UART_PP_MSE Modem Support Extended 3 4 UART_PP_NB 9-Bit Support 1 2 UART_PP_SC Smart Card Support 0 1 UART0RIS UART Raw Interrupt Status 0x3C read-write n 0x0 0x0 UART_RIS_9BITRIS 9-Bit Mode Raw Interrupt Status 12 13 UART_RIS_BERIS UART Break Error Raw Interrupt Status 9 10 UART_RIS_CTSRIS UART Clear to Send Modem Raw Interrupt Status 1 2 UART_RIS_DCDRIS UART Data Carrier Detect Modem Raw Interrupt Status 2 3 UART_RIS_DMARXRIS Receive DMA Raw Interrupt Status 16 17 UART_RIS_DMATXRIS Transmit DMA Raw Interrupt Status 17 18 UART_RIS_DSRRIS UART Data Set Ready Modem Raw Interrupt Status 3 4 UART_RIS_EOTRIS End of Transmission Raw Interrupt Status 11 12 UART_RIS_FERIS UART Framing Error Raw Interrupt Status 7 8 UART_RIS_OERIS UART Overrun Error Raw Interrupt Status 10 11 UART_RIS_PERIS UART Parity Error Raw Interrupt Status 8 9 UART_RIS_RIRIS UART Ring Indicator Modem Raw Interrupt Status 0 1 UART_RIS_RTRIS UART Receive Time-Out Raw Interrupt Status 6 7 UART_RIS_RXRIS UART Receive Raw Interrupt Status 4 5 UART_RIS_TXRIS UART Transmit Raw Interrupt Status 5 6 UART0RSR UART Receive Status/Error Clear 0x4 read-write n 0x0 0x0 UART_RSR_BE UART Break Error 2 3 UART_RSR_FE UART Framing Error 0 1 UART_RSR_OE UART Overrun Error 3 4 UART_RSR_PE UART Parity Error 1 2 _9BITADDR UART 9-Bit Self Address 0xA4 -1 read-write n 0x0 0x0 UART_9BITADDR_9BITEN Enable 9-Bit Mode 15 16 UART_9BITADDR_ADDR Self Address for 9-Bit Mode 0 8 _9BITAMASK UART 9-Bit Self Address Mask 0xA8 -1 read-write n 0x0 0x0 UART_9BITAMASK_MASK Self Address Mask for 9-Bit Mode 0 8 UART3 Register map for UART0 peripheral UART 0x0 0x0 0x1000 registers n UART3 56 9BITADDR UART 9-Bit Self Address 0xA4 read-write n 0x0 0x0 UART_9BITADDR_9BITEN Enable 9-Bit Mode 15 16 UART_9BITADDR_ADDR Self Address for 9-Bit Mode 0 8 9BITAMASK UART 9-Bit Self Address Mask 0xA8 read-write n 0x0 0x0 UART_9BITAMASK_MASK Self Address Mask for 9-Bit Mode 0 8 CC UART Clock Configuration 0xFC8 -1 read-write n 0x0 0x0 UART_CC_CS UART Baud Clock Source 0 4 UART_CC_CS_SYSCLK System clock (based on clock source and divisor factor) 0x0 UART_CC_CS_PIOSC PIOSC 0x5 CTL UART Control 0x30 -1 read-write n 0x0 0x0 UART_CTL_CTSEN Enable Clear To Send 15 16 UART_CTL_DTR Data Terminal Ready 10 11 UART_CTL_EOT End of Transmission 4 5 UART_CTL_HSE High-Speed Enable 5 6 UART_CTL_LBE UART Loop Back Enable 7 8 UART_CTL_RTS Request to Send 11 12 UART_CTL_RTSEN Enable Request to Send 14 15 UART_CTL_RXE UART Receive Enable 9 10 UART_CTL_SIREN UART SIR Enable 1 2 UART_CTL_SIRLP UART SIR Low-Power Mode 2 3 UART_CTL_SMART ISO 7816 Smart Card Support 3 4 UART_CTL_TXE UART Transmit Enable 8 9 UART_CTL_UARTEN UART Enable 0 1 DMACTL UART DMA Control 0x48 -1 read-write n 0x0 0x0 UART_DMACTL_DMAERR DMA on Error 2 3 UART_DMACTL_RXDMAE Receive DMA Enable 0 1 UART_DMACTL_TXDMAE Transmit DMA Enable 1 2 DR UART Data 0x0 -1 read-write n 0x0 0x0 UART_DR_BE UART Break Error 10 11 UART_DR_DATA Data Transmitted or Received 0 8 UART_DR_FE UART Framing Error 8 9 UART_DR_OE UART Overrun Error 11 12 UART_DR_PE UART Parity Error 9 10 ECR UART Receive Status/Error Clear 0x4 -1 read-write n 0x0 0x0 UART_ECR_DATA Error Clear 0 8 FBRD UART Fractional Baud-Rate Divisor 0x28 -1 read-write n 0x0 0x0 UART_FBRD_DIVFRAC Fractional Baud-Rate Divisor 0 6 FR UART Flag 0x18 -1 read-write n 0x0 0x0 UART_FR_BUSY UART Busy 3 4 UART_FR_CTS Clear To Send 0 1 UART_FR_DCD Data Carrier Detect 2 3 UART_FR_DSR Data Set Ready 1 2 UART_FR_RI Ring Indicator 8 9 UART_FR_RXFE UART Receive FIFO Empty 4 5 UART_FR_RXFF UART Receive FIFO Full 6 7 UART_FR_TXFE UART Transmit FIFO Empty 7 8 UART_FR_TXFF UART Transmit FIFO Full 5 6 IBRD UART Integer Baud-Rate Divisor 0x24 -1 read-write n 0x0 0x0 UART_IBRD_DIVINT Integer Baud-Rate Divisor 0 16 ICR UART Interrupt Clear 0x44 -1 write-only n 0x0 0x0 UART_ICR_9BITIC 9-Bit Mode Interrupt Clear 12 13 write-only UART_ICR_BEIC Break Error Interrupt Clear 9 10 write-only UART_ICR_CTSMIC UART Clear to Send Modem Interrupt Clear 1 2 write-only UART_ICR_DCDMIC UART Data Carrier Detect Modem Interrupt Clear 2 3 write-only UART_ICR_DMARXIC Receive DMA Interrupt Clear 16 17 write-only UART_ICR_DMATXIC Transmit DMA Interrupt Clear 17 18 write-only UART_ICR_DSRMIC UART Data Set Ready Modem Interrupt Clear 3 4 write-only UART_ICR_EOTIC End of Transmission Interrupt Clear 11 12 write-only UART_ICR_FEIC Framing Error Interrupt Clear 7 8 write-only UART_ICR_OEIC Overrun Error Interrupt Clear 10 11 write-only UART_ICR_PEIC Parity Error Interrupt Clear 8 9 write-only UART_ICR_RIMIC UART Ring Indicator Modem Interrupt Clear 0 1 write-only UART_ICR_RTIC Receive Time-Out Interrupt Clear 6 7 write-only UART_ICR_RXIC Receive Interrupt Clear 4 5 write-only UART_ICR_TXIC Transmit Interrupt Clear 5 6 write-only IFLS UART Interrupt FIFO Level Select 0x34 -1 read-write n 0x0 0x0 UART_IFLS_RX UART Receive Interrupt FIFO Level Select 3 6 UART_IFLS_RX1_8 RX FIFO >= 1/8 full 0x0 UART_IFLS_RX2_8 RX FIFO >= 1/4 full 0x1 UART_IFLS_RX4_8 RX FIFO >= 1/2 full (default) 0x2 UART_IFLS_RX6_8 RX FIFO >= 3/4 full 0x3 UART_IFLS_RX7_8 RX FIFO >= 7/8 full 0x4 UART_IFLS_TX UART Transmit Interrupt FIFO Level Select 0 3 UART_IFLS_TX1_8 TX FIFO and lt = 1/8 full 0x0 UART_IFLS_TX2_8 TX FIFO and lt = 1/4 full 0x1 UART_IFLS_TX4_8 TX FIFO and lt = 1/2 full (default) 0x2 UART_IFLS_TX6_8 TX FIFO and lt = 3/4 full 0x3 UART_IFLS_TX7_8 TX FIFO and lt = 7/8 full 0x4 ILPR UART IrDA Low-Power Register 0x20 -1 read-write n 0x0 0x0 UART_ILPR_ILPDVSR IrDA Low-Power Divisor 0 8 IM UART Interrupt Mask 0x38 -1 read-write n 0x0 0x0 UART_IM_9BITIM 9-Bit Mode Interrupt Mask 12 13 UART_IM_BEIM UART Break Error Interrupt Mask 9 10 UART_IM_CTSMIM UART Clear to Send Modem Interrupt Mask 1 2 UART_IM_DCDMIM UART Data Carrier Detect Modem Interrupt Mask 2 3 UART_IM_DMARXIM Receive DMA Interrupt Mask 16 17 UART_IM_DMATXIM Transmit DMA Interrupt Mask 17 18 UART_IM_DSRMIM UART Data Set Ready Modem Interrupt Mask 3 4 UART_IM_EOTIM End of Transmission Interrupt Mask 11 12 UART_IM_FEIM UART Framing Error Interrupt Mask 7 8 UART_IM_OEIM UART Overrun Error Interrupt Mask 10 11 UART_IM_PEIM UART Parity Error Interrupt Mask 8 9 UART_IM_RIMIM UART Ring Indicator Modem Interrupt Mask 0 1 UART_IM_RTIM UART Receive Time-Out Interrupt Mask 6 7 UART_IM_RXIM UART Receive Interrupt Mask 4 5 UART_IM_TXIM UART Transmit Interrupt Mask 5 6 LCRH UART Line Control 0x2C -1 read-write n 0x0 0x0 UART_LCRH_BRK UART Send Break 0 1 UART_LCRH_EPS UART Even Parity Select 2 3 UART_LCRH_FEN UART Enable FIFOs 4 5 UART_LCRH_PEN UART Parity Enable 1 2 UART_LCRH_SPS UART Stick Parity Select 7 8 UART_LCRH_STP2 UART Two Stop Bits Select 3 4 UART_LCRH_WLEN UART Word Length 5 7 UART_LCRH_WLEN_5 5 bits (default) 0x0 UART_LCRH_WLEN_6 6 bits 0x1 UART_LCRH_WLEN_7 7 bits 0x2 UART_LCRH_WLEN_8 8 bits 0x3 MIS UART Masked Interrupt Status 0x40 -1 read-write n 0x0 0x0 UART_MIS_9BITMIS 9-Bit Mode Masked Interrupt Status 12 13 UART_MIS_BEMIS UART Break Error Masked Interrupt Status 9 10 UART_MIS_CTSMIS UART Clear to Send Modem Masked Interrupt Status 1 2 UART_MIS_DCDMIS UART Data Carrier Detect Modem Masked Interrupt Status 2 3 UART_MIS_DMARXMIS Receive DMA Masked Interrupt Status 16 17 UART_MIS_DMATXMIS Transmit DMA Masked Interrupt Status 17 18 UART_MIS_DSRMIS UART Data Set Ready Modem Masked Interrupt Status 3 4 UART_MIS_EOTMIS End of Transmission Masked Interrupt Status 11 12 UART_MIS_FEMIS UART Framing Error Masked Interrupt Status 7 8 UART_MIS_OEMIS UART Overrun Error Masked Interrupt Status 10 11 UART_MIS_PEMIS UART Parity Error Masked Interrupt Status 8 9 UART_MIS_RIMIS UART Ring Indicator Modem Masked Interrupt Status 0 1 UART_MIS_RTMIS UART Receive Time-Out Masked Interrupt Status 6 7 UART_MIS_RXMIS UART Receive Masked Interrupt Status 4 5 UART_MIS_TXMIS UART Transmit Masked Interrupt Status 5 6 PP UART Peripheral Properties 0xFC0 -1 read-write n 0x0 0x0 UART_PP_MS Modem Support 2 3 UART_PP_MSE Modem Support Extended 3 4 UART_PP_NB 9-Bit Support 1 2 UART_PP_SC Smart Card Support 0 1 RIS UART Raw Interrupt Status 0x3C -1 read-write n 0x0 0x0 UART_RIS_9BITRIS 9-Bit Mode Raw Interrupt Status 12 13 UART_RIS_BERIS UART Break Error Raw Interrupt Status 9 10 UART_RIS_CTSRIS UART Clear to Send Modem Raw Interrupt Status 1 2 UART_RIS_DCDRIS UART Data Carrier Detect Modem Raw Interrupt Status 2 3 UART_RIS_DMARXRIS Receive DMA Raw Interrupt Status 16 17 UART_RIS_DMATXRIS Transmit DMA Raw Interrupt Status 17 18 UART_RIS_DSRRIS UART Data Set Ready Modem Raw Interrupt Status 3 4 UART_RIS_EOTRIS End of Transmission Raw Interrupt Status 11 12 UART_RIS_FERIS UART Framing Error Raw Interrupt Status 7 8 UART_RIS_OERIS UART Overrun Error Raw Interrupt Status 10 11 UART_RIS_PERIS UART Parity Error Raw Interrupt Status 8 9 UART_RIS_RIRIS UART Ring Indicator Modem Raw Interrupt Status 0 1 UART_RIS_RTRIS UART Receive Time-Out Raw Interrupt Status 6 7 UART_RIS_RXRIS UART Receive Raw Interrupt Status 4 5 UART_RIS_TXRIS UART Transmit Raw Interrupt Status 5 6 RSR UART Receive Status/Error Clear 0x4 -1 read-write n 0x0 0x0 UART_RSR_BE UART Break Error 2 3 UART_RSR_FE UART Framing Error 0 1 UART_RSR_OE UART Overrun Error 3 4 UART_RSR_PE UART Parity Error 1 2 UART0CC UART Clock Configuration 0xFC8 read-write n 0x0 0x0 UART_CC_CS UART Baud Clock Source 0 4 UART_CC_CS_SYSCLK System clock (based on clock source and divisor factor) 0x0 UART_CC_CS_PIOSC PIOSC 0x5 UART0CTL UART Control 0x30 read-write n 0x0 0x0 UART_CTL_CTSEN Enable Clear To Send 15 16 UART_CTL_DTR Data Terminal Ready 10 11 UART_CTL_EOT End of Transmission 4 5 UART_CTL_HSE High-Speed Enable 5 6 UART_CTL_LBE UART Loop Back Enable 7 8 UART_CTL_RTS Request to Send 11 12 UART_CTL_RTSEN Enable Request to Send 14 15 UART_CTL_RXE UART Receive Enable 9 10 UART_CTL_SIREN UART SIR Enable 1 2 UART_CTL_SIRLP UART SIR Low-Power Mode 2 3 UART_CTL_SMART ISO 7816 Smart Card Support 3 4 UART_CTL_TXE UART Transmit Enable 8 9 UART_CTL_UARTEN UART Enable 0 1 UART0DMACTL UART DMA Control 0x48 read-write n 0x0 0x0 UART_DMACTL_DMAERR DMA on Error 2 3 UART_DMACTL_RXDMAE Receive DMA Enable 0 1 UART_DMACTL_TXDMAE Transmit DMA Enable 1 2 UART0DR UART Data 0x0 read-write n 0x0 0x0 UART_DR_BE UART Break Error 10 11 UART_DR_DATA Data Transmitted or Received 0 8 UART_DR_FE UART Framing Error 8 9 UART_DR_OE UART Overrun Error 11 12 UART_DR_PE UART Parity Error 9 10 UART0ECR UART Receive Status/Error Clear UART_ALT 0x4 read-write n 0x0 0x0 UART_ECR_DATA Error Clear 0 8 UART0FBRD UART Fractional Baud-Rate Divisor 0x28 read-write n 0x0 0x0 UART_FBRD_DIVFRAC Fractional Baud-Rate Divisor 0 6 UART0FR UART Flag 0x18 read-write n 0x0 0x0 UART_FR_BUSY UART Busy 3 4 UART_FR_CTS Clear To Send 0 1 UART_FR_DCD Data Carrier Detect 2 3 UART_FR_DSR Data Set Ready 1 2 UART_FR_RI Ring Indicator 8 9 UART_FR_RXFE UART Receive FIFO Empty 4 5 UART_FR_RXFF UART Receive FIFO Full 6 7 UART_FR_TXFE UART Transmit FIFO Empty 7 8 UART_FR_TXFF UART Transmit FIFO Full 5 6 UART0IBRD UART Integer Baud-Rate Divisor 0x24 read-write n 0x0 0x0 UART_IBRD_DIVINT Integer Baud-Rate Divisor 0 16 UART0ICR UART Interrupt Clear 0x44 write-only n 0x0 0x0 UART_ICR_9BITIC 9-Bit Mode Interrupt Clear 12 13 write-only UART_ICR_BEIC Break Error Interrupt Clear 9 10 write-only UART_ICR_CTSMIC UART Clear to Send Modem Interrupt Clear 1 2 write-only UART_ICR_DCDMIC UART Data Carrier Detect Modem Interrupt Clear 2 3 write-only UART_ICR_DMARXIC Receive DMA Interrupt Clear 16 17 write-only UART_ICR_DMATXIC Transmit DMA Interrupt Clear 17 18 write-only UART_ICR_DSRMIC UART Data Set Ready Modem Interrupt Clear 3 4 write-only UART_ICR_EOTIC End of Transmission Interrupt Clear 11 12 write-only UART_ICR_FEIC Framing Error Interrupt Clear 7 8 write-only UART_ICR_OEIC Overrun Error Interrupt Clear 10 11 write-only UART_ICR_PEIC Parity Error Interrupt Clear 8 9 write-only UART_ICR_RIMIC UART Ring Indicator Modem Interrupt Clear 0 1 write-only UART_ICR_RTIC Receive Time-Out Interrupt Clear 6 7 write-only UART_ICR_RXIC Receive Interrupt Clear 4 5 write-only UART_ICR_TXIC Transmit Interrupt Clear 5 6 write-only UART0IFLS UART Interrupt FIFO Level Select 0x34 read-write n 0x0 0x0 UART_IFLS_RX UART Receive Interrupt FIFO Level Select 3 6 UART_IFLS_RX1_8 RX FIFO >= 1/8 full 0x0 UART_IFLS_RX2_8 RX FIFO >= 1/4 full 0x1 UART_IFLS_RX4_8 RX FIFO >= 1/2 full (default) 0x2 UART_IFLS_RX6_8 RX FIFO >= 3/4 full 0x3 UART_IFLS_RX7_8 RX FIFO >= 7/8 full 0x4 UART_IFLS_TX UART Transmit Interrupt FIFO Level Select 0 3 UART_IFLS_TX1_8 TX FIFO <= 1/8 full 0x0 UART_IFLS_TX2_8 TX FIFO <= 1/4 full 0x1 UART_IFLS_TX4_8 TX FIFO <= 1/2 full (default) 0x2 UART_IFLS_TX6_8 TX FIFO <= 3/4 full 0x3 UART_IFLS_TX7_8 TX FIFO <= 7/8 full 0x4 UART0ILPR UART IrDA Low-Power Register 0x20 read-write n 0x0 0x0 UART_ILPR_ILPDVSR IrDA Low-Power Divisor 0 8 UART0IM UART Interrupt Mask 0x38 read-write n 0x0 0x0 UART_IM_9BITIM 9-Bit Mode Interrupt Mask 12 13 UART_IM_BEIM UART Break Error Interrupt Mask 9 10 UART_IM_CTSMIM UART Clear to Send Modem Interrupt Mask 1 2 UART_IM_DCDMIM UART Data Carrier Detect Modem Interrupt Mask 2 3 UART_IM_DMARXIM Receive DMA Interrupt Mask 16 17 UART_IM_DMATXIM Transmit DMA Interrupt Mask 17 18 UART_IM_DSRMIM UART Data Set Ready Modem Interrupt Mask 3 4 UART_IM_EOTIM End of Transmission Interrupt Mask 11 12 UART_IM_FEIM UART Framing Error Interrupt Mask 7 8 UART_IM_OEIM UART Overrun Error Interrupt Mask 10 11 UART_IM_PEIM UART Parity Error Interrupt Mask 8 9 UART_IM_RIMIM UART Ring Indicator Modem Interrupt Mask 0 1 UART_IM_RTIM UART Receive Time-Out Interrupt Mask 6 7 UART_IM_RXIM UART Receive Interrupt Mask 4 5 UART_IM_TXIM UART Transmit Interrupt Mask 5 6 UART0LCRH UART Line Control 0x2C read-write n 0x0 0x0 UART_LCRH_BRK UART Send Break 0 1 UART_LCRH_EPS UART Even Parity Select 2 3 UART_LCRH_FEN UART Enable FIFOs 4 5 UART_LCRH_PEN UART Parity Enable 1 2 UART_LCRH_SPS UART Stick Parity Select 7 8 UART_LCRH_STP2 UART Two Stop Bits Select 3 4 UART_LCRH_WLEN UART Word Length 5 7 UART_LCRH_WLEN_5 5 bits (default) 0x0 UART_LCRH_WLEN_6 6 bits 0x1 UART_LCRH_WLEN_7 7 bits 0x2 UART_LCRH_WLEN_8 8 bits 0x3 UART0MIS UART Masked Interrupt Status 0x40 read-write n 0x0 0x0 UART_MIS_9BITMIS 9-Bit Mode Masked Interrupt Status 12 13 UART_MIS_BEMIS UART Break Error Masked Interrupt Status 9 10 UART_MIS_CTSMIS UART Clear to Send Modem Masked Interrupt Status 1 2 UART_MIS_DCDMIS UART Data Carrier Detect Modem Masked Interrupt Status 2 3 UART_MIS_DMARXMIS Receive DMA Masked Interrupt Status 16 17 UART_MIS_DMATXMIS Transmit DMA Masked Interrupt Status 17 18 UART_MIS_DSRMIS UART Data Set Ready Modem Masked Interrupt Status 3 4 UART_MIS_EOTMIS End of Transmission Masked Interrupt Status 11 12 UART_MIS_FEMIS UART Framing Error Masked Interrupt Status 7 8 UART_MIS_OEMIS UART Overrun Error Masked Interrupt Status 10 11 UART_MIS_PEMIS UART Parity Error Masked Interrupt Status 8 9 UART_MIS_RIMIS UART Ring Indicator Modem Masked Interrupt Status 0 1 UART_MIS_RTMIS UART Receive Time-Out Masked Interrupt Status 6 7 UART_MIS_RXMIS UART Receive Masked Interrupt Status 4 5 UART_MIS_TXMIS UART Transmit Masked Interrupt Status 5 6 UART0PP UART Peripheral Properties 0xFC0 read-write n 0x0 0x0 UART_PP_MS Modem Support 2 3 UART_PP_MSE Modem Support Extended 3 4 UART_PP_NB 9-Bit Support 1 2 UART_PP_SC Smart Card Support 0 1 UART0RIS UART Raw Interrupt Status 0x3C read-write n 0x0 0x0 UART_RIS_9BITRIS 9-Bit Mode Raw Interrupt Status 12 13 UART_RIS_BERIS UART Break Error Raw Interrupt Status 9 10 UART_RIS_CTSRIS UART Clear to Send Modem Raw Interrupt Status 1 2 UART_RIS_DCDRIS UART Data Carrier Detect Modem Raw Interrupt Status 2 3 UART_RIS_DMARXRIS Receive DMA Raw Interrupt Status 16 17 UART_RIS_DMATXRIS Transmit DMA Raw Interrupt Status 17 18 UART_RIS_DSRRIS UART Data Set Ready Modem Raw Interrupt Status 3 4 UART_RIS_EOTRIS End of Transmission Raw Interrupt Status 11 12 UART_RIS_FERIS UART Framing Error Raw Interrupt Status 7 8 UART_RIS_OERIS UART Overrun Error Raw Interrupt Status 10 11 UART_RIS_PERIS UART Parity Error Raw Interrupt Status 8 9 UART_RIS_RIRIS UART Ring Indicator Modem Raw Interrupt Status 0 1 UART_RIS_RTRIS UART Receive Time-Out Raw Interrupt Status 6 7 UART_RIS_RXRIS UART Receive Raw Interrupt Status 4 5 UART_RIS_TXRIS UART Transmit Raw Interrupt Status 5 6 UART0RSR UART Receive Status/Error Clear 0x4 read-write n 0x0 0x0 UART_RSR_BE UART Break Error 2 3 UART_RSR_FE UART Framing Error 0 1 UART_RSR_OE UART Overrun Error 3 4 UART_RSR_PE UART Parity Error 1 2 _9BITADDR UART 9-Bit Self Address 0xA4 -1 read-write n 0x0 0x0 UART_9BITADDR_9BITEN Enable 9-Bit Mode 15 16 UART_9BITADDR_ADDR Self Address for 9-Bit Mode 0 8 _9BITAMASK UART 9-Bit Self Address Mask 0xA8 -1 read-write n 0x0 0x0 UART_9BITAMASK_MASK Self Address Mask for 9-Bit Mode 0 8 UART4 Register map for UART0 peripheral UART 0x0 0x0 0x1000 registers n UART4 57 9BITADDR UART 9-Bit Self Address 0xA4 read-write n 0x0 0x0 UART_9BITADDR_9BITEN Enable 9-Bit Mode 15 16 UART_9BITADDR_ADDR Self Address for 9-Bit Mode 0 8 9BITAMASK UART 9-Bit Self Address Mask 0xA8 read-write n 0x0 0x0 UART_9BITAMASK_MASK Self Address Mask for 9-Bit Mode 0 8 CC UART Clock Configuration 0xFC8 -1 read-write n 0x0 0x0 UART_CC_CS UART Baud Clock Source 0 4 UART_CC_CS_SYSCLK System clock (based on clock source and divisor factor) 0x0 UART_CC_CS_PIOSC PIOSC 0x5 CTL UART Control 0x30 -1 read-write n 0x0 0x0 UART_CTL_CTSEN Enable Clear To Send 15 16 UART_CTL_DTR Data Terminal Ready 10 11 UART_CTL_EOT End of Transmission 4 5 UART_CTL_HSE High-Speed Enable 5 6 UART_CTL_LBE UART Loop Back Enable 7 8 UART_CTL_RTS Request to Send 11 12 UART_CTL_RTSEN Enable Request to Send 14 15 UART_CTL_RXE UART Receive Enable 9 10 UART_CTL_SIREN UART SIR Enable 1 2 UART_CTL_SIRLP UART SIR Low-Power Mode 2 3 UART_CTL_SMART ISO 7816 Smart Card Support 3 4 UART_CTL_TXE UART Transmit Enable 8 9 UART_CTL_UARTEN UART Enable 0 1 DMACTL UART DMA Control 0x48 -1 read-write n 0x0 0x0 UART_DMACTL_DMAERR DMA on Error 2 3 UART_DMACTL_RXDMAE Receive DMA Enable 0 1 UART_DMACTL_TXDMAE Transmit DMA Enable 1 2 DR UART Data 0x0 -1 read-write n 0x0 0x0 UART_DR_BE UART Break Error 10 11 UART_DR_DATA Data Transmitted or Received 0 8 UART_DR_FE UART Framing Error 8 9 UART_DR_OE UART Overrun Error 11 12 UART_DR_PE UART Parity Error 9 10 ECR UART Receive Status/Error Clear 0x4 -1 read-write n 0x0 0x0 UART_ECR_DATA Error Clear 0 8 FBRD UART Fractional Baud-Rate Divisor 0x28 -1 read-write n 0x0 0x0 UART_FBRD_DIVFRAC Fractional Baud-Rate Divisor 0 6 FR UART Flag 0x18 -1 read-write n 0x0 0x0 UART_FR_BUSY UART Busy 3 4 UART_FR_CTS Clear To Send 0 1 UART_FR_DCD Data Carrier Detect 2 3 UART_FR_DSR Data Set Ready 1 2 UART_FR_RI Ring Indicator 8 9 UART_FR_RXFE UART Receive FIFO Empty 4 5 UART_FR_RXFF UART Receive FIFO Full 6 7 UART_FR_TXFE UART Transmit FIFO Empty 7 8 UART_FR_TXFF UART Transmit FIFO Full 5 6 IBRD UART Integer Baud-Rate Divisor 0x24 -1 read-write n 0x0 0x0 UART_IBRD_DIVINT Integer Baud-Rate Divisor 0 16 ICR UART Interrupt Clear 0x44 -1 write-only n 0x0 0x0 UART_ICR_9BITIC 9-Bit Mode Interrupt Clear 12 13 write-only UART_ICR_BEIC Break Error Interrupt Clear 9 10 write-only UART_ICR_CTSMIC UART Clear to Send Modem Interrupt Clear 1 2 write-only UART_ICR_DCDMIC UART Data Carrier Detect Modem Interrupt Clear 2 3 write-only UART_ICR_DMARXIC Receive DMA Interrupt Clear 16 17 write-only UART_ICR_DMATXIC Transmit DMA Interrupt Clear 17 18 write-only UART_ICR_DSRMIC UART Data Set Ready Modem Interrupt Clear 3 4 write-only UART_ICR_EOTIC End of Transmission Interrupt Clear 11 12 write-only UART_ICR_FEIC Framing Error Interrupt Clear 7 8 write-only UART_ICR_OEIC Overrun Error Interrupt Clear 10 11 write-only UART_ICR_PEIC Parity Error Interrupt Clear 8 9 write-only UART_ICR_RIMIC UART Ring Indicator Modem Interrupt Clear 0 1 write-only UART_ICR_RTIC Receive Time-Out Interrupt Clear 6 7 write-only UART_ICR_RXIC Receive Interrupt Clear 4 5 write-only UART_ICR_TXIC Transmit Interrupt Clear 5 6 write-only IFLS UART Interrupt FIFO Level Select 0x34 -1 read-write n 0x0 0x0 UART_IFLS_RX UART Receive Interrupt FIFO Level Select 3 6 UART_IFLS_RX1_8 RX FIFO >= 1/8 full 0x0 UART_IFLS_RX2_8 RX FIFO >= 1/4 full 0x1 UART_IFLS_RX4_8 RX FIFO >= 1/2 full (default) 0x2 UART_IFLS_RX6_8 RX FIFO >= 3/4 full 0x3 UART_IFLS_RX7_8 RX FIFO >= 7/8 full 0x4 UART_IFLS_TX UART Transmit Interrupt FIFO Level Select 0 3 UART_IFLS_TX1_8 TX FIFO and lt = 1/8 full 0x0 UART_IFLS_TX2_8 TX FIFO and lt = 1/4 full 0x1 UART_IFLS_TX4_8 TX FIFO and lt = 1/2 full (default) 0x2 UART_IFLS_TX6_8 TX FIFO and lt = 3/4 full 0x3 UART_IFLS_TX7_8 TX FIFO and lt = 7/8 full 0x4 ILPR UART IrDA Low-Power Register 0x20 -1 read-write n 0x0 0x0 UART_ILPR_ILPDVSR IrDA Low-Power Divisor 0 8 IM UART Interrupt Mask 0x38 -1 read-write n 0x0 0x0 UART_IM_9BITIM 9-Bit Mode Interrupt Mask 12 13 UART_IM_BEIM UART Break Error Interrupt Mask 9 10 UART_IM_CTSMIM UART Clear to Send Modem Interrupt Mask 1 2 UART_IM_DCDMIM UART Data Carrier Detect Modem Interrupt Mask 2 3 UART_IM_DMARXIM Receive DMA Interrupt Mask 16 17 UART_IM_DMATXIM Transmit DMA Interrupt Mask 17 18 UART_IM_DSRMIM UART Data Set Ready Modem Interrupt Mask 3 4 UART_IM_EOTIM End of Transmission Interrupt Mask 11 12 UART_IM_FEIM UART Framing Error Interrupt Mask 7 8 UART_IM_OEIM UART Overrun Error Interrupt Mask 10 11 UART_IM_PEIM UART Parity Error Interrupt Mask 8 9 UART_IM_RIMIM UART Ring Indicator Modem Interrupt Mask 0 1 UART_IM_RTIM UART Receive Time-Out Interrupt Mask 6 7 UART_IM_RXIM UART Receive Interrupt Mask 4 5 UART_IM_TXIM UART Transmit Interrupt Mask 5 6 LCRH UART Line Control 0x2C -1 read-write n 0x0 0x0 UART_LCRH_BRK UART Send Break 0 1 UART_LCRH_EPS UART Even Parity Select 2 3 UART_LCRH_FEN UART Enable FIFOs 4 5 UART_LCRH_PEN UART Parity Enable 1 2 UART_LCRH_SPS UART Stick Parity Select 7 8 UART_LCRH_STP2 UART Two Stop Bits Select 3 4 UART_LCRH_WLEN UART Word Length 5 7 UART_LCRH_WLEN_5 5 bits (default) 0x0 UART_LCRH_WLEN_6 6 bits 0x1 UART_LCRH_WLEN_7 7 bits 0x2 UART_LCRH_WLEN_8 8 bits 0x3 MIS UART Masked Interrupt Status 0x40 -1 read-write n 0x0 0x0 UART_MIS_9BITMIS 9-Bit Mode Masked Interrupt Status 12 13 UART_MIS_BEMIS UART Break Error Masked Interrupt Status 9 10 UART_MIS_CTSMIS UART Clear to Send Modem Masked Interrupt Status 1 2 UART_MIS_DCDMIS UART Data Carrier Detect Modem Masked Interrupt Status 2 3 UART_MIS_DMARXMIS Receive DMA Masked Interrupt Status 16 17 UART_MIS_DMATXMIS Transmit DMA Masked Interrupt Status 17 18 UART_MIS_DSRMIS UART Data Set Ready Modem Masked Interrupt Status 3 4 UART_MIS_EOTMIS End of Transmission Masked Interrupt Status 11 12 UART_MIS_FEMIS UART Framing Error Masked Interrupt Status 7 8 UART_MIS_OEMIS UART Overrun Error Masked Interrupt Status 10 11 UART_MIS_PEMIS UART Parity Error Masked Interrupt Status 8 9 UART_MIS_RIMIS UART Ring Indicator Modem Masked Interrupt Status 0 1 UART_MIS_RTMIS UART Receive Time-Out Masked Interrupt Status 6 7 UART_MIS_RXMIS UART Receive Masked Interrupt Status 4 5 UART_MIS_TXMIS UART Transmit Masked Interrupt Status 5 6 PP UART Peripheral Properties 0xFC0 -1 read-write n 0x0 0x0 UART_PP_MS Modem Support 2 3 UART_PP_MSE Modem Support Extended 3 4 UART_PP_NB 9-Bit Support 1 2 UART_PP_SC Smart Card Support 0 1 RIS UART Raw Interrupt Status 0x3C -1 read-write n 0x0 0x0 UART_RIS_9BITRIS 9-Bit Mode Raw Interrupt Status 12 13 UART_RIS_BERIS UART Break Error Raw Interrupt Status 9 10 UART_RIS_CTSRIS UART Clear to Send Modem Raw Interrupt Status 1 2 UART_RIS_DCDRIS UART Data Carrier Detect Modem Raw Interrupt Status 2 3 UART_RIS_DMARXRIS Receive DMA Raw Interrupt Status 16 17 UART_RIS_DMATXRIS Transmit DMA Raw Interrupt Status 17 18 UART_RIS_DSRRIS UART Data Set Ready Modem Raw Interrupt Status 3 4 UART_RIS_EOTRIS End of Transmission Raw Interrupt Status 11 12 UART_RIS_FERIS UART Framing Error Raw Interrupt Status 7 8 UART_RIS_OERIS UART Overrun Error Raw Interrupt Status 10 11 UART_RIS_PERIS UART Parity Error Raw Interrupt Status 8 9 UART_RIS_RIRIS UART Ring Indicator Modem Raw Interrupt Status 0 1 UART_RIS_RTRIS UART Receive Time-Out Raw Interrupt Status 6 7 UART_RIS_RXRIS UART Receive Raw Interrupt Status 4 5 UART_RIS_TXRIS UART Transmit Raw Interrupt Status 5 6 RSR UART Receive Status/Error Clear 0x4 -1 read-write n 0x0 0x0 UART_RSR_BE UART Break Error 2 3 UART_RSR_FE UART Framing Error 0 1 UART_RSR_OE UART Overrun Error 3 4 UART_RSR_PE UART Parity Error 1 2 UART0CC UART Clock Configuration 0xFC8 read-write n 0x0 0x0 UART_CC_CS UART Baud Clock Source 0 4 UART_CC_CS_SYSCLK System clock (based on clock source and divisor factor) 0x0 UART_CC_CS_PIOSC PIOSC 0x5 UART0CTL UART Control 0x30 read-write n 0x0 0x0 UART_CTL_CTSEN Enable Clear To Send 15 16 UART_CTL_DTR Data Terminal Ready 10 11 UART_CTL_EOT End of Transmission 4 5 UART_CTL_HSE High-Speed Enable 5 6 UART_CTL_LBE UART Loop Back Enable 7 8 UART_CTL_RTS Request to Send 11 12 UART_CTL_RTSEN Enable Request to Send 14 15 UART_CTL_RXE UART Receive Enable 9 10 UART_CTL_SIREN UART SIR Enable 1 2 UART_CTL_SIRLP UART SIR Low-Power Mode 2 3 UART_CTL_SMART ISO 7816 Smart Card Support 3 4 UART_CTL_TXE UART Transmit Enable 8 9 UART_CTL_UARTEN UART Enable 0 1 UART0DMACTL UART DMA Control 0x48 read-write n 0x0 0x0 UART_DMACTL_DMAERR DMA on Error 2 3 UART_DMACTL_RXDMAE Receive DMA Enable 0 1 UART_DMACTL_TXDMAE Transmit DMA Enable 1 2 UART0DR UART Data 0x0 read-write n 0x0 0x0 UART_DR_BE UART Break Error 10 11 UART_DR_DATA Data Transmitted or Received 0 8 UART_DR_FE UART Framing Error 8 9 UART_DR_OE UART Overrun Error 11 12 UART_DR_PE UART Parity Error 9 10 UART0ECR UART Receive Status/Error Clear UART_ALT 0x4 read-write n 0x0 0x0 UART_ECR_DATA Error Clear 0 8 UART0FBRD UART Fractional Baud-Rate Divisor 0x28 read-write n 0x0 0x0 UART_FBRD_DIVFRAC Fractional Baud-Rate Divisor 0 6 UART0FR UART Flag 0x18 read-write n 0x0 0x0 UART_FR_BUSY UART Busy 3 4 UART_FR_CTS Clear To Send 0 1 UART_FR_DCD Data Carrier Detect 2 3 UART_FR_DSR Data Set Ready 1 2 UART_FR_RI Ring Indicator 8 9 UART_FR_RXFE UART Receive FIFO Empty 4 5 UART_FR_RXFF UART Receive FIFO Full 6 7 UART_FR_TXFE UART Transmit FIFO Empty 7 8 UART_FR_TXFF UART Transmit FIFO Full 5 6 UART0IBRD UART Integer Baud-Rate Divisor 0x24 read-write n 0x0 0x0 UART_IBRD_DIVINT Integer Baud-Rate Divisor 0 16 UART0ICR UART Interrupt Clear 0x44 write-only n 0x0 0x0 UART_ICR_9BITIC 9-Bit Mode Interrupt Clear 12 13 write-only UART_ICR_BEIC Break Error Interrupt Clear 9 10 write-only UART_ICR_CTSMIC UART Clear to Send Modem Interrupt Clear 1 2 write-only UART_ICR_DCDMIC UART Data Carrier Detect Modem Interrupt Clear 2 3 write-only UART_ICR_DMARXIC Receive DMA Interrupt Clear 16 17 write-only UART_ICR_DMATXIC Transmit DMA Interrupt Clear 17 18 write-only UART_ICR_DSRMIC UART Data Set Ready Modem Interrupt Clear 3 4 write-only UART_ICR_EOTIC End of Transmission Interrupt Clear 11 12 write-only UART_ICR_FEIC Framing Error Interrupt Clear 7 8 write-only UART_ICR_OEIC Overrun Error Interrupt Clear 10 11 write-only UART_ICR_PEIC Parity Error Interrupt Clear 8 9 write-only UART_ICR_RIMIC UART Ring Indicator Modem Interrupt Clear 0 1 write-only UART_ICR_RTIC Receive Time-Out Interrupt Clear 6 7 write-only UART_ICR_RXIC Receive Interrupt Clear 4 5 write-only UART_ICR_TXIC Transmit Interrupt Clear 5 6 write-only UART0IFLS UART Interrupt FIFO Level Select 0x34 read-write n 0x0 0x0 UART_IFLS_RX UART Receive Interrupt FIFO Level Select 3 6 UART_IFLS_RX1_8 RX FIFO >= 1/8 full 0x0 UART_IFLS_RX2_8 RX FIFO >= 1/4 full 0x1 UART_IFLS_RX4_8 RX FIFO >= 1/2 full (default) 0x2 UART_IFLS_RX6_8 RX FIFO >= 3/4 full 0x3 UART_IFLS_RX7_8 RX FIFO >= 7/8 full 0x4 UART_IFLS_TX UART Transmit Interrupt FIFO Level Select 0 3 UART_IFLS_TX1_8 TX FIFO <= 1/8 full 0x0 UART_IFLS_TX2_8 TX FIFO <= 1/4 full 0x1 UART_IFLS_TX4_8 TX FIFO <= 1/2 full (default) 0x2 UART_IFLS_TX6_8 TX FIFO <= 3/4 full 0x3 UART_IFLS_TX7_8 TX FIFO <= 7/8 full 0x4 UART0ILPR UART IrDA Low-Power Register 0x20 read-write n 0x0 0x0 UART_ILPR_ILPDVSR IrDA Low-Power Divisor 0 8 UART0IM UART Interrupt Mask 0x38 read-write n 0x0 0x0 UART_IM_9BITIM 9-Bit Mode Interrupt Mask 12 13 UART_IM_BEIM UART Break Error Interrupt Mask 9 10 UART_IM_CTSMIM UART Clear to Send Modem Interrupt Mask 1 2 UART_IM_DCDMIM UART Data Carrier Detect Modem Interrupt Mask 2 3 UART_IM_DMARXIM Receive DMA Interrupt Mask 16 17 UART_IM_DMATXIM Transmit DMA Interrupt Mask 17 18 UART_IM_DSRMIM UART Data Set Ready Modem Interrupt Mask 3 4 UART_IM_EOTIM End of Transmission Interrupt Mask 11 12 UART_IM_FEIM UART Framing Error Interrupt Mask 7 8 UART_IM_OEIM UART Overrun Error Interrupt Mask 10 11 UART_IM_PEIM UART Parity Error Interrupt Mask 8 9 UART_IM_RIMIM UART Ring Indicator Modem Interrupt Mask 0 1 UART_IM_RTIM UART Receive Time-Out Interrupt Mask 6 7 UART_IM_RXIM UART Receive Interrupt Mask 4 5 UART_IM_TXIM UART Transmit Interrupt Mask 5 6 UART0LCRH UART Line Control 0x2C read-write n 0x0 0x0 UART_LCRH_BRK UART Send Break 0 1 UART_LCRH_EPS UART Even Parity Select 2 3 UART_LCRH_FEN UART Enable FIFOs 4 5 UART_LCRH_PEN UART Parity Enable 1 2 UART_LCRH_SPS UART Stick Parity Select 7 8 UART_LCRH_STP2 UART Two Stop Bits Select 3 4 UART_LCRH_WLEN UART Word Length 5 7 UART_LCRH_WLEN_5 5 bits (default) 0x0 UART_LCRH_WLEN_6 6 bits 0x1 UART_LCRH_WLEN_7 7 bits 0x2 UART_LCRH_WLEN_8 8 bits 0x3 UART0MIS UART Masked Interrupt Status 0x40 read-write n 0x0 0x0 UART_MIS_9BITMIS 9-Bit Mode Masked Interrupt Status 12 13 UART_MIS_BEMIS UART Break Error Masked Interrupt Status 9 10 UART_MIS_CTSMIS UART Clear to Send Modem Masked Interrupt Status 1 2 UART_MIS_DCDMIS UART Data Carrier Detect Modem Masked Interrupt Status 2 3 UART_MIS_DMARXMIS Receive DMA Masked Interrupt Status 16 17 UART_MIS_DMATXMIS Transmit DMA Masked Interrupt Status 17 18 UART_MIS_DSRMIS UART Data Set Ready Modem Masked Interrupt Status 3 4 UART_MIS_EOTMIS End of Transmission Masked Interrupt Status 11 12 UART_MIS_FEMIS UART Framing Error Masked Interrupt Status 7 8 UART_MIS_OEMIS UART Overrun Error Masked Interrupt Status 10 11 UART_MIS_PEMIS UART Parity Error Masked Interrupt Status 8 9 UART_MIS_RIMIS UART Ring Indicator Modem Masked Interrupt Status 0 1 UART_MIS_RTMIS UART Receive Time-Out Masked Interrupt Status 6 7 UART_MIS_RXMIS UART Receive Masked Interrupt Status 4 5 UART_MIS_TXMIS UART Transmit Masked Interrupt Status 5 6 UART0PP UART Peripheral Properties 0xFC0 read-write n 0x0 0x0 UART_PP_MS Modem Support 2 3 UART_PP_MSE Modem Support Extended 3 4 UART_PP_NB 9-Bit Support 1 2 UART_PP_SC Smart Card Support 0 1 UART0RIS UART Raw Interrupt Status 0x3C read-write n 0x0 0x0 UART_RIS_9BITRIS 9-Bit Mode Raw Interrupt Status 12 13 UART_RIS_BERIS UART Break Error Raw Interrupt Status 9 10 UART_RIS_CTSRIS UART Clear to Send Modem Raw Interrupt Status 1 2 UART_RIS_DCDRIS UART Data Carrier Detect Modem Raw Interrupt Status 2 3 UART_RIS_DMARXRIS Receive DMA Raw Interrupt Status 16 17 UART_RIS_DMATXRIS Transmit DMA Raw Interrupt Status 17 18 UART_RIS_DSRRIS UART Data Set Ready Modem Raw Interrupt Status 3 4 UART_RIS_EOTRIS End of Transmission Raw Interrupt Status 11 12 UART_RIS_FERIS UART Framing Error Raw Interrupt Status 7 8 UART_RIS_OERIS UART Overrun Error Raw Interrupt Status 10 11 UART_RIS_PERIS UART Parity Error Raw Interrupt Status 8 9 UART_RIS_RIRIS UART Ring Indicator Modem Raw Interrupt Status 0 1 UART_RIS_RTRIS UART Receive Time-Out Raw Interrupt Status 6 7 UART_RIS_RXRIS UART Receive Raw Interrupt Status 4 5 UART_RIS_TXRIS UART Transmit Raw Interrupt Status 5 6 UART0RSR UART Receive Status/Error Clear 0x4 read-write n 0x0 0x0 UART_RSR_BE UART Break Error 2 3 UART_RSR_FE UART Framing Error 0 1 UART_RSR_OE UART Overrun Error 3 4 UART_RSR_PE UART Parity Error 1 2 _9BITADDR UART 9-Bit Self Address 0xA4 -1 read-write n 0x0 0x0 UART_9BITADDR_9BITEN Enable 9-Bit Mode 15 16 UART_9BITADDR_ADDR Self Address for 9-Bit Mode 0 8 _9BITAMASK UART 9-Bit Self Address Mask 0xA8 -1 read-write n 0x0 0x0 UART_9BITAMASK_MASK Self Address Mask for 9-Bit Mode 0 8 UART5 Register map for UART0 peripheral UART 0x0 0x0 0x1000 registers n UART5 58 9BITADDR UART 9-Bit Self Address 0xA4 read-write n 0x0 0x0 UART_9BITADDR_9BITEN Enable 9-Bit Mode 15 16 UART_9BITADDR_ADDR Self Address for 9-Bit Mode 0 8 9BITAMASK UART 9-Bit Self Address Mask 0xA8 read-write n 0x0 0x0 UART_9BITAMASK_MASK Self Address Mask for 9-Bit Mode 0 8 CC UART Clock Configuration 0xFC8 -1 read-write n 0x0 0x0 UART_CC_CS UART Baud Clock Source 0 4 UART_CC_CS_SYSCLK System clock (based on clock source and divisor factor) 0x0 UART_CC_CS_PIOSC PIOSC 0x5 CTL UART Control 0x30 -1 read-write n 0x0 0x0 UART_CTL_CTSEN Enable Clear To Send 15 16 UART_CTL_DTR Data Terminal Ready 10 11 UART_CTL_EOT End of Transmission 4 5 UART_CTL_HSE High-Speed Enable 5 6 UART_CTL_LBE UART Loop Back Enable 7 8 UART_CTL_RTS Request to Send 11 12 UART_CTL_RTSEN Enable Request to Send 14 15 UART_CTL_RXE UART Receive Enable 9 10 UART_CTL_SIREN UART SIR Enable 1 2 UART_CTL_SIRLP UART SIR Low-Power Mode 2 3 UART_CTL_SMART ISO 7816 Smart Card Support 3 4 UART_CTL_TXE UART Transmit Enable 8 9 UART_CTL_UARTEN UART Enable 0 1 DMACTL UART DMA Control 0x48 -1 read-write n 0x0 0x0 UART_DMACTL_DMAERR DMA on Error 2 3 UART_DMACTL_RXDMAE Receive DMA Enable 0 1 UART_DMACTL_TXDMAE Transmit DMA Enable 1 2 DR UART Data 0x0 -1 read-write n 0x0 0x0 UART_DR_BE UART Break Error 10 11 UART_DR_DATA Data Transmitted or Received 0 8 UART_DR_FE UART Framing Error 8 9 UART_DR_OE UART Overrun Error 11 12 UART_DR_PE UART Parity Error 9 10 ECR UART Receive Status/Error Clear 0x4 -1 read-write n 0x0 0x0 UART_ECR_DATA Error Clear 0 8 FBRD UART Fractional Baud-Rate Divisor 0x28 -1 read-write n 0x0 0x0 UART_FBRD_DIVFRAC Fractional Baud-Rate Divisor 0 6 FR UART Flag 0x18 -1 read-write n 0x0 0x0 UART_FR_BUSY UART Busy 3 4 UART_FR_CTS Clear To Send 0 1 UART_FR_DCD Data Carrier Detect 2 3 UART_FR_DSR Data Set Ready 1 2 UART_FR_RI Ring Indicator 8 9 UART_FR_RXFE UART Receive FIFO Empty 4 5 UART_FR_RXFF UART Receive FIFO Full 6 7 UART_FR_TXFE UART Transmit FIFO Empty 7 8 UART_FR_TXFF UART Transmit FIFO Full 5 6 IBRD UART Integer Baud-Rate Divisor 0x24 -1 read-write n 0x0 0x0 UART_IBRD_DIVINT Integer Baud-Rate Divisor 0 16 ICR UART Interrupt Clear 0x44 -1 write-only n 0x0 0x0 UART_ICR_9BITIC 9-Bit Mode Interrupt Clear 12 13 write-only UART_ICR_BEIC Break Error Interrupt Clear 9 10 write-only UART_ICR_CTSMIC UART Clear to Send Modem Interrupt Clear 1 2 write-only UART_ICR_DCDMIC UART Data Carrier Detect Modem Interrupt Clear 2 3 write-only UART_ICR_DMARXIC Receive DMA Interrupt Clear 16 17 write-only UART_ICR_DMATXIC Transmit DMA Interrupt Clear 17 18 write-only UART_ICR_DSRMIC UART Data Set Ready Modem Interrupt Clear 3 4 write-only UART_ICR_EOTIC End of Transmission Interrupt Clear 11 12 write-only UART_ICR_FEIC Framing Error Interrupt Clear 7 8 write-only UART_ICR_OEIC Overrun Error Interrupt Clear 10 11 write-only UART_ICR_PEIC Parity Error Interrupt Clear 8 9 write-only UART_ICR_RIMIC UART Ring Indicator Modem Interrupt Clear 0 1 write-only UART_ICR_RTIC Receive Time-Out Interrupt Clear 6 7 write-only UART_ICR_RXIC Receive Interrupt Clear 4 5 write-only UART_ICR_TXIC Transmit Interrupt Clear 5 6 write-only IFLS UART Interrupt FIFO Level Select 0x34 -1 read-write n 0x0 0x0 UART_IFLS_RX UART Receive Interrupt FIFO Level Select 3 6 UART_IFLS_RX1_8 RX FIFO >= 1/8 full 0x0 UART_IFLS_RX2_8 RX FIFO >= 1/4 full 0x1 UART_IFLS_RX4_8 RX FIFO >= 1/2 full (default) 0x2 UART_IFLS_RX6_8 RX FIFO >= 3/4 full 0x3 UART_IFLS_RX7_8 RX FIFO >= 7/8 full 0x4 UART_IFLS_TX UART Transmit Interrupt FIFO Level Select 0 3 UART_IFLS_TX1_8 TX FIFO and lt = 1/8 full 0x0 UART_IFLS_TX2_8 TX FIFO and lt = 1/4 full 0x1 UART_IFLS_TX4_8 TX FIFO and lt = 1/2 full (default) 0x2 UART_IFLS_TX6_8 TX FIFO and lt = 3/4 full 0x3 UART_IFLS_TX7_8 TX FIFO and lt = 7/8 full 0x4 ILPR UART IrDA Low-Power Register 0x20 -1 read-write n 0x0 0x0 UART_ILPR_ILPDVSR IrDA Low-Power Divisor 0 8 IM UART Interrupt Mask 0x38 -1 read-write n 0x0 0x0 UART_IM_9BITIM 9-Bit Mode Interrupt Mask 12 13 UART_IM_BEIM UART Break Error Interrupt Mask 9 10 UART_IM_CTSMIM UART Clear to Send Modem Interrupt Mask 1 2 UART_IM_DCDMIM UART Data Carrier Detect Modem Interrupt Mask 2 3 UART_IM_DMARXIM Receive DMA Interrupt Mask 16 17 UART_IM_DMATXIM Transmit DMA Interrupt Mask 17 18 UART_IM_DSRMIM UART Data Set Ready Modem Interrupt Mask 3 4 UART_IM_EOTIM End of Transmission Interrupt Mask 11 12 UART_IM_FEIM UART Framing Error Interrupt Mask 7 8 UART_IM_OEIM UART Overrun Error Interrupt Mask 10 11 UART_IM_PEIM UART Parity Error Interrupt Mask 8 9 UART_IM_RIMIM UART Ring Indicator Modem Interrupt Mask 0 1 UART_IM_RTIM UART Receive Time-Out Interrupt Mask 6 7 UART_IM_RXIM UART Receive Interrupt Mask 4 5 UART_IM_TXIM UART Transmit Interrupt Mask 5 6 LCRH UART Line Control 0x2C -1 read-write n 0x0 0x0 UART_LCRH_BRK UART Send Break 0 1 UART_LCRH_EPS UART Even Parity Select 2 3 UART_LCRH_FEN UART Enable FIFOs 4 5 UART_LCRH_PEN UART Parity Enable 1 2 UART_LCRH_SPS UART Stick Parity Select 7 8 UART_LCRH_STP2 UART Two Stop Bits Select 3 4 UART_LCRH_WLEN UART Word Length 5 7 UART_LCRH_WLEN_5 5 bits (default) 0x0 UART_LCRH_WLEN_6 6 bits 0x1 UART_LCRH_WLEN_7 7 bits 0x2 UART_LCRH_WLEN_8 8 bits 0x3 MIS UART Masked Interrupt Status 0x40 -1 read-write n 0x0 0x0 UART_MIS_9BITMIS 9-Bit Mode Masked Interrupt Status 12 13 UART_MIS_BEMIS UART Break Error Masked Interrupt Status 9 10 UART_MIS_CTSMIS UART Clear to Send Modem Masked Interrupt Status 1 2 UART_MIS_DCDMIS UART Data Carrier Detect Modem Masked Interrupt Status 2 3 UART_MIS_DMARXMIS Receive DMA Masked Interrupt Status 16 17 UART_MIS_DMATXMIS Transmit DMA Masked Interrupt Status 17 18 UART_MIS_DSRMIS UART Data Set Ready Modem Masked Interrupt Status 3 4 UART_MIS_EOTMIS End of Transmission Masked Interrupt Status 11 12 UART_MIS_FEMIS UART Framing Error Masked Interrupt Status 7 8 UART_MIS_OEMIS UART Overrun Error Masked Interrupt Status 10 11 UART_MIS_PEMIS UART Parity Error Masked Interrupt Status 8 9 UART_MIS_RIMIS UART Ring Indicator Modem Masked Interrupt Status 0 1 UART_MIS_RTMIS UART Receive Time-Out Masked Interrupt Status 6 7 UART_MIS_RXMIS UART Receive Masked Interrupt Status 4 5 UART_MIS_TXMIS UART Transmit Masked Interrupt Status 5 6 PP UART Peripheral Properties 0xFC0 -1 read-write n 0x0 0x0 UART_PP_MS Modem Support 2 3 UART_PP_MSE Modem Support Extended 3 4 UART_PP_NB 9-Bit Support 1 2 UART_PP_SC Smart Card Support 0 1 RIS UART Raw Interrupt Status 0x3C -1 read-write n 0x0 0x0 UART_RIS_9BITRIS 9-Bit Mode Raw Interrupt Status 12 13 UART_RIS_BERIS UART Break Error Raw Interrupt Status 9 10 UART_RIS_CTSRIS UART Clear to Send Modem Raw Interrupt Status 1 2 UART_RIS_DCDRIS UART Data Carrier Detect Modem Raw Interrupt Status 2 3 UART_RIS_DMARXRIS Receive DMA Raw Interrupt Status 16 17 UART_RIS_DMATXRIS Transmit DMA Raw Interrupt Status 17 18 UART_RIS_DSRRIS UART Data Set Ready Modem Raw Interrupt Status 3 4 UART_RIS_EOTRIS End of Transmission Raw Interrupt Status 11 12 UART_RIS_FERIS UART Framing Error Raw Interrupt Status 7 8 UART_RIS_OERIS UART Overrun Error Raw Interrupt Status 10 11 UART_RIS_PERIS UART Parity Error Raw Interrupt Status 8 9 UART_RIS_RIRIS UART Ring Indicator Modem Raw Interrupt Status 0 1 UART_RIS_RTRIS UART Receive Time-Out Raw Interrupt Status 6 7 UART_RIS_RXRIS UART Receive Raw Interrupt Status 4 5 UART_RIS_TXRIS UART Transmit Raw Interrupt Status 5 6 RSR UART Receive Status/Error Clear 0x4 -1 read-write n 0x0 0x0 UART_RSR_BE UART Break Error 2 3 UART_RSR_FE UART Framing Error 0 1 UART_RSR_OE UART Overrun Error 3 4 UART_RSR_PE UART Parity Error 1 2 UART0CC UART Clock Configuration 0xFC8 read-write n 0x0 0x0 UART_CC_CS UART Baud Clock Source 0 4 UART_CC_CS_SYSCLK System clock (based on clock source and divisor factor) 0x0 UART_CC_CS_PIOSC PIOSC 0x5 UART0CTL UART Control 0x30 read-write n 0x0 0x0 UART_CTL_CTSEN Enable Clear To Send 15 16 UART_CTL_DTR Data Terminal Ready 10 11 UART_CTL_EOT End of Transmission 4 5 UART_CTL_HSE High-Speed Enable 5 6 UART_CTL_LBE UART Loop Back Enable 7 8 UART_CTL_RTS Request to Send 11 12 UART_CTL_RTSEN Enable Request to Send 14 15 UART_CTL_RXE UART Receive Enable 9 10 UART_CTL_SIREN UART SIR Enable 1 2 UART_CTL_SIRLP UART SIR Low-Power Mode 2 3 UART_CTL_SMART ISO 7816 Smart Card Support 3 4 UART_CTL_TXE UART Transmit Enable 8 9 UART_CTL_UARTEN UART Enable 0 1 UART0DMACTL UART DMA Control 0x48 read-write n 0x0 0x0 UART_DMACTL_DMAERR DMA on Error 2 3 UART_DMACTL_RXDMAE Receive DMA Enable 0 1 UART_DMACTL_TXDMAE Transmit DMA Enable 1 2 UART0DR UART Data 0x0 read-write n 0x0 0x0 UART_DR_BE UART Break Error 10 11 UART_DR_DATA Data Transmitted or Received 0 8 UART_DR_FE UART Framing Error 8 9 UART_DR_OE UART Overrun Error 11 12 UART_DR_PE UART Parity Error 9 10 UART0ECR UART Receive Status/Error Clear UART_ALT 0x4 read-write n 0x0 0x0 UART_ECR_DATA Error Clear 0 8 UART0FBRD UART Fractional Baud-Rate Divisor 0x28 read-write n 0x0 0x0 UART_FBRD_DIVFRAC Fractional Baud-Rate Divisor 0 6 UART0FR UART Flag 0x18 read-write n 0x0 0x0 UART_FR_BUSY UART Busy 3 4 UART_FR_CTS Clear To Send 0 1 UART_FR_DCD Data Carrier Detect 2 3 UART_FR_DSR Data Set Ready 1 2 UART_FR_RI Ring Indicator 8 9 UART_FR_RXFE UART Receive FIFO Empty 4 5 UART_FR_RXFF UART Receive FIFO Full 6 7 UART_FR_TXFE UART Transmit FIFO Empty 7 8 UART_FR_TXFF UART Transmit FIFO Full 5 6 UART0IBRD UART Integer Baud-Rate Divisor 0x24 read-write n 0x0 0x0 UART_IBRD_DIVINT Integer Baud-Rate Divisor 0 16 UART0ICR UART Interrupt Clear 0x44 write-only n 0x0 0x0 UART_ICR_9BITIC 9-Bit Mode Interrupt Clear 12 13 write-only UART_ICR_BEIC Break Error Interrupt Clear 9 10 write-only UART_ICR_CTSMIC UART Clear to Send Modem Interrupt Clear 1 2 write-only UART_ICR_DCDMIC UART Data Carrier Detect Modem Interrupt Clear 2 3 write-only UART_ICR_DMARXIC Receive DMA Interrupt Clear 16 17 write-only UART_ICR_DMATXIC Transmit DMA Interrupt Clear 17 18 write-only UART_ICR_DSRMIC UART Data Set Ready Modem Interrupt Clear 3 4 write-only UART_ICR_EOTIC End of Transmission Interrupt Clear 11 12 write-only UART_ICR_FEIC Framing Error Interrupt Clear 7 8 write-only UART_ICR_OEIC Overrun Error Interrupt Clear 10 11 write-only UART_ICR_PEIC Parity Error Interrupt Clear 8 9 write-only UART_ICR_RIMIC UART Ring Indicator Modem Interrupt Clear 0 1 write-only UART_ICR_RTIC Receive Time-Out Interrupt Clear 6 7 write-only UART_ICR_RXIC Receive Interrupt Clear 4 5 write-only UART_ICR_TXIC Transmit Interrupt Clear 5 6 write-only UART0IFLS UART Interrupt FIFO Level Select 0x34 read-write n 0x0 0x0 UART_IFLS_RX UART Receive Interrupt FIFO Level Select 3 6 UART_IFLS_RX1_8 RX FIFO >= 1/8 full 0x0 UART_IFLS_RX2_8 RX FIFO >= 1/4 full 0x1 UART_IFLS_RX4_8 RX FIFO >= 1/2 full (default) 0x2 UART_IFLS_RX6_8 RX FIFO >= 3/4 full 0x3 UART_IFLS_RX7_8 RX FIFO >= 7/8 full 0x4 UART_IFLS_TX UART Transmit Interrupt FIFO Level Select 0 3 UART_IFLS_TX1_8 TX FIFO <= 1/8 full 0x0 UART_IFLS_TX2_8 TX FIFO <= 1/4 full 0x1 UART_IFLS_TX4_8 TX FIFO <= 1/2 full (default) 0x2 UART_IFLS_TX6_8 TX FIFO <= 3/4 full 0x3 UART_IFLS_TX7_8 TX FIFO <= 7/8 full 0x4 UART0ILPR UART IrDA Low-Power Register 0x20 read-write n 0x0 0x0 UART_ILPR_ILPDVSR IrDA Low-Power Divisor 0 8 UART0IM UART Interrupt Mask 0x38 read-write n 0x0 0x0 UART_IM_9BITIM 9-Bit Mode Interrupt Mask 12 13 UART_IM_BEIM UART Break Error Interrupt Mask 9 10 UART_IM_CTSMIM UART Clear to Send Modem Interrupt Mask 1 2 UART_IM_DCDMIM UART Data Carrier Detect Modem Interrupt Mask 2 3 UART_IM_DMARXIM Receive DMA Interrupt Mask 16 17 UART_IM_DMATXIM Transmit DMA Interrupt Mask 17 18 UART_IM_DSRMIM UART Data Set Ready Modem Interrupt Mask 3 4 UART_IM_EOTIM End of Transmission Interrupt Mask 11 12 UART_IM_FEIM UART Framing Error Interrupt Mask 7 8 UART_IM_OEIM UART Overrun Error Interrupt Mask 10 11 UART_IM_PEIM UART Parity Error Interrupt Mask 8 9 UART_IM_RIMIM UART Ring Indicator Modem Interrupt Mask 0 1 UART_IM_RTIM UART Receive Time-Out Interrupt Mask 6 7 UART_IM_RXIM UART Receive Interrupt Mask 4 5 UART_IM_TXIM UART Transmit Interrupt Mask 5 6 UART0LCRH UART Line Control 0x2C read-write n 0x0 0x0 UART_LCRH_BRK UART Send Break 0 1 UART_LCRH_EPS UART Even Parity Select 2 3 UART_LCRH_FEN UART Enable FIFOs 4 5 UART_LCRH_PEN UART Parity Enable 1 2 UART_LCRH_SPS UART Stick Parity Select 7 8 UART_LCRH_STP2 UART Two Stop Bits Select 3 4 UART_LCRH_WLEN UART Word Length 5 7 UART_LCRH_WLEN_5 5 bits (default) 0x0 UART_LCRH_WLEN_6 6 bits 0x1 UART_LCRH_WLEN_7 7 bits 0x2 UART_LCRH_WLEN_8 8 bits 0x3 UART0MIS UART Masked Interrupt Status 0x40 read-write n 0x0 0x0 UART_MIS_9BITMIS 9-Bit Mode Masked Interrupt Status 12 13 UART_MIS_BEMIS UART Break Error Masked Interrupt Status 9 10 UART_MIS_CTSMIS UART Clear to Send Modem Masked Interrupt Status 1 2 UART_MIS_DCDMIS UART Data Carrier Detect Modem Masked Interrupt Status 2 3 UART_MIS_DMARXMIS Receive DMA Masked Interrupt Status 16 17 UART_MIS_DMATXMIS Transmit DMA Masked Interrupt Status 17 18 UART_MIS_DSRMIS UART Data Set Ready Modem Masked Interrupt Status 3 4 UART_MIS_EOTMIS End of Transmission Masked Interrupt Status 11 12 UART_MIS_FEMIS UART Framing Error Masked Interrupt Status 7 8 UART_MIS_OEMIS UART Overrun Error Masked Interrupt Status 10 11 UART_MIS_PEMIS UART Parity Error Masked Interrupt Status 8 9 UART_MIS_RIMIS UART Ring Indicator Modem Masked Interrupt Status 0 1 UART_MIS_RTMIS UART Receive Time-Out Masked Interrupt Status 6 7 UART_MIS_RXMIS UART Receive Masked Interrupt Status 4 5 UART_MIS_TXMIS UART Transmit Masked Interrupt Status 5 6 UART0PP UART Peripheral Properties 0xFC0 read-write n 0x0 0x0 UART_PP_MS Modem Support 2 3 UART_PP_MSE Modem Support Extended 3 4 UART_PP_NB 9-Bit Support 1 2 UART_PP_SC Smart Card Support 0 1 UART0RIS UART Raw Interrupt Status 0x3C read-write n 0x0 0x0 UART_RIS_9BITRIS 9-Bit Mode Raw Interrupt Status 12 13 UART_RIS_BERIS UART Break Error Raw Interrupt Status 9 10 UART_RIS_CTSRIS UART Clear to Send Modem Raw Interrupt Status 1 2 UART_RIS_DCDRIS UART Data Carrier Detect Modem Raw Interrupt Status 2 3 UART_RIS_DMARXRIS Receive DMA Raw Interrupt Status 16 17 UART_RIS_DMATXRIS Transmit DMA Raw Interrupt Status 17 18 UART_RIS_DSRRIS UART Data Set Ready Modem Raw Interrupt Status 3 4 UART_RIS_EOTRIS End of Transmission Raw Interrupt Status 11 12 UART_RIS_FERIS UART Framing Error Raw Interrupt Status 7 8 UART_RIS_OERIS UART Overrun Error Raw Interrupt Status 10 11 UART_RIS_PERIS UART Parity Error Raw Interrupt Status 8 9 UART_RIS_RIRIS UART Ring Indicator Modem Raw Interrupt Status 0 1 UART_RIS_RTRIS UART Receive Time-Out Raw Interrupt Status 6 7 UART_RIS_RXRIS UART Receive Raw Interrupt Status 4 5 UART_RIS_TXRIS UART Transmit Raw Interrupt Status 5 6 UART0RSR UART Receive Status/Error Clear 0x4 read-write n 0x0 0x0 UART_RSR_BE UART Break Error 2 3 UART_RSR_FE UART Framing Error 0 1 UART_RSR_OE UART Overrun Error 3 4 UART_RSR_PE UART Parity Error 1 2 _9BITADDR UART 9-Bit Self Address 0xA4 -1 read-write n 0x0 0x0 UART_9BITADDR_9BITEN Enable 9-Bit Mode 15 16 UART_9BITADDR_ADDR Self Address for 9-Bit Mode 0 8 _9BITAMASK UART 9-Bit Self Address Mask 0xA8 -1 read-write n 0x0 0x0 UART_9BITAMASK_MASK Self Address Mask for 9-Bit Mode 0 8 UART6 Register map for UART0 peripheral UART 0x0 0x0 0x1000 registers n UART6 59 9BITADDR UART 9-Bit Self Address 0xA4 read-write n 0x0 0x0 UART_9BITADDR_9BITEN Enable 9-Bit Mode 15 16 UART_9BITADDR_ADDR Self Address for 9-Bit Mode 0 8 9BITAMASK UART 9-Bit Self Address Mask 0xA8 read-write n 0x0 0x0 UART_9BITAMASK_MASK Self Address Mask for 9-Bit Mode 0 8 CC UART Clock Configuration 0xFC8 -1 read-write n 0x0 0x0 UART_CC_CS UART Baud Clock Source 0 4 UART_CC_CS_SYSCLK System clock (based on clock source and divisor factor) 0x0 UART_CC_CS_PIOSC PIOSC 0x5 CTL UART Control 0x30 -1 read-write n 0x0 0x0 UART_CTL_CTSEN Enable Clear To Send 15 16 UART_CTL_DTR Data Terminal Ready 10 11 UART_CTL_EOT End of Transmission 4 5 UART_CTL_HSE High-Speed Enable 5 6 UART_CTL_LBE UART Loop Back Enable 7 8 UART_CTL_RTS Request to Send 11 12 UART_CTL_RTSEN Enable Request to Send 14 15 UART_CTL_RXE UART Receive Enable 9 10 UART_CTL_SIREN UART SIR Enable 1 2 UART_CTL_SIRLP UART SIR Low-Power Mode 2 3 UART_CTL_SMART ISO 7816 Smart Card Support 3 4 UART_CTL_TXE UART Transmit Enable 8 9 UART_CTL_UARTEN UART Enable 0 1 DMACTL UART DMA Control 0x48 -1 read-write n 0x0 0x0 UART_DMACTL_DMAERR DMA on Error 2 3 UART_DMACTL_RXDMAE Receive DMA Enable 0 1 UART_DMACTL_TXDMAE Transmit DMA Enable 1 2 DR UART Data 0x0 -1 read-write n 0x0 0x0 UART_DR_BE UART Break Error 10 11 UART_DR_DATA Data Transmitted or Received 0 8 UART_DR_FE UART Framing Error 8 9 UART_DR_OE UART Overrun Error 11 12 UART_DR_PE UART Parity Error 9 10 ECR UART Receive Status/Error Clear 0x4 -1 read-write n 0x0 0x0 UART_ECR_DATA Error Clear 0 8 FBRD UART Fractional Baud-Rate Divisor 0x28 -1 read-write n 0x0 0x0 UART_FBRD_DIVFRAC Fractional Baud-Rate Divisor 0 6 FR UART Flag 0x18 -1 read-write n 0x0 0x0 UART_FR_BUSY UART Busy 3 4 UART_FR_CTS Clear To Send 0 1 UART_FR_DCD Data Carrier Detect 2 3 UART_FR_DSR Data Set Ready 1 2 UART_FR_RI Ring Indicator 8 9 UART_FR_RXFE UART Receive FIFO Empty 4 5 UART_FR_RXFF UART Receive FIFO Full 6 7 UART_FR_TXFE UART Transmit FIFO Empty 7 8 UART_FR_TXFF UART Transmit FIFO Full 5 6 IBRD UART Integer Baud-Rate Divisor 0x24 -1 read-write n 0x0 0x0 UART_IBRD_DIVINT Integer Baud-Rate Divisor 0 16 ICR UART Interrupt Clear 0x44 -1 write-only n 0x0 0x0 UART_ICR_9BITIC 9-Bit Mode Interrupt Clear 12 13 write-only UART_ICR_BEIC Break Error Interrupt Clear 9 10 write-only UART_ICR_CTSMIC UART Clear to Send Modem Interrupt Clear 1 2 write-only UART_ICR_DCDMIC UART Data Carrier Detect Modem Interrupt Clear 2 3 write-only UART_ICR_DMARXIC Receive DMA Interrupt Clear 16 17 write-only UART_ICR_DMATXIC Transmit DMA Interrupt Clear 17 18 write-only UART_ICR_DSRMIC UART Data Set Ready Modem Interrupt Clear 3 4 write-only UART_ICR_EOTIC End of Transmission Interrupt Clear 11 12 write-only UART_ICR_FEIC Framing Error Interrupt Clear 7 8 write-only UART_ICR_OEIC Overrun Error Interrupt Clear 10 11 write-only UART_ICR_PEIC Parity Error Interrupt Clear 8 9 write-only UART_ICR_RIMIC UART Ring Indicator Modem Interrupt Clear 0 1 write-only UART_ICR_RTIC Receive Time-Out Interrupt Clear 6 7 write-only UART_ICR_RXIC Receive Interrupt Clear 4 5 write-only UART_ICR_TXIC Transmit Interrupt Clear 5 6 write-only IFLS UART Interrupt FIFO Level Select 0x34 -1 read-write n 0x0 0x0 UART_IFLS_RX UART Receive Interrupt FIFO Level Select 3 6 UART_IFLS_RX1_8 RX FIFO >= 1/8 full 0x0 UART_IFLS_RX2_8 RX FIFO >= 1/4 full 0x1 UART_IFLS_RX4_8 RX FIFO >= 1/2 full (default) 0x2 UART_IFLS_RX6_8 RX FIFO >= 3/4 full 0x3 UART_IFLS_RX7_8 RX FIFO >= 7/8 full 0x4 UART_IFLS_TX UART Transmit Interrupt FIFO Level Select 0 3 UART_IFLS_TX1_8 TX FIFO and lt = 1/8 full 0x0 UART_IFLS_TX2_8 TX FIFO and lt = 1/4 full 0x1 UART_IFLS_TX4_8 TX FIFO and lt = 1/2 full (default) 0x2 UART_IFLS_TX6_8 TX FIFO and lt = 3/4 full 0x3 UART_IFLS_TX7_8 TX FIFO and lt = 7/8 full 0x4 ILPR UART IrDA Low-Power Register 0x20 -1 read-write n 0x0 0x0 UART_ILPR_ILPDVSR IrDA Low-Power Divisor 0 8 IM UART Interrupt Mask 0x38 -1 read-write n 0x0 0x0 UART_IM_9BITIM 9-Bit Mode Interrupt Mask 12 13 UART_IM_BEIM UART Break Error Interrupt Mask 9 10 UART_IM_CTSMIM UART Clear to Send Modem Interrupt Mask 1 2 UART_IM_DCDMIM UART Data Carrier Detect Modem Interrupt Mask 2 3 UART_IM_DMARXIM Receive DMA Interrupt Mask 16 17 UART_IM_DMATXIM Transmit DMA Interrupt Mask 17 18 UART_IM_DSRMIM UART Data Set Ready Modem Interrupt Mask 3 4 UART_IM_EOTIM End of Transmission Interrupt Mask 11 12 UART_IM_FEIM UART Framing Error Interrupt Mask 7 8 UART_IM_OEIM UART Overrun Error Interrupt Mask 10 11 UART_IM_PEIM UART Parity Error Interrupt Mask 8 9 UART_IM_RIMIM UART Ring Indicator Modem Interrupt Mask 0 1 UART_IM_RTIM UART Receive Time-Out Interrupt Mask 6 7 UART_IM_RXIM UART Receive Interrupt Mask 4 5 UART_IM_TXIM UART Transmit Interrupt Mask 5 6 LCRH UART Line Control 0x2C -1 read-write n 0x0 0x0 UART_LCRH_BRK UART Send Break 0 1 UART_LCRH_EPS UART Even Parity Select 2 3 UART_LCRH_FEN UART Enable FIFOs 4 5 UART_LCRH_PEN UART Parity Enable 1 2 UART_LCRH_SPS UART Stick Parity Select 7 8 UART_LCRH_STP2 UART Two Stop Bits Select 3 4 UART_LCRH_WLEN UART Word Length 5 7 UART_LCRH_WLEN_5 5 bits (default) 0x0 UART_LCRH_WLEN_6 6 bits 0x1 UART_LCRH_WLEN_7 7 bits 0x2 UART_LCRH_WLEN_8 8 bits 0x3 MIS UART Masked Interrupt Status 0x40 -1 read-write n 0x0 0x0 UART_MIS_9BITMIS 9-Bit Mode Masked Interrupt Status 12 13 UART_MIS_BEMIS UART Break Error Masked Interrupt Status 9 10 UART_MIS_CTSMIS UART Clear to Send Modem Masked Interrupt Status 1 2 UART_MIS_DCDMIS UART Data Carrier Detect Modem Masked Interrupt Status 2 3 UART_MIS_DMARXMIS Receive DMA Masked Interrupt Status 16 17 UART_MIS_DMATXMIS Transmit DMA Masked Interrupt Status 17 18 UART_MIS_DSRMIS UART Data Set Ready Modem Masked Interrupt Status 3 4 UART_MIS_EOTMIS End of Transmission Masked Interrupt Status 11 12 UART_MIS_FEMIS UART Framing Error Masked Interrupt Status 7 8 UART_MIS_OEMIS UART Overrun Error Masked Interrupt Status 10 11 UART_MIS_PEMIS UART Parity Error Masked Interrupt Status 8 9 UART_MIS_RIMIS UART Ring Indicator Modem Masked Interrupt Status 0 1 UART_MIS_RTMIS UART Receive Time-Out Masked Interrupt Status 6 7 UART_MIS_RXMIS UART Receive Masked Interrupt Status 4 5 UART_MIS_TXMIS UART Transmit Masked Interrupt Status 5 6 PP UART Peripheral Properties 0xFC0 -1 read-write n 0x0 0x0 UART_PP_MS Modem Support 2 3 UART_PP_MSE Modem Support Extended 3 4 UART_PP_NB 9-Bit Support 1 2 UART_PP_SC Smart Card Support 0 1 RIS UART Raw Interrupt Status 0x3C -1 read-write n 0x0 0x0 UART_RIS_9BITRIS 9-Bit Mode Raw Interrupt Status 12 13 UART_RIS_BERIS UART Break Error Raw Interrupt Status 9 10 UART_RIS_CTSRIS UART Clear to Send Modem Raw Interrupt Status 1 2 UART_RIS_DCDRIS UART Data Carrier Detect Modem Raw Interrupt Status 2 3 UART_RIS_DMARXRIS Receive DMA Raw Interrupt Status 16 17 UART_RIS_DMATXRIS Transmit DMA Raw Interrupt Status 17 18 UART_RIS_DSRRIS UART Data Set Ready Modem Raw Interrupt Status 3 4 UART_RIS_EOTRIS End of Transmission Raw Interrupt Status 11 12 UART_RIS_FERIS UART Framing Error Raw Interrupt Status 7 8 UART_RIS_OERIS UART Overrun Error Raw Interrupt Status 10 11 UART_RIS_PERIS UART Parity Error Raw Interrupt Status 8 9 UART_RIS_RIRIS UART Ring Indicator Modem Raw Interrupt Status 0 1 UART_RIS_RTRIS UART Receive Time-Out Raw Interrupt Status 6 7 UART_RIS_RXRIS UART Receive Raw Interrupt Status 4 5 UART_RIS_TXRIS UART Transmit Raw Interrupt Status 5 6 RSR UART Receive Status/Error Clear 0x4 -1 read-write n 0x0 0x0 UART_RSR_BE UART Break Error 2 3 UART_RSR_FE UART Framing Error 0 1 UART_RSR_OE UART Overrun Error 3 4 UART_RSR_PE UART Parity Error 1 2 UART0CC UART Clock Configuration 0xFC8 read-write n 0x0 0x0 UART_CC_CS UART Baud Clock Source 0 4 UART_CC_CS_SYSCLK System clock (based on clock source and divisor factor) 0x0 UART_CC_CS_PIOSC PIOSC 0x5 UART0CTL UART Control 0x30 read-write n 0x0 0x0 UART_CTL_CTSEN Enable Clear To Send 15 16 UART_CTL_DTR Data Terminal Ready 10 11 UART_CTL_EOT End of Transmission 4 5 UART_CTL_HSE High-Speed Enable 5 6 UART_CTL_LBE UART Loop Back Enable 7 8 UART_CTL_RTS Request to Send 11 12 UART_CTL_RTSEN Enable Request to Send 14 15 UART_CTL_RXE UART Receive Enable 9 10 UART_CTL_SIREN UART SIR Enable 1 2 UART_CTL_SIRLP UART SIR Low-Power Mode 2 3 UART_CTL_SMART ISO 7816 Smart Card Support 3 4 UART_CTL_TXE UART Transmit Enable 8 9 UART_CTL_UARTEN UART Enable 0 1 UART0DMACTL UART DMA Control 0x48 read-write n 0x0 0x0 UART_DMACTL_DMAERR DMA on Error 2 3 UART_DMACTL_RXDMAE Receive DMA Enable 0 1 UART_DMACTL_TXDMAE Transmit DMA Enable 1 2 UART0DR UART Data 0x0 read-write n 0x0 0x0 UART_DR_BE UART Break Error 10 11 UART_DR_DATA Data Transmitted or Received 0 8 UART_DR_FE UART Framing Error 8 9 UART_DR_OE UART Overrun Error 11 12 UART_DR_PE UART Parity Error 9 10 UART0ECR UART Receive Status/Error Clear UART_ALT 0x4 read-write n 0x0 0x0 UART_ECR_DATA Error Clear 0 8 UART0FBRD UART Fractional Baud-Rate Divisor 0x28 read-write n 0x0 0x0 UART_FBRD_DIVFRAC Fractional Baud-Rate Divisor 0 6 UART0FR UART Flag 0x18 read-write n 0x0 0x0 UART_FR_BUSY UART Busy 3 4 UART_FR_CTS Clear To Send 0 1 UART_FR_DCD Data Carrier Detect 2 3 UART_FR_DSR Data Set Ready 1 2 UART_FR_RI Ring Indicator 8 9 UART_FR_RXFE UART Receive FIFO Empty 4 5 UART_FR_RXFF UART Receive FIFO Full 6 7 UART_FR_TXFE UART Transmit FIFO Empty 7 8 UART_FR_TXFF UART Transmit FIFO Full 5 6 UART0IBRD UART Integer Baud-Rate Divisor 0x24 read-write n 0x0 0x0 UART_IBRD_DIVINT Integer Baud-Rate Divisor 0 16 UART0ICR UART Interrupt Clear 0x44 write-only n 0x0 0x0 UART_ICR_9BITIC 9-Bit Mode Interrupt Clear 12 13 write-only UART_ICR_BEIC Break Error Interrupt Clear 9 10 write-only UART_ICR_CTSMIC UART Clear to Send Modem Interrupt Clear 1 2 write-only UART_ICR_DCDMIC UART Data Carrier Detect Modem Interrupt Clear 2 3 write-only UART_ICR_DMARXIC Receive DMA Interrupt Clear 16 17 write-only UART_ICR_DMATXIC Transmit DMA Interrupt Clear 17 18 write-only UART_ICR_DSRMIC UART Data Set Ready Modem Interrupt Clear 3 4 write-only UART_ICR_EOTIC End of Transmission Interrupt Clear 11 12 write-only UART_ICR_FEIC Framing Error Interrupt Clear 7 8 write-only UART_ICR_OEIC Overrun Error Interrupt Clear 10 11 write-only UART_ICR_PEIC Parity Error Interrupt Clear 8 9 write-only UART_ICR_RIMIC UART Ring Indicator Modem Interrupt Clear 0 1 write-only UART_ICR_RTIC Receive Time-Out Interrupt Clear 6 7 write-only UART_ICR_RXIC Receive Interrupt Clear 4 5 write-only UART_ICR_TXIC Transmit Interrupt Clear 5 6 write-only UART0IFLS UART Interrupt FIFO Level Select 0x34 read-write n 0x0 0x0 UART_IFLS_RX UART Receive Interrupt FIFO Level Select 3 6 UART_IFLS_RX1_8 RX FIFO >= 1/8 full 0x0 UART_IFLS_RX2_8 RX FIFO >= 1/4 full 0x1 UART_IFLS_RX4_8 RX FIFO >= 1/2 full (default) 0x2 UART_IFLS_RX6_8 RX FIFO >= 3/4 full 0x3 UART_IFLS_RX7_8 RX FIFO >= 7/8 full 0x4 UART_IFLS_TX UART Transmit Interrupt FIFO Level Select 0 3 UART_IFLS_TX1_8 TX FIFO <= 1/8 full 0x0 UART_IFLS_TX2_8 TX FIFO <= 1/4 full 0x1 UART_IFLS_TX4_8 TX FIFO <= 1/2 full (default) 0x2 UART_IFLS_TX6_8 TX FIFO <= 3/4 full 0x3 UART_IFLS_TX7_8 TX FIFO <= 7/8 full 0x4 UART0ILPR UART IrDA Low-Power Register 0x20 read-write n 0x0 0x0 UART_ILPR_ILPDVSR IrDA Low-Power Divisor 0 8 UART0IM UART Interrupt Mask 0x38 read-write n 0x0 0x0 UART_IM_9BITIM 9-Bit Mode Interrupt Mask 12 13 UART_IM_BEIM UART Break Error Interrupt Mask 9 10 UART_IM_CTSMIM UART Clear to Send Modem Interrupt Mask 1 2 UART_IM_DCDMIM UART Data Carrier Detect Modem Interrupt Mask 2 3 UART_IM_DMARXIM Receive DMA Interrupt Mask 16 17 UART_IM_DMATXIM Transmit DMA Interrupt Mask 17 18 UART_IM_DSRMIM UART Data Set Ready Modem Interrupt Mask 3 4 UART_IM_EOTIM End of Transmission Interrupt Mask 11 12 UART_IM_FEIM UART Framing Error Interrupt Mask 7 8 UART_IM_OEIM UART Overrun Error Interrupt Mask 10 11 UART_IM_PEIM UART Parity Error Interrupt Mask 8 9 UART_IM_RIMIM UART Ring Indicator Modem Interrupt Mask 0 1 UART_IM_RTIM UART Receive Time-Out Interrupt Mask 6 7 UART_IM_RXIM UART Receive Interrupt Mask 4 5 UART_IM_TXIM UART Transmit Interrupt Mask 5 6 UART0LCRH UART Line Control 0x2C read-write n 0x0 0x0 UART_LCRH_BRK UART Send Break 0 1 UART_LCRH_EPS UART Even Parity Select 2 3 UART_LCRH_FEN UART Enable FIFOs 4 5 UART_LCRH_PEN UART Parity Enable 1 2 UART_LCRH_SPS UART Stick Parity Select 7 8 UART_LCRH_STP2 UART Two Stop Bits Select 3 4 UART_LCRH_WLEN UART Word Length 5 7 UART_LCRH_WLEN_5 5 bits (default) 0x0 UART_LCRH_WLEN_6 6 bits 0x1 UART_LCRH_WLEN_7 7 bits 0x2 UART_LCRH_WLEN_8 8 bits 0x3 UART0MIS UART Masked Interrupt Status 0x40 read-write n 0x0 0x0 UART_MIS_9BITMIS 9-Bit Mode Masked Interrupt Status 12 13 UART_MIS_BEMIS UART Break Error Masked Interrupt Status 9 10 UART_MIS_CTSMIS UART Clear to Send Modem Masked Interrupt Status 1 2 UART_MIS_DCDMIS UART Data Carrier Detect Modem Masked Interrupt Status 2 3 UART_MIS_DMARXMIS Receive DMA Masked Interrupt Status 16 17 UART_MIS_DMATXMIS Transmit DMA Masked Interrupt Status 17 18 UART_MIS_DSRMIS UART Data Set Ready Modem Masked Interrupt Status 3 4 UART_MIS_EOTMIS End of Transmission Masked Interrupt Status 11 12 UART_MIS_FEMIS UART Framing Error Masked Interrupt Status 7 8 UART_MIS_OEMIS UART Overrun Error Masked Interrupt Status 10 11 UART_MIS_PEMIS UART Parity Error Masked Interrupt Status 8 9 UART_MIS_RIMIS UART Ring Indicator Modem Masked Interrupt Status 0 1 UART_MIS_RTMIS UART Receive Time-Out Masked Interrupt Status 6 7 UART_MIS_RXMIS UART Receive Masked Interrupt Status 4 5 UART_MIS_TXMIS UART Transmit Masked Interrupt Status 5 6 UART0PP UART Peripheral Properties 0xFC0 read-write n 0x0 0x0 UART_PP_MS Modem Support 2 3 UART_PP_MSE Modem Support Extended 3 4 UART_PP_NB 9-Bit Support 1 2 UART_PP_SC Smart Card Support 0 1 UART0RIS UART Raw Interrupt Status 0x3C read-write n 0x0 0x0 UART_RIS_9BITRIS 9-Bit Mode Raw Interrupt Status 12 13 UART_RIS_BERIS UART Break Error Raw Interrupt Status 9 10 UART_RIS_CTSRIS UART Clear to Send Modem Raw Interrupt Status 1 2 UART_RIS_DCDRIS UART Data Carrier Detect Modem Raw Interrupt Status 2 3 UART_RIS_DMARXRIS Receive DMA Raw Interrupt Status 16 17 UART_RIS_DMATXRIS Transmit DMA Raw Interrupt Status 17 18 UART_RIS_DSRRIS UART Data Set Ready Modem Raw Interrupt Status 3 4 UART_RIS_EOTRIS End of Transmission Raw Interrupt Status 11 12 UART_RIS_FERIS UART Framing Error Raw Interrupt Status 7 8 UART_RIS_OERIS UART Overrun Error Raw Interrupt Status 10 11 UART_RIS_PERIS UART Parity Error Raw Interrupt Status 8 9 UART_RIS_RIRIS UART Ring Indicator Modem Raw Interrupt Status 0 1 UART_RIS_RTRIS UART Receive Time-Out Raw Interrupt Status 6 7 UART_RIS_RXRIS UART Receive Raw Interrupt Status 4 5 UART_RIS_TXRIS UART Transmit Raw Interrupt Status 5 6 UART0RSR UART Receive Status/Error Clear 0x4 read-write n 0x0 0x0 UART_RSR_BE UART Break Error 2 3 UART_RSR_FE UART Framing Error 0 1 UART_RSR_OE UART Overrun Error 3 4 UART_RSR_PE UART Parity Error 1 2 _9BITADDR UART 9-Bit Self Address 0xA4 -1 read-write n 0x0 0x0 UART_9BITADDR_9BITEN Enable 9-Bit Mode 15 16 UART_9BITADDR_ADDR Self Address for 9-Bit Mode 0 8 _9BITAMASK UART 9-Bit Self Address Mask 0xA8 -1 read-write n 0x0 0x0 UART_9BITAMASK_MASK Self Address Mask for 9-Bit Mode 0 8 UART7 Register map for UART0 peripheral UART 0x0 0x0 0x1000 registers n UART7 60 9BITADDR UART 9-Bit Self Address 0xA4 read-write n 0x0 0x0 UART_9BITADDR_9BITEN Enable 9-Bit Mode 15 16 UART_9BITADDR_ADDR Self Address for 9-Bit Mode 0 8 9BITAMASK UART 9-Bit Self Address Mask 0xA8 read-write n 0x0 0x0 UART_9BITAMASK_MASK Self Address Mask for 9-Bit Mode 0 8 CC UART Clock Configuration 0xFC8 -1 read-write n 0x0 0x0 UART_CC_CS UART Baud Clock Source 0 4 UART_CC_CS_SYSCLK System clock (based on clock source and divisor factor) 0x0 UART_CC_CS_PIOSC PIOSC 0x5 CTL UART Control 0x30 -1 read-write n 0x0 0x0 UART_CTL_CTSEN Enable Clear To Send 15 16 UART_CTL_DTR Data Terminal Ready 10 11 UART_CTL_EOT End of Transmission 4 5 UART_CTL_HSE High-Speed Enable 5 6 UART_CTL_LBE UART Loop Back Enable 7 8 UART_CTL_RTS Request to Send 11 12 UART_CTL_RTSEN Enable Request to Send 14 15 UART_CTL_RXE UART Receive Enable 9 10 UART_CTL_SIREN UART SIR Enable 1 2 UART_CTL_SIRLP UART SIR Low-Power Mode 2 3 UART_CTL_SMART ISO 7816 Smart Card Support 3 4 UART_CTL_TXE UART Transmit Enable 8 9 UART_CTL_UARTEN UART Enable 0 1 DMACTL UART DMA Control 0x48 -1 read-write n 0x0 0x0 UART_DMACTL_DMAERR DMA on Error 2 3 UART_DMACTL_RXDMAE Receive DMA Enable 0 1 UART_DMACTL_TXDMAE Transmit DMA Enable 1 2 DR UART Data 0x0 -1 read-write n 0x0 0x0 UART_DR_BE UART Break Error 10 11 UART_DR_DATA Data Transmitted or Received 0 8 UART_DR_FE UART Framing Error 8 9 UART_DR_OE UART Overrun Error 11 12 UART_DR_PE UART Parity Error 9 10 ECR UART Receive Status/Error Clear 0x4 -1 read-write n 0x0 0x0 UART_ECR_DATA Error Clear 0 8 FBRD UART Fractional Baud-Rate Divisor 0x28 -1 read-write n 0x0 0x0 UART_FBRD_DIVFRAC Fractional Baud-Rate Divisor 0 6 FR UART Flag 0x18 -1 read-write n 0x0 0x0 UART_FR_BUSY UART Busy 3 4 UART_FR_CTS Clear To Send 0 1 UART_FR_DCD Data Carrier Detect 2 3 UART_FR_DSR Data Set Ready 1 2 UART_FR_RI Ring Indicator 8 9 UART_FR_RXFE UART Receive FIFO Empty 4 5 UART_FR_RXFF UART Receive FIFO Full 6 7 UART_FR_TXFE UART Transmit FIFO Empty 7 8 UART_FR_TXFF UART Transmit FIFO Full 5 6 IBRD UART Integer Baud-Rate Divisor 0x24 -1 read-write n 0x0 0x0 UART_IBRD_DIVINT Integer Baud-Rate Divisor 0 16 ICR UART Interrupt Clear 0x44 -1 write-only n 0x0 0x0 UART_ICR_9BITIC 9-Bit Mode Interrupt Clear 12 13 write-only UART_ICR_BEIC Break Error Interrupt Clear 9 10 write-only UART_ICR_CTSMIC UART Clear to Send Modem Interrupt Clear 1 2 write-only UART_ICR_DCDMIC UART Data Carrier Detect Modem Interrupt Clear 2 3 write-only UART_ICR_DMARXIC Receive DMA Interrupt Clear 16 17 write-only UART_ICR_DMATXIC Transmit DMA Interrupt Clear 17 18 write-only UART_ICR_DSRMIC UART Data Set Ready Modem Interrupt Clear 3 4 write-only UART_ICR_EOTIC End of Transmission Interrupt Clear 11 12 write-only UART_ICR_FEIC Framing Error Interrupt Clear 7 8 write-only UART_ICR_OEIC Overrun Error Interrupt Clear 10 11 write-only UART_ICR_PEIC Parity Error Interrupt Clear 8 9 write-only UART_ICR_RIMIC UART Ring Indicator Modem Interrupt Clear 0 1 write-only UART_ICR_RTIC Receive Time-Out Interrupt Clear 6 7 write-only UART_ICR_RXIC Receive Interrupt Clear 4 5 write-only UART_ICR_TXIC Transmit Interrupt Clear 5 6 write-only IFLS UART Interrupt FIFO Level Select 0x34 -1 read-write n 0x0 0x0 UART_IFLS_RX UART Receive Interrupt FIFO Level Select 3 6 UART_IFLS_RX1_8 RX FIFO >= 1/8 full 0x0 UART_IFLS_RX2_8 RX FIFO >= 1/4 full 0x1 UART_IFLS_RX4_8 RX FIFO >= 1/2 full (default) 0x2 UART_IFLS_RX6_8 RX FIFO >= 3/4 full 0x3 UART_IFLS_RX7_8 RX FIFO >= 7/8 full 0x4 UART_IFLS_TX UART Transmit Interrupt FIFO Level Select 0 3 UART_IFLS_TX1_8 TX FIFO and lt = 1/8 full 0x0 UART_IFLS_TX2_8 TX FIFO and lt = 1/4 full 0x1 UART_IFLS_TX4_8 TX FIFO and lt = 1/2 full (default) 0x2 UART_IFLS_TX6_8 TX FIFO and lt = 3/4 full 0x3 UART_IFLS_TX7_8 TX FIFO and lt = 7/8 full 0x4 ILPR UART IrDA Low-Power Register 0x20 -1 read-write n 0x0 0x0 UART_ILPR_ILPDVSR IrDA Low-Power Divisor 0 8 IM UART Interrupt Mask 0x38 -1 read-write n 0x0 0x0 UART_IM_9BITIM 9-Bit Mode Interrupt Mask 12 13 UART_IM_BEIM UART Break Error Interrupt Mask 9 10 UART_IM_CTSMIM UART Clear to Send Modem Interrupt Mask 1 2 UART_IM_DCDMIM UART Data Carrier Detect Modem Interrupt Mask 2 3 UART_IM_DMARXIM Receive DMA Interrupt Mask 16 17 UART_IM_DMATXIM Transmit DMA Interrupt Mask 17 18 UART_IM_DSRMIM UART Data Set Ready Modem Interrupt Mask 3 4 UART_IM_EOTIM End of Transmission Interrupt Mask 11 12 UART_IM_FEIM UART Framing Error Interrupt Mask 7 8 UART_IM_OEIM UART Overrun Error Interrupt Mask 10 11 UART_IM_PEIM UART Parity Error Interrupt Mask 8 9 UART_IM_RIMIM UART Ring Indicator Modem Interrupt Mask 0 1 UART_IM_RTIM UART Receive Time-Out Interrupt Mask 6 7 UART_IM_RXIM UART Receive Interrupt Mask 4 5 UART_IM_TXIM UART Transmit Interrupt Mask 5 6 LCRH UART Line Control 0x2C -1 read-write n 0x0 0x0 UART_LCRH_BRK UART Send Break 0 1 UART_LCRH_EPS UART Even Parity Select 2 3 UART_LCRH_FEN UART Enable FIFOs 4 5 UART_LCRH_PEN UART Parity Enable 1 2 UART_LCRH_SPS UART Stick Parity Select 7 8 UART_LCRH_STP2 UART Two Stop Bits Select 3 4 UART_LCRH_WLEN UART Word Length 5 7 UART_LCRH_WLEN_5 5 bits (default) 0x0 UART_LCRH_WLEN_6 6 bits 0x1 UART_LCRH_WLEN_7 7 bits 0x2 UART_LCRH_WLEN_8 8 bits 0x3 MIS UART Masked Interrupt Status 0x40 -1 read-write n 0x0 0x0 UART_MIS_9BITMIS 9-Bit Mode Masked Interrupt Status 12 13 UART_MIS_BEMIS UART Break Error Masked Interrupt Status 9 10 UART_MIS_CTSMIS UART Clear to Send Modem Masked Interrupt Status 1 2 UART_MIS_DCDMIS UART Data Carrier Detect Modem Masked Interrupt Status 2 3 UART_MIS_DMARXMIS Receive DMA Masked Interrupt Status 16 17 UART_MIS_DMATXMIS Transmit DMA Masked Interrupt Status 17 18 UART_MIS_DSRMIS UART Data Set Ready Modem Masked Interrupt Status 3 4 UART_MIS_EOTMIS End of Transmission Masked Interrupt Status 11 12 UART_MIS_FEMIS UART Framing Error Masked Interrupt Status 7 8 UART_MIS_OEMIS UART Overrun Error Masked Interrupt Status 10 11 UART_MIS_PEMIS UART Parity Error Masked Interrupt Status 8 9 UART_MIS_RIMIS UART Ring Indicator Modem Masked Interrupt Status 0 1 UART_MIS_RTMIS UART Receive Time-Out Masked Interrupt Status 6 7 UART_MIS_RXMIS UART Receive Masked Interrupt Status 4 5 UART_MIS_TXMIS UART Transmit Masked Interrupt Status 5 6 PP UART Peripheral Properties 0xFC0 -1 read-write n 0x0 0x0 UART_PP_MS Modem Support 2 3 UART_PP_MSE Modem Support Extended 3 4 UART_PP_NB 9-Bit Support 1 2 UART_PP_SC Smart Card Support 0 1 RIS UART Raw Interrupt Status 0x3C -1 read-write n 0x0 0x0 UART_RIS_9BITRIS 9-Bit Mode Raw Interrupt Status 12 13 UART_RIS_BERIS UART Break Error Raw Interrupt Status 9 10 UART_RIS_CTSRIS UART Clear to Send Modem Raw Interrupt Status 1 2 UART_RIS_DCDRIS UART Data Carrier Detect Modem Raw Interrupt Status 2 3 UART_RIS_DMARXRIS Receive DMA Raw Interrupt Status 16 17 UART_RIS_DMATXRIS Transmit DMA Raw Interrupt Status 17 18 UART_RIS_DSRRIS UART Data Set Ready Modem Raw Interrupt Status 3 4 UART_RIS_EOTRIS End of Transmission Raw Interrupt Status 11 12 UART_RIS_FERIS UART Framing Error Raw Interrupt Status 7 8 UART_RIS_OERIS UART Overrun Error Raw Interrupt Status 10 11 UART_RIS_PERIS UART Parity Error Raw Interrupt Status 8 9 UART_RIS_RIRIS UART Ring Indicator Modem Raw Interrupt Status 0 1 UART_RIS_RTRIS UART Receive Time-Out Raw Interrupt Status 6 7 UART_RIS_RXRIS UART Receive Raw Interrupt Status 4 5 UART_RIS_TXRIS UART Transmit Raw Interrupt Status 5 6 RSR UART Receive Status/Error Clear 0x4 -1 read-write n 0x0 0x0 UART_RSR_BE UART Break Error 2 3 UART_RSR_FE UART Framing Error 0 1 UART_RSR_OE UART Overrun Error 3 4 UART_RSR_PE UART Parity Error 1 2 UART0CC UART Clock Configuration 0xFC8 read-write n 0x0 0x0 UART_CC_CS UART Baud Clock Source 0 4 UART_CC_CS_SYSCLK System clock (based on clock source and divisor factor) 0x0 UART_CC_CS_PIOSC PIOSC 0x5 UART0CTL UART Control 0x30 read-write n 0x0 0x0 UART_CTL_CTSEN Enable Clear To Send 15 16 UART_CTL_DTR Data Terminal Ready 10 11 UART_CTL_EOT End of Transmission 4 5 UART_CTL_HSE High-Speed Enable 5 6 UART_CTL_LBE UART Loop Back Enable 7 8 UART_CTL_RTS Request to Send 11 12 UART_CTL_RTSEN Enable Request to Send 14 15 UART_CTL_RXE UART Receive Enable 9 10 UART_CTL_SIREN UART SIR Enable 1 2 UART_CTL_SIRLP UART SIR Low-Power Mode 2 3 UART_CTL_SMART ISO 7816 Smart Card Support 3 4 UART_CTL_TXE UART Transmit Enable 8 9 UART_CTL_UARTEN UART Enable 0 1 UART0DMACTL UART DMA Control 0x48 read-write n 0x0 0x0 UART_DMACTL_DMAERR DMA on Error 2 3 UART_DMACTL_RXDMAE Receive DMA Enable 0 1 UART_DMACTL_TXDMAE Transmit DMA Enable 1 2 UART0DR UART Data 0x0 read-write n 0x0 0x0 UART_DR_BE UART Break Error 10 11 UART_DR_DATA Data Transmitted or Received 0 8 UART_DR_FE UART Framing Error 8 9 UART_DR_OE UART Overrun Error 11 12 UART_DR_PE UART Parity Error 9 10 UART0ECR UART Receive Status/Error Clear UART_ALT 0x4 read-write n 0x0 0x0 UART_ECR_DATA Error Clear 0 8 UART0FBRD UART Fractional Baud-Rate Divisor 0x28 read-write n 0x0 0x0 UART_FBRD_DIVFRAC Fractional Baud-Rate Divisor 0 6 UART0FR UART Flag 0x18 read-write n 0x0 0x0 UART_FR_BUSY UART Busy 3 4 UART_FR_CTS Clear To Send 0 1 UART_FR_DCD Data Carrier Detect 2 3 UART_FR_DSR Data Set Ready 1 2 UART_FR_RI Ring Indicator 8 9 UART_FR_RXFE UART Receive FIFO Empty 4 5 UART_FR_RXFF UART Receive FIFO Full 6 7 UART_FR_TXFE UART Transmit FIFO Empty 7 8 UART_FR_TXFF UART Transmit FIFO Full 5 6 UART0IBRD UART Integer Baud-Rate Divisor 0x24 read-write n 0x0 0x0 UART_IBRD_DIVINT Integer Baud-Rate Divisor 0 16 UART0ICR UART Interrupt Clear 0x44 write-only n 0x0 0x0 UART_ICR_9BITIC 9-Bit Mode Interrupt Clear 12 13 write-only UART_ICR_BEIC Break Error Interrupt Clear 9 10 write-only UART_ICR_CTSMIC UART Clear to Send Modem Interrupt Clear 1 2 write-only UART_ICR_DCDMIC UART Data Carrier Detect Modem Interrupt Clear 2 3 write-only UART_ICR_DMARXIC Receive DMA Interrupt Clear 16 17 write-only UART_ICR_DMATXIC Transmit DMA Interrupt Clear 17 18 write-only UART_ICR_DSRMIC UART Data Set Ready Modem Interrupt Clear 3 4 write-only UART_ICR_EOTIC End of Transmission Interrupt Clear 11 12 write-only UART_ICR_FEIC Framing Error Interrupt Clear 7 8 write-only UART_ICR_OEIC Overrun Error Interrupt Clear 10 11 write-only UART_ICR_PEIC Parity Error Interrupt Clear 8 9 write-only UART_ICR_RIMIC UART Ring Indicator Modem Interrupt Clear 0 1 write-only UART_ICR_RTIC Receive Time-Out Interrupt Clear 6 7 write-only UART_ICR_RXIC Receive Interrupt Clear 4 5 write-only UART_ICR_TXIC Transmit Interrupt Clear 5 6 write-only UART0IFLS UART Interrupt FIFO Level Select 0x34 read-write n 0x0 0x0 UART_IFLS_RX UART Receive Interrupt FIFO Level Select 3 6 UART_IFLS_RX1_8 RX FIFO >= 1/8 full 0x0 UART_IFLS_RX2_8 RX FIFO >= 1/4 full 0x1 UART_IFLS_RX4_8 RX FIFO >= 1/2 full (default) 0x2 UART_IFLS_RX6_8 RX FIFO >= 3/4 full 0x3 UART_IFLS_RX7_8 RX FIFO >= 7/8 full 0x4 UART_IFLS_TX UART Transmit Interrupt FIFO Level Select 0 3 UART_IFLS_TX1_8 TX FIFO <= 1/8 full 0x0 UART_IFLS_TX2_8 TX FIFO <= 1/4 full 0x1 UART_IFLS_TX4_8 TX FIFO <= 1/2 full (default) 0x2 UART_IFLS_TX6_8 TX FIFO <= 3/4 full 0x3 UART_IFLS_TX7_8 TX FIFO <= 7/8 full 0x4 UART0ILPR UART IrDA Low-Power Register 0x20 read-write n 0x0 0x0 UART_ILPR_ILPDVSR IrDA Low-Power Divisor 0 8 UART0IM UART Interrupt Mask 0x38 read-write n 0x0 0x0 UART_IM_9BITIM 9-Bit Mode Interrupt Mask 12 13 UART_IM_BEIM UART Break Error Interrupt Mask 9 10 UART_IM_CTSMIM UART Clear to Send Modem Interrupt Mask 1 2 UART_IM_DCDMIM UART Data Carrier Detect Modem Interrupt Mask 2 3 UART_IM_DMARXIM Receive DMA Interrupt Mask 16 17 UART_IM_DMATXIM Transmit DMA Interrupt Mask 17 18 UART_IM_DSRMIM UART Data Set Ready Modem Interrupt Mask 3 4 UART_IM_EOTIM End of Transmission Interrupt Mask 11 12 UART_IM_FEIM UART Framing Error Interrupt Mask 7 8 UART_IM_OEIM UART Overrun Error Interrupt Mask 10 11 UART_IM_PEIM UART Parity Error Interrupt Mask 8 9 UART_IM_RIMIM UART Ring Indicator Modem Interrupt Mask 0 1 UART_IM_RTIM UART Receive Time-Out Interrupt Mask 6 7 UART_IM_RXIM UART Receive Interrupt Mask 4 5 UART_IM_TXIM UART Transmit Interrupt Mask 5 6 UART0LCRH UART Line Control 0x2C read-write n 0x0 0x0 UART_LCRH_BRK UART Send Break 0 1 UART_LCRH_EPS UART Even Parity Select 2 3 UART_LCRH_FEN UART Enable FIFOs 4 5 UART_LCRH_PEN UART Parity Enable 1 2 UART_LCRH_SPS UART Stick Parity Select 7 8 UART_LCRH_STP2 UART Two Stop Bits Select 3 4 UART_LCRH_WLEN UART Word Length 5 7 UART_LCRH_WLEN_5 5 bits (default) 0x0 UART_LCRH_WLEN_6 6 bits 0x1 UART_LCRH_WLEN_7 7 bits 0x2 UART_LCRH_WLEN_8 8 bits 0x3 UART0MIS UART Masked Interrupt Status 0x40 read-write n 0x0 0x0 UART_MIS_9BITMIS 9-Bit Mode Masked Interrupt Status 12 13 UART_MIS_BEMIS UART Break Error Masked Interrupt Status 9 10 UART_MIS_CTSMIS UART Clear to Send Modem Masked Interrupt Status 1 2 UART_MIS_DCDMIS UART Data Carrier Detect Modem Masked Interrupt Status 2 3 UART_MIS_DMARXMIS Receive DMA Masked Interrupt Status 16 17 UART_MIS_DMATXMIS Transmit DMA Masked Interrupt Status 17 18 UART_MIS_DSRMIS UART Data Set Ready Modem Masked Interrupt Status 3 4 UART_MIS_EOTMIS End of Transmission Masked Interrupt Status 11 12 UART_MIS_FEMIS UART Framing Error Masked Interrupt Status 7 8 UART_MIS_OEMIS UART Overrun Error Masked Interrupt Status 10 11 UART_MIS_PEMIS UART Parity Error Masked Interrupt Status 8 9 UART_MIS_RIMIS UART Ring Indicator Modem Masked Interrupt Status 0 1 UART_MIS_RTMIS UART Receive Time-Out Masked Interrupt Status 6 7 UART_MIS_RXMIS UART Receive Masked Interrupt Status 4 5 UART_MIS_TXMIS UART Transmit Masked Interrupt Status 5 6 UART0PP UART Peripheral Properties 0xFC0 read-write n 0x0 0x0 UART_PP_MS Modem Support 2 3 UART_PP_MSE Modem Support Extended 3 4 UART_PP_NB 9-Bit Support 1 2 UART_PP_SC Smart Card Support 0 1 UART0RIS UART Raw Interrupt Status 0x3C read-write n 0x0 0x0 UART_RIS_9BITRIS 9-Bit Mode Raw Interrupt Status 12 13 UART_RIS_BERIS UART Break Error Raw Interrupt Status 9 10 UART_RIS_CTSRIS UART Clear to Send Modem Raw Interrupt Status 1 2 UART_RIS_DCDRIS UART Data Carrier Detect Modem Raw Interrupt Status 2 3 UART_RIS_DMARXRIS Receive DMA Raw Interrupt Status 16 17 UART_RIS_DMATXRIS Transmit DMA Raw Interrupt Status 17 18 UART_RIS_DSRRIS UART Data Set Ready Modem Raw Interrupt Status 3 4 UART_RIS_EOTRIS End of Transmission Raw Interrupt Status 11 12 UART_RIS_FERIS UART Framing Error Raw Interrupt Status 7 8 UART_RIS_OERIS UART Overrun Error Raw Interrupt Status 10 11 UART_RIS_PERIS UART Parity Error Raw Interrupt Status 8 9 UART_RIS_RIRIS UART Ring Indicator Modem Raw Interrupt Status 0 1 UART_RIS_RTRIS UART Receive Time-Out Raw Interrupt Status 6 7 UART_RIS_RXRIS UART Receive Raw Interrupt Status 4 5 UART_RIS_TXRIS UART Transmit Raw Interrupt Status 5 6 UART0RSR UART Receive Status/Error Clear 0x4 read-write n 0x0 0x0 UART_RSR_BE UART Break Error 2 3 UART_RSR_FE UART Framing Error 0 1 UART_RSR_OE UART Overrun Error 3 4 UART_RSR_PE UART Parity Error 1 2 _9BITADDR UART 9-Bit Self Address 0xA4 -1 read-write n 0x0 0x0 UART_9BITADDR_9BITEN Enable 9-Bit Mode 15 16 UART_9BITADDR_ADDR Self Address for 9-Bit Mode 0 8 _9BITAMASK UART 9-Bit Self Address Mask 0xA8 -1 read-write n 0x0 0x0 UART_9BITAMASK_MASK Self Address Mask for 9-Bit Mode 0 8 UDMA Register map for UDMA peripheral UDM 0x0 0x0 0x1000 registers n UDMA 44 UDMAERR 45 ALTBASE DMA Alternate Channel Control Base Pointer 0xC -1 read-write n 0x0 0x0 UDMA_ALTBASE_ADDR Alternate Channel Address Pointer 0 32 ALTCLR DMA Channel Primary Alternate Clear 0x34 -1 write-only n 0x0 0x0 UDMA_ALTCLR_CLR Channel [n] Alternate Clear 0 32 write-only ALTSET DMA Channel Primary Alternate Set 0x30 -1 read-write n 0x0 0x0 UDMA_ALTSET_SET Channel [n] Alternate Set 0 32 CFG DMA Configuration 0x4 -1 write-only n 0x0 0x0 UDMA_CFG_MASTEN Controller Master Enable 0 1 write-only CHASGN DMA Channel Assignment 0x500 -1 read-write n 0x0 0x0 UDMA_CHASGN Channel [n] Assignment Select 0 32 UDMA_CHASGN_PRIMARY Use the primary channel assignment 0x0 UDMA_CHASGN_SECONDARY Use the secondary channel assignment 0x1 CHMAP0 DMA Channel Map Select 0 0x510 -1 read-write n 0x0 0x0 UDMA_CHMAP0_CH0SEL uDMA Channel 0 Source Select 0 4 UDMA_CHMAP0_CH1SEL uDMA Channel 1 Source Select 4 8 UDMA_CHMAP0_CH2SEL uDMA Channel 2 Source Select 8 12 UDMA_CHMAP0_CH3SEL uDMA Channel 3 Source Select 12 16 UDMA_CHMAP0_CH4SEL uDMA Channel 4 Source Select 16 20 UDMA_CHMAP0_CH5SEL uDMA Channel 5 Source Select 20 24 UDMA_CHMAP0_CH6SEL uDMA Channel 6 Source Select 24 28 UDMA_CHMAP0_CH7SEL uDMA Channel 7 Source Select 28 32 CHMAP1 DMA Channel Map Select 1 0x514 -1 read-write n 0x0 0x0 UDMA_CHMAP1_CH10SEL uDMA Channel 10 Source Select 8 12 UDMA_CHMAP1_CH11SEL uDMA Channel 11 Source Select 12 16 UDMA_CHMAP1_CH12SEL uDMA Channel 12 Source Select 16 20 UDMA_CHMAP1_CH13SEL uDMA Channel 13 Source Select 20 24 UDMA_CHMAP1_CH14SEL uDMA Channel 14 Source Select 24 28 UDMA_CHMAP1_CH15SEL uDMA Channel 15 Source Select 28 32 UDMA_CHMAP1_CH8SEL uDMA Channel 8 Source Select 0 4 UDMA_CHMAP1_CH9SEL uDMA Channel 9 Source Select 4 8 CHMAP2 DMA Channel Map Select 2 0x518 -1 read-write n 0x0 0x0 UDMA_CHMAP2_CH16SEL uDMA Channel 16 Source Select 0 4 UDMA_CHMAP2_CH17SEL uDMA Channel 17 Source Select 4 8 UDMA_CHMAP2_CH18SEL uDMA Channel 18 Source Select 8 12 UDMA_CHMAP2_CH19SEL uDMA Channel 19 Source Select 12 16 UDMA_CHMAP2_CH20SEL uDMA Channel 20 Source Select 16 20 UDMA_CHMAP2_CH21SEL uDMA Channel 21 Source Select 20 24 UDMA_CHMAP2_CH22SEL uDMA Channel 22 Source Select 24 28 UDMA_CHMAP2_CH23SEL uDMA Channel 23 Source Select 28 32 CHMAP3 DMA Channel Map Select 3 0x51C -1 read-write n 0x0 0x0 UDMA_CHMAP3_CH24SEL uDMA Channel 24 Source Select 0 4 UDMA_CHMAP3_CH25SEL uDMA Channel 25 Source Select 4 8 UDMA_CHMAP3_CH26SEL uDMA Channel 26 Source Select 8 12 UDMA_CHMAP3_CH27SEL uDMA Channel 27 Source Select 12 16 UDMA_CHMAP3_CH28SEL uDMA Channel 28 Source Select 16 20 UDMA_CHMAP3_CH29SEL uDMA Channel 29 Source Select 20 24 UDMA_CHMAP3_CH30SEL uDMA Channel 30 Source Select 24 28 UDMA_CHMAP3_CH31SEL uDMA Channel 31 Source Select 28 32 CTLBASE DMA Channel Control Base Pointer 0x8 -1 read-write n 0x0 0x0 UDMA_CTLBASE_ADDR Channel Control Base Address 10 32 ENACLR DMA Channel Enable Clear 0x2C -1 write-only n 0x0 0x0 UDMA_ENACLR_CLR Clear Channel [n] Enable Clear 0 32 write-only ENASET DMA Channel Enable Set 0x28 -1 read-write n 0x0 0x0 UDMA_ENASET_SET Channel [n] Enable Set 0 32 ERRCLR DMA Bus Error Clear 0x4C -1 read-write n 0x0 0x0 UDMA_ERRCLR_ERRCLR uDMA Bus Error Status 0 1 PRIOCLR DMA Channel Priority Clear 0x3C -1 write-only n 0x0 0x0 UDMA_PRIOCLR_CLR Channel [n] Priority Clear 0 32 write-only PRIOSET DMA Channel Priority Set 0x38 -1 read-write n 0x0 0x0 UDMA_PRIOSET_SET Channel [n] Priority Set 0 32 REQMASKCLR DMA Channel Request Mask Clear 0x24 -1 write-only n 0x0 0x0 UDMA_REQMASKCLR_CLR Channel [n] Request Mask Clear 0 32 write-only REQMASKSET DMA Channel Request Mask Set 0x20 -1 read-write n 0x0 0x0 UDMA_REQMASKSET_SET Channel [n] Request Mask Set 0 32 STAT DMA Status 0x0 -1 read-write n 0x0 0x0 UDMA_STAT_DMACHANS Available uDMA Channels Minus 1 16 21 UDMA_STAT_MASTEN Master Enable Status 0 1 UDMA_STAT_STATE Control State Machine Status 4 8 UDMA_STAT_STATE_IDLE Idle 0x0 UDMA_STAT_STATE_RD_CTRL Reading channel controller data 0x1 UDMA_STAT_STATE_RD_SRCENDP Reading source end pointer 0x2 UDMA_STAT_STATE_RD_DSTENDP Reading destination end pointer 0x3 UDMA_STAT_STATE_RD_SRCDAT Reading source data 0x4 UDMA_STAT_STATE_WR_DSTDAT Writing destination data 0x5 UDMA_STAT_STATE_WAIT Waiting for uDMA request to clear 0x6 UDMA_STAT_STATE_WR_CTRL Writing channel controller data 0x7 UDMA_STAT_STATE_STALL Stalled 0x8 UDMA_STAT_STATE_DONE Done 0x9 UDMA_STAT_STATE_UNDEF Undefined 0xa SWREQ DMA Channel Software Request 0x14 -1 write-only n 0x0 0x0 UDMA_SWREQ Channel [n] Software Request 0 32 write-only UDMAALTBASE DMA Alternate Channel Control Base Pointer 0xC read-write n 0x0 0x0 UDMA_ALTBASE_ADDR Alternate Channel Address Pointer 0 32 UDMAALTCLR DMA Channel Primary Alternate Clear 0x34 write-only n 0x0 0x0 UDMA_ALTCLR_CLR Channel [n] Alternate Clear 0 32 write-only UDMAALTSET DMA Channel Primary Alternate Set 0x30 read-write n 0x0 0x0 UDMA_ALTSET_SET Channel [n] Alternate Set 0 32 UDMACFG DMA Configuration 0x4 write-only n 0x0 0x0 UDMA_CFG_MASTEN Controller Master Enable 0 1 write-only UDMACHASGN DMA Channel Assignment 0x500 read-write n 0x0 0x0 UDMA_CHASGN Channel [n] Assignment Select 0 32 UDMA_CHASGN_PRIMARY Use the primary channel assignment 0x0 UDMA_CHASGN_SECONDARY Use the secondary channel assignment 0x1 UDMACHMAP0 DMA Channel Map Select 0 0x510 read-write n 0x0 0x0 UDMA_CHMAP0_CH0SEL uDMA Channel 0 Source Select 0 4 UDMA_CHMAP0_CH1SEL uDMA Channel 1 Source Select 4 8 UDMA_CHMAP0_CH2SEL uDMA Channel 2 Source Select 8 12 UDMA_CHMAP0_CH3SEL uDMA Channel 3 Source Select 12 16 UDMA_CHMAP0_CH4SEL uDMA Channel 4 Source Select 16 20 UDMA_CHMAP0_CH5SEL uDMA Channel 5 Source Select 20 24 UDMA_CHMAP0_CH6SEL uDMA Channel 6 Source Select 24 28 UDMA_CHMAP0_CH7SEL uDMA Channel 7 Source Select 28 32 UDMACHMAP1 DMA Channel Map Select 1 0x514 read-write n 0x0 0x0 UDMA_CHMAP1_CH10SEL uDMA Channel 10 Source Select 8 12 UDMA_CHMAP1_CH11SEL uDMA Channel 11 Source Select 12 16 UDMA_CHMAP1_CH12SEL uDMA Channel 12 Source Select 16 20 UDMA_CHMAP1_CH13SEL uDMA Channel 13 Source Select 20 24 UDMA_CHMAP1_CH14SEL uDMA Channel 14 Source Select 24 28 UDMA_CHMAP1_CH15SEL uDMA Channel 15 Source Select 28 32 UDMA_CHMAP1_CH8SEL uDMA Channel 8 Source Select 0 4 UDMA_CHMAP1_CH9SEL uDMA Channel 9 Source Select 4 8 UDMACHMAP2 DMA Channel Map Select 2 0x518 read-write n 0x0 0x0 UDMA_CHMAP2_CH16SEL uDMA Channel 16 Source Select 0 4 UDMA_CHMAP2_CH17SEL uDMA Channel 17 Source Select 4 8 UDMA_CHMAP2_CH18SEL uDMA Channel 18 Source Select 8 12 UDMA_CHMAP2_CH19SEL uDMA Channel 19 Source Select 12 16 UDMA_CHMAP2_CH20SEL uDMA Channel 20 Source Select 16 20 UDMA_CHMAP2_CH21SEL uDMA Channel 21 Source Select 20 24 UDMA_CHMAP2_CH22SEL uDMA Channel 22 Source Select 24 28 UDMA_CHMAP2_CH23SEL uDMA Channel 23 Source Select 28 32 UDMACHMAP3 DMA Channel Map Select 3 0x51C read-write n 0x0 0x0 UDMA_CHMAP3_CH24SEL uDMA Channel 24 Source Select 0 4 UDMA_CHMAP3_CH25SEL uDMA Channel 25 Source Select 4 8 UDMA_CHMAP3_CH26SEL uDMA Channel 26 Source Select 8 12 UDMA_CHMAP3_CH27SEL uDMA Channel 27 Source Select 12 16 UDMA_CHMAP3_CH28SEL uDMA Channel 28 Source Select 16 20 UDMA_CHMAP3_CH29SEL uDMA Channel 29 Source Select 20 24 UDMA_CHMAP3_CH30SEL uDMA Channel 30 Source Select 24 28 UDMA_CHMAP3_CH31SEL uDMA Channel 31 Source Select 28 32 UDMACTLBASE DMA Channel Control Base Pointer 0x8 read-write n 0x0 0x0 UDMA_CTLBASE_ADDR Channel Control Base Address 10 32 UDMAENACLR DMA Channel Enable Clear 0x2C write-only n 0x0 0x0 UDMA_ENACLR_CLR Clear Channel [n] Enable Clear 0 32 write-only UDMAENASET DMA Channel Enable Set 0x28 read-write n 0x0 0x0 UDMA_ENASET_SET Channel [n] Enable Set 0 32 UDMAERRCLR DMA Bus Error Clear 0x4C read-write n 0x0 0x0 UDMA_ERRCLR_ERRCLR uDMA Bus Error Status 0 1 UDMAPRIOCLR DMA Channel Priority Clear 0x3C write-only n 0x0 0x0 UDMA_PRIOCLR_CLR Channel [n] Priority Clear 0 32 write-only UDMAPRIOSET DMA Channel Priority Set 0x38 read-write n 0x0 0x0 UDMA_PRIOSET_SET Channel [n] Priority Set 0 32 UDMAREQMASKCLR DMA Channel Request Mask Clear 0x24 write-only n 0x0 0x0 UDMA_REQMASKCLR_CLR Channel [n] Request Mask Clear 0 32 write-only UDMAREQMASKSET DMA Channel Request Mask Set 0x20 read-write n 0x0 0x0 UDMA_REQMASKSET_SET Channel [n] Request Mask Set 0 32 UDMASTAT DMA Status 0x0 read-write n 0x0 0x0 UDMA_STAT_DMACHANS Available uDMA Channels Minus 1 16 21 UDMA_STAT_MASTEN Master Enable Status 0 1 UDMA_STAT_STATE Control State Machine Status 4 8 UDMA_STAT_STATE_IDLE Idle 0x0 UDMA_STAT_STATE_RD_CTRL Reading channel controller data 0x1 UDMA_STAT_STATE_RD_SRCENDP Reading source end pointer 0x2 UDMA_STAT_STATE_RD_DSTENDP Reading destination end pointer 0x3 UDMA_STAT_STATE_RD_SRCDAT Reading source data 0x4 UDMA_STAT_STATE_WR_DSTDAT Writing destination data 0x5 UDMA_STAT_STATE_WAIT Waiting for uDMA request to clear 0x6 UDMA_STAT_STATE_WR_CTRL Writing channel controller data 0x7 UDMA_STAT_STATE_STALL Stalled 0x8 UDMA_STAT_STATE_DONE Done 0x9 UDMA_STAT_STATE_UNDEF Undefined 0xa UDMASWREQ DMA Channel Software Request 0x14 write-only n 0x0 0x0 UDMA_SWREQ Channel [n] Software Request 0 32 write-only UDMAUSEBURSTCLR DMA Channel Useburst Clear 0x1C write-only n 0x0 0x0 UDMA_USEBURSTCLR_CLR Channel [n] Useburst Clear 0 32 write-only UDMAUSEBURSTSET DMA Channel Useburst Set 0x18 read-write n 0x0 0x0 UDMA_USEBURSTSET_SET Channel [n] Useburst Set 0 32 UDMAWAITSTAT DMA Channel Wait-on-Request Status 0x10 read-write n 0x0 0x0 UDMA_WAITSTAT_WAITREQ Channel [n] Wait Status 0 32 USEBURSTCLR DMA Channel Useburst Clear 0x1C -1 write-only n 0x0 0x0 UDMA_USEBURSTCLR_CLR Channel [n] Useburst Clear 0 32 write-only USEBURSTSET DMA Channel Useburst Set 0x18 -1 read-write n 0x0 0x0 UDMA_USEBURSTSET_SET Channel [n] Useburst Set 0 32 WAITSTAT DMA Channel Wait-on-Request Status 0x10 -1 read-write n 0x0 0x0 UDMA_WAITSTAT_WAITREQ Channel [n] Wait Status 0 32 USB0 Register map for USB0 peripheral USB 0x0 0x0 0x1000 registers n USB0 42 CC USB Clock Configuration 0xFC8 -1 read-write n 0x0 0x0 USB_CC_CLKDIV PLL Clock Divisor 0 4 USB_CC_CLKEN USB Clock Enable 9 10 USB_CC_CSD Clock Source/Direction 8 9 CCONF USB Common Configuration 0x61 8 read-write n 0x0 0x0 USB_CCONF_RXEDMA TX Early DMA Enable 0 1 USB_CCONF_TXEDMA TX Early DMA Enable 1 2 CONTIM USB Connect Timing 0x7A 8 read-write n 0x0 0x0 USB_CONTIM_WTCON Connect Wait 4 8 USB_CONTIM_WTID Wait ID 0 4 COUNT0 USB Receive Byte Count Endpoint 0 0x108 8 read-write n 0x0 0x0 USB_COUNT0_COUNT FIFO Count 0 7 CSRH0 USB Control and Status Endpoint 0 High 0x103 8 write-only n 0x0 0x0 USB_CSRH0_DISPING PING Disable 3 4 write-only USB_CSRH0_DT Data Toggle 1 2 write-only USB_CSRH0_DTWE Data Toggle Write Enable 2 3 write-only USB_CSRH0_FLUSH Flush FIFO 0 1 write-only CSRL0 USB Control and Status Endpoint 0 Low 0x102 8 write-only n 0x0 0x0 USB_CSRL0_DATAEND Data End 3 4 write-only USB_CSRL0_ERROR Error 4 5 write-only USB_CSRL0_NAKTO NAK Timeout 7 8 write-only USB_CSRL0_REQPKT Request Packet 5 6 write-only USB_CSRL0_RXRDY Receive Packet Ready 0 1 write-only USB_CSRL0_RXRDYC RXRDY Clear 6 7 write-only USB_CSRL0_SETEND Setup End 4 5 write-only USB_CSRL0_SETENDC Setup End Clear 7 8 write-only USB_CSRL0_SETUP Setup Packet 3 4 write-only USB_CSRL0_STALL Send Stall 5 6 write-only USB_CSRL0_STALLED Endpoint Stalled 2 3 write-only USB_CSRL0_STATUS STATUS Packet 6 7 write-only USB_CSRL0_TXRDY Transmit Packet Ready 1 2 write-only CTO USB Chirp Timeout 0x344 16 read-write n 0x0 0x0 USB_CTO_CCTV Configurable Chirp Timeout Value 0 16 DEVCTL USB Device Control 0x60 8 read-write n 0x0 0x0 USB_DEVCTL_DEV Device Mode (OTG only) 7 8 USB_DEVCTL_FSDEV Full-Speed Device Detected 6 7 USB_DEVCTL_HOST Host Mode 2 3 USB_DEVCTL_HOSTREQ Host Request (OTG only) 1 2 USB_DEVCTL_LSDEV Low-Speed Device Detected 5 6 USB_DEVCTL_SESSION Session Start/End (OTG only) 0 1 USB_DEVCTL_VBUS VBUS Level (OTG only) 3 5 USB_DEVCTL_VBUS_NONE Below SessionEnd 0x0 USB_DEVCTL_VBUS_SEND Above SessionEnd, below AValid 0x1 USB_DEVCTL_VBUS_AVALID Above AValid, below VBUSValid 0x2 USB_DEVCTL_VBUS_VALID Above VBUSValid 0x3 DMAADDR0 USB DMA Address 0 0x208 -1 read-write n 0x0 0x0 USB_DMAADDR0_ADDR DMA Address 2 32 DMAADDR1 USB DMA Address 1 0x218 -1 read-write n 0x0 0x0 USB_DMAADDR1_ADDR DMA Address 2 32 DMAADDR2 USB DMA Address 2 0x228 -1 read-write n 0x0 0x0 USB_DMAADDR2_ADDR DMA Address 2 32 DMAADDR3 USB DMA Address 3 0x238 -1 read-write n 0x0 0x0 USB_DMAADDR3_ADDR DMA Address 2 32 DMAADDR4 USB DMA Address 4 0x248 -1 read-write n 0x0 0x0 USB_DMAADDR4_ADDR DMA Address 2 32 DMAADDR5 USB DMA Address 5 0x258 -1 read-write n 0x0 0x0 USB_DMAADDR5_ADDR DMA Address 2 32 DMAADDR6 USB DMA Address 6 0x268 -1 read-write n 0x0 0x0 USB_DMAADDR6_ADDR DMA Address 2 32 DMAADDR7 USB DMA Address 7 0x278 -1 read-write n 0x0 0x0 USB_DMAADDR7_ADDR DMA Address 2 32 DMACOUNT0 USB DMA Count 0 0x20C -1 read-write n 0x0 0x0 USB_DMACOUNT0_COUNT DMA Count 2 32 DMACOUNT1 USB DMA Count 1 0x21C -1 read-write n 0x0 0x0 USB_DMACOUNT1_COUNT DMA Count 2 32 DMACOUNT2 USB DMA Count 2 0x22C -1 read-write n 0x0 0x0 USB_DMACOUNT2_COUNT DMA Count 2 32 DMACOUNT3 USB DMA Count 3 0x23C -1 read-write n 0x0 0x0 USB_DMACOUNT3_COUNT DMA Count 2 32 DMACOUNT4 USB DMA Count 4 0x24C -1 read-write n 0x0 0x0 USB_DMACOUNT4_COUNT DMA Count 2 32 DMACOUNT5 USB DMA Count 5 0x25C -1 read-write n 0x0 0x0 USB_DMACOUNT5_COUNT DMA Count 2 32 DMACOUNT6 USB DMA Count 6 0x26C -1 read-write n 0x0 0x0 USB_DMACOUNT6_COUNT DMA Count 2 32 DMACOUNT7 USB DMA Count 7 0x27C -1 read-write n 0x0 0x0 USB_DMACOUNT7_COUNT DMA Count 2 32 DMACTL0 USB DMA Control 0 0x204 16 read-write n 0x0 0x0 USB_DMACTL0_BRSTM Burst Mode 9 11 USB_DMACTL0_BRSTM_ANY Bursts of unspecified length 0x0 USB_DMACTL0_BRSTM_INC4 INCR4 or unspecified length 0x1 USB_DMACTL0_BRSTM_INC8 INCR8, INCR4 or unspecified length 0x2 USB_DMACTL0_BRSTM_INC16 INCR16, INCR8, INCR4 or unspecified length 0x3 USB_DMACTL0_DIR DMA Direction 1 2 USB_DMACTL0_ENABLE DMA Transfer Enable 0 1 USB_DMACTL0_EP Endpoint number 4 8 USB_DMACTL0_ERR Bus Error Bit 8 9 USB_DMACTL0_IE DMA Interrupt Enable 3 4 USB_DMACTL0_MODE DMA Transfer Mode 2 3 DMACTL1 USB DMA Control 1 0x214 16 read-write n 0x0 0x0 USB_DMACTL1_BRSTM Burst Mode 9 11 USB_DMACTL1_BRSTM_ANY Bursts of unspecified length 0x0 USB_DMACTL1_BRSTM_INC4 INCR4 or unspecified length 0x1 USB_DMACTL1_BRSTM_INC8 INCR8, INCR4 or unspecified length 0x2 USB_DMACTL1_BRSTM_INC16 INCR16, INCR8, INCR4 or unspecified length 0x3 USB_DMACTL1_DIR DMA Direction 1 2 USB_DMACTL1_ENABLE DMA Transfer Enable 0 1 USB_DMACTL1_EP Endpoint number 4 8 USB_DMACTL1_ERR Bus Error Bit 8 9 USB_DMACTL1_IE DMA Interrupt Enable 3 4 USB_DMACTL1_MODE DMA Transfer Mode 2 3 DMACTL2 USB DMA Control 2 0x224 16 read-write n 0x0 0x0 USB_DMACTL2_BRSTM Burst Mode 9 11 USB_DMACTL2_BRSTM_ANY Bursts of unspecified length 0x0 USB_DMACTL2_BRSTM_INC4 INCR4 or unspecified length 0x1 USB_DMACTL2_BRSTM_INC8 INCR8, INCR4 or unspecified length 0x2 USB_DMACTL2_BRSTM_INC16 INCR16, INCR8, INCR4 or unspecified length 0x3 USB_DMACTL2_DIR DMA Direction 1 2 USB_DMACTL2_ENABLE DMA Transfer Enable 0 1 USB_DMACTL2_EP Endpoint number 4 8 USB_DMACTL2_ERR Bus Error Bit 8 9 USB_DMACTL2_IE DMA Interrupt Enable 3 4 USB_DMACTL2_MODE DMA Transfer Mode 2 3 DMACTL3 USB DMA Control 3 0x234 16 read-write n 0x0 0x0 USB_DMACTL3_BRSTM Burst Mode 9 11 USB_DMACTL3_BRSTM_ANY Bursts of unspecified length 0x0 USB_DMACTL3_BRSTM_INC4 INCR4 or unspecified length 0x1 USB_DMACTL3_BRSTM_INC8 INCR8, INCR4 or unspecified length 0x2 USB_DMACTL3_BRSTM_INC16 INCR16, INCR8, INCR4 or unspecified length 0x3 USB_DMACTL3_DIR DMA Direction 1 2 USB_DMACTL3_ENABLE DMA Transfer Enable 0 1 USB_DMACTL3_EP Endpoint number 4 8 USB_DMACTL3_ERR Bus Error Bit 8 9 USB_DMACTL3_IE DMA Interrupt Enable 3 4 USB_DMACTL3_MODE DMA Transfer Mode 2 3 DMACTL4 USB DMA Control 4 0x244 16 read-write n 0x0 0x0 USB_DMACTL4_BRSTM Burst Mode 9 11 USB_DMACTL4_BRSTM_ANY Bursts of unspecified length 0x0 USB_DMACTL4_BRSTM_INC4 INCR4 or unspecified length 0x1 USB_DMACTL4_BRSTM_INC8 INCR8, INCR4 or unspecified length 0x2 USB_DMACTL4_BRSTM_INC16 INCR16, INCR8, INCR4 or unspecified length 0x3 USB_DMACTL4_DIR DMA Direction 1 2 USB_DMACTL4_ENABLE DMA Transfer Enable 0 1 USB_DMACTL4_EP Endpoint number 4 8 USB_DMACTL4_ERR Bus Error Bit 8 9 USB_DMACTL4_IE DMA Interrupt Enable 3 4 USB_DMACTL4_MODE DMA Transfer Mode 2 3 DMACTL5 USB DMA Control 5 0x254 16 read-write n 0x0 0x0 USB_DMACTL5_BRSTM Burst Mode 9 11 USB_DMACTL5_BRSTM_ANY Bursts of unspecified length 0x0 USB_DMACTL5_BRSTM_INC4 INCR4 or unspecified length 0x1 USB_DMACTL5_BRSTM_INC8 INCR8, INCR4 or unspecified length 0x2 USB_DMACTL5_BRSTM_INC16 INCR16, INCR8, INCR4 or unspecified length 0x3 USB_DMACTL5_DIR DMA Direction 1 2 USB_DMACTL5_ENABLE DMA Transfer Enable 0 1 USB_DMACTL5_EP Endpoint number 4 8 USB_DMACTL5_ERR Bus Error Bit 8 9 USB_DMACTL5_IE DMA Interrupt Enable 3 4 USB_DMACTL5_MODE DMA Transfer Mode 2 3 DMACTL6 USB DMA Control 6 0x264 16 read-write n 0x0 0x0 USB_DMACTL6_BRSTM Burst Mode 9 11 USB_DMACTL6_BRSTM_ANY Bursts of unspecified length 0x0 USB_DMACTL6_BRSTM_INC4 INCR4 or unspecified length 0x1 USB_DMACTL6_BRSTM_INC8 INCR8, INCR4 or unspecified length 0x2 USB_DMACTL6_BRSTM_INC16 INCR16, INCR8, INCR4 or unspecified length 0x3 USB_DMACTL6_DIR DMA Direction 1 2 USB_DMACTL6_ENABLE DMA Transfer Enable 0 1 USB_DMACTL6_EP Endpoint number 4 8 USB_DMACTL6_ERR Bus Error Bit 8 9 USB_DMACTL6_IE DMA Interrupt Enable 3 4 USB_DMACTL6_MODE DMA Transfer Mode 2 3 DMACTL7 USB DMA Control 7 0x274 16 read-write n 0x0 0x0 USB_DMACTL7_BRSTM Burst Mode 9 11 USB_DMACTL7_BRSTM_ANY Bursts of unspecified length 0x0 USB_DMACTL7_BRSTM_INC4 INCR4 or unspecified length 0x1 USB_DMACTL7_BRSTM_INC8 INCR8, INCR4 or unspecified length 0x2 USB_DMACTL7_BRSTM_INC16 INCR16, INCR8, INCR4 or unspecified length 0x3 USB_DMACTL7_DIR DMA Direction 1 2 USB_DMACTL7_ENABLE DMA Transfer Enable 0 1 USB_DMACTL7_EP Endpoint number 4 8 USB_DMACTL7_ERR Bus Error Bit 8 9 USB_DMACTL7_IE DMA Interrupt Enable 3 4 USB_DMACTL7_MODE DMA Transfer Mode 2 3 DMAINTR USB DMA Interrupt 0x200 8 read-write n 0x0 0x0 USB_DMAINTR_CH0 Channel 0 DMA Interrupt 0 1 USB_DMAINTR_CH1 Channel 1 DMA Interrupt 1 2 USB_DMAINTR_CH2 Channel 2 DMA Interrupt 2 3 USB_DMAINTR_CH3 Channel 3 DMA Interrupt 3 4 USB_DMAINTR_CH4 Channel 4 DMA Interrupt 4 5 USB_DMAINTR_CH5 Channel 5 DMA Interrupt 5 6 USB_DMAINTR_CH6 Channel 6 DMA Interrupt 6 7 USB_DMAINTR_CH7 Channel 7 DMA Interrupt 7 8 DRIM USB Device RESUME Interrupt Mask 0x414 -1 read-write n 0x0 0x0 USB_DRIM_RESUME RESUME Interrupt Mask 0 1 DRISC USB Device RESUME Interrupt Status and Clear 0x418 -1 write-only n 0x0 0x0 USB_DRISC_RESUME RESUME Interrupt Status and Clear 0 1 write-only DRRIS USB Device RESUME Raw Interrupt Status 0x410 -1 read-write n 0x0 0x0 USB_DRRIS_RESUME RESUME Interrupt Status 0 1 EPC USB External Power Control 0x400 -1 read-write n 0x0 0x0 USB_EPC_EPEN External Power Supply Enable Configuration 0 2 USB_EPC_EPEN_LOW Power Enable Active Low 0x0 USB_EPC_EPEN_HIGH Power Enable Active High 0x1 USB_EPC_EPEN_VBLOW Power Enable High if VBUS Low (OTG only) 0x2 USB_EPC_EPEN_VBHIGH Power Enable High if VBUS High (OTG only) 0x3 USB_EPC_EPENDE EPEN Drive Enable 2 3 USB_EPC_PFLTACT Power Fault Action 8 10 USB_EPC_PFLTACT_UNCHG Unchanged 0x0 USB_EPC_PFLTACT_TRIS Tristate 0x1 USB_EPC_PFLTACT_LOW Low 0x2 USB_EPC_PFLTACT_HIGH High 0x3 USB_EPC_PFLTAEN Power Fault Action Enable 6 7 USB_EPC_PFLTEN Power Fault Input Enable 4 5 USB_EPC_PFLTSEN_HIGH Power Fault Sense 5 6 EPCIM USB External Power Control Interrupt Mask 0x408 -1 read-write n 0x0 0x0 USB_EPCIM_PF USB Power Fault Interrupt Mask 0 1 EPCISC USB External Power Control Interrupt Status and Clear 0x40C -1 read-write n 0x0 0x0 USB_EPCISC_PF USB Power Fault Interrupt Status and Clear 0 1 EPCRIS USB External Power Control Raw Interrupt Status 0x404 -1 read-write n 0x0 0x0 USB_EPCRIS_PF USB Power Fault Interrupt Status 0 1 EPIDX USB Endpoint Index 0xE 8 read-write n 0x0 0x0 USB_EPIDX_EPIDX Endpoint Index 0 4 EPINFO USB Endpoint Information 0x78 8 read-write n 0x0 0x0 USB_EPINFO_RXEP RX Endpoints 4 8 USB_EPINFO_TXEP TX Endpoints 0 4 FADDR USB Device Functional Address 0x0 8 read-write n 0x0 0x0 USB_FADDR Function Address 0 7 FIFO0 USB FIFO Endpoint 0 0x20 -1 read-write n 0x0 0x0 USB_FIFO0_EPDATA Endpoint Data 0 32 FIFO1 USB FIFO Endpoint 1 0x24 -1 read-write n 0x0 0x0 USB_FIFO1_EPDATA Endpoint Data 0 32 FIFO2 USB FIFO Endpoint 2 0x28 -1 read-write n 0x0 0x0 USB_FIFO2_EPDATA Endpoint Data 0 32 FIFO3 USB FIFO Endpoint 3 0x2C -1 read-write n 0x0 0x0 USB_FIFO3_EPDATA Endpoint Data 0 32 FIFO4 USB FIFO Endpoint 4 0x30 -1 read-write n 0x0 0x0 USB_FIFO4_EPDATA Endpoint Data 0 32 FIFO5 USB FIFO Endpoint 5 0x34 -1 read-write n 0x0 0x0 USB_FIFO5_EPDATA Endpoint Data 0 32 FIFO6 USB FIFO Endpoint 6 0x38 -1 read-write n 0x0 0x0 USB_FIFO6_EPDATA Endpoint Data 0 32 FIFO7 USB FIFO Endpoint 7 0x3C -1 read-write n 0x0 0x0 USB_FIFO7_EPDATA Endpoint Data 0 32 FRAME USB Frame Value 0xC 16 read-write n 0x0 0x0 USB_FRAME Frame Number 0 11 FSEOF USB Full-Speed Last Transaction to End of Frame Timing 0x7D 8 read-write n 0x0 0x0 USB_FSEOF_FSEOFG Full-Speed End-of-Frame Gap 0 8 GPCS USB General-Purpose Control and Status 0x41C -1 read-write n 0x0 0x0 USB_GPCS_DEVMOD Device Mode 0 3 USB_GPCS_DEVMOD_OTG Use USB0VBUS and USB0ID pin 0x0 USB_GPCS_DEVMOD_HOST Force USB0VBUS and USB0ID low 0x2 USB_GPCS_DEVMOD_DEV Force USB0VBUS and USB0ID high 0x3 USB_GPCS_DEVMOD_HOSTVBUS Use USB0VBUS and force USB0ID low 0x4 USB_GPCS_DEVMOD_DEVVBUS Use USB0VBUS and force USB0ID high 0x5 HHSRTN USB High Speed to UTM Operating Delay 0x346 16 read-write n 0x0 0x0 USB_HHSRTN_HHSRTN HIgh Speed to UTM Operating Delay 0 16 HSBT USB High Speed Time-out Adder 0x348 16 read-write n 0x0 0x0 USB_HSBT_HSBT High Speed Timeout Adder 0 4 HSEOF USB High-Speed Last Transaction to End of Frame Timing 0x7C 8 read-write n 0x0 0x0 USB_HSEOF_HSEOFG HIgh-Speed End-of-Frame Gap 0 8 IE USB Interrupt Enable 0xB 8 read-write n 0x0 0x0 USB_IE_BABBLE Enable Babble Interrupt 2 3 USB_IE_CONN Enable Connect Interrupt 4 5 USB_IE_DISCON Enable Disconnect Interrupt 5 6 USB_IE_RESET Enable RESET Interrupt 2 3 USB_IE_RESUME Enable RESUME Interrupt 1 2 USB_IE_SESREQ Enable Session Request (OTG only) 6 7 USB_IE_SOF Enable Start-of-Frame Interrupt 3 4 USB_IE_SUSPND Enable SUSPEND Interrupt 0 1 USB_IE_VBUSERR Enable VBUS Error Interrupt (OTG only) 7 8 IS USB General Interrupt Status 0xA 8 read-write n 0x0 0x0 USB_IS_BABBLE Babble Detected 2 3 USB_IS_CONN Session Connect 4 5 USB_IS_DISCON Session Disconnect (OTG only) 5 6 USB_IS_RESET RESET Signaling Detected 2 3 USB_IS_RESUME RESUME Signaling Detected 1 2 USB_IS_SESREQ SESSION REQUEST (OTG only) 6 7 USB_IS_SOF Start of Frame 3 4 USB_IS_SUSPEND SUSPEND Signaling Detected 0 1 USB_IS_VBUSERR VBUS Error (OTG only) 7 8 LPMATTR USB LPM Attributes 0x360 16 read-write n 0x0 0x0 USB_LPMATTR_ENDPT Endpoint 12 16 USB_LPMATTR_HIRD Host Initiated Resume Duration 4 8 USB_LPMATTR_LS Link State 0 4 USB_LPMATTR_LS_L1 Sleep State (L1) 0x1 USB_LPMATTR_RMTWAK Remote Wake 8 9 LPMCNTRL USB LPM Control 0x362 8 read-write n 0x0 0x0 USB_LPMCNTRL_EN LPM Enable 2 4 USB_LPMCNTRL_EN_NONE LPM and Extended transactions are not supported. In this case, the USB does not respond to LPM transactions and LPM transactions cause a timeout 0x0 USB_LPMCNTRL_EN_EXT LPM is not supported but extended transactions are supported. In this case, the USB does respond to an LPM transaction with a STALL 0x1 USB_LPMCNTRL_EN_LPMEXT The USB supports LPM extended transactions. In this case, the USB responds with a NYET or an ACK as determined by the value of TXLPM and other conditions 0x3 USB_LPMCNTRL_NAK LPM NAK 4 5 USB_LPMCNTRL_RES LPM Resume 1 2 USB_LPMCNTRL_TXLPM Transmit LPM Transaction Enable 0 1 LPMFADDR USB LPM Function Address 0x365 8 read-write n 0x0 0x0 USB_LPMFADDR_ADDR LPM Function Address 0 7 LPMIM USB LPM Interrupt Mask 0x363 8 read-write n 0x0 0x0 USB_LPMIM_ACK LPM ACK Interrupt Mask 2 3 USB_LPMIM_ERR LPM Error Interrupt Mask 5 6 USB_LPMIM_NC LPM NC Interrupt Mask 3 4 USB_LPMIM_NY LPM NY Interrupt Mask 1 2 USB_LPMIM_RES LPM Resume Interrupt Mask 4 5 USB_LPMIM_STALL LPM STALL Interrupt Mask 0 1 LPMRIS USB LPM Raw Interrupt Status 0x364 8 read-write n 0x0 0x0 USB_LPMRIS_ACK LPM ACK Interrupt Status 2 3 USB_LPMRIS_ERR LPM Interrupt Status 5 6 USB_LPMRIS_LPMST LPM STALL Interrupt Status 0 1 USB_LPMRIS_NC LPM NC Interrupt Status 3 4 USB_LPMRIS_NY LPM NY Interrupt Status 1 2 USB_LPMRIS_RES LPM Resume Interrupt Status 4 5 LSEOF USB Low-Speed Last Transaction to End of Frame Timing 0x7E 8 read-write n 0x0 0x0 USB_LSEOF_LSEOFG Low-Speed End-of-Frame Gap 0 8 NAKLMT USB NAK Limit 0x10B 8 read-write n 0x0 0x0 USB_NAKLMT_NAKLMT EP0 NAK Limit 0 5 PC USB Peripheral Configuration 0xFC4 -1 read-write n 0x0 0x0 USB_PC_ULPIEN ULPI Enable 16 17 POWER USB Power 0x1 8 read-write n 0x0 0x0 USB_POWER_HSENAB High Speed Enable 5 6 USB_POWER_HSMODE High Speed Enable 4 5 USB_POWER_ISOUP Isochronous Update 7 8 USB_POWER_PWRDNPHY Power Down PHY 0 1 USB_POWER_RESET RESET Signaling 3 4 USB_POWER_RESUME RESUME Signaling 2 3 USB_POWER_SOFTCONN Soft Connect/Disconnect 6 7 USB_POWER_SUSPEND SUSPEND Mode 1 2 PP USB Peripheral Properties 0xFC0 -1 read-write n 0x0 0x0 USB_PP_ECNT Endpoint Count 8 16 USB_PP_PHY PHY Present 4 5 USB_PP_TYPE Controller Type 0 4 USB_PP_TYPE_0 The first-generation USB controller 0x0 USB_PP_TYPE_1 Second-generation USB controller.The controller implemented in post Icestorm devices that use the 3.0 version of the Mentor controller 0x1 USB_PP_ULPI ULPI Present 5 6 USB_PP_USB USB Capability 6 8 USB_PP_USB_DEVICE DEVICE 0x1 USB_PP_USB_HOSTDEVICE HOST 0x2 USB_PP_USB_OTG OTG 0x3 RAMINFO USB RAM Information 0x79 8 read-write n 0x0 0x0 USB_RAMINFO_DMACHAN DMA Channels 4 8 USB_RAMINFO_RAMBITS RAM Address Bus Width 0 4 RQPKTCOUNT1 USB Request Packet Count in Block Transfer Endpoint 1 0x304 16 read-write n 0x0 0x0 USB_RQPKTCOUNT1 Block Transfer Packet Count 0 16 RQPKTCOUNT2 USB Request Packet Count in Block Transfer Endpoint 2 0x308 16 read-write n 0x0 0x0 USB_RQPKTCOUNT2 Block Transfer Packet Count 0 16 RQPKTCOUNT3 USB Request Packet Count in Block Transfer Endpoint 3 0x30C 16 read-write n 0x0 0x0 USB_RQPKTCOUNT3 Block Transfer Packet Count 0 16 RQPKTCOUNT4 USB Request Packet Count in Block Transfer Endpoint 4 0x310 16 read-write n 0x0 0x0 USB_RQPKTCOUNT4_COUNT Block Transfer Packet Count 0 16 RQPKTCOUNT5 USB Request Packet Count in Block Transfer Endpoint 5 0x314 16 read-write n 0x0 0x0 USB_RQPKTCOUNT5_COUNT Block Transfer Packet Count 0 16 RQPKTCOUNT6 USB Request Packet Count in Block Transfer Endpoint 6 0x318 16 read-write n 0x0 0x0 USB_RQPKTCOUNT6_COUNT Block Transfer Packet Count 0 16 RQPKTCOUNT7 USB Request Packet Count in Block Transfer Endpoint 7 0x31C 16 read-write n 0x0 0x0 USB_RQPKTCOUNT7_COUNT Block Transfer Packet Count 0 16 RXCOUNT1 USB Receive Byte Count Endpoint 1 0x118 16 read-write n 0x0 0x0 USB_RXCOUNT1_COUNT Receive Packet Count 0 13 RXCOUNT2 USB Receive Byte Count Endpoint 2 0x128 16 read-write n 0x0 0x0 USB_RXCOUNT2_COUNT Receive Packet Count 0 13 RXCOUNT3 USB Receive Byte Count Endpoint 3 0x138 16 read-write n 0x0 0x0 USB_RXCOUNT3_COUNT Receive Packet Count 0 13 RXCOUNT4 USB Receive Byte Count Endpoint 4 0x148 16 read-write n 0x0 0x0 USB_RXCOUNT4_COUNT Receive Packet Count 0 13 RXCOUNT5 USB Receive Byte Count Endpoint 5 0x158 16 read-write n 0x0 0x0 USB_RXCOUNT5_COUNT Receive Packet Count 0 13 RXCOUNT6 USB Receive Byte Count Endpoint 6 0x168 16 read-write n 0x0 0x0 USB_RXCOUNT6_COUNT Receive Packet Count 0 13 RXCOUNT7 USB Receive Byte Count Endpoint 7 0x178 16 read-write n 0x0 0x0 USB_RXCOUNT7_COUNT Receive Packet Count 0 13 RXCSRH1 USB Receive Control and Status Endpoint 1 High 0x117 8 read-write n 0x0 0x0 USB_RXCSRH1_AUTOCL Auto Clear 7 8 USB_RXCSRH1_AUTORQ Auto Request 6 7 USB_RXCSRH1_DISNYET Disable NYET 4 5 USB_RXCSRH1_DMAEN DMA Request Enable 5 6 USB_RXCSRH1_DMAMOD DMA Request Mode 3 4 USB_RXCSRH1_DT Data Toggle 1 2 USB_RXCSRH1_DTWE Data Toggle Write Enable 2 3 USB_RXCSRH1_INCOMPRX Incomplete RX Transmission Status 0 1 USB_RXCSRH1_ISO Isochronous Transfers 6 7 USB_RXCSRH1_PIDERR PID Error 4 5 RXCSRH2 USB Receive Control and Status Endpoint 2 High 0x127 8 read-write n 0x0 0x0 USB_RXCSRH2_AUTOCL Auto Clear 7 8 USB_RXCSRH2_AUTORQ Auto Request 6 7 USB_RXCSRH2_DISNYET Disable NYET 4 5 USB_RXCSRH2_DMAEN DMA Request Enable 5 6 USB_RXCSRH2_DMAMOD DMA Request Mode 3 4 USB_RXCSRH2_DT Data Toggle 1 2 USB_RXCSRH2_DTWE Data Toggle Write Enable 2 3 USB_RXCSRH2_INCOMPRX Incomplete RX Transmission Status 0 1 USB_RXCSRH2_ISO Isochronous Transfers 6 7 USB_RXCSRH2_PIDERR PID Error 4 5 RXCSRH3 USB Receive Control and Status Endpoint 3 High 0x137 8 read-write n 0x0 0x0 USB_RXCSRH3_AUTOCL Auto Clear 7 8 USB_RXCSRH3_AUTORQ Auto Request 6 7 USB_RXCSRH3_DISNYET Disable NYET 4 5 USB_RXCSRH3_DMAEN DMA Request Enable 5 6 USB_RXCSRH3_DMAMOD DMA Request Mode 3 4 USB_RXCSRH3_DT Data Toggle 1 2 USB_RXCSRH3_DTWE Data Toggle Write Enable 2 3 USB_RXCSRH3_INCOMPRX Incomplete RX Transmission Status 0 1 USB_RXCSRH3_ISO Isochronous Transfers 6 7 USB_RXCSRH3_PIDERR PID Error 4 5 RXCSRH4 USB Receive Control and Status Endpoint 4 High 0x147 8 read-write n 0x0 0x0 USB_RXCSRH4_AUTOCL Auto Clear 7 8 USB_RXCSRH4_AUTORQ Auto Request 6 7 USB_RXCSRH4_DISNYET Disable NYET 4 5 USB_RXCSRH4_DMAEN DMA Request Enable 5 6 USB_RXCSRH4_DMAMOD DMA Request Mode 3 4 USB_RXCSRH4_DT Data Toggle 1 2 USB_RXCSRH4_DTWE Data Toggle Write Enable 2 3 USB_RXCSRH4_INCOMPRX Incomplete RX Transmission Status 0 1 USB_RXCSRH4_ISO Isochronous Transfers 6 7 USB_RXCSRH4_PIDERR PID Error 4 5 RXCSRH5 USB Receive Control and Status Endpoint 5 High 0x157 8 read-write n 0x0 0x0 USB_RXCSRH5_AUTOCL Auto Clear 7 8 USB_RXCSRH5_AUTORQ Auto Request 6 7 USB_RXCSRH5_DISNYET Disable NYET 4 5 USB_RXCSRH5_DMAEN DMA Request Enable 5 6 USB_RXCSRH5_DMAMOD DMA Request Mode 3 4 USB_RXCSRH5_DT Data Toggle 1 2 USB_RXCSRH5_DTWE Data Toggle Write Enable 2 3 USB_RXCSRH5_INCOMPRX Incomplete RX Transmission Status 0 1 USB_RXCSRH5_ISO Isochronous Transfers 6 7 USB_RXCSRH5_PIDERR PID Error 4 5 RXCSRH6 USB Receive Control and Status Endpoint 6 High 0x167 8 read-write n 0x0 0x0 USB_RXCSRH6_AUTOCL Auto Clear 7 8 USB_RXCSRH6_AUTORQ Auto Request 6 7 USB_RXCSRH6_DISNYET Disable NYET 4 5 USB_RXCSRH6_DMAEN DMA Request Enable 5 6 USB_RXCSRH6_DMAMOD DMA Request Mode 3 4 USB_RXCSRH6_DT Data Toggle 1 2 USB_RXCSRH6_DTWE Data Toggle Write Enable 2 3 USB_RXCSRH6_INCOMPRX Incomplete RX Transmission Status 0 1 USB_RXCSRH6_ISO Isochronous Transfers 6 7 USB_RXCSRH6_PIDERR PID Error 4 5 RXCSRH7 USB Receive Control and Status Endpoint 7 High 0x177 8 read-write n 0x0 0x0 USB_RXCSRH7_AUTOCL Auto Clear 7 8 USB_RXCSRH7_AUTORQ Auto Request 6 7 USB_RXCSRH7_DISNYET Disable NYET 4 5 USB_RXCSRH7_DMAEN DMA Request Enable 5 6 USB_RXCSRH7_DMAMOD DMA Request Mode 3 4 USB_RXCSRH7_DT Data Toggle 1 2 USB_RXCSRH7_DTWE Data Toggle Write Enable 2 3 USB_RXCSRH7_INCOMPRX Incomplete RX Transmission Status 0 1 USB_RXCSRH7_ISO Isochronous Transfers 6 7 USB_RXCSRH7_PIDERR PID Error 4 5 RXCSRL1 USB Receive Control and Status Endpoint 1 Low 0x116 8 read-write n 0x0 0x0 USB_RXCSRL1_CLRDT Clear Data Toggle 7 8 USB_RXCSRL1_DATAERR Data Error 3 4 USB_RXCSRL1_ERROR Error 2 3 USB_RXCSRL1_FLUSH Flush FIFO 4 5 USB_RXCSRL1_FULL FIFO Full 1 2 USB_RXCSRL1_NAKTO NAK Timeout 3 4 USB_RXCSRL1_OVER Overrun 2 3 USB_RXCSRL1_REQPKT Request Packet 5 6 USB_RXCSRL1_RXRDY Receive Packet Ready 0 1 USB_RXCSRL1_STALL Send STALL 5 6 USB_RXCSRL1_STALLED Endpoint Stalled 6 7 RXCSRL2 USB Receive Control and Status Endpoint 2 Low 0x126 8 read-write n 0x0 0x0 USB_RXCSRL2_CLRDT Clear Data Toggle 7 8 USB_RXCSRL2_DATAERR Data Error 3 4 USB_RXCSRL2_ERROR Error 2 3 USB_RXCSRL2_FLUSH Flush FIFO 4 5 USB_RXCSRL2_FULL FIFO Full 1 2 USB_RXCSRL2_NAKTO NAK Timeout 3 4 USB_RXCSRL2_OVER Overrun 2 3 USB_RXCSRL2_REQPKT Request Packet 5 6 USB_RXCSRL2_RXRDY Receive Packet Ready 0 1 USB_RXCSRL2_STALL Send STALL 5 6 USB_RXCSRL2_STALLED Endpoint Stalled 6 7 RXCSRL3 USB Receive Control and Status Endpoint 3 Low 0x136 8 read-write n 0x0 0x0 USB_RXCSRL3_CLRDT Clear Data Toggle 7 8 USB_RXCSRL3_DATAERR Data Error 3 4 USB_RXCSRL3_ERROR Error 2 3 USB_RXCSRL3_FLUSH Flush FIFO 4 5 USB_RXCSRL3_FULL FIFO Full 1 2 USB_RXCSRL3_NAKTO NAK Timeout 3 4 USB_RXCSRL3_OVER Overrun 2 3 USB_RXCSRL3_REQPKT Request Packet 5 6 USB_RXCSRL3_RXRDY Receive Packet Ready 0 1 USB_RXCSRL3_STALL Send STALL 5 6 USB_RXCSRL3_STALLED Endpoint Stalled 6 7 RXCSRL4 USB Receive Control and Status Endpoint 4 Low 0x146 8 read-write n 0x0 0x0 USB_RXCSRL4_CLRDT Clear Data Toggle 7 8 USB_RXCSRL4_DATAERR Data Error 3 4 USB_RXCSRL4_ERROR Error 2 3 USB_RXCSRL4_FLUSH Flush FIFO 4 5 USB_RXCSRL4_FULL FIFO Full 1 2 USB_RXCSRL4_NAKTO NAK Timeout 3 4 USB_RXCSRL4_OVER Overrun 2 3 USB_RXCSRL4_REQPKT Request Packet 5 6 USB_RXCSRL4_RXRDY Receive Packet Ready 0 1 USB_RXCSRL4_STALL Send STALL 5 6 USB_RXCSRL4_STALLED Endpoint Stalled 6 7 RXCSRL5 USB Receive Control and Status Endpoint 5 Low 0x156 8 read-write n 0x0 0x0 USB_RXCSRL5_CLRDT Clear Data Toggle 7 8 USB_RXCSRL5_DATAERR Data Error 3 4 USB_RXCSRL5_ERROR Error 2 3 USB_RXCSRL5_FLUSH Flush FIFO 4 5 USB_RXCSRL5_FULL FIFO Full 1 2 USB_RXCSRL5_NAKTO NAK Timeout 3 4 USB_RXCSRL5_OVER Overrun 2 3 USB_RXCSRL5_REQPKT Request Packet 5 6 USB_RXCSRL5_RXRDY Receive Packet Ready 0 1 USB_RXCSRL5_STALL Send STALL 5 6 USB_RXCSRL5_STALLED Endpoint Stalled 6 7 RXCSRL6 USB Receive Control and Status Endpoint 6 Low 0x166 8 read-write n 0x0 0x0 USB_RXCSRL6_CLRDT Clear Data Toggle 7 8 USB_RXCSRL6_DATAERR Data Error 3 4 USB_RXCSRL6_ERROR Error 2 3 USB_RXCSRL6_FLUSH Flush FIFO 4 5 USB_RXCSRL6_FULL FIFO Full 1 2 USB_RXCSRL6_NAKTO NAK Timeout 3 4 USB_RXCSRL6_OVER Overrun 2 3 USB_RXCSRL6_REQPKT Request Packet 5 6 USB_RXCSRL6_RXRDY Receive Packet Ready 0 1 USB_RXCSRL6_STALL Send STALL 5 6 USB_RXCSRL6_STALLED Endpoint Stalled 6 7 RXCSRL7 USB Receive Control and Status Endpoint 7 Low 0x176 8 read-write n 0x0 0x0 USB_RXCSRL7_CLRDT Clear Data Toggle 7 8 USB_RXCSRL7_DATAERR Data Error 3 4 USB_RXCSRL7_ERROR Error 2 3 USB_RXCSRL7_FLUSH Flush FIFO 4 5 USB_RXCSRL7_FULL FIFO Full 1 2 USB_RXCSRL7_NAKTO NAK Timeout 3 4 USB_RXCSRL7_OVER Overrun 2 3 USB_RXCSRL7_REQPKT Request Packet 5 6 USB_RXCSRL7_RXRDY Receive Packet Ready 0 1 USB_RXCSRL7_STALL Send STALL 5 6 USB_RXCSRL7_STALLED Endpoint Stalled 6 7 RXDPKTBUFDIS USB Receive Double Packet Buffer Disable 0x340 16 read-write n 0x0 0x0 USB_RXDPKTBUFDIS_EP1 EP1 RX Double-Packet Buffer Disable 1 2 USB_RXDPKTBUFDIS_EP2 EP2 RX Double-Packet Buffer Disable 2 3 USB_RXDPKTBUFDIS_EP3 EP3 RX Double-Packet Buffer Disable 3 4 USB_RXDPKTBUFDIS_EP4 EP4 RX Double-Packet Buffer Disable 4 5 USB_RXDPKTBUFDIS_EP5 EP5 RX Double-Packet Buffer Disable 5 6 USB_RXDPKTBUFDIS_EP6 EP6 RX Double-Packet Buffer Disable 6 7 USB_RXDPKTBUFDIS_EP7 EP7 RX Double-Packet Buffer Disable 7 8 RXFIFOADD USB Receive FIFO Start Address 0x66 16 read-write n 0x0 0x0 USB_RXFIFOADD_ADDR Transmit/Receive Start Address 0 9 RXFIFOSZ USB Receive Dynamic FIFO Sizing 0x63 8 read-write n 0x0 0x0 USB_RXFIFOSZ_DPB Double Packet Buffer Support 4 5 USB_RXFIFOSZ_SIZE Max Packet Size 0 4 USB_RXFIFOSZ_SIZE_8 8 0x0 USB_RXFIFOSZ_SIZE_16 16 0x1 USB_RXFIFOSZ_SIZE_32 32 0x2 USB_RXFIFOSZ_SIZE_64 64 0x3 USB_RXFIFOSZ_SIZE_128 128 0x4 USB_RXFIFOSZ_SIZE_256 256 0x5 USB_RXFIFOSZ_SIZE_512 512 0x6 USB_RXFIFOSZ_SIZE_1024 1024 0x7 USB_RXFIFOSZ_SIZE_2048 2048 0x8 RXFUNCADDR1 USB Receive Functional Address Endpoint 1 0x8C 8 read-write n 0x0 0x0 USB_RXFUNCADDR1_ADDR Device Address 0 7 RXFUNCADDR2 USB Receive Functional Address Endpoint 2 0x94 8 read-write n 0x0 0x0 USB_RXFUNCADDR2_ADDR Device Address 0 7 RXFUNCADDR3 USB Receive Functional Address Endpoint 3 0x9C 8 read-write n 0x0 0x0 USB_RXFUNCADDR3_ADDR Device Address 0 7 RXFUNCADDR4 USB Receive Functional Address Endpoint 4 0xA4 8 read-write n 0x0 0x0 USB_RXFUNCADDR4_ADDR Device Address 0 7 RXFUNCADDR5 USB Receive Functional Address Endpoint 5 0xAC 8 read-write n 0x0 0x0 USB_RXFUNCADDR5_ADDR Device Address 0 7 RXFUNCADDR6 USB Receive Functional Address Endpoint 6 0xB4 8 read-write n 0x0 0x0 USB_RXFUNCADDR6_ADDR Device Address 0 7 RXFUNCADDR7 USB Receive Functional Address Endpoint 7 0xBC 8 read-write n 0x0 0x0 USB_RXFUNCADDR7_ADDR Device Address 0 7 RXHUBADDR1 USB Receive Hub Address Endpoint 1 0x8E 8 read-write n 0x0 0x0 USB_RXHUBADDR1_ADDR Hub Address 0 7 RXHUBADDR2 USB Receive Hub Address Endpoint 2 0x96 8 read-write n 0x0 0x0 USB_RXHUBADDR2_ADDR Hub Address 0 7 RXHUBADDR3 USB Receive Hub Address Endpoint 3 0x9E 8 read-write n 0x0 0x0 USB_RXHUBADDR3_ADDR Hub Address 0 7 RXHUBADDR4 USB Receive Hub Address Endpoint 4 0xA6 8 read-write n 0x0 0x0 USB_RXHUBADDR4_ADDR Hub Address 0 7 RXHUBADDR5 USB Receive Hub Address Endpoint 5 0xAE 8 read-write n 0x0 0x0 USB_RXHUBADDR5_ADDR Hub Address 0 7 RXHUBADDR6 USB Receive Hub Address Endpoint 6 0xB6 8 read-write n 0x0 0x0 USB_RXHUBADDR6_ADDR Hub Address 0 7 RXHUBADDR7 USB Receive Hub Address Endpoint 7 0xBE 8 read-write n 0x0 0x0 USB_RXHUBADDR7_ADDR Hub Address 0 7 RXHUBPORT1 USB Receive Hub Port Endpoint 1 0x8F 8 read-write n 0x0 0x0 USB_RXHUBPORT1_PORT Hub Port 0 7 RXHUBPORT2 USB Receive Hub Port Endpoint 2 0x97 8 read-write n 0x0 0x0 USB_RXHUBPORT2_PORT Hub Port 0 7 RXHUBPORT3 USB Receive Hub Port Endpoint 3 0x9F 8 read-write n 0x0 0x0 USB_RXHUBPORT3_PORT Hub Port 0 7 RXHUBPORT4 USB Receive Hub Port Endpoint 4 0xA7 8 read-write n 0x0 0x0 USB_RXHUBPORT4_PORT Hub Port 0 7 RXHUBPORT5 USB Receive Hub Port Endpoint 5 0xAF 8 read-write n 0x0 0x0 USB_RXHUBPORT5_PORT Hub Port 0 7 RXHUBPORT6 USB Receive Hub Port Endpoint 6 0xB7 8 read-write n 0x0 0x0 USB_RXHUBPORT6_PORT Hub Port 0 7 RXHUBPORT7 USB Receive Hub Port Endpoint 7 0xBF 8 read-write n 0x0 0x0 USB_RXHUBPORT7_PORT Hub Port 0 7 RXIE USB Receive Interrupt Enable 0x8 16 read-write n 0x0 0x0 USB_RXIE_EP1 RX Endpoint 1 Interrupt Enable 1 2 USB_RXIE_EP2 RX Endpoint 2 Interrupt Enable 2 3 USB_RXIE_EP3 RX Endpoint 3 Interrupt Enable 3 4 USB_RXIE_EP4 RX Endpoint 4 Interrupt Enable 4 5 USB_RXIE_EP5 RX Endpoint 5 Interrupt Enable 5 6 USB_RXIE_EP6 RX Endpoint 6 Interrupt Enable 6 7 USB_RXIE_EP7 RX Endpoint 7 Interrupt Enable 7 8 RXINTERVAL1 USB Host Receive Polling Interval Endpoint 1 0x11D 8 read-write n 0x0 0x0 USB_RXINTERVAL1_NAKLMT NAK Limit 0 8 USB_RXINTERVAL1_TXPOLL RX Polling 0 8 RXINTERVAL2 USB Host Receive Polling Interval Endpoint 2 0x12D 8 read-write n 0x0 0x0 USB_RXINTERVAL2_NAKLMT NAK Limit 0 8 USB_RXINTERVAL2_TXPOLL RX Polling 0 8 RXINTERVAL3 USB Host Receive Polling Interval Endpoint 3 0x13D 8 read-write n 0x0 0x0 USB_RXINTERVAL3_NAKLMT NAK Limit 0 8 USB_RXINTERVAL3_TXPOLL RX Polling 0 8 RXINTERVAL4 USB Host Receive Polling Interval Endpoint 4 0x14D 8 read-write n 0x0 0x0 USB_RXINTERVAL4_NAKLMT NAK Limit 0 8 USB_RXINTERVAL4_TXPOLL RX Polling 0 8 RXINTERVAL5 USB Host Receive Polling Interval Endpoint 5 0x15D 8 read-write n 0x0 0x0 USB_RXINTERVAL5_NAKLMT NAK Limit 0 8 USB_RXINTERVAL5_TXPOLL RX Polling 0 8 RXINTERVAL6 USB Host Receive Polling Interval Endpoint 6 0x16D 8 read-write n 0x0 0x0 USB_RXINTERVAL6_NAKLMT NAK Limit 0 8 USB_RXINTERVAL6_TXPOLL RX Polling 0 8 RXINTERVAL7 USB Host Receive Polling Interval Endpoint 7 0x17D 8 read-write n 0x0 0x0 USB_RXINTERVAL7_NAKLMT NAK Limit 0 8 USB_RXINTERVAL7_TXPOLL RX Polling 0 8 RXIS USB Receive Interrupt Status 0x4 16 read-write n 0x0 0x0 USB_RXIS_EP1 RX Endpoint 1 Interrupt 1 2 USB_RXIS_EP2 RX Endpoint 2 Interrupt 2 3 USB_RXIS_EP3 RX Endpoint 3 Interrupt 3 4 USB_RXIS_EP4 RX Endpoint 4 Interrupt 4 5 USB_RXIS_EP5 RX Endpoint 5 Interrupt 5 6 USB_RXIS_EP6 RX Endpoint 6 Interrupt 6 7 USB_RXIS_EP7 RX Endpoint 7 Interrupt 7 8 RXMAXP1 USB Maximum Receive Data Endpoint 1 0x114 16 read-write n 0x0 0x0 USB_RXMAXP1_MAXLOAD Maximum Payload 0 11 RXMAXP2 USB Maximum Receive Data Endpoint 2 0x124 16 read-write n 0x0 0x0 USB_RXMAXP2_MAXLOAD Maximum Payload 0 11 RXMAXP3 USB Maximum Receive Data Endpoint 3 0x134 16 read-write n 0x0 0x0 USB_RXMAXP3_MAXLOAD Maximum Payload 0 11 RXMAXP4 USB Maximum Receive Data Endpoint 4 0x144 16 read-write n 0x0 0x0 USB_RXMAXP4_MAXLOAD Maximum Payload 0 11 RXMAXP5 USB Maximum Receive Data Endpoint 5 0x154 16 read-write n 0x0 0x0 USB_RXMAXP5_MAXLOAD Maximum Payload 0 11 RXMAXP6 USB Maximum Receive Data Endpoint 6 0x164 16 read-write n 0x0 0x0 USB_RXMAXP6_MAXLOAD Maximum Payload 0 11 RXMAXP7 USB Maximum Receive Data Endpoint 7 0x174 16 read-write n 0x0 0x0 USB_RXMAXP7_MAXLOAD Maximum Payload 0 11 RXTYPE1 USB Host Configure Receive Type Endpoint 1 0x11C 8 read-write n 0x0 0x0 USB_RXTYPE1_PROTO Protocol 4 6 USB_RXTYPE1_PROTO_CTRL Control 0x0 USB_RXTYPE1_PROTO_ISOC Isochronous 0x1 USB_RXTYPE1_PROTO_BULK Bulk 0x2 USB_RXTYPE1_PROTO_INT Interrupt 0x3 USB_RXTYPE1_SPEED Operating Speed 6 8 USB_RXTYPE1_SPEED_DFLT Default 0x0 USB_RXTYPE1_SPEED_HIGH High 0x1 USB_RXTYPE1_SPEED_FULL Full 0x2 USB_RXTYPE1_SPEED_LOW Low 0x3 USB_RXTYPE1_TEP Target Endpoint Number 0 4 RXTYPE2 USB Host Configure Receive Type Endpoint 2 0x12C 8 read-write n 0x0 0x0 USB_RXTYPE2_PROTO Protocol 4 6 USB_RXTYPE2_PROTO_CTRL Control 0x0 USB_RXTYPE2_PROTO_ISOC Isochronous 0x1 USB_RXTYPE2_PROTO_BULK Bulk 0x2 USB_RXTYPE2_PROTO_INT Interrupt 0x3 USB_RXTYPE2_SPEED Operating Speed 6 8 USB_RXTYPE2_SPEED_DFLT Default 0x0 USB_RXTYPE2_SPEED_HIGH High 0x1 USB_RXTYPE2_SPEED_FULL Full 0x2 USB_RXTYPE2_SPEED_LOW Low 0x3 USB_RXTYPE2_TEP Target Endpoint Number 0 4 RXTYPE3 USB Host Configure Receive Type Endpoint 3 0x13C 8 read-write n 0x0 0x0 USB_RXTYPE3_PROTO Protocol 4 6 USB_RXTYPE3_PROTO_CTRL Control 0x0 USB_RXTYPE3_PROTO_ISOC Isochronous 0x1 USB_RXTYPE3_PROTO_BULK Bulk 0x2 USB_RXTYPE3_PROTO_INT Interrupt 0x3 USB_RXTYPE3_SPEED Operating Speed 6 8 USB_RXTYPE3_SPEED_DFLT Default 0x0 USB_RXTYPE3_SPEED_HIGH High 0x1 USB_RXTYPE3_SPEED_FULL Full 0x2 USB_RXTYPE3_SPEED_LOW Low 0x3 USB_RXTYPE3_TEP Target Endpoint Number 0 4 RXTYPE4 USB Host Configure Receive Type Endpoint 4 0x14C 8 read-write n 0x0 0x0 USB_RXTYPE4_PROTO Protocol 4 6 USB_RXTYPE4_PROTO_CTRL Control 0x0 USB_RXTYPE4_PROTO_ISOC Isochronous 0x1 USB_RXTYPE4_PROTO_BULK Bulk 0x2 USB_RXTYPE4_PROTO_INT Interrupt 0x3 USB_RXTYPE4_SPEED Operating Speed 6 8 USB_RXTYPE4_SPEED_DFLT Default 0x0 USB_RXTYPE4_SPEED_HIGH High 0x1 USB_RXTYPE4_SPEED_FULL Full 0x2 USB_RXTYPE4_SPEED_LOW Low 0x3 USB_RXTYPE4_TEP Target Endpoint Number 0 4 RXTYPE5 USB Host Configure Receive Type Endpoint 5 0x15C 8 read-write n 0x0 0x0 USB_RXTYPE5_PROTO Protocol 4 6 USB_RXTYPE5_PROTO_CTRL Control 0x0 USB_RXTYPE5_PROTO_ISOC Isochronous 0x1 USB_RXTYPE5_PROTO_BULK Bulk 0x2 USB_RXTYPE5_PROTO_INT Interrupt 0x3 USB_RXTYPE5_SPEED Operating Speed 6 8 USB_RXTYPE5_SPEED_DFLT Default 0x0 USB_RXTYPE5_SPEED_HIGH High 0x1 USB_RXTYPE5_SPEED_FULL Full 0x2 USB_RXTYPE5_SPEED_LOW Low 0x3 USB_RXTYPE5_TEP Target Endpoint Number 0 4 RXTYPE6 USB Host Configure Receive Type Endpoint 6 0x16C 8 read-write n 0x0 0x0 USB_RXTYPE6_PROTO Protocol 4 6 USB_RXTYPE6_PROTO_CTRL Control 0x0 USB_RXTYPE6_PROTO_ISOC Isochronous 0x1 USB_RXTYPE6_PROTO_BULK Bulk 0x2 USB_RXTYPE6_PROTO_INT Interrupt 0x3 USB_RXTYPE6_SPEED Operating Speed 6 8 USB_RXTYPE6_SPEED_DFLT Default 0x0 USB_RXTYPE6_SPEED_HIGH High 0x1 USB_RXTYPE6_SPEED_FULL Full 0x2 USB_RXTYPE6_SPEED_LOW Low 0x3 USB_RXTYPE6_TEP Target Endpoint Number 0 4 RXTYPE7 USB Host Configure Receive Type Endpoint 7 0x17C 8 read-write n 0x0 0x0 USB_RXTYPE7_PROTO Protocol 4 6 USB_RXTYPE7_PROTO_CTRL Control 0x0 USB_RXTYPE7_PROTO_ISOC Isochronous 0x1 USB_RXTYPE7_PROTO_BULK Bulk 0x2 USB_RXTYPE7_PROTO_INT Interrupt 0x3 USB_RXTYPE7_SPEED Operating Speed 6 8 USB_RXTYPE7_SPEED_DFLT Default 0x0 USB_RXTYPE7_SPEED_HIGH High 0x1 USB_RXTYPE7_SPEED_FULL Full 0x2 USB_RXTYPE7_SPEED_LOW Low 0x3 USB_RXTYPE7_TEP Target Endpoint Number 0 4 TEST USB Test Mode 0xF 8 read-write n 0x0 0x0 USB_TEST_FIFOACC FIFO Access 6 7 USB_TEST_FORCEFS Force Full-Speed Mode 5 6 USB_TEST_FORCEH Force Host Mode 7 8 USB_TEST_FORCEHS Force High-Speed Mode 4 5 USB_TEST_TESTJ Test_J Mode Enable 1 2 USB_TEST_TESTK Test_K Mode Enable 2 3 USB_TEST_TESTPKT Test Packet Mode Enable 3 4 USB_TEST_TESTSE0NAK Test_SE0_NAK Test Mode Enable 0 1 TXCSRH1 USB Transmit Control and Status Endpoint 1 High 0x113 8 read-write n 0x0 0x0 USB_TXCSRH1_AUTOSET Auto Set 7 8 USB_TXCSRH1_DMAEN DMA Request Enable 4 5 USB_TXCSRH1_DMAMOD DMA Request Mode 2 3 USB_TXCSRH1_DT Data Toggle 0 1 USB_TXCSRH1_DTWE Data Toggle Write Enable 1 2 USB_TXCSRH1_FDT Force Data Toggle 3 4 USB_TXCSRH1_ISO Isochronous Transfers 6 7 USB_TXCSRH1_MODE Mode 5 6 TXCSRH2 USB Transmit Control and Status Endpoint 2 High 0x123 8 read-write n 0x0 0x0 USB_TXCSRH2_AUTOSET Auto Set 7 8 USB_TXCSRH2_DMAEN DMA Request Enable 4 5 USB_TXCSRH2_DMAMOD DMA Request Mode 2 3 USB_TXCSRH2_DT Data Toggle 0 1 USB_TXCSRH2_DTWE Data Toggle Write Enable 1 2 USB_TXCSRH2_FDT Force Data Toggle 3 4 USB_TXCSRH2_ISO Isochronous Transfers 6 7 USB_TXCSRH2_MODE Mode 5 6 TXCSRH3 USB Transmit Control and Status Endpoint 3 High 0x133 8 read-write n 0x0 0x0 USB_TXCSRH3_AUTOSET Auto Set 7 8 USB_TXCSRH3_DMAEN DMA Request Enable 4 5 USB_TXCSRH3_DMAMOD DMA Request Mode 2 3 USB_TXCSRH3_DT Data Toggle 0 1 USB_TXCSRH3_DTWE Data Toggle Write Enable 1 2 USB_TXCSRH3_FDT Force Data Toggle 3 4 USB_TXCSRH3_ISO Isochronous Transfers 6 7 USB_TXCSRH3_MODE Mode 5 6 TXCSRH4 USB Transmit Control and Status Endpoint 4 High 0x143 8 read-write n 0x0 0x0 USB_TXCSRH4_AUTOSET Auto Set 7 8 USB_TXCSRH4_DMAEN DMA Request Enable 4 5 USB_TXCSRH4_DMAMOD DMA Request Mode 2 3 USB_TXCSRH4_DT Data Toggle 0 1 USB_TXCSRH4_DTWE Data Toggle Write Enable 1 2 USB_TXCSRH4_FDT Force Data Toggle 3 4 USB_TXCSRH4_ISO Isochronous Transfers 6 7 USB_TXCSRH4_MODE Mode 5 6 TXCSRH5 USB Transmit Control and Status Endpoint 5 High 0x153 8 read-write n 0x0 0x0 USB_TXCSRH5_AUTOSET Auto Set 7 8 USB_TXCSRH5_DMAEN DMA Request Enable 4 5 USB_TXCSRH5_DMAMOD DMA Request Mode 2 3 USB_TXCSRH5_DT Data Toggle 0 1 USB_TXCSRH5_DTWE Data Toggle Write Enable 1 2 USB_TXCSRH5_FDT Force Data Toggle 3 4 USB_TXCSRH5_ISO Isochronous Transfers 6 7 USB_TXCSRH5_MODE Mode 5 6 TXCSRH6 USB Transmit Control and Status Endpoint 6 High 0x163 8 read-write n 0x0 0x0 USB_TXCSRH6_AUTOSET Auto Set 7 8 USB_TXCSRH6_DMAEN DMA Request Enable 4 5 USB_TXCSRH6_DMAMOD DMA Request Mode 2 3 USB_TXCSRH6_DT Data Toggle 0 1 USB_TXCSRH6_DTWE Data Toggle Write Enable 1 2 USB_TXCSRH6_FDT Force Data Toggle 3 4 USB_TXCSRH6_ISO Isochronous Transfers 6 7 USB_TXCSRH6_MODE Mode 5 6 TXCSRH7 USB Transmit Control and Status Endpoint 7 High 0x173 8 read-write n 0x0 0x0 USB_TXCSRH7_AUTOSET Auto Set 7 8 USB_TXCSRH7_DMAEN DMA Request Enable 4 5 USB_TXCSRH7_DMAMOD DMA Request Mode 2 3 USB_TXCSRH7_DT Data Toggle 0 1 USB_TXCSRH7_DTWE Data Toggle Write Enable 1 2 USB_TXCSRH7_FDT Force Data Toggle 3 4 USB_TXCSRH7_ISO Isochronous Transfers 6 7 USB_TXCSRH7_MODE Mode 5 6 TXCSRL1 USB Transmit Control and Status Endpoint 1 Low 0x112 8 read-write n 0x0 0x0 USB_TXCSRL1_CLRDT Clear Data Toggle 6 7 USB_TXCSRL1_ERROR Error 2 3 USB_TXCSRL1_FIFONE FIFO Not Empty 1 2 USB_TXCSRL1_FLUSH Flush FIFO 3 4 USB_TXCSRL1_NAKTO NAK Timeout 7 8 USB_TXCSRL1_SETUP Setup Packet 4 5 USB_TXCSRL1_STALL Send STALL 4 5 USB_TXCSRL1_STALLED Endpoint Stalled 5 6 USB_TXCSRL1_TXRDY Transmit Packet Ready 0 1 USB_TXCSRL1_UNDRN Underrun 2 3 TXCSRL2 USB Transmit Control and Status Endpoint 2 Low 0x122 8 read-write n 0x0 0x0 USB_TXCSRL2_CLRDT Clear Data Toggle 6 7 USB_TXCSRL2_ERROR Error 2 3 USB_TXCSRL2_FIFONE FIFO Not Empty 1 2 USB_TXCSRL2_FLUSH Flush FIFO 3 4 USB_TXCSRL2_NAKTO NAK Timeout 7 8 USB_TXCSRL2_SETUP Setup Packet 4 5 USB_TXCSRL2_STALL Send STALL 4 5 USB_TXCSRL2_STALLED Endpoint Stalled 5 6 USB_TXCSRL2_TXRDY Transmit Packet Ready 0 1 USB_TXCSRL2_UNDRN Underrun 2 3 TXCSRL3 USB Transmit Control and Status Endpoint 3 Low 0x132 8 read-write n 0x0 0x0 USB_TXCSRL3_CLRDT Clear Data Toggle 6 7 USB_TXCSRL3_ERROR Error 2 3 USB_TXCSRL3_FIFONE FIFO Not Empty 1 2 USB_TXCSRL3_FLUSH Flush FIFO 3 4 USB_TXCSRL3_NAKTO NAK Timeout 7 8 USB_TXCSRL3_SETUP Setup Packet 4 5 USB_TXCSRL3_STALL Send STALL 4 5 USB_TXCSRL3_STALLED Endpoint Stalled 5 6 USB_TXCSRL3_TXRDY Transmit Packet Ready 0 1 USB_TXCSRL3_UNDRN Underrun 2 3 TXCSRL4 USB Transmit Control and Status Endpoint 4 Low 0x142 8 read-write n 0x0 0x0 USB_TXCSRL4_CLRDT Clear Data Toggle 6 7 USB_TXCSRL4_ERROR Error 2 3 USB_TXCSRL4_FIFONE FIFO Not Empty 1 2 USB_TXCSRL4_FLUSH Flush FIFO 3 4 USB_TXCSRL4_NAKTO NAK Timeout 7 8 USB_TXCSRL4_SETUP Setup Packet 4 5 USB_TXCSRL4_STALL Send STALL 4 5 USB_TXCSRL4_STALLED Endpoint Stalled 5 6 USB_TXCSRL4_TXRDY Transmit Packet Ready 0 1 USB_TXCSRL4_UNDRN Underrun 2 3 TXCSRL5 USB Transmit Control and Status Endpoint 5 Low 0x152 8 read-write n 0x0 0x0 USB_TXCSRL5_CLRDT Clear Data Toggle 6 7 USB_TXCSRL5_ERROR Error 2 3 USB_TXCSRL5_FIFONE FIFO Not Empty 1 2 USB_TXCSRL5_FLUSH Flush FIFO 3 4 USB_TXCSRL5_NAKTO NAK Timeout 7 8 USB_TXCSRL5_SETUP Setup Packet 4 5 USB_TXCSRL5_STALL Send STALL 4 5 USB_TXCSRL5_STALLED Endpoint Stalled 5 6 USB_TXCSRL5_TXRDY Transmit Packet Ready 0 1 USB_TXCSRL5_UNDRN Underrun 2 3 TXCSRL6 USB Transmit Control and Status Endpoint 6 Low 0x162 8 read-write n 0x0 0x0 USB_TXCSRL6_CLRDT Clear Data Toggle 6 7 USB_TXCSRL6_ERROR Error 2 3 USB_TXCSRL6_FIFONE FIFO Not Empty 1 2 USB_TXCSRL6_FLUSH Flush FIFO 3 4 USB_TXCSRL6_NAKTO NAK Timeout 7 8 USB_TXCSRL6_SETUP Setup Packet 4 5 USB_TXCSRL6_STALL Send STALL 4 5 USB_TXCSRL6_STALLED Endpoint Stalled 5 6 USB_TXCSRL6_TXRDY Transmit Packet Ready 0 1 USB_TXCSRL6_UNDRN Underrun 2 3 TXCSRL7 USB Transmit Control and Status Endpoint 7 Low 0x172 8 read-write n 0x0 0x0 USB_TXCSRL7_CLRDT Clear Data Toggle 6 7 USB_TXCSRL7_ERROR Error 2 3 USB_TXCSRL7_FIFONE FIFO Not Empty 1 2 USB_TXCSRL7_FLUSH Flush FIFO 3 4 USB_TXCSRL7_NAKTO NAK Timeout 7 8 USB_TXCSRL7_SETUP Setup Packet 4 5 USB_TXCSRL7_STALL Send STALL 4 5 USB_TXCSRL7_STALLED Endpoint Stalled 5 6 USB_TXCSRL7_TXRDY Transmit Packet Ready 0 1 USB_TXCSRL7_UNDRN Underrun 2 3 TXDPKTBUFDIS USB Transmit Double Packet Buffer Disable 0x342 16 read-write n 0x0 0x0 USB_TXDPKTBUFDIS_EP1 EP1 TX Double-Packet Buffer Disable 1 2 USB_TXDPKTBUFDIS_EP2 EP2 TX Double-Packet Buffer Disable 2 3 USB_TXDPKTBUFDIS_EP3 EP3 TX Double-Packet Buffer Disable 3 4 USB_TXDPKTBUFDIS_EP4 EP4 TX Double-Packet Buffer Disable 4 5 USB_TXDPKTBUFDIS_EP5 EP5 TX Double-Packet Buffer Disable 5 6 USB_TXDPKTBUFDIS_EP6 EP6 TX Double-Packet Buffer Disable 6 7 USB_TXDPKTBUFDIS_EP7 EP7 TX Double-Packet Buffer Disable 7 8 TXFIFOADD USB Transmit FIFO Start Address 0x64 16 read-write n 0x0 0x0 USB_TXFIFOADD_ADDR Transmit/Receive Start Address 0 9 TXFIFOSZ USB Transmit Dynamic FIFO Sizing 0x62 8 read-write n 0x0 0x0 USB_TXFIFOSZ_DPB Double Packet Buffer Support 4 5 USB_TXFIFOSZ_SIZE Max Packet Size 0 4 USB_TXFIFOSZ_SIZE_8 8 0x0 USB_TXFIFOSZ_SIZE_16 16 0x1 USB_TXFIFOSZ_SIZE_32 32 0x2 USB_TXFIFOSZ_SIZE_64 64 0x3 USB_TXFIFOSZ_SIZE_128 128 0x4 USB_TXFIFOSZ_SIZE_256 256 0x5 USB_TXFIFOSZ_SIZE_512 512 0x6 USB_TXFIFOSZ_SIZE_1024 1024 0x7 USB_TXFIFOSZ_SIZE_2048 2048 0x8 TXFUNCADDR0 USB Transmit Functional Address Endpoint 0 0x80 8 read-write n 0x0 0x0 USB_TXFUNCADDR0_ADDR Device Address 0 7 TXFUNCADDR1 USB Transmit Functional Address Endpoint 1 0x88 8 read-write n 0x0 0x0 USB_TXFUNCADDR1_ADDR Device Address 0 7 TXFUNCADDR2 USB Transmit Functional Address Endpoint 2 0x90 8 read-write n 0x0 0x0 USB_TXFUNCADDR2_ADDR Device Address 0 7 TXFUNCADDR3 USB Transmit Functional Address Endpoint 3 0x98 8 read-write n 0x0 0x0 USB_TXFUNCADDR3_ADDR Device Address 0 7 TXFUNCADDR4 USB Transmit Functional Address Endpoint 4 0xA0 8 read-write n 0x0 0x0 USB_TXFUNCADDR4_ADDR Device Address 0 7 TXFUNCADDR5 USB Transmit Functional Address Endpoint 5 0xA8 8 read-write n 0x0 0x0 USB_TXFUNCADDR5_ADDR Device Address 0 7 TXFUNCADDR6 USB Transmit Functional Address Endpoint 6 0xB0 8 read-write n 0x0 0x0 USB_TXFUNCADDR6_ADDR Device Address 0 7 TXFUNCADDR7 USB Transmit Functional Address Endpoint 7 0xB8 8 read-write n 0x0 0x0 USB_TXFUNCADDR7_ADDR Device Address 0 7 TXHUBADDR0 USB Transmit Hub Address Endpoint 0 0x82 8 read-write n 0x0 0x0 USB_TXHUBADDR0_ADDR Hub Address 0 7 TXHUBADDR1 USB Transmit Hub Address Endpoint 1 0x8A 8 read-write n 0x0 0x0 USB_TXHUBADDR1_ADDR Hub Address 0 7 TXHUBADDR2 USB Transmit Hub Address Endpoint 2 0x92 8 read-write n 0x0 0x0 USB_TXHUBADDR2_ADDR Hub Address 0 7 TXHUBADDR3 USB Transmit Hub Address Endpoint 3 0x9A 8 read-write n 0x0 0x0 USB_TXHUBADDR3_ADDR Hub Address 0 7 TXHUBADDR4 USB Transmit Hub Address Endpoint 4 0xA2 8 read-write n 0x0 0x0 USB_TXHUBADDR4_ADDR Hub Address 0 7 TXHUBADDR5 USB Transmit Hub Address Endpoint 5 0xAA 8 read-write n 0x0 0x0 USB_TXHUBADDR5_ADDR Hub Address 0 7 TXHUBADDR6 USB Transmit Hub Address Endpoint 6 0xB2 8 read-write n 0x0 0x0 USB_TXHUBADDR6_ADDR Hub Address 0 7 TXHUBADDR7 USB Transmit Hub Address Endpoint 7 0xBA 8 read-write n 0x0 0x0 USB_TXHUBADDR7_ADDR Hub Address 0 7 TXHUBPORT0 USB Transmit Hub Port Endpoint 0 0x83 8 read-write n 0x0 0x0 USB_TXHUBPORT0_PORT Hub Port 0 7 TXHUBPORT1 USB Transmit Hub Port Endpoint 1 0x8B 8 read-write n 0x0 0x0 USB_TXHUBPORT1_PORT Hub Port 0 7 TXHUBPORT2 USB Transmit Hub Port Endpoint 2 0x93 8 read-write n 0x0 0x0 USB_TXHUBPORT2_PORT Hub Port 0 7 TXHUBPORT3 USB Transmit Hub Port Endpoint 3 0x9B 8 read-write n 0x0 0x0 USB_TXHUBPORT3_PORT Hub Port 0 7 TXHUBPORT4 USB Transmit Hub Port Endpoint 4 0xA3 8 read-write n 0x0 0x0 USB_TXHUBPORT4_PORT Hub Port 0 7 TXHUBPORT5 USB Transmit Hub Port Endpoint 5 0xAB 8 read-write n 0x0 0x0 USB_TXHUBPORT5_PORT Hub Port 0 7 TXHUBPORT6 USB Transmit Hub Port Endpoint 6 0xB3 8 read-write n 0x0 0x0 USB_TXHUBPORT6_PORT Hub Port 0 7 TXHUBPORT7 USB Transmit Hub Port Endpoint 7 0xBB 8 read-write n 0x0 0x0 USB_TXHUBPORT7_PORT Hub Port 0 7 TXIE USB Transmit Interrupt Enable 0x6 16 read-write n 0x0 0x0 USB_TXIE_EP0 TX and RX Endpoint 0 Interrupt Enable 0 1 USB_TXIE_EP1 TX Endpoint 1 Interrupt Enable 1 2 USB_TXIE_EP2 TX Endpoint 2 Interrupt Enable 2 3 USB_TXIE_EP3 TX Endpoint 3 Interrupt Enable 3 4 USB_TXIE_EP4 TX Endpoint 4 Interrupt Enable 4 5 USB_TXIE_EP5 TX Endpoint 5 Interrupt Enable 5 6 USB_TXIE_EP6 TX Endpoint 6 Interrupt Enable 6 7 USB_TXIE_EP7 TX Endpoint 7 Interrupt Enable 7 8 TXINTERVAL1 USB Host Transmit Interval Endpoint 1 0x11B 8 read-write n 0x0 0x0 USB_TXINTERVAL1_NAKLMT NAK Limit 0 8 USB_TXINTERVAL1_TXPOLL TX Polling 0 8 TXINTERVAL2 USB Host Transmit Interval Endpoint 2 0x12B 8 read-write n 0x0 0x0 USB_TXINTERVAL2_NAKLMT NAK Limit 0 8 USB_TXINTERVAL2_TXPOLL TX Polling 0 8 TXINTERVAL3 USB Host Transmit Interval Endpoint 3 0x13B 8 read-write n 0x0 0x0 USB_TXINTERVAL3_NAKLMT NAK Limit 0 8 USB_TXINTERVAL3_TXPOLL TX Polling 0 8 TXINTERVAL4 USB Host Transmit Interval Endpoint 4 0x14B 8 read-write n 0x0 0x0 USB_TXINTERVAL4_NAKLMT NAK Limit 0 8 USB_TXINTERVAL4_TXPOLL TX Polling 0 8 TXINTERVAL5 USB Host Transmit Interval Endpoint 5 0x15B 8 read-write n 0x0 0x0 USB_TXINTERVAL5_NAKLMT NAK Limit 0 8 USB_TXINTERVAL5_TXPOLL TX Polling 0 8 TXINTERVAL6 USB Host Transmit Interval Endpoint 6 0x16B 8 read-write n 0x0 0x0 USB_TXINTERVAL6_NAKLMT NAK Limit 0 8 USB_TXINTERVAL6_TXPOLL TX Polling 0 8 TXINTERVAL7 USB Host Transmit Interval Endpoint 7 0x17B 8 read-write n 0x0 0x0 USB_TXINTERVAL7_NAKLMT NAK Limit 0 8 USB_TXINTERVAL7_TXPOLL TX Polling 0 8 TXIS USB Transmit Interrupt Status 0x2 16 read-write n 0x0 0x0 USB_TXIS_EP0 TX and RX Endpoint 0 Interrupt 0 1 USB_TXIS_EP1 TX Endpoint 1 Interrupt 1 2 USB_TXIS_EP2 TX Endpoint 2 Interrupt 2 3 USB_TXIS_EP3 TX Endpoint 3 Interrupt 3 4 USB_TXIS_EP4 TX Endpoint 4 Interrupt 4 5 USB_TXIS_EP5 TX Endpoint 5 Interrupt 5 6 USB_TXIS_EP6 TX Endpoint 6 Interrupt 6 7 USB_TXIS_EP7 TX Endpoint 7 Interrupt 7 8 TXMAXP1 USB Maximum Transmit Data Endpoint 1 0x110 16 read-write n 0x0 0x0 USB_TXMAXP1_MAXLOAD Maximum Payload 0 11 TXMAXP2 USB Maximum Transmit Data Endpoint 2 0x120 16 read-write n 0x0 0x0 USB_TXMAXP2_MAXLOAD Maximum Payload 0 11 TXMAXP3 USB Maximum Transmit Data Endpoint 3 0x130 16 read-write n 0x0 0x0 USB_TXMAXP3_MAXLOAD Maximum Payload 0 11 TXMAXP4 USB Maximum Transmit Data Endpoint 4 0x140 16 read-write n 0x0 0x0 USB_TXMAXP4_MAXLOAD Maximum Payload 0 11 TXMAXP5 USB Maximum Transmit Data Endpoint 5 0x150 16 read-write n 0x0 0x0 USB_TXMAXP5_MAXLOAD Maximum Payload 0 11 TXMAXP6 USB Maximum Transmit Data Endpoint 6 0x160 16 read-write n 0x0 0x0 USB_TXMAXP6_MAXLOAD Maximum Payload 0 11 TXMAXP7 USB Maximum Transmit Data Endpoint 7 0x170 16 read-write n 0x0 0x0 USB_TXMAXP7_MAXLOAD Maximum Payload 0 11 TXTYPE1 USB Host Transmit Configure Type Endpoint 1 0x11A 8 read-write n 0x0 0x0 USB_TXTYPE1_PROTO Protocol 4 6 USB_TXTYPE1_PROTO_CTRL Control 0x0 USB_TXTYPE1_PROTO_ISOC Isochronous 0x1 USB_TXTYPE1_PROTO_BULK Bulk 0x2 USB_TXTYPE1_PROTO_INT Interrupt 0x3 USB_TXTYPE1_SPEED Operating Speed 6 8 USB_TXTYPE1_SPEED_DFLT Default 0x0 USB_TXTYPE1_SPEED_HIGH High 0x1 USB_TXTYPE1_SPEED_FULL Full 0x2 USB_TXTYPE1_SPEED_LOW Low 0x3 USB_TXTYPE1_TEP Target Endpoint Number 0 4 TXTYPE2 USB Host Transmit Configure Type Endpoint 2 0x12A 8 read-write n 0x0 0x0 USB_TXTYPE2_PROTO Protocol 4 6 USB_TXTYPE2_PROTO_CTRL Control 0x0 USB_TXTYPE2_PROTO_ISOC Isochronous 0x1 USB_TXTYPE2_PROTO_BULK Bulk 0x2 USB_TXTYPE2_PROTO_INT Interrupt 0x3 USB_TXTYPE2_SPEED Operating Speed 6 8 USB_TXTYPE2_SPEED_DFLT Default 0x0 USB_TXTYPE2_SPEED_HIGH High 0x1 USB_TXTYPE2_SPEED_FULL Full 0x2 USB_TXTYPE2_SPEED_LOW Low 0x3 USB_TXTYPE2_TEP Target Endpoint Number 0 4 TXTYPE3 USB Host Transmit Configure Type Endpoint 3 0x13A 8 read-write n 0x0 0x0 USB_TXTYPE3_PROTO Protocol 4 6 USB_TXTYPE3_PROTO_CTRL Control 0x0 USB_TXTYPE3_PROTO_ISOC Isochronous 0x1 USB_TXTYPE3_PROTO_BULK Bulk 0x2 USB_TXTYPE3_PROTO_INT Interrupt 0x3 USB_TXTYPE3_SPEED Operating Speed 6 8 USB_TXTYPE3_SPEED_DFLT Default 0x0 USB_TXTYPE3_SPEED_HIGH High 0x1 USB_TXTYPE3_SPEED_FULL Full 0x2 USB_TXTYPE3_SPEED_LOW Low 0x3 USB_TXTYPE3_TEP Target Endpoint Number 0 4 TXTYPE4 USB Host Transmit Configure Type Endpoint 4 0x14A 8 read-write n 0x0 0x0 USB_TXTYPE4_PROTO Protocol 4 6 USB_TXTYPE4_PROTO_CTRL Control 0x0 USB_TXTYPE4_PROTO_ISOC Isochronous 0x1 USB_TXTYPE4_PROTO_BULK Bulk 0x2 USB_TXTYPE4_PROTO_INT Interrupt 0x3 USB_TXTYPE4_SPEED Operating Speed 6 8 USB_TXTYPE4_SPEED_DFLT Default 0x0 USB_TXTYPE4_SPEED_HIGH High 0x1 USB_TXTYPE4_SPEED_FULL Full 0x2 USB_TXTYPE4_SPEED_LOW Low 0x3 USB_TXTYPE4_TEP Target Endpoint Number 0 4 TXTYPE5 USB Host Transmit Configure Type Endpoint 5 0x15A 8 read-write n 0x0 0x0 USB_TXTYPE5_PROTO Protocol 4 6 USB_TXTYPE5_PROTO_CTRL Control 0x0 USB_TXTYPE5_PROTO_ISOC Isochronous 0x1 USB_TXTYPE5_PROTO_BULK Bulk 0x2 USB_TXTYPE5_PROTO_INT Interrupt 0x3 USB_TXTYPE5_SPEED Operating Speed 6 8 USB_TXTYPE5_SPEED_DFLT Default 0x0 USB_TXTYPE5_SPEED_HIGH High 0x1 USB_TXTYPE5_SPEED_FULL Full 0x2 USB_TXTYPE5_SPEED_LOW Low 0x3 USB_TXTYPE5_TEP Target Endpoint Number 0 4 TXTYPE6 USB Host Transmit Configure Type Endpoint 6 0x16A 8 read-write n 0x0 0x0 USB_TXTYPE6_PROTO Protocol 4 6 USB_TXTYPE6_PROTO_CTRL Control 0x0 USB_TXTYPE6_PROTO_ISOC Isochronous 0x1 USB_TXTYPE6_PROTO_BULK Bulk 0x2 USB_TXTYPE6_PROTO_INT Interrupt 0x3 USB_TXTYPE6_SPEED Operating Speed 6 8 USB_TXTYPE6_SPEED_DFLT Default 0x0 USB_TXTYPE6_SPEED_HIGH High 0x1 USB_TXTYPE6_SPEED_FULL Full 0x2 USB_TXTYPE6_SPEED_LOW Low 0x3 USB_TXTYPE6_TEP Target Endpoint Number 0 4 TXTYPE7 USB Host Transmit Configure Type Endpoint 7 0x17A 8 read-write n 0x0 0x0 USB_TXTYPE7_PROTO Protocol 4 6 USB_TXTYPE7_PROTO_CTRL Control 0x0 USB_TXTYPE7_PROTO_ISOC Isochronous 0x1 USB_TXTYPE7_PROTO_BULK Bulk 0x2 USB_TXTYPE7_PROTO_INT Interrupt 0x3 USB_TXTYPE7_SPEED Operating Speed 6 8 USB_TXTYPE7_SPEED_DFLT Default 0x0 USB_TXTYPE7_SPEED_HIGH High 0x1 USB_TXTYPE7_SPEED_FULL Full 0x2 USB_TXTYPE7_SPEED_LOW Low 0x3 USB_TXTYPE7_TEP Target Endpoint Number 0 4 TYPE0 USB Type Endpoint 0 0x10A 8 read-write n 0x0 0x0 USB_TYPE0_SPEED Operating Speed 6 8 USB_TYPE0_SPEED_HIGH High 0x1 USB_TYPE0_SPEED_FULL Full 0x2 USB_TYPE0_SPEED_LOW Low 0x3 ULPIREGADDR USB ULPI Register Address 0x75 8 read-write n 0x0 0x0 USB_ULPIREGADDR_ADDR Register Address 0 8 ULPIREGCTL USB ULPI Register Control 0x76 8 read-write n 0x0 0x0 USB_ULPIREGCTL_RDWR Read/Write Control 2 3 USB_ULPIREGCTL_REGACC Initiate Register Access 0 1 USB_ULPIREGCTL_REGCMPLT Register Access Complete 1 2 ULPIREGDATA USB ULPI Register Data 0x74 8 read-write n 0x0 0x0 USB_ULPIREGDATA_REGDATA Register Data 0 8 ULPIVBUSCTL USB ULPI VBUS Control 0x70 8 read-write n 0x0 0x0 USB_ULPIVBUSCTL_USEEXTVBUS Use External VBUS 0 1 USB_ULPIVBUSCTL_USEEXTVBUSIND Use External VBUS Indicator 1 2 USB0CC USB Clock Configuration 0xFC8 read-write n 0x0 0x0 USB_CC_CLKDIV PLL Clock Divisor 0 4 USB_CC_CLKEN USB Clock Enable 9 10 USB_CC_CSD Clock Source/Direction 8 9 USB0CCONF USB Common Configuration 0x61 8 read-write n 0x0 0x0 USB_CCONF_RXEDMA TX Early DMA Enable 0 1 USB_CCONF_TXEDMA TX Early DMA Enable 1 2 USB0CONTIM USB Connect Timing 0x7A 8 read-write n 0x0 0x0 USB_CONTIM_WTCON Connect Wait 4 8 USB_CONTIM_WTID Wait ID 0 4 USB0COUNT0 USB Receive Byte Count Endpoint 0 0x108 8 read-write n 0x0 0x0 USB_COUNT0_COUNT FIFO Count 0 7 USB0CSRH0 USB Control and Status Endpoint 0 High 0x103 8 write-only n 0x0 0x0 USB_CSRH0_DISPING PING Disable 3 4 write-only USB_CSRH0_DT Data Toggle 1 2 write-only USB_CSRH0_DTWE Data Toggle Write Enable 2 3 write-only USB_CSRH0_FLUSH Flush FIFO 0 1 write-only USB0CSRL0 USB Control and Status Endpoint 0 Low 0x102 8 write-only n 0x0 0x0 USB_CSRL0_DATAEND Data End 3 4 write-only USB_CSRL0_RXRDY Receive Packet Ready 0 1 write-only USB_CSRL0_RXRDYC RXRDY Clear 6 7 write-only USB_CSRL0_SETEND Setup End 4 5 write-only USB_CSRL0_SETENDC Setup End Clear 7 8 write-only USB_CSRL0_STALL Send Stall 5 6 write-only USB_CSRL0_STALLED Endpoint Stalled 2 3 write-only USB_CSRL0_TXRDY Transmit Packet Ready 1 2 write-only USB0CTO USB Chirp Timeout 0x344 16 read-write n 0x0 0x0 USB_CTO_CCTV Configurable Chirp Timeout Value 0 16 USB0DEVCTL USB Device Control 0x60 8 read-write n 0x0 0x0 USB_DEVCTL_DEV Device Mode (OTG only) 7 8 USB_DEVCTL_FSDEV Full-Speed Device Detected 6 7 USB_DEVCTL_HOST Host Mode 2 3 USB_DEVCTL_HOSTREQ Host Request (OTG only) 1 2 USB_DEVCTL_LSDEV Low-Speed Device Detected 5 6 USB_DEVCTL_SESSION Session Start/End (OTG only) 0 1 USB_DEVCTL_VBUS VBUS Level (OTG only) 3 5 USB_DEVCTL_VBUS_NONE Below SessionEnd 0x0 USB_DEVCTL_VBUS_SEND Above SessionEnd, below AValid 0x1 USB_DEVCTL_VBUS_AVALID Above AValid, below VBUSValid 0x2 USB_DEVCTL_VBUS_VALID Above VBUSValid 0x3 USB0DMAADDR0 USB DMA Address 0 0x208 read-write n 0x0 0x0 USB_DMAADDR0_ADDR DMA Address 2 32 USB0DMAADDR1 USB DMA Address 1 0x218 read-write n 0x0 0x0 USB_DMAADDR1_ADDR DMA Address 2 32 USB0DMAADDR2 USB DMA Address 2 0x228 read-write n 0x0 0x0 USB_DMAADDR2_ADDR DMA Address 2 32 USB0DMAADDR3 USB DMA Address 3 0x238 read-write n 0x0 0x0 USB_DMAADDR3_ADDR DMA Address 2 32 USB0DMAADDR4 USB DMA Address 4 0x248 read-write n 0x0 0x0 USB_DMAADDR4_ADDR DMA Address 2 32 USB0DMAADDR5 USB DMA Address 5 0x258 read-write n 0x0 0x0 USB_DMAADDR5_ADDR DMA Address 2 32 USB0DMAADDR6 USB DMA Address 6 0x268 read-write n 0x0 0x0 USB_DMAADDR6_ADDR DMA Address 2 32 USB0DMAADDR7 USB DMA Address 7 0x278 read-write n 0x0 0x0 USB_DMAADDR7_ADDR DMA Address 2 32 USB0DMACOUNT0 USB DMA Count 0 0x20C read-write n 0x0 0x0 USB_DMACOUNT0_COUNT DMA Count 2 32 USB0DMACOUNT1 USB DMA Count 1 0x21C read-write n 0x0 0x0 USB_DMACOUNT1_COUNT DMA Count 2 32 USB0DMACOUNT2 USB DMA Count 2 0x22C read-write n 0x0 0x0 USB_DMACOUNT2_COUNT DMA Count 2 32 USB0DMACOUNT3 USB DMA Count 3 0x23C read-write n 0x0 0x0 USB_DMACOUNT3_COUNT DMA Count 2 32 USB0DMACOUNT4 USB DMA Count 4 0x24C read-write n 0x0 0x0 USB_DMACOUNT4_COUNT DMA Count 2 32 USB0DMACOUNT5 USB DMA Count 5 0x25C read-write n 0x0 0x0 USB_DMACOUNT5_COUNT DMA Count 2 32 USB0DMACOUNT6 USB DMA Count 6 0x26C read-write n 0x0 0x0 USB_DMACOUNT6_COUNT DMA Count 2 32 USB0DMACOUNT7 USB DMA Count 7 0x27C read-write n 0x0 0x0 USB_DMACOUNT7_COUNT DMA Count 2 32 USB0DMACTL0 USB DMA Control 0 0x204 16 read-write n 0x0 0x0 USB_DMACTL0_BRSTM Burst Mode 9 11 USB_DMACTL0_BRSTM_ANY Bursts of unspecified length 0x0 USB_DMACTL0_BRSTM_INC4 INCR4 or unspecified length 0x1 USB_DMACTL0_BRSTM_INC8 INCR8, INCR4 or unspecified length 0x2 USB_DMACTL0_BRSTM_INC16 INCR16, INCR8, INCR4 or unspecified length 0x3 USB_DMACTL0_DIR DMA Direction 1 2 USB_DMACTL0_ENABLE DMA Transfer Enable 0 1 USB_DMACTL0_EP Endpoint number 4 8 USB_DMACTL0_ERR Bus Error Bit 8 9 USB_DMACTL0_IE DMA Interrupt Enable 3 4 USB_DMACTL0_MODE DMA Transfer Mode 2 3 USB0DMACTL1 USB DMA Control 1 0x214 16 read-write n 0x0 0x0 USB_DMACTL1_BRSTM Burst Mode 9 11 USB_DMACTL1_BRSTM_ANY Bursts of unspecified length 0x0 USB_DMACTL1_BRSTM_INC4 INCR4 or unspecified length 0x1 USB_DMACTL1_BRSTM_INC8 INCR8, INCR4 or unspecified length 0x2 USB_DMACTL1_BRSTM_INC16 INCR16, INCR8, INCR4 or unspecified length 0x3 USB_DMACTL1_DIR DMA Direction 1 2 USB_DMACTL1_ENABLE DMA Transfer Enable 0 1 USB_DMACTL1_EP Endpoint number 4 8 USB_DMACTL1_ERR Bus Error Bit 8 9 USB_DMACTL1_IE DMA Interrupt Enable 3 4 USB_DMACTL1_MODE DMA Transfer Mode 2 3 USB0DMACTL2 USB DMA Control 2 0x224 16 read-write n 0x0 0x0 USB_DMACTL2_BRSTM Burst Mode 9 11 USB_DMACTL2_BRSTM_ANY Bursts of unspecified length 0x0 USB_DMACTL2_BRSTM_INC4 INCR4 or unspecified length 0x1 USB_DMACTL2_BRSTM_INC8 INCR8, INCR4 or unspecified length 0x2 USB_DMACTL2_BRSTM_INC16 INCR16, INCR8, INCR4 or unspecified length 0x3 USB_DMACTL2_DIR DMA Direction 1 2 USB_DMACTL2_ENABLE DMA Transfer Enable 0 1 USB_DMACTL2_EP Endpoint number 4 8 USB_DMACTL2_ERR Bus Error Bit 8 9 USB_DMACTL2_IE DMA Interrupt Enable 3 4 USB_DMACTL2_MODE DMA Transfer Mode 2 3 USB0DMACTL3 USB DMA Control 3 0x234 16 read-write n 0x0 0x0 USB_DMACTL3_BRSTM Burst Mode 9 11 USB_DMACTL3_BRSTM_ANY Bursts of unspecified length 0x0 USB_DMACTL3_BRSTM_INC4 INCR4 or unspecified length 0x1 USB_DMACTL3_BRSTM_INC8 INCR8, INCR4 or unspecified length 0x2 USB_DMACTL3_BRSTM_INC16 INCR16, INCR8, INCR4 or unspecified length 0x3 USB_DMACTL3_DIR DMA Direction 1 2 USB_DMACTL3_ENABLE DMA Transfer Enable 0 1 USB_DMACTL3_EP Endpoint number 4 8 USB_DMACTL3_ERR Bus Error Bit 8 9 USB_DMACTL3_IE DMA Interrupt Enable 3 4 USB_DMACTL3_MODE DMA Transfer Mode 2 3 USB0DMACTL4 USB DMA Control 4 0x244 16 read-write n 0x0 0x0 USB_DMACTL4_BRSTM Burst Mode 9 11 USB_DMACTL4_BRSTM_ANY Bursts of unspecified length 0x0 USB_DMACTL4_BRSTM_INC4 INCR4 or unspecified length 0x1 USB_DMACTL4_BRSTM_INC8 INCR8, INCR4 or unspecified length 0x2 USB_DMACTL4_BRSTM_INC16 INCR16, INCR8, INCR4 or unspecified length 0x3 USB_DMACTL4_DIR DMA Direction 1 2 USB_DMACTL4_ENABLE DMA Transfer Enable 0 1 USB_DMACTL4_EP Endpoint number 4 8 USB_DMACTL4_ERR Bus Error Bit 8 9 USB_DMACTL4_IE DMA Interrupt Enable 3 4 USB_DMACTL4_MODE DMA Transfer Mode 2 3 USB0DMACTL5 USB DMA Control 5 0x254 16 read-write n 0x0 0x0 USB_DMACTL5_BRSTM Burst Mode 9 11 USB_DMACTL5_BRSTM_ANY Bursts of unspecified length 0x0 USB_DMACTL5_BRSTM_INC4 INCR4 or unspecified length 0x1 USB_DMACTL5_BRSTM_INC8 INCR8, INCR4 or unspecified length 0x2 USB_DMACTL5_BRSTM_INC16 INCR16, INCR8, INCR4 or unspecified length 0x3 USB_DMACTL5_DIR DMA Direction 1 2 USB_DMACTL5_ENABLE DMA Transfer Enable 0 1 USB_DMACTL5_EP Endpoint number 4 8 USB_DMACTL5_ERR Bus Error Bit 8 9 USB_DMACTL5_IE DMA Interrupt Enable 3 4 USB_DMACTL5_MODE DMA Transfer Mode 2 3 USB0DMACTL6 USB DMA Control 6 0x264 16 read-write n 0x0 0x0 USB_DMACTL6_BRSTM Burst Mode 9 11 USB_DMACTL6_BRSTM_ANY Bursts of unspecified length 0x0 USB_DMACTL6_BRSTM_INC4 INCR4 or unspecified length 0x1 USB_DMACTL6_BRSTM_INC8 INCR8, INCR4 or unspecified length 0x2 USB_DMACTL6_BRSTM_INC16 INCR16, INCR8, INCR4 or unspecified length 0x3 USB_DMACTL6_DIR DMA Direction 1 2 USB_DMACTL6_ENABLE DMA Transfer Enable 0 1 USB_DMACTL6_EP Endpoint number 4 8 USB_DMACTL6_ERR Bus Error Bit 8 9 USB_DMACTL6_IE DMA Interrupt Enable 3 4 USB_DMACTL6_MODE DMA Transfer Mode 2 3 USB0DMACTL7 USB DMA Control 7 0x274 16 read-write n 0x0 0x0 USB_DMACTL7_BRSTM Burst Mode 9 11 USB_DMACTL7_BRSTM_ANY Bursts of unspecified length 0x0 USB_DMACTL7_BRSTM_INC4 INCR4 or unspecified length 0x1 USB_DMACTL7_BRSTM_INC8 INCR8, INCR4 or unspecified length 0x2 USB_DMACTL7_BRSTM_INC16 INCR16, INCR8, INCR4 or unspecified length 0x3 USB_DMACTL7_DIR DMA Direction 1 2 USB_DMACTL7_ENABLE DMA Transfer Enable 0 1 USB_DMACTL7_EP Endpoint number 4 8 USB_DMACTL7_ERR Bus Error Bit 8 9 USB_DMACTL7_IE DMA Interrupt Enable 3 4 USB_DMACTL7_MODE DMA Transfer Mode 2 3 USB0DMAINTR USB DMA Interrupt 0x200 8 read-write n 0x0 0x0 USB_DMAINTR_CH0 Channel 0 DMA Interrupt 0 1 USB_DMAINTR_CH1 Channel 1 DMA Interrupt 1 2 USB_DMAINTR_CH2 Channel 2 DMA Interrupt 2 3 USB_DMAINTR_CH3 Channel 3 DMA Interrupt 3 4 USB_DMAINTR_CH4 Channel 4 DMA Interrupt 4 5 USB_DMAINTR_CH5 Channel 5 DMA Interrupt 5 6 USB_DMAINTR_CH6 Channel 6 DMA Interrupt 6 7 USB_DMAINTR_CH7 Channel 7 DMA Interrupt 7 8 USB0DRIM USB Device RESUME Interrupt Mask 0x414 read-write n 0x0 0x0 USB_DRIM_RESUME RESUME Interrupt Mask 0 1 USB0DRISC USB Device RESUME Interrupt Status and Clear 0x418 write-only n 0x0 0x0 USB_DRISC_RESUME RESUME Interrupt Status and Clear 0 1 write-only USB0DRRIS USB Device RESUME Raw Interrupt Status 0x410 read-write n 0x0 0x0 USB_DRRIS_RESUME RESUME Interrupt Status 0 1 USB0EPC USB External Power Control 0x400 read-write n 0x0 0x0 USB_EPC_EPEN External Power Supply Enable Configuration 0 2 USB_EPC_EPEN_LOW Power Enable Active Low 0x0 USB_EPC_EPEN_HIGH Power Enable Active High 0x1 USB_EPC_EPEN_VBLOW Power Enable High if VBUS Low (OTG only) 0x2 USB_EPC_EPEN_VBHIGH Power Enable High if VBUS High (OTG only) 0x3 USB_EPC_EPENDE EPEN Drive Enable 2 3 USB_EPC_PFLTACT Power Fault Action 8 10 USB_EPC_PFLTACT_UNCHG Unchanged 0x0 USB_EPC_PFLTACT_TRIS Tristate 0x1 USB_EPC_PFLTACT_LOW Low 0x2 USB_EPC_PFLTACT_HIGH High 0x3 USB_EPC_PFLTAEN Power Fault Action Enable 6 7 USB_EPC_PFLTEN Power Fault Input Enable 4 5 USB_EPC_PFLTSEN_HIGH Power Fault Sense 5 6 USB0EPCIM USB External Power Control Interrupt Mask 0x408 read-write n 0x0 0x0 USB_EPCIM_PF USB Power Fault Interrupt Mask 0 1 USB0EPCISC USB External Power Control Interrupt Status and Clear 0x40C read-write n 0x0 0x0 USB_EPCISC_PF USB Power Fault Interrupt Status and Clear 0 1 USB0EPCRIS USB External Power Control Raw Interrupt Status 0x404 read-write n 0x0 0x0 USB_EPCRIS_PF USB Power Fault Interrupt Status 0 1 USB0EPIDX USB Endpoint Index 0xE 8 read-write n 0x0 0x0 USB_EPIDX_EPIDX Endpoint Index 0 4 USB0EPINFO USB Endpoint Information 0x78 8 read-write n 0x0 0x0 USB_EPINFO_RXEP RX Endpoints 4 8 USB_EPINFO_TXEP TX Endpoints 0 4 USB0FADDR USB Device Functional Address 0x0 8 read-write n 0x0 0x0 USB_FADDR Function Address 0 7 USB0FIFO0 USB FIFO Endpoint 0 0x20 read-write n 0x0 0x0 USB_FIFO0_EPDATA Endpoint Data 0 32 USB0FIFO1 USB FIFO Endpoint 1 0x24 read-write n 0x0 0x0 USB_FIFO1_EPDATA Endpoint Data 0 32 USB0FIFO2 USB FIFO Endpoint 2 0x28 read-write n 0x0 0x0 USB_FIFO2_EPDATA Endpoint Data 0 32 USB0FIFO3 USB FIFO Endpoint 3 0x2C read-write n 0x0 0x0 USB_FIFO3_EPDATA Endpoint Data 0 32 USB0FIFO4 USB FIFO Endpoint 4 0x30 read-write n 0x0 0x0 USB_FIFO4_EPDATA Endpoint Data 0 32 USB0FIFO5 USB FIFO Endpoint 5 0x34 read-write n 0x0 0x0 USB_FIFO5_EPDATA Endpoint Data 0 32 USB0FIFO6 USB FIFO Endpoint 6 0x38 read-write n 0x0 0x0 USB_FIFO6_EPDATA Endpoint Data 0 32 USB0FIFO7 USB FIFO Endpoint 7 0x3C read-write n 0x0 0x0 USB_FIFO7_EPDATA Endpoint Data 0 32 USB0FRAME USB Frame Value 0xC 16 read-write n 0x0 0x0 USB_FRAME Frame Number 0 11 USB0FSEOF USB Full-Speed Last Transaction to End of Frame Timing 0x7D 8 read-write n 0x0 0x0 USB_FSEOF_FSEOFG Full-Speed End-of-Frame Gap 0 8 USB0GPCS USB General-Purpose Control and Status 0x41C read-write n 0x0 0x0 USB_GPCS_DEVMOD Device Mode 0 3 USB_GPCS_DEVMOD_OTG Use USB0VBUS and USB0ID pin 0x0 USB_GPCS_DEVMOD_HOST Force USB0VBUS and USB0ID low 0x2 USB_GPCS_DEVMOD_DEV Force USB0VBUS and USB0ID high 0x3 USB_GPCS_DEVMOD_HOSTVBUS Use USB0VBUS and force USB0ID low 0x4 USB_GPCS_DEVMOD_DEVVBUS Use USB0VBUS and force USB0ID high 0x5 USB0HHSRTN USB High Speed to UTM Operating Delay 0x346 16 read-write n 0x0 0x0 USB_HHSRTN_HHSRTN HIgh Speed to UTM Operating Delay 0 16 USB0HSBT USB High Speed Time-out Adder 0x348 16 read-write n 0x0 0x0 USB_HSBT_HSBT High Speed Timeout Adder 0 4 USB0HSEOF USB High-Speed Last Transaction to End of Frame Timing 0x7C 8 read-write n 0x0 0x0 USB_HSEOF_HSEOFG HIgh-Speed End-of-Frame Gap 0 8 USB0IE USB Interrupt Enable 0xB 8 read-write n 0x0 0x0 USB_IE_BABBLE Enable Babble Interrupt 2 3 USB_IE_CONN Enable Connect Interrupt 4 5 USB_IE_DISCON Enable Disconnect Interrupt 5 6 USB_IE_RESUME Enable RESUME Interrupt 1 2 USB_IE_SESREQ Enable Session Request (OTG only) 6 7 USB_IE_SOF Enable Start-of-Frame Interrupt 3 4 USB_IE_SUSPND Enable SUSPEND Interrupt 0 1 USB_IE_VBUSERR Enable VBUS Error Interrupt (OTG only) 7 8 USB0IS USB General Interrupt Status 0xA 8 read-write n 0x0 0x0 USB_IS_BABBLE Babble Detected 2 3 USB_IS_CONN Session Connect 4 5 USB_IS_DISCON Session Disconnect (OTG only) 5 6 USB_IS_RESUME RESUME Signaling Detected 1 2 USB_IS_SESREQ SESSION REQUEST (OTG only) 6 7 USB_IS_SOF Start of Frame 3 4 USB_IS_SUSPEND SUSPEND Signaling Detected 0 1 USB_IS_VBUSERR VBUS Error (OTG only) 7 8 USB0LPMATTR USB LPM Attributes 0x360 16 read-write n 0x0 0x0 USB_LPMATTR_ENDPT Endpoint 12 16 USB_LPMATTR_HIRD Host Initiated Resume Duration 4 8 USB_LPMATTR_LS Link State 0 4 USB_LPMATTR_LS_L1 Sleep State (L1) 0x1 USB_LPMATTR_RMTWAK Remote Wake 8 9 USB0LPMCNTRL USB LPM Control 0x362 8 read-write n 0x0 0x0 USB_LPMCNTRL_EN LPM Enable 2 4 USB_LPMCNTRL_EN_NONE LPM and Extended transactions are not supported. In this case, the USB does not respond to LPM transactions and LPM transactions cause a timeout 0x0 USB_LPMCNTRL_EN_EXT LPM is not supported but extended transactions are supported. In this case, the USB does respond to an LPM transaction with a STALL 0x1 USB_LPMCNTRL_EN_LPMEXT The USB supports LPM extended transactions. In this case, the USB responds with a NYET or an ACK as determined by the value of TXLPM and other conditions 0x3 USB_LPMCNTRL_NAK LPM NAK 4 5 USB_LPMCNTRL_RES LPM Resume 1 2 USB_LPMCNTRL_TXLPM Transmit LPM Transaction Enable 0 1 USB0LPMFADDR USB LPM Function Address 0x365 8 read-write n 0x0 0x0 USB_LPMFADDR_ADDR LPM Function Address 0 7 USB0LPMIM USB LPM Interrupt Mask 0x363 8 read-write n 0x0 0x0 USB_LPMIM_ACK LPM ACK Interrupt Mask 2 3 USB_LPMIM_ERR LPM Error Interrupt Mask 5 6 USB_LPMIM_NC LPM NC Interrupt Mask 3 4 USB_LPMIM_NY LPM NY Interrupt Mask 1 2 USB_LPMIM_RES LPM Resume Interrupt Mask 4 5 USB_LPMIM_STALL LPM STALL Interrupt Mask 0 1 USB0LPMRIS USB LPM Raw Interrupt Status 0x364 8 read-write n 0x0 0x0 USB_LPMRIS_ACK LPM ACK Interrupt Status 2 3 USB_LPMRIS_ERR LPM Interrupt Status 5 6 USB_LPMRIS_LPMST LPM STALL Interrupt Status 0 1 USB_LPMRIS_NC LPM NC Interrupt Status 3 4 USB_LPMRIS_NY LPM NY Interrupt Status 1 2 USB_LPMRIS_RES LPM Resume Interrupt Status 4 5 USB0LSEOF USB Low-Speed Last Transaction to End of Frame Timing 0x7E 8 read-write n 0x0 0x0 USB_LSEOF_LSEOFG Low-Speed End-of-Frame Gap 0 8 USB0NAKLMT USB NAK Limit 0x10B 8 read-write n 0x0 0x0 USB_NAKLMT_NAKLMT EP0 NAK Limit 0 5 USB0PC USB Peripheral Configuration 0xFC4 read-write n 0x0 0x0 USB_PC_ULPIEN ULPI Enable 16 17 USB0POWER USB Power 0x1 8 read-write n 0x0 0x0 USB_POWER_HSENAB High Speed Enable 5 6 USB_POWER_HSMODE High Speed Enable 4 5 USB_POWER_ISOUP Isochronous Update 7 8 USB_POWER_PWRDNPHY Power Down PHY 0 1 USB_POWER_RESET RESET Signaling 3 4 USB_POWER_RESUME RESUME Signaling 2 3 USB_POWER_SOFTCONN Soft Connect/Disconnect 6 7 USB_POWER_SUSPEND SUSPEND Mode 1 2 USB0PP USB Peripheral Properties 0xFC0 read-write n 0x0 0x0 USB_PP_ECNT Endpoint Count 8 16 USB_PP_PHY PHY Present 4 5 USB_PP_TYPE Controller Type 0 4 USB_PP_TYPE_0 The first-generation USB controller 0x0 USB_PP_TYPE_1 Second-generation USB controller.The controller implemented in post Icestorm devices that use the 3.0 version of the Mentor controller 0x1 USB_PP_ULPI ULPI Present 5 6 USB_PP_USB USB Capability 6 8 USB_PP_USB_DEVICE DEVICE 0x1 USB_PP_USB_HOSTDEVICE HOST 0x2 USB_PP_USB_OTG OTG 0x3 USB0RAMINFO USB RAM Information 0x79 8 read-write n 0x0 0x0 USB_RAMINFO_DMACHAN DMA Channels 4 8 USB_RAMINFO_RAMBITS RAM Address Bus Width 0 4 USB0RQPKTCOUNT1 USB Request Packet Count in Block Transfer Endpoint 1 0x304 16 read-write n 0x0 0x0 USB_RQPKTCOUNT1 Block Transfer Packet Count 0 16 USB0RQPKTCOUNT2 USB Request Packet Count in Block Transfer Endpoint 2 0x308 16 read-write n 0x0 0x0 USB_RQPKTCOUNT2 Block Transfer Packet Count 0 16 USB0RQPKTCOUNT3 USB Request Packet Count in Block Transfer Endpoint 3 0x30C 16 read-write n 0x0 0x0 USB_RQPKTCOUNT3 Block Transfer Packet Count 0 16 USB0RQPKTCOUNT4 USB Request Packet Count in Block Transfer Endpoint 4 0x310 16 read-write n 0x0 0x0 USB_RQPKTCOUNT4_COUNT Block Transfer Packet Count 0 16 USB0RQPKTCOUNT5 USB Request Packet Count in Block Transfer Endpoint 5 0x314 16 read-write n 0x0 0x0 USB_RQPKTCOUNT5_COUNT Block Transfer Packet Count 0 16 USB0RQPKTCOUNT6 USB Request Packet Count in Block Transfer Endpoint 6 0x318 16 read-write n 0x0 0x0 USB_RQPKTCOUNT6_COUNT Block Transfer Packet Count 0 16 USB0RQPKTCOUNT7 USB Request Packet Count in Block Transfer Endpoint 7 0x31C 16 read-write n 0x0 0x0 USB_RQPKTCOUNT7_COUNT Block Transfer Packet Count 0 16 USB0RXCOUNT1 USB Receive Byte Count Endpoint 1 0x118 16 read-write n 0x0 0x0 USB_RXCOUNT1_COUNT Receive Packet Count 0 13 USB0RXCOUNT2 USB Receive Byte Count Endpoint 2 0x128 16 read-write n 0x0 0x0 USB_RXCOUNT2_COUNT Receive Packet Count 0 13 USB0RXCOUNT3 USB Receive Byte Count Endpoint 3 0x138 16 read-write n 0x0 0x0 USB_RXCOUNT3_COUNT Receive Packet Count 0 13 USB0RXCOUNT4 USB Receive Byte Count Endpoint 4 0x148 16 read-write n 0x0 0x0 USB_RXCOUNT4_COUNT Receive Packet Count 0 13 USB0RXCOUNT5 USB Receive Byte Count Endpoint 5 0x158 16 read-write n 0x0 0x0 USB_RXCOUNT5_COUNT Receive Packet Count 0 13 USB0RXCOUNT6 USB Receive Byte Count Endpoint 6 0x168 16 read-write n 0x0 0x0 USB_RXCOUNT6_COUNT Receive Packet Count 0 13 USB0RXCOUNT7 USB Receive Byte Count Endpoint 7 0x178 16 read-write n 0x0 0x0 USB_RXCOUNT7_COUNT Receive Packet Count 0 13 USB0RXCSRH1 USB Receive Control and Status Endpoint 1 High 0x117 8 read-write n 0x0 0x0 USB_RXCSRH1_AUTOCL Auto Clear 7 8 USB_RXCSRH1_AUTORQ Auto Request 6 7 USB_RXCSRH1_DMAEN DMA Request Enable 5 6 USB_RXCSRH1_DMAMOD DMA Request Mode 3 4 USB_RXCSRH1_DT Data Toggle 1 2 USB_RXCSRH1_DTWE Data Toggle Write Enable 2 3 USB_RXCSRH1_INCOMPRX Incomplete RX Transmission Status 0 1 USB_RXCSRH1_PIDERR PID Error 4 5 USB0RXCSRH2 USB Receive Control and Status Endpoint 2 High 0x127 8 read-write n 0x0 0x0 USB_RXCSRH2_AUTOCL Auto Clear 7 8 USB_RXCSRH2_AUTORQ Auto Request 6 7 USB_RXCSRH2_DMAEN DMA Request Enable 5 6 USB_RXCSRH2_DMAMOD DMA Request Mode 3 4 USB_RXCSRH2_DT Data Toggle 1 2 USB_RXCSRH2_DTWE Data Toggle Write Enable 2 3 USB_RXCSRH2_INCOMPRX Incomplete RX Transmission Status 0 1 USB_RXCSRH2_PIDERR PID Error 4 5 USB0RXCSRH3 USB Receive Control and Status Endpoint 3 High 0x137 8 read-write n 0x0 0x0 USB_RXCSRH3_AUTOCL Auto Clear 7 8 USB_RXCSRH3_AUTORQ Auto Request 6 7 USB_RXCSRH3_DMAEN DMA Request Enable 5 6 USB_RXCSRH3_DMAMOD DMA Request Mode 3 4 USB_RXCSRH3_DT Data Toggle 1 2 USB_RXCSRH3_DTWE Data Toggle Write Enable 2 3 USB_RXCSRH3_INCOMPRX Incomplete RX Transmission Status 0 1 USB_RXCSRH3_PIDERR PID Error 4 5 USB0RXCSRH4 USB Receive Control and Status Endpoint 4 High 0x147 8 read-write n 0x0 0x0 USB_RXCSRH4_AUTOCL Auto Clear 7 8 USB_RXCSRH4_AUTORQ Auto Request 6 7 USB_RXCSRH4_DMAEN DMA Request Enable 5 6 USB_RXCSRH4_DMAMOD DMA Request Mode 3 4 USB_RXCSRH4_DT Data Toggle 1 2 USB_RXCSRH4_DTWE Data Toggle Write Enable 2 3 USB_RXCSRH4_INCOMPRX Incomplete RX Transmission Status 0 1 USB_RXCSRH4_PIDERR PID Error 4 5 USB0RXCSRH5 USB Receive Control and Status Endpoint 5 High 0x157 8 read-write n 0x0 0x0 USB_RXCSRH5_AUTOCL Auto Clear 7 8 USB_RXCSRH5_AUTORQ Auto Request 6 7 USB_RXCSRH5_DMAEN DMA Request Enable 5 6 USB_RXCSRH5_DMAMOD DMA Request Mode 3 4 USB_RXCSRH5_DT Data Toggle 1 2 USB_RXCSRH5_DTWE Data Toggle Write Enable 2 3 USB_RXCSRH5_INCOMPRX Incomplete RX Transmission Status 0 1 USB_RXCSRH5_PIDERR PID Error 4 5 USB0RXCSRH6 USB Receive Control and Status Endpoint 6 High 0x167 8 read-write n 0x0 0x0 USB_RXCSRH6_AUTOCL Auto Clear 7 8 USB_RXCSRH6_AUTORQ Auto Request 6 7 USB_RXCSRH6_DMAEN DMA Request Enable 5 6 USB_RXCSRH6_DMAMOD DMA Request Mode 3 4 USB_RXCSRH6_DT Data Toggle 1 2 USB_RXCSRH6_DTWE Data Toggle Write Enable 2 3 USB_RXCSRH6_INCOMPRX Incomplete RX Transmission Status 0 1 USB_RXCSRH6_PIDERR PID Error 4 5 USB0RXCSRH7 USB Receive Control and Status Endpoint 7 High 0x177 8 read-write n 0x0 0x0 USB_RXCSRH7_AUTOCL Auto Clear 7 8 USB_RXCSRH7_AUTORQ Auto Request 6 7 USB_RXCSRH7_DMAEN DMA Request Enable 5 6 USB_RXCSRH7_DMAMOD DMA Request Mode 3 4 USB_RXCSRH7_DT Data Toggle 1 2 USB_RXCSRH7_DTWE Data Toggle Write Enable 2 3 USB_RXCSRH7_INCOMPRX Incomplete RX Transmission Status 0 1 USB_RXCSRH7_PIDERR PID Error 4 5 USB0RXCSRL1 USB Receive Control and Status Endpoint 1 Low 0x116 8 read-write n 0x0 0x0 USB_RXCSRL1_CLRDT Clear Data Toggle 7 8 USB_RXCSRL1_DATAERR Data Error 3 4 USB_RXCSRL1_FLUSH Flush FIFO 4 5 USB_RXCSRL1_FULL FIFO Full 1 2 USB_RXCSRL1_OVER Overrun 2 3 USB_RXCSRL1_RXRDY Receive Packet Ready 0 1 USB_RXCSRL1_STALL Send STALL 5 6 USB_RXCSRL1_STALLED Endpoint Stalled 6 7 USB0RXCSRL2 USB Receive Control and Status Endpoint 2 Low 0x126 8 read-write n 0x0 0x0 USB_RXCSRL2_CLRDT Clear Data Toggle 7 8 USB_RXCSRL2_DATAERR Data Error 3 4 USB_RXCSRL2_FLUSH Flush FIFO 4 5 USB_RXCSRL2_FULL FIFO Full 1 2 USB_RXCSRL2_OVER Overrun 2 3 USB_RXCSRL2_RXRDY Receive Packet Ready 0 1 USB_RXCSRL2_STALL Send STALL 5 6 USB_RXCSRL2_STALLED Endpoint Stalled 6 7 USB0RXCSRL3 USB Receive Control and Status Endpoint 3 Low 0x136 8 read-write n 0x0 0x0 USB_RXCSRL3_CLRDT Clear Data Toggle 7 8 USB_RXCSRL3_DATAERR Data Error 3 4 USB_RXCSRL3_FLUSH Flush FIFO 4 5 USB_RXCSRL3_FULL FIFO Full 1 2 USB_RXCSRL3_OVER Overrun 2 3 USB_RXCSRL3_RXRDY Receive Packet Ready 0 1 USB_RXCSRL3_STALL Send STALL 5 6 USB_RXCSRL3_STALLED Endpoint Stalled 6 7 USB0RXCSRL4 USB Receive Control and Status Endpoint 4 Low 0x146 8 read-write n 0x0 0x0 USB_RXCSRL4_CLRDT Clear Data Toggle 7 8 USB_RXCSRL4_DATAERR Data Error 3 4 USB_RXCSRL4_FLUSH Flush FIFO 4 5 USB_RXCSRL4_FULL FIFO Full 1 2 USB_RXCSRL4_OVER Overrun 2 3 USB_RXCSRL4_RXRDY Receive Packet Ready 0 1 USB_RXCSRL4_STALL Send STALL 5 6 USB_RXCSRL4_STALLED Endpoint Stalled 6 7 USB0RXCSRL5 USB Receive Control and Status Endpoint 5 Low 0x156 8 read-write n 0x0 0x0 USB_RXCSRL5_CLRDT Clear Data Toggle 7 8 USB_RXCSRL5_DATAERR Data Error 3 4 USB_RXCSRL5_FLUSH Flush FIFO 4 5 USB_RXCSRL5_FULL FIFO Full 1 2 USB_RXCSRL5_OVER Overrun 2 3 USB_RXCSRL5_RXRDY Receive Packet Ready 0 1 USB_RXCSRL5_STALL Send STALL 5 6 USB_RXCSRL5_STALLED Endpoint Stalled 6 7 USB0RXCSRL6 USB Receive Control and Status Endpoint 6 Low 0x166 8 read-write n 0x0 0x0 USB_RXCSRL6_CLRDT Clear Data Toggle 7 8 USB_RXCSRL6_DATAERR Data Error 3 4 USB_RXCSRL6_FLUSH Flush FIFO 4 5 USB_RXCSRL6_FULL FIFO Full 1 2 USB_RXCSRL6_OVER Overrun 2 3 USB_RXCSRL6_RXRDY Receive Packet Ready 0 1 USB_RXCSRL6_STALL Send STALL 5 6 USB_RXCSRL6_STALLED Endpoint Stalled 6 7 USB0RXCSRL7 USB Receive Control and Status Endpoint 7 Low 0x176 8 read-write n 0x0 0x0 USB_RXCSRL7_CLRDT Clear Data Toggle 7 8 USB_RXCSRL7_DATAERR Data Error 3 4 USB_RXCSRL7_FLUSH Flush FIFO 4 5 USB_RXCSRL7_FULL FIFO Full 1 2 USB_RXCSRL7_OVER Overrun 2 3 USB_RXCSRL7_RXRDY Receive Packet Ready 0 1 USB_RXCSRL7_STALL Send STALL 5 6 USB_RXCSRL7_STALLED Endpoint Stalled 6 7 USB0RXDPKTBUFDIS USB Receive Double Packet Buffer Disable 0x340 16 read-write n 0x0 0x0 USB_RXDPKTBUFDIS_EP1 EP1 RX Double-Packet Buffer Disable 1 2 USB_RXDPKTBUFDIS_EP2 EP2 RX Double-Packet Buffer Disable 2 3 USB_RXDPKTBUFDIS_EP3 EP3 RX Double-Packet Buffer Disable 3 4 USB_RXDPKTBUFDIS_EP4 EP4 RX Double-Packet Buffer Disable 4 5 USB_RXDPKTBUFDIS_EP5 EP5 RX Double-Packet Buffer Disable 5 6 USB_RXDPKTBUFDIS_EP6 EP6 RX Double-Packet Buffer Disable 6 7 USB_RXDPKTBUFDIS_EP7 EP7 RX Double-Packet Buffer Disable 7 8 USB0RXFIFOADD USB Receive FIFO Start Address 0x66 16 read-write n 0x0 0x0 USB_RXFIFOADD_ADDR Transmit/Receive Start Address 0 9 USB0RXFIFOSZ USB Receive Dynamic FIFO Sizing 0x63 8 read-write n 0x0 0x0 USB_RXFIFOSZ_DPB Double Packet Buffer Support 4 5 USB_RXFIFOSZ_SIZE Max Packet Size 0 4 USB_RXFIFOSZ_SIZE_8 8 0x0 USB_RXFIFOSZ_SIZE_16 16 0x1 USB_RXFIFOSZ_SIZE_32 32 0x2 USB_RXFIFOSZ_SIZE_64 64 0x3 USB_RXFIFOSZ_SIZE_128 128 0x4 USB_RXFIFOSZ_SIZE_256 256 0x5 USB_RXFIFOSZ_SIZE_512 512 0x6 USB_RXFIFOSZ_SIZE_1024 1024 0x7 USB_RXFIFOSZ_SIZE_2048 2048 0x8 USB0RXFUNCADDR1 USB Receive Functional Address Endpoint 1 0x8C 8 read-write n 0x0 0x0 USB_RXFUNCADDR1_ADDR Device Address 0 7 USB0RXFUNCADDR2 USB Receive Functional Address Endpoint 2 0x94 8 read-write n 0x0 0x0 USB_RXFUNCADDR2_ADDR Device Address 0 7 USB0RXFUNCADDR3 USB Receive Functional Address Endpoint 3 0x9C 8 read-write n 0x0 0x0 USB_RXFUNCADDR3_ADDR Device Address 0 7 USB0RXFUNCADDR4 USB Receive Functional Address Endpoint 4 0xA4 8 read-write n 0x0 0x0 USB_RXFUNCADDR4_ADDR Device Address 0 7 USB0RXFUNCADDR5 USB Receive Functional Address Endpoint 5 0xAC 8 read-write n 0x0 0x0 USB_RXFUNCADDR5_ADDR Device Address 0 7 USB0RXFUNCADDR6 USB Receive Functional Address Endpoint 6 0xB4 8 read-write n 0x0 0x0 USB_RXFUNCADDR6_ADDR Device Address 0 7 USB0RXFUNCADDR7 USB Receive Functional Address Endpoint 7 0xBC 8 read-write n 0x0 0x0 USB_RXFUNCADDR7_ADDR Device Address 0 7 USB0RXHUBADDR1 USB Receive Hub Address Endpoint 1 0x8E 8 read-write n 0x0 0x0 USB_RXHUBADDR1_ADDR Hub Address 0 7 USB0RXHUBADDR2 USB Receive Hub Address Endpoint 2 0x96 8 read-write n 0x0 0x0 USB_RXHUBADDR2_ADDR Hub Address 0 7 USB0RXHUBADDR3 USB Receive Hub Address Endpoint 3 0x9E 8 read-write n 0x0 0x0 USB_RXHUBADDR3_ADDR Hub Address 0 7 USB0RXHUBADDR4 USB Receive Hub Address Endpoint 4 0xA6 8 read-write n 0x0 0x0 USB_RXHUBADDR4_ADDR Hub Address 0 7 USB0RXHUBADDR5 USB Receive Hub Address Endpoint 5 0xAE 8 read-write n 0x0 0x0 USB_RXHUBADDR5_ADDR Hub Address 0 7 USB0RXHUBADDR6 USB Receive Hub Address Endpoint 6 0xB6 8 read-write n 0x0 0x0 USB_RXHUBADDR6_ADDR Hub Address 0 7 USB0RXHUBADDR7 USB Receive Hub Address Endpoint 7 0xBE 8 read-write n 0x0 0x0 USB_RXHUBADDR7_ADDR Hub Address 0 7 USB0RXHUBPORT1 USB Receive Hub Port Endpoint 1 0x8F 8 read-write n 0x0 0x0 USB_RXHUBPORT1_PORT Hub Port 0 7 USB0RXHUBPORT2 USB Receive Hub Port Endpoint 2 0x97 8 read-write n 0x0 0x0 USB_RXHUBPORT2_PORT Hub Port 0 7 USB0RXHUBPORT3 USB Receive Hub Port Endpoint 3 0x9F 8 read-write n 0x0 0x0 USB_RXHUBPORT3_PORT Hub Port 0 7 USB0RXHUBPORT4 USB Receive Hub Port Endpoint 4 0xA7 8 read-write n 0x0 0x0 USB_RXHUBPORT4_PORT Hub Port 0 7 USB0RXHUBPORT5 USB Receive Hub Port Endpoint 5 0xAF 8 read-write n 0x0 0x0 USB_RXHUBPORT5_PORT Hub Port 0 7 USB0RXHUBPORT6 USB Receive Hub Port Endpoint 6 0xB7 8 read-write n 0x0 0x0 USB_RXHUBPORT6_PORT Hub Port 0 7 USB0RXHUBPORT7 USB Receive Hub Port Endpoint 7 0xBF 8 read-write n 0x0 0x0 USB_RXHUBPORT7_PORT Hub Port 0 7 USB0RXIE USB Receive Interrupt Enable 0x8 16 read-write n 0x0 0x0 USB_RXIE_EP1 RX Endpoint 1 Interrupt Enable 1 2 USB_RXIE_EP2 RX Endpoint 2 Interrupt Enable 2 3 USB_RXIE_EP3 RX Endpoint 3 Interrupt Enable 3 4 USB_RXIE_EP4 RX Endpoint 4 Interrupt Enable 4 5 USB_RXIE_EP5 RX Endpoint 5 Interrupt Enable 5 6 USB_RXIE_EP6 RX Endpoint 6 Interrupt Enable 6 7 USB_RXIE_EP7 RX Endpoint 7 Interrupt Enable 7 8 USB0RXINTERVAL1 USB Host Receive Polling Interval Endpoint 1 0x11D 8 read-write n 0x0 0x0 USB_RXINTERVAL1_TXPOLL RX Polling 0 8 USB0RXINTERVAL2 USB Host Receive Polling Interval Endpoint 2 0x12D 8 read-write n 0x0 0x0 USB_RXINTERVAL2_TXPOLL RX Polling 0 8 USB0RXINTERVAL3 USB Host Receive Polling Interval Endpoint 3 0x13D 8 read-write n 0x0 0x0 USB_RXINTERVAL3_TXPOLL RX Polling 0 8 USB0RXINTERVAL4 USB Host Receive Polling Interval Endpoint 4 0x14D 8 read-write n 0x0 0x0 USB_RXINTERVAL4_TXPOLL RX Polling 0 8 USB0RXINTERVAL5 USB Host Receive Polling Interval Endpoint 5 0x15D 8 read-write n 0x0 0x0 USB_RXINTERVAL5_TXPOLL RX Polling 0 8 USB0RXINTERVAL6 USB Host Receive Polling Interval Endpoint 6 0x16D 8 read-write n 0x0 0x0 USB_RXINTERVAL6_TXPOLL RX Polling 0 8 USB0RXINTERVAL7 USB Host Receive Polling Interval Endpoint 7 0x17D 8 read-write n 0x0 0x0 USB_RXINTERVAL7_TXPOLL RX Polling 0 8 USB0RXIS USB Receive Interrupt Status 0x4 16 read-write n 0x0 0x0 USB_RXIS_EP1 RX Endpoint 1 Interrupt 1 2 USB_RXIS_EP2 RX Endpoint 2 Interrupt 2 3 USB_RXIS_EP3 RX Endpoint 3 Interrupt 3 4 USB_RXIS_EP4 RX Endpoint 4 Interrupt 4 5 USB_RXIS_EP5 RX Endpoint 5 Interrupt 5 6 USB_RXIS_EP6 RX Endpoint 6 Interrupt 6 7 USB_RXIS_EP7 RX Endpoint 7 Interrupt 7 8 USB0RXMAXP1 USB Maximum Receive Data Endpoint 1 0x114 16 read-write n 0x0 0x0 USB_RXMAXP1_MAXLOAD Maximum Payload 0 11 USB0RXMAXP2 USB Maximum Receive Data Endpoint 2 0x124 16 read-write n 0x0 0x0 USB_RXMAXP2_MAXLOAD Maximum Payload 0 11 USB0RXMAXP3 USB Maximum Receive Data Endpoint 3 0x134 16 read-write n 0x0 0x0 USB_RXMAXP3_MAXLOAD Maximum Payload 0 11 USB0RXMAXP4 USB Maximum Receive Data Endpoint 4 0x144 16 read-write n 0x0 0x0 USB_RXMAXP4_MAXLOAD Maximum Payload 0 11 USB0RXMAXP5 USB Maximum Receive Data Endpoint 5 0x154 16 read-write n 0x0 0x0 USB_RXMAXP5_MAXLOAD Maximum Payload 0 11 USB0RXMAXP6 USB Maximum Receive Data Endpoint 6 0x164 16 read-write n 0x0 0x0 USB_RXMAXP6_MAXLOAD Maximum Payload 0 11 USB0RXMAXP7 USB Maximum Receive Data Endpoint 7 0x174 16 read-write n 0x0 0x0 USB_RXMAXP7_MAXLOAD Maximum Payload 0 11 USB0RXTYPE1 USB Host Configure Receive Type Endpoint 1 0x11C 8 read-write n 0x0 0x0 USB_RXTYPE1_PROTO Protocol 4 6 USB_RXTYPE1_PROTO_CTRL Control 0x0 USB_RXTYPE1_PROTO_ISOC Isochronous 0x1 USB_RXTYPE1_PROTO_BULK Bulk 0x2 USB_RXTYPE1_PROTO_INT Interrupt 0x3 USB_RXTYPE1_SPEED Operating Speed 6 8 USB_RXTYPE1_SPEED_DFLT Default 0x0 USB_RXTYPE1_SPEED_HIGH High 0x1 USB_RXTYPE1_SPEED_FULL Full 0x2 USB_RXTYPE1_SPEED_LOW Low 0x3 USB_RXTYPE1_TEP Target Endpoint Number 0 4 USB0RXTYPE2 USB Host Configure Receive Type Endpoint 2 0x12C 8 read-write n 0x0 0x0 USB_RXTYPE2_PROTO Protocol 4 6 USB_RXTYPE2_PROTO_CTRL Control 0x0 USB_RXTYPE2_PROTO_ISOC Isochronous 0x1 USB_RXTYPE2_PROTO_BULK Bulk 0x2 USB_RXTYPE2_PROTO_INT Interrupt 0x3 USB_RXTYPE2_SPEED Operating Speed 6 8 USB_RXTYPE2_SPEED_DFLT Default 0x0 USB_RXTYPE2_SPEED_HIGH High 0x1 USB_RXTYPE2_SPEED_FULL Full 0x2 USB_RXTYPE2_SPEED_LOW Low 0x3 USB_RXTYPE2_TEP Target Endpoint Number 0 4 USB0RXTYPE3 USB Host Configure Receive Type Endpoint 3 0x13C 8 read-write n 0x0 0x0 USB_RXTYPE3_PROTO Protocol 4 6 USB_RXTYPE3_PROTO_CTRL Control 0x0 USB_RXTYPE3_PROTO_ISOC Isochronous 0x1 USB_RXTYPE3_PROTO_BULK Bulk 0x2 USB_RXTYPE3_PROTO_INT Interrupt 0x3 USB_RXTYPE3_SPEED Operating Speed 6 8 USB_RXTYPE3_SPEED_DFLT Default 0x0 USB_RXTYPE3_SPEED_HIGH High 0x1 USB_RXTYPE3_SPEED_FULL Full 0x2 USB_RXTYPE3_SPEED_LOW Low 0x3 USB_RXTYPE3_TEP Target Endpoint Number 0 4 USB0RXTYPE4 USB Host Configure Receive Type Endpoint 4 0x14C 8 read-write n 0x0 0x0 USB_RXTYPE4_PROTO Protocol 4 6 USB_RXTYPE4_PROTO_CTRL Control 0x0 USB_RXTYPE4_PROTO_ISOC Isochronous 0x1 USB_RXTYPE4_PROTO_BULK Bulk 0x2 USB_RXTYPE4_PROTO_INT Interrupt 0x3 USB_RXTYPE4_SPEED Operating Speed 6 8 USB_RXTYPE4_SPEED_DFLT Default 0x0 USB_RXTYPE4_SPEED_HIGH High 0x1 USB_RXTYPE4_SPEED_FULL Full 0x2 USB_RXTYPE4_SPEED_LOW Low 0x3 USB_RXTYPE4_TEP Target Endpoint Number 0 4 USB0RXTYPE5 USB Host Configure Receive Type Endpoint 5 0x15C 8 read-write n 0x0 0x0 USB_RXTYPE5_PROTO Protocol 4 6 USB_RXTYPE5_PROTO_CTRL Control 0x0 USB_RXTYPE5_PROTO_ISOC Isochronous 0x1 USB_RXTYPE5_PROTO_BULK Bulk 0x2 USB_RXTYPE5_PROTO_INT Interrupt 0x3 USB_RXTYPE5_SPEED Operating Speed 6 8 USB_RXTYPE5_SPEED_DFLT Default 0x0 USB_RXTYPE5_SPEED_HIGH High 0x1 USB_RXTYPE5_SPEED_FULL Full 0x2 USB_RXTYPE5_SPEED_LOW Low 0x3 USB_RXTYPE5_TEP Target Endpoint Number 0 4 USB0RXTYPE6 USB Host Configure Receive Type Endpoint 6 0x16C 8 read-write n 0x0 0x0 USB_RXTYPE6_PROTO Protocol 4 6 USB_RXTYPE6_PROTO_CTRL Control 0x0 USB_RXTYPE6_PROTO_ISOC Isochronous 0x1 USB_RXTYPE6_PROTO_BULK Bulk 0x2 USB_RXTYPE6_PROTO_INT Interrupt 0x3 USB_RXTYPE6_SPEED Operating Speed 6 8 USB_RXTYPE6_SPEED_DFLT Default 0x0 USB_RXTYPE6_SPEED_HIGH High 0x1 USB_RXTYPE6_SPEED_FULL Full 0x2 USB_RXTYPE6_SPEED_LOW Low 0x3 USB_RXTYPE6_TEP Target Endpoint Number 0 4 USB0RXTYPE7 USB Host Configure Receive Type Endpoint 7 0x17C 8 read-write n 0x0 0x0 USB_RXTYPE7_PROTO Protocol 4 6 USB_RXTYPE7_PROTO_CTRL Control 0x0 USB_RXTYPE7_PROTO_ISOC Isochronous 0x1 USB_RXTYPE7_PROTO_BULK Bulk 0x2 USB_RXTYPE7_PROTO_INT Interrupt 0x3 USB_RXTYPE7_SPEED Operating Speed 6 8 USB_RXTYPE7_SPEED_DFLT Default 0x0 USB_RXTYPE7_SPEED_HIGH High 0x1 USB_RXTYPE7_SPEED_FULL Full 0x2 USB_RXTYPE7_SPEED_LOW Low 0x3 USB_RXTYPE7_TEP Target Endpoint Number 0 4 USB0TEST USB Test Mode 0xF 8 read-write n 0x0 0x0 USB_TEST_FIFOACC FIFO Access 6 7 USB_TEST_FORCEFS Force Full-Speed Mode 5 6 USB_TEST_FORCEH Force Host Mode 7 8 USB_TEST_FORCEHS Force High-Speed Mode 4 5 USB_TEST_TESTJ Test_J Mode Enable 1 2 USB_TEST_TESTK Test_K Mode Enable 2 3 USB_TEST_TESTPKT Test Packet Mode Enable 3 4 USB_TEST_TESTSE0NAK Test_SE0_NAK Test Mode Enable 0 1 USB0TXCSRH1 USB Transmit Control and Status Endpoint 1 High 0x113 8 read-write n 0x0 0x0 USB_TXCSRH1_AUTOSET Auto Set 7 8 USB_TXCSRH1_DMAEN DMA Request Enable 4 5 USB_TXCSRH1_DMAMOD DMA Request Mode 2 3 USB_TXCSRH1_DT Data Toggle 0 1 USB_TXCSRH1_DTWE Data Toggle Write Enable 1 2 USB_TXCSRH1_FDT Force Data Toggle 3 4 USB_TXCSRH1_ISO Isochronous Transfers 6 7 USB_TXCSRH1_MODE Mode 5 6 USB0TXCSRH2 USB Transmit Control and Status Endpoint 2 High 0x123 8 read-write n 0x0 0x0 USB_TXCSRH2_AUTOSET Auto Set 7 8 USB_TXCSRH2_DMAEN DMA Request Enable 4 5 USB_TXCSRH2_DMAMOD DMA Request Mode 2 3 USB_TXCSRH2_DT Data Toggle 0 1 USB_TXCSRH2_DTWE Data Toggle Write Enable 1 2 USB_TXCSRH2_FDT Force Data Toggle 3 4 USB_TXCSRH2_ISO Isochronous Transfers 6 7 USB_TXCSRH2_MODE Mode 5 6 USB0TXCSRH3 USB Transmit Control and Status Endpoint 3 High 0x133 8 read-write n 0x0 0x0 USB_TXCSRH3_AUTOSET Auto Set 7 8 USB_TXCSRH3_DMAEN DMA Request Enable 4 5 USB_TXCSRH3_DMAMOD DMA Request Mode 2 3 USB_TXCSRH3_DT Data Toggle 0 1 USB_TXCSRH3_DTWE Data Toggle Write Enable 1 2 USB_TXCSRH3_FDT Force Data Toggle 3 4 USB_TXCSRH3_ISO Isochronous Transfers 6 7 USB_TXCSRH3_MODE Mode 5 6 USB0TXCSRH4 USB Transmit Control and Status Endpoint 4 High 0x143 8 read-write n 0x0 0x0 USB_TXCSRH4_AUTOSET Auto Set 7 8 USB_TXCSRH4_DMAEN DMA Request Enable 4 5 USB_TXCSRH4_DMAMOD DMA Request Mode 2 3 USB_TXCSRH4_DT Data Toggle 0 1 USB_TXCSRH4_DTWE Data Toggle Write Enable 1 2 USB_TXCSRH4_FDT Force Data Toggle 3 4 USB_TXCSRH4_ISO Isochronous Transfers 6 7 USB_TXCSRH4_MODE Mode 5 6 USB0TXCSRH5 USB Transmit Control and Status Endpoint 5 High 0x153 8 read-write n 0x0 0x0 USB_TXCSRH5_AUTOSET Auto Set 7 8 USB_TXCSRH5_DMAEN DMA Request Enable 4 5 USB_TXCSRH5_DMAMOD DMA Request Mode 2 3 USB_TXCSRH5_DT Data Toggle 0 1 USB_TXCSRH5_DTWE Data Toggle Write Enable 1 2 USB_TXCSRH5_FDT Force Data Toggle 3 4 USB_TXCSRH5_ISO Isochronous Transfers 6 7 USB_TXCSRH5_MODE Mode 5 6 USB0TXCSRH6 USB Transmit Control and Status Endpoint 6 High 0x163 8 read-write n 0x0 0x0 USB_TXCSRH6_AUTOSET Auto Set 7 8 USB_TXCSRH6_DMAEN DMA Request Enable 4 5 USB_TXCSRH6_DMAMOD DMA Request Mode 2 3 USB_TXCSRH6_DT Data Toggle 0 1 USB_TXCSRH6_DTWE Data Toggle Write Enable 1 2 USB_TXCSRH6_FDT Force Data Toggle 3 4 USB_TXCSRH6_ISO Isochronous Transfers 6 7 USB_TXCSRH6_MODE Mode 5 6 USB0TXCSRH7 USB Transmit Control and Status Endpoint 7 High 0x173 8 read-write n 0x0 0x0 USB_TXCSRH7_AUTOSET Auto Set 7 8 USB_TXCSRH7_DMAEN DMA Request Enable 4 5 USB_TXCSRH7_DMAMOD DMA Request Mode 2 3 USB_TXCSRH7_DT Data Toggle 0 1 USB_TXCSRH7_DTWE Data Toggle Write Enable 1 2 USB_TXCSRH7_FDT Force Data Toggle 3 4 USB_TXCSRH7_ISO Isochronous Transfers 6 7 USB_TXCSRH7_MODE Mode 5 6 USB0TXCSRL1 USB Transmit Control and Status Endpoint 1 Low 0x112 8 read-write n 0x0 0x0 USB_TXCSRL1_CLRDT Clear Data Toggle 6 7 USB_TXCSRL1_ERROR Error 2 3 USB_TXCSRL1_FIFONE FIFO Not Empty 1 2 USB_TXCSRL1_FLUSH Flush FIFO 3 4 USB_TXCSRL1_NAKTO NAK Timeout 7 8 USB_TXCSRL1_SETUP Setup Packet 4 5 USB_TXCSRL1_STALLED Endpoint Stalled 5 6 USB_TXCSRL1_TXRDY Transmit Packet Ready 0 1 USB0TXCSRL2 USB Transmit Control and Status Endpoint 2 Low 0x122 8 read-write n 0x0 0x0 USB_TXCSRL2_CLRDT Clear Data Toggle 6 7 USB_TXCSRL2_ERROR Error 2 3 USB_TXCSRL2_FIFONE FIFO Not Empty 1 2 USB_TXCSRL2_FLUSH Flush FIFO 3 4 USB_TXCSRL2_NAKTO NAK Timeout 7 8 USB_TXCSRL2_SETUP Setup Packet 4 5 USB_TXCSRL2_STALLED Endpoint Stalled 5 6 USB_TXCSRL2_TXRDY Transmit Packet Ready 0 1 USB0TXCSRL3 USB Transmit Control and Status Endpoint 3 Low 0x132 8 read-write n 0x0 0x0 USB_TXCSRL3_CLRDT Clear Data Toggle 6 7 USB_TXCSRL3_ERROR Error 2 3 USB_TXCSRL3_FIFONE FIFO Not Empty 1 2 USB_TXCSRL3_FLUSH Flush FIFO 3 4 USB_TXCSRL3_NAKTO NAK Timeout 7 8 USB_TXCSRL3_SETUP Setup Packet 4 5 USB_TXCSRL3_STALLED Endpoint Stalled 5 6 USB_TXCSRL3_TXRDY Transmit Packet Ready 0 1 USB0TXCSRL4 USB Transmit Control and Status Endpoint 4 Low 0x142 8 read-write n 0x0 0x0 USB_TXCSRL4_CLRDT Clear Data Toggle 6 7 USB_TXCSRL4_ERROR Error 2 3 USB_TXCSRL4_FIFONE FIFO Not Empty 1 2 USB_TXCSRL4_FLUSH Flush FIFO 3 4 USB_TXCSRL4_NAKTO NAK Timeout 7 8 USB_TXCSRL4_SETUP Setup Packet 4 5 USB_TXCSRL4_STALLED Endpoint Stalled 5 6 USB_TXCSRL4_TXRDY Transmit Packet Ready 0 1 USB0TXCSRL5 USB Transmit Control and Status Endpoint 5 Low 0x152 8 read-write n 0x0 0x0 USB_TXCSRL5_CLRDT Clear Data Toggle 6 7 USB_TXCSRL5_ERROR Error 2 3 USB_TXCSRL5_FIFONE FIFO Not Empty 1 2 USB_TXCSRL5_FLUSH Flush FIFO 3 4 USB_TXCSRL5_NAKTO NAK Timeout 7 8 USB_TXCSRL5_SETUP Setup Packet 4 5 USB_TXCSRL5_STALLED Endpoint Stalled 5 6 USB_TXCSRL5_TXRDY Transmit Packet Ready 0 1 USB0TXCSRL6 USB Transmit Control and Status Endpoint 6 Low 0x162 8 read-write n 0x0 0x0 USB_TXCSRL6_CLRDT Clear Data Toggle 6 7 USB_TXCSRL6_ERROR Error 2 3 USB_TXCSRL6_FIFONE FIFO Not Empty 1 2 USB_TXCSRL6_FLUSH Flush FIFO 3 4 USB_TXCSRL6_NAKTO NAK Timeout 7 8 USB_TXCSRL6_SETUP Setup Packet 4 5 USB_TXCSRL6_STALLED Endpoint Stalled 5 6 USB_TXCSRL6_TXRDY Transmit Packet Ready 0 1 USB0TXCSRL7 USB Transmit Control and Status Endpoint 7 Low 0x172 8 read-write n 0x0 0x0 USB_TXCSRL7_CLRDT Clear Data Toggle 6 7 USB_TXCSRL7_ERROR Error 2 3 USB_TXCSRL7_FIFONE FIFO Not Empty 1 2 USB_TXCSRL7_FLUSH Flush FIFO 3 4 USB_TXCSRL7_NAKTO NAK Timeout 7 8 USB_TXCSRL7_SETUP Setup Packet 4 5 USB_TXCSRL7_STALLED Endpoint Stalled 5 6 USB_TXCSRL7_TXRDY Transmit Packet Ready 0 1 USB0TXDPKTBUFDIS USB Transmit Double Packet Buffer Disable 0x342 16 read-write n 0x0 0x0 USB_TXDPKTBUFDIS_EP1 EP1 TX Double-Packet Buffer Disable 1 2 USB_TXDPKTBUFDIS_EP2 EP2 TX Double-Packet Buffer Disable 2 3 USB_TXDPKTBUFDIS_EP3 EP3 TX Double-Packet Buffer Disable 3 4 USB_TXDPKTBUFDIS_EP4 EP4 TX Double-Packet Buffer Disable 4 5 USB_TXDPKTBUFDIS_EP5 EP5 TX Double-Packet Buffer Disable 5 6 USB_TXDPKTBUFDIS_EP6 EP6 TX Double-Packet Buffer Disable 6 7 USB_TXDPKTBUFDIS_EP7 EP7 TX Double-Packet Buffer Disable 7 8 USB0TXFIFOADD USB Transmit FIFO Start Address 0x64 16 read-write n 0x0 0x0 USB_TXFIFOADD_ADDR Transmit/Receive Start Address 0 9 USB0TXFIFOSZ USB Transmit Dynamic FIFO Sizing 0x62 8 read-write n 0x0 0x0 USB_TXFIFOSZ_DPB Double Packet Buffer Support 4 5 USB_TXFIFOSZ_SIZE Max Packet Size 0 4 USB_TXFIFOSZ_SIZE_8 8 0x0 USB_TXFIFOSZ_SIZE_16 16 0x1 USB_TXFIFOSZ_SIZE_32 32 0x2 USB_TXFIFOSZ_SIZE_64 64 0x3 USB_TXFIFOSZ_SIZE_128 128 0x4 USB_TXFIFOSZ_SIZE_256 256 0x5 USB_TXFIFOSZ_SIZE_512 512 0x6 USB_TXFIFOSZ_SIZE_1024 1024 0x7 USB_TXFIFOSZ_SIZE_2048 2048 0x8 USB0TXFUNCADDR0 USB Transmit Functional Address Endpoint 0 0x80 8 read-write n 0x0 0x0 USB_TXFUNCADDR0_ADDR Device Address 0 7 USB0TXFUNCADDR1 USB Transmit Functional Address Endpoint 1 0x88 8 read-write n 0x0 0x0 USB_TXFUNCADDR1_ADDR Device Address 0 7 USB0TXFUNCADDR2 USB Transmit Functional Address Endpoint 2 0x90 8 read-write n 0x0 0x0 USB_TXFUNCADDR2_ADDR Device Address 0 7 USB0TXFUNCADDR3 USB Transmit Functional Address Endpoint 3 0x98 8 read-write n 0x0 0x0 USB_TXFUNCADDR3_ADDR Device Address 0 7 USB0TXFUNCADDR4 USB Transmit Functional Address Endpoint 4 0xA0 8 read-write n 0x0 0x0 USB_TXFUNCADDR4_ADDR Device Address 0 7 USB0TXFUNCADDR5 USB Transmit Functional Address Endpoint 5 0xA8 8 read-write n 0x0 0x0 USB_TXFUNCADDR5_ADDR Device Address 0 7 USB0TXFUNCADDR6 USB Transmit Functional Address Endpoint 6 0xB0 8 read-write n 0x0 0x0 USB_TXFUNCADDR6_ADDR Device Address 0 7 USB0TXFUNCADDR7 USB Transmit Functional Address Endpoint 7 0xB8 8 read-write n 0x0 0x0 USB_TXFUNCADDR7_ADDR Device Address 0 7 USB0TXHUBADDR0 USB Transmit Hub Address Endpoint 0 0x82 8 read-write n 0x0 0x0 USB_TXHUBADDR0_ADDR Hub Address 0 7 USB0TXHUBADDR1 USB Transmit Hub Address Endpoint 1 0x8A 8 read-write n 0x0 0x0 USB_TXHUBADDR1_ADDR Hub Address 0 7 USB0TXHUBADDR2 USB Transmit Hub Address Endpoint 2 0x92 8 read-write n 0x0 0x0 USB_TXHUBADDR2_ADDR Hub Address 0 7 USB0TXHUBADDR3 USB Transmit Hub Address Endpoint 3 0x9A 8 read-write n 0x0 0x0 USB_TXHUBADDR3_ADDR Hub Address 0 7 USB0TXHUBADDR4 USB Transmit Hub Address Endpoint 4 0xA2 8 read-write n 0x0 0x0 USB_TXHUBADDR4_ADDR Hub Address 0 7 USB0TXHUBADDR5 USB Transmit Hub Address Endpoint 5 0xAA 8 read-write n 0x0 0x0 USB_TXHUBADDR5_ADDR Hub Address 0 7 USB0TXHUBADDR6 USB Transmit Hub Address Endpoint 6 0xB2 8 read-write n 0x0 0x0 USB_TXHUBADDR6_ADDR Hub Address 0 7 USB0TXHUBADDR7 USB Transmit Hub Address Endpoint 7 0xBA 8 read-write n 0x0 0x0 USB_TXHUBADDR7_ADDR Hub Address 0 7 USB0TXHUBPORT0 USB Transmit Hub Port Endpoint 0 0x83 8 read-write n 0x0 0x0 USB_TXHUBPORT0_PORT Hub Port 0 7 USB0TXHUBPORT1 USB Transmit Hub Port Endpoint 1 0x8B 8 read-write n 0x0 0x0 USB_TXHUBPORT1_PORT Hub Port 0 7 USB0TXHUBPORT2 USB Transmit Hub Port Endpoint 2 0x93 8 read-write n 0x0 0x0 USB_TXHUBPORT2_PORT Hub Port 0 7 USB0TXHUBPORT3 USB Transmit Hub Port Endpoint 3 0x9B 8 read-write n 0x0 0x0 USB_TXHUBPORT3_PORT Hub Port 0 7 USB0TXHUBPORT4 USB Transmit Hub Port Endpoint 4 0xA3 8 read-write n 0x0 0x0 USB_TXHUBPORT4_PORT Hub Port 0 7 USB0TXHUBPORT5 USB Transmit Hub Port Endpoint 5 0xAB 8 read-write n 0x0 0x0 USB_TXHUBPORT5_PORT Hub Port 0 7 USB0TXHUBPORT6 USB Transmit Hub Port Endpoint 6 0xB3 8 read-write n 0x0 0x0 USB_TXHUBPORT6_PORT Hub Port 0 7 USB0TXHUBPORT7 USB Transmit Hub Port Endpoint 7 0xBB 8 read-write n 0x0 0x0 USB_TXHUBPORT7_PORT Hub Port 0 7 USB0TXIE USB Transmit Interrupt Enable 0x6 16 read-write n 0x0 0x0 USB_TXIE_EP0 TX and RX Endpoint 0 Interrupt Enable 0 1 USB_TXIE_EP1 TX Endpoint 1 Interrupt Enable 1 2 USB_TXIE_EP2 TX Endpoint 2 Interrupt Enable 2 3 USB_TXIE_EP3 TX Endpoint 3 Interrupt Enable 3 4 USB_TXIE_EP4 TX Endpoint 4 Interrupt Enable 4 5 USB_TXIE_EP5 TX Endpoint 5 Interrupt Enable 5 6 USB_TXIE_EP6 TX Endpoint 6 Interrupt Enable 6 7 USB_TXIE_EP7 TX Endpoint 7 Interrupt Enable 7 8 USB0TXINTERVAL1 USB Host Transmit Interval Endpoint 1 0x11B 8 read-write n 0x0 0x0 USB_TXINTERVAL1_TXPOLL TX Polling 0 8 USB0TXINTERVAL2 USB Host Transmit Interval Endpoint 2 0x12B 8 read-write n 0x0 0x0 USB_TXINTERVAL2_TXPOLL TX Polling 0 8 USB0TXINTERVAL3 USB Host Transmit Interval Endpoint 3 0x13B 8 read-write n 0x0 0x0 USB_TXINTERVAL3_TXPOLL TX Polling 0 8 USB0TXINTERVAL4 USB Host Transmit Interval Endpoint 4 0x14B 8 read-write n 0x0 0x0 USB_TXINTERVAL4_TXPOLL TX Polling 0 8 USB0TXINTERVAL5 USB Host Transmit Interval Endpoint 5 0x15B 8 read-write n 0x0 0x0 USB_TXINTERVAL5_TXPOLL TX Polling 0 8 USB0TXINTERVAL6 USB Host Transmit Interval Endpoint 6 0x16B 8 read-write n 0x0 0x0 USB_TXINTERVAL6_TXPOLL TX Polling 0 8 USB0TXINTERVAL7 USB Host Transmit Interval Endpoint 7 0x17B 8 read-write n 0x0 0x0 USB_TXINTERVAL7_TXPOLL TX Polling 0 8 USB0TXIS USB Transmit Interrupt Status 0x2 16 read-write n 0x0 0x0 USB_TXIS_EP0 TX and RX Endpoint 0 Interrupt 0 1 USB_TXIS_EP1 TX Endpoint 1 Interrupt 1 2 USB_TXIS_EP2 TX Endpoint 2 Interrupt 2 3 USB_TXIS_EP3 TX Endpoint 3 Interrupt 3 4 USB_TXIS_EP4 TX Endpoint 4 Interrupt 4 5 USB_TXIS_EP5 TX Endpoint 5 Interrupt 5 6 USB_TXIS_EP6 TX Endpoint 6 Interrupt 6 7 USB_TXIS_EP7 TX Endpoint 7 Interrupt 7 8 USB0TXMAXP1 USB Maximum Transmit Data Endpoint 1 0x110 16 read-write n 0x0 0x0 USB_TXMAXP1_MAXLOAD Maximum Payload 0 11 USB0TXMAXP2 USB Maximum Transmit Data Endpoint 2 0x120 16 read-write n 0x0 0x0 USB_TXMAXP2_MAXLOAD Maximum Payload 0 11 USB0TXMAXP3 USB Maximum Transmit Data Endpoint 3 0x130 16 read-write n 0x0 0x0 USB_TXMAXP3_MAXLOAD Maximum Payload 0 11 USB0TXMAXP4 USB Maximum Transmit Data Endpoint 4 0x140 16 read-write n 0x0 0x0 USB_TXMAXP4_MAXLOAD Maximum Payload 0 11 USB0TXMAXP5 USB Maximum Transmit Data Endpoint 5 0x150 16 read-write n 0x0 0x0 USB_TXMAXP5_MAXLOAD Maximum Payload 0 11 USB0TXMAXP6 USB Maximum Transmit Data Endpoint 6 0x160 16 read-write n 0x0 0x0 USB_TXMAXP6_MAXLOAD Maximum Payload 0 11 USB0TXMAXP7 USB Maximum Transmit Data Endpoint 7 0x170 16 read-write n 0x0 0x0 USB_TXMAXP7_MAXLOAD Maximum Payload 0 11 USB0TXTYPE1 USB Host Transmit Configure Type Endpoint 1 0x11A 8 read-write n 0x0 0x0 USB_TXTYPE1_PROTO Protocol 4 6 USB_TXTYPE1_PROTO_CTRL Control 0x0 USB_TXTYPE1_PROTO_ISOC Isochronous 0x1 USB_TXTYPE1_PROTO_BULK Bulk 0x2 USB_TXTYPE1_PROTO_INT Interrupt 0x3 USB_TXTYPE1_SPEED Operating Speed 6 8 USB_TXTYPE1_SPEED_DFLT Default 0x0 USB_TXTYPE1_SPEED_HIGH High 0x1 USB_TXTYPE1_SPEED_FULL Full 0x2 USB_TXTYPE1_SPEED_LOW Low 0x3 USB_TXTYPE1_TEP Target Endpoint Number 0 4 USB0TXTYPE2 USB Host Transmit Configure Type Endpoint 2 0x12A 8 read-write n 0x0 0x0 USB_TXTYPE2_PROTO Protocol 4 6 USB_TXTYPE2_PROTO_CTRL Control 0x0 USB_TXTYPE2_PROTO_ISOC Isochronous 0x1 USB_TXTYPE2_PROTO_BULK Bulk 0x2 USB_TXTYPE2_PROTO_INT Interrupt 0x3 USB_TXTYPE2_SPEED Operating Speed 6 8 USB_TXTYPE2_SPEED_DFLT Default 0x0 USB_TXTYPE2_SPEED_HIGH High 0x1 USB_TXTYPE2_SPEED_FULL Full 0x2 USB_TXTYPE2_SPEED_LOW Low 0x3 USB_TXTYPE2_TEP Target Endpoint Number 0 4 USB0TXTYPE3 USB Host Transmit Configure Type Endpoint 3 0x13A 8 read-write n 0x0 0x0 USB_TXTYPE3_PROTO Protocol 4 6 USB_TXTYPE3_PROTO_CTRL Control 0x0 USB_TXTYPE3_PROTO_ISOC Isochronous 0x1 USB_TXTYPE3_PROTO_BULK Bulk 0x2 USB_TXTYPE3_PROTO_INT Interrupt 0x3 USB_TXTYPE3_SPEED Operating Speed 6 8 USB_TXTYPE3_SPEED_DFLT Default 0x0 USB_TXTYPE3_SPEED_HIGH High 0x1 USB_TXTYPE3_SPEED_FULL Full 0x2 USB_TXTYPE3_SPEED_LOW Low 0x3 USB_TXTYPE3_TEP Target Endpoint Number 0 4 USB0TXTYPE4 USB Host Transmit Configure Type Endpoint 4 0x14A 8 read-write n 0x0 0x0 USB_TXTYPE4_PROTO Protocol 4 6 USB_TXTYPE4_PROTO_CTRL Control 0x0 USB_TXTYPE4_PROTO_ISOC Isochronous 0x1 USB_TXTYPE4_PROTO_BULK Bulk 0x2 USB_TXTYPE4_PROTO_INT Interrupt 0x3 USB_TXTYPE4_SPEED Operating Speed 6 8 USB_TXTYPE4_SPEED_DFLT Default 0x0 USB_TXTYPE4_SPEED_HIGH High 0x1 USB_TXTYPE4_SPEED_FULL Full 0x2 USB_TXTYPE4_SPEED_LOW Low 0x3 USB_TXTYPE4_TEP Target Endpoint Number 0 4 USB0TXTYPE5 USB Host Transmit Configure Type Endpoint 5 0x15A 8 read-write n 0x0 0x0 USB_TXTYPE5_PROTO Protocol 4 6 USB_TXTYPE5_PROTO_CTRL Control 0x0 USB_TXTYPE5_PROTO_ISOC Isochronous 0x1 USB_TXTYPE5_PROTO_BULK Bulk 0x2 USB_TXTYPE5_PROTO_INT Interrupt 0x3 USB_TXTYPE5_SPEED Operating Speed 6 8 USB_TXTYPE5_SPEED_DFLT Default 0x0 USB_TXTYPE5_SPEED_HIGH High 0x1 USB_TXTYPE5_SPEED_FULL Full 0x2 USB_TXTYPE5_SPEED_LOW Low 0x3 USB_TXTYPE5_TEP Target Endpoint Number 0 4 USB0TXTYPE6 USB Host Transmit Configure Type Endpoint 6 0x16A 8 read-write n 0x0 0x0 USB_TXTYPE6_PROTO Protocol 4 6 USB_TXTYPE6_PROTO_CTRL Control 0x0 USB_TXTYPE6_PROTO_ISOC Isochronous 0x1 USB_TXTYPE6_PROTO_BULK Bulk 0x2 USB_TXTYPE6_PROTO_INT Interrupt 0x3 USB_TXTYPE6_SPEED Operating Speed 6 8 USB_TXTYPE6_SPEED_DFLT Default 0x0 USB_TXTYPE6_SPEED_HIGH High 0x1 USB_TXTYPE6_SPEED_FULL Full 0x2 USB_TXTYPE6_SPEED_LOW Low 0x3 USB_TXTYPE6_TEP Target Endpoint Number 0 4 USB0TXTYPE7 USB Host Transmit Configure Type Endpoint 7 0x17A 8 read-write n 0x0 0x0 USB_TXTYPE7_PROTO Protocol 4 6 USB_TXTYPE7_PROTO_CTRL Control 0x0 USB_TXTYPE7_PROTO_ISOC Isochronous 0x1 USB_TXTYPE7_PROTO_BULK Bulk 0x2 USB_TXTYPE7_PROTO_INT Interrupt 0x3 USB_TXTYPE7_SPEED Operating Speed 6 8 USB_TXTYPE7_SPEED_DFLT Default 0x0 USB_TXTYPE7_SPEED_HIGH High 0x1 USB_TXTYPE7_SPEED_FULL Full 0x2 USB_TXTYPE7_SPEED_LOW Low 0x3 USB_TXTYPE7_TEP Target Endpoint Number 0 4 USB0TYPE0 USB Type Endpoint 0 0x10A 8 read-write n 0x0 0x0 USB_TYPE0_SPEED Operating Speed 6 8 USB_TYPE0_SPEED_HIGH High 0x1 USB_TYPE0_SPEED_FULL Full 0x2 USB_TYPE0_SPEED_LOW Low 0x3 USB0ULPIREGADDR USB ULPI Register Address 0x75 8 read-write n 0x0 0x0 USB_ULPIREGADDR_ADDR Register Address 0 8 USB0ULPIREGCTL USB ULPI Register Control 0x76 8 read-write n 0x0 0x0 USB_ULPIREGCTL_RDWR Read/Write Control 2 3 USB_ULPIREGCTL_REGACC Initiate Register Access 0 1 USB_ULPIREGCTL_REGCMPLT Register Access Complete 1 2 USB0ULPIREGDATA USB ULPI Register Data 0x74 8 read-write n 0x0 0x0 USB_ULPIREGDATA_REGDATA Register Data 0 8 USB0ULPIVBUSCTL USB ULPI VBUS Control 0x70 8 read-write n 0x0 0x0 USB_ULPIVBUSCTL_USEEXTVBUS Use External VBUS 0 1 USB_ULPIVBUSCTL_USEEXTVBUSIND Use External VBUS Indicator 1 2 USB0VDC USB VBUS Droop Control 0x430 read-write n 0x0 0x0 USB_VDC_VBDEN VBUS Droop Enable 0 1 USB0VDCIM USB VBUS Droop Control Interrupt Mask 0x438 read-write n 0x0 0x0 USB_VDCIM_VD VBUS Droop Interrupt Mask 0 1 USB0VDCISC USB VBUS Droop Control Interrupt Status and Clear 0x43C read-write n 0x0 0x0 USB_VDCISC_VD VBUS Droop Interrupt Status and Clear 0 1 USB0VDCRIS USB VBUS Droop Control Raw Interrupt Status 0x434 read-write n 0x0 0x0 USB_VDCRIS_VD VBUS Droop Raw Interrupt Status 0 1 USB0VPLEN USB OTG VBUS Pulse Timing 0x7B 8 read-write n 0x0 0x0 USB_VPLEN_VPLEN VBUS Pulse Length 0 8 VDC USB VBUS Droop Control 0x430 -1 read-write n 0x0 0x0 USB_VDC_VBDEN VBUS Droop Enable 0 1 VDCIM USB VBUS Droop Control Interrupt Mask 0x438 -1 read-write n 0x0 0x0 USB_VDCIM_VD VBUS Droop Interrupt Mask 0 1 VDCISC USB VBUS Droop Control Interrupt Status and Clear 0x43C -1 read-write n 0x0 0x0 USB_VDCISC_VD VBUS Droop Interrupt Status and Clear 0 1 VDCRIS USB VBUS Droop Control Raw Interrupt Status 0x434 -1 read-write n 0x0 0x0 USB_VDCRIS_VD VBUS Droop Raw Interrupt Status 0 1 VPLEN USB OTG VBUS Pulse Timing 0x7B 8 read-write n 0x0 0x0 USB_VPLEN_VPLEN VBUS Pulse Length 0 8 WATCHDOG0 Register map for WATCHDOG0 peripheral WATCHDOG 0x0 0x0 0x1000 registers n WATCHDOG0 18 CTL Watchdog Control 0x8 -1 read-write n 0x0 0x0 WDT_CTL_INTEN Watchdog Interrupt Enable 0 1 WDT_CTL_INTTYPE Watchdog Interrupt Type 2 3 WDT_CTL_RESEN Watchdog Reset Enable 1 2 WDT_CTL_WRC Write Complete 31 32 ICR Watchdog Interrupt Clear 0xC -1 write-only n 0x0 0x0 WDT_ICR Watchdog Interrupt Clear 0 32 write-only LOAD Watchdog Load 0x0 -1 read-write n 0x0 0x0 WDT_LOAD Watchdog Load Value 0 32 LOCK Watchdog Lock 0xC00 -1 read-write n 0x0 0x0 WDT_LOCK Watchdog Lock 0 32 WDT_LOCK_UNLOCKED Unlocked 0x0 WDT_LOCK_LOCKED Locked 0x1 WDT_LOCK_UNLOCK Unlocks the watchdog timer 0x1acce551 MIS Watchdog Masked Interrupt Status 0x14 -1 read-write n 0x0 0x0 WDT_MIS_WDTMIS Watchdog Masked Interrupt Status 0 1 RIS Watchdog Raw Interrupt Status 0x10 -1 read-write n 0x0 0x0 WDT_RIS_WDTRIS Watchdog Raw Interrupt Status 0 1 TEST Watchdog Test 0x418 -1 read-write n 0x0 0x0 WDT_TEST_STALL Watchdog Stall Enable 8 9 VALUE Watchdog Value 0x4 -1 read-write n 0x0 0x0 WDT_VALUE Watchdog Value 0 32 WATCHDOG0CTL Watchdog Control 0x8 read-write n 0x0 0x0 WDT_CTL_INTEN Watchdog Interrupt Enable 0 1 WDT_CTL_INTTYPE Watchdog Interrupt Type 2 3 WDT_CTL_RESEN Watchdog Reset Enable 1 2 WDT_CTL_WRC Write Complete 31 32 WATCHDOG0ICR Watchdog Interrupt Clear 0xC write-only n 0x0 0x0 WDT_ICR Watchdog Interrupt Clear 0 32 write-only WATCHDOG0LOAD Watchdog Load 0x0 read-write n 0x0 0x0 WDT_LOAD Watchdog Load Value 0 32 WATCHDOG0LOCK Watchdog Lock 0xC00 read-write n 0x0 0x0 WDT_LOCK Watchdog Lock 0 32 WDT_LOCK_UNLOCKED Unlocked 0x0 WDT_LOCK_LOCKED Locked 0x1 WDT_LOCK_UNLOCK Unlocks the watchdog timer 0x1acce551 WATCHDOG0MIS Watchdog Masked Interrupt Status 0x14 read-write n 0x0 0x0 WDT_MIS_WDTMIS Watchdog Masked Interrupt Status 0 1 WATCHDOG0RIS Watchdog Raw Interrupt Status 0x10 read-write n 0x0 0x0 WDT_RIS_WDTRIS Watchdog Raw Interrupt Status 0 1 WATCHDOG0TEST Watchdog Test 0x418 read-write n 0x0 0x0 WDT_TEST_STALL Watchdog Stall Enable 8 9 WATCHDOG0VALUE Watchdog Value 0x4 read-write n 0x0 0x0 WDT_VALUE Watchdog Value 0 32 WATCHDOG1 Register map for WATCHDOG0 peripheral WATCHDOG 0x0 0x0 0x1000 registers n CTL Watchdog Control 0x8 -1 read-write n 0x0 0x0 WDT_CTL_INTEN Watchdog Interrupt Enable 0 1 WDT_CTL_INTTYPE Watchdog Interrupt Type 2 3 WDT_CTL_RESEN Watchdog Reset Enable 1 2 WDT_CTL_WRC Write Complete 31 32 ICR Watchdog Interrupt Clear 0xC -1 write-only n 0x0 0x0 WDT_ICR Watchdog Interrupt Clear 0 32 write-only LOAD Watchdog Load 0x0 -1 read-write n 0x0 0x0 WDT_LOAD Watchdog Load Value 0 32 LOCK Watchdog Lock 0xC00 -1 read-write n 0x0 0x0 WDT_LOCK Watchdog Lock 0 32 WDT_LOCK_UNLOCKED Unlocked 0x0 WDT_LOCK_LOCKED Locked 0x1 WDT_LOCK_UNLOCK Unlocks the watchdog timer 0x1acce551 MIS Watchdog Masked Interrupt Status 0x14 -1 read-write n 0x0 0x0 WDT_MIS_WDTMIS Watchdog Masked Interrupt Status 0 1 RIS Watchdog Raw Interrupt Status 0x10 -1 read-write n 0x0 0x0 WDT_RIS_WDTRIS Watchdog Raw Interrupt Status 0 1 TEST Watchdog Test 0x418 -1 read-write n 0x0 0x0 WDT_TEST_STALL Watchdog Stall Enable 8 9 VALUE Watchdog Value 0x4 -1 read-write n 0x0 0x0 WDT_VALUE Watchdog Value 0 32 WATCHDOG0CTL Watchdog Control 0x8 read-write n 0x0 0x0 WDT_CTL_INTEN Watchdog Interrupt Enable 0 1 WDT_CTL_INTTYPE Watchdog Interrupt Type 2 3 WDT_CTL_RESEN Watchdog Reset Enable 1 2 WDT_CTL_WRC Write Complete 31 32 WATCHDOG0ICR Watchdog Interrupt Clear 0xC write-only n 0x0 0x0 WDT_ICR Watchdog Interrupt Clear 0 32 write-only WATCHDOG0LOAD Watchdog Load 0x0 read-write n 0x0 0x0 WDT_LOAD Watchdog Load Value 0 32 WATCHDOG0LOCK Watchdog Lock 0xC00 read-write n 0x0 0x0 WDT_LOCK Watchdog Lock 0 32 WDT_LOCK_UNLOCKED Unlocked 0x0 WDT_LOCK_LOCKED Locked 0x1 WDT_LOCK_UNLOCK Unlocks the watchdog timer 0x1acce551 WATCHDOG0MIS Watchdog Masked Interrupt Status 0x14 read-write n 0x0 0x0 WDT_MIS_WDTMIS Watchdog Masked Interrupt Status 0 1 WATCHDOG0RIS Watchdog Raw Interrupt Status 0x10 read-write n 0x0 0x0 WDT_RIS_WDTRIS Watchdog Raw Interrupt Status 0 1 WATCHDOG0TEST Watchdog Test 0x418 read-write n 0x0 0x0 WDT_TEST_STALL Watchdog Stall Enable 8 9 WATCHDOG0VALUE Watchdog Value 0x4 read-write n 0x0 0x0 WDT_VALUE Watchdog Value 0 32